Metal silicide preparation method and semiconductor device

Abstract

The invention provides a metal silicide preparation method and a semiconductor device, and the method comprises the steps: depositing a silicon nitride film on a substrate before a temporary silicon oxide layer of a silicide barrier layer is formed; oxidizing the silicon nitride film into a first silicon oxide layer; a second silicon oxide layer is formed on the surface of the first silicon oxide layer, the first silicon oxide layer and the second silicon oxide layer jointly form a silicon oxide layer, and at the moment, the thicknesses of the silicon oxide layers on the surfaces of the substrates in the NMOS source-drain region and the PMOS source-drain region are consistent; performing dry etching on the silicon oxide layer to retain the silicon oxide layer on the side walls of the NMOS gate structure and the PMOS gate structure; and performing a subsequent metal silicide process. According to the invention, the thickness of the temporary silicon oxide layer of the silicide barrier layer finally formed on the substrate can be ensured to be the same, so that the temporary silicon oxide layer can be simultaneously removed in the subsequent process, and the defect that the metal silicide part is lost in the PMOS is avoided.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a method for preparing metal silicides and a semiconductor device. Background Technology

[0002] In existing semiconductor processes, metal silicide technology adds silicon metallization steps to the standard CMOS process and is performed after source and drain ion implantation. Due to the different ion implantation rates in the N MOS and P MOS regions, the deposition rate of the temporary silicon oxide layer (SABOX) in the silicide barrier module differs significantly. This results in temporary silicon oxide layers of different thicknesses forming in N / P MOS, with the PMOS having a thicker temporary silicon oxide layer. During subsequent etching, the PMOS with the thicker temporary silicon oxide layer will have some residual silicon oxide, leading to defects such as partial missing metal silicide in the PMOS during the subsequent silicon metallization process, significantly impacting yield. Summary of the Invention

[0003] In view of the above-mentioned defects or improvement needs of the prior art, this application proposes a method and semiconductor device for improving the partial absence of metal silicide in PMOS.

[0004] To achieve the above objectives, this application provides a method for improving the partial loss of metal silicide in PMOS. A silicon nitride thin film is deposited on a substrate; the substrate includes a base, and an NMOS gate structure and a PMOS gate structure spaced apart on the base, wherein the base located on both sides of the NMOS gate structure and the PMOS gate structure are the NMOS source / drain region and the PMOS source / drain region, respectively; the silicon nitride thin film is deposited on the surface of the NMOS source / drain region and the PMOS source / drain region, the sidewall and the top surface of the NMOS gate structure and the PMOS gate structure; The silicon nitride thin film is oxidized into a first silicon oxide layer; A second silicon oxide layer is formed on the surface of the first silicon oxide layer. The first silicon oxide layer and the second silicon oxide layer together constitute a silicon oxide layer. At this time, the thickness of the silicon oxide layer on the surface of the NMOS source / drain region and the PMOS source / drain region is the same. Dry etching of the silicon oxide layer is used to preserve the silicon oxide layer located on the sidewalls of the NMOS gate structure and the PMOS gate structure. Then proceed with the subsequent metal silicide process.

[0005] According to the above scheme, a silicon nitride thin film is deposited on the substrate using plasma-enhanced chemical vapor deposition.

[0006] According to the above scheme, the thickness of the silicon nitride film is 5-20 Å.

[0007] According to the above scheme, high-density plasma chemical vapor deposition is used to oxidize the silicon nitride film into the first silicon oxide layer by using high-density plasma and introducing reactive gas.

[0008] According to the above scheme, the reaction gases include oxygen or nitrous oxide.

[0009] According to the above scheme, during the process of oxidizing the silicon nitride thin film into the first silicon oxide layer, the power of the high-density plasma is above 5000W.

[0010] According to the above scheme, the reaction temperature for dry etching of silicon oxide layer is 30-50℃, the source power is 200-500W, the bias power is 100-200W, and the chamber pressure is 5-30mTorr.

[0011] According to the above scheme, the subsequent metal silicide process includes: depositing a metal silicide layer.

[0012] According to the above scheme, the metal silicide layer is a nickel silicide layer.

[0013] This application also provides a semiconductor device obtained by the method described above for improving the partial absence of metal silicide in a PMOS.

[0014] In summary, compared with the prior art, the above-described technical solutions conceived in this application can achieve the following beneficial effects: 1. By first forming a silicon nitride film of uniform thickness, and then oxidizing the silicon nitride film to obtain a first silicon oxide layer of uniform thickness, and then forming a second silicon oxide layer on the first silicon oxide layer, an unexpected effect is that it ensures that the temporary silicon oxide layer of the silicide barrier layer formed on the substrate has the same thickness. This allows it to be removed simultaneously in subsequent processes, preventing the problem of residual silicon oxide in PMOS. This ensures that there is no difference between N / PMOS in the metal silicide process, that is, it ensures that there will be no defects of missing metal silicide in PMOS.

[0015] 2. Utilizing the principle that plasma-enhanced chemical vapor deposition (PECVD) can deposit silicon nitride thin films at the same deposition rate on NMOS and PMOS, and the principle that silicon nitride can be oxidized to silicon oxide, an unexpected effect is that it further ensures that the thickness of the first silicon oxide layer deposited on the substrate surface of NMOS and PMOS is the same.

[0016] Of course, any product implementing this application does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] Figure 1 This is a flowchart of a method provided in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the product structure in its initial state provided in the embodiments of this application.

[0019] Figure 3 This is a schematic diagram of the product structure corresponding to S1 provided in the embodiments of this application.

[0020] Figure 4 This is a schematic diagram of the product structure corresponding to S2 provided in the embodiments of this application.

[0021] Figure 5 This is a schematic diagram of the product structure corresponding to S3 provided in the embodiments of this application.

[0022] Figure 6 This is a schematic diagram of the product structure corresponding to S4 provided in the embodiments of this application.

[0023] Figure 7 This is a schematic diagram of the product structure corresponding to S5 provided in the embodiments of this application.

[0024] In the figure: 1-substrate, 21-PMOS source region, 22-NMOS source region, 31-PMOS drain region, 32-NMOS drain region, 411-PMOS gate, 412-PMOS sidewall, 421-NMOS gate, 422-NMOS sidewall, 5-silicon nitride thin film, 51-first silicon oxide layer, 601-silicon oxide layer of the substrate, 602-silicon oxide layer on top of the gate, 603-silicon oxide layer of the gate sidewall, 701-metal silicide of the substrate, 702-metal silicide on top of the gate. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0026] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0028] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0029] In some semiconductor processes, a silicide metallization step needs to be added to the standard CMOS process. This is typically performed after gate etching and source / drain ion implantation. A metal layer (usually Ti, Co, or Ni) is deposited on polysilicon via sputtering, followed by a first rapid temperature annealing (RTA) process. This allows the polysilicon surface and the deposited metal to react, forming metal silicides. Prior to this, a temporary silicon oxide (SABOX) layer is formed as a silicide barrier. Due to differences in ion implantation rates in the N- and P-regions, the deposition rate of the temporary SABOX layer varies significantly, resulting in inconsistent thicknesses in the NMOS and PMOS regions. During subsequent removal, the thicker PMOS region may have residual silicon oxide, constituting a defect of missing metal silicide in the PMOS. This application aims to improve this situation.

[0030] This embodiment provides a method for improving the partial absence of metal silicide in PMOS, including the following steps: A silicon nitride thin film is deposited on a substrate. The substrate includes a base and an NMOS gate structure and a PMOS gate structure spaced apart on the base. The base on either side of the NMOS gate structure and the PMOS gate structure are the NMOS source / drain regions and the PMOS source / drain regions, respectively. The silicon nitride thin film is deposited on the surfaces of the NMOS source / drain regions and the PMOS source / drain regions, as well as the sidewalls and top surfaces of the NMOS gate structure and the PMOS gate structure. The main principle of this step is to find a process and materials whose deposition rate is not affected by the different source / drain implanted ions.

[0031] The silicon nitride film is oxidized into a first silicon oxide layer. This step oxidizes the deposited silicon nitride film into a temporary silicon oxide layer of the same material as the silicide barrier layer, thereby enabling it to be integrated with and simultaneously removed from the subsequently formed silicon oxide layer.

[0032] A second silicon oxide layer is formed on the surface of the first silicon oxide layer. The first and second silicon oxide layers together constitute a silicon oxide layer. At this time, the thickness of the silicon oxide layer on the surface of the NMOS source / drain region and the PMOS source / drain region is the same.

[0033] Dry etching of the silicon oxide layer is used to preserve the silicon oxide layer located on the sidewalls of the NMOS gate structure and the PMOS gate structure.

[0034] Then proceed with the subsequent metal silicide process.

[0035] Based on the above method, the method provided in this embodiment for improving the partial loss defect of metal silicide in PMOS is as follows: Figure 1 As shown, the specific steps include: S1. Before forming the temporary silicon oxide layer of the silicide barrier layer, a silicon nitride thin film is formed in the active region of the substrate, such that the substrate surface, gate sidewall and gate top surface are all covered with a silicon nitride thin film, and the thickness of the silicon nitride thin film on the surface of the NMOS source drain region and the PMOS source drain region is the same.

[0036] like Figure 2 As shown, before the temporary silicon oxide layer forming the silicide barrier layer, the substrate includes a substrate 1 and a PMOS gate structure and an NMOS gate structure located on the substrate 1. The PMOS gate structure includes a PMOS gate 411 and a PMOS sidewall 412 surrounding the PMOS gate 411. The PMOS source region 21 and the PMOS drain region 31 are located on opposite sides of the PMOS gate structure, respectively. The NMOS gate structure includes an NMOS gate 421 and an NMOS sidewall 422 surrounding the NMOS gate 421. The PMOS source region 21 and the PMOS drain region 31 are located on opposite sides of the PMOS gate structure, respectively. The upper surfaces of the NMOS source / drain regions and the PMOS source / drain regions are the surfaces of the substrate 1.

[0037] exist Figure 2 Based on this, a silicon nitride thin film 5 is formed in the active region, resulting in the structure shown below. Figure 3 As shown in the figure, the top of the substrate 1, the PMOS gate 411 and the NMOS gate 421, as well as the outer walls of the PMOS sidewall 412 and the NMOS sidewall 422 are all covered with a silicon nitride thin film 5.

[0038] In this embodiment, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a silicon nitride thin film with a thickness of 5-20 Å in the active region, preferably 10 Å.

[0039] PECVD is a process for preparing thin film materials using plasma-assisted chemical vapor deposition. It generates plasma to activate reactive gases, enabling the deposition of high-quality thin films at relatively low temperatures. Because the deposition rate of silicon nitride thin films using PECVD is unaffected by differences in source / drain implanted ions—that is, the deposition rate of the silicon nitride thin film is the same regardless of the ions implanted in the N-region and P-region—the thickness of the silicon nitride thin film deposited on the substrate surfaces of NMOS and PMOS devices is consistent. Therefore, this embodiment utilizes this principle; due to the consistent deposition rate, a uniformly thick silicon nitride thin film can be deposited before the temporary silicon oxide layer forming the silicide barrier layer.

[0040] In some embodiments, the ions implanted into the PMOS source and drain regions are B or BF2, with a concentration ≥ 1 × 10⁻⁶. 14 cm - ², while the ions implanted in the source and drain regions of NMOS are P, As, or F, with a concentration ≥ 1×10⁻⁶. 14 cm - ². It can be observed that the ions implanted in the N-region and P-region are different. By employing the method of this invention, the deposition rate of the silicon nitride thin film is not affected by the different ion implantations in the PMOS and NMOS source / drain regions.

[0041] Since the silicon nitride films deposited on the substrate surfaces of NMOS and PMOS are of the same thickness, the temporary silicon oxide layer (SAB OX) in the subsequently formed silicide barrier layer is also of the same thickness. It will be removed synchronously during the subsequent removal process, and there will be no problem of silicon oxide residue.

[0042] In some embodiments, when depositing silicon nitride thin films using PECVD, the power needs to be controlled between 400 and 600 W, the SiH4 flow rate between 100 and 200 sccm, the N2 flow rate between 170,000 and 20,000 sccm, and the pressure between 1 and 3 Torr. Under these conditions, the "overhang" of the sidewall SiN can be minimized, resulting in a uniform sidewall SiN thickness, which facilitates subsequent simultaneous removal. The overhang refers to the portion of SiN that "protrudes" outward from the top of the sidewall; simply put, it is an extra ring of "eaves"-like protrusions that grows from the top of the sidewall after deposition.

[0043] S2. Oxidize the silicon nitride thin film 5 to form a first silicon oxide layer 51, resulting in the following: Figure 4 The structure shown.

[0044] This step is mainly to remove the deposited silicon nitride film 5 and the temporary silicon oxide layer (SAB OX) in the silicide barrier layer that needs to be formed later in one step, that is: to oxidize the silicon nitride film 5 into the same material as the temporary silicon oxide layer.

[0045] In this embodiment, high-density plasma chemical vapor deposition (HDP) is used. High-density plasma, with the introduction of a reactive gas, is used to oxidize the silicon nitride film 5 into a first silicon oxide layer 51. The reactive gas is either oxygen or nitrous oxide. During the oxidation process, the plasma power of HDP must be maintained above 5000W, and an oxidizing gas must be present.

[0046] Specifically, HDP (High Density Plasma) technology, also known as High Density Plasma Chemical Vapor Deposition (HDP-CVD), is a special form of chemical vapor deposition (CVD). Its core principle is to excite high-density plasma (ion density > 10⁻⁶) using a radio frequency or microwave power source. 11 cm - ³), achieving a dynamic balance between deposition and sputtering etching simultaneously under low pressure.

[0047] S3. A second silicon oxide layer is formed on the surface of the first silicon oxide layer 51. The first silicon oxide layer 51 and the second silicon oxide layer together constitute a silicon oxide layer, forming as shown in the figure. Figure 5 The structure shown includes a silicon oxide layer 601 on the substrate, a silicon oxide layer 602 on the top of the gate, and a silicon oxide layer 603 on the gate sidewall.

[0048] Since the second silicon oxide layer is deposited on the surface of the first silicon oxide layer 51, the deposition rate is the same. Therefore, the thickness of the resulting silicon oxide layer on the substrate surface located in the NMOS and PMOS source / drain regions is also consistent.

[0049] In some embodiments, the HDP oxidation process requires a relatively high power output, preferably between 5000 and 10000 kW, a temperature between 350 and 550°C, and the flow rate of the oxidizing gas O2 or N2O needs to be controlled between 80 and 120 sccm. Optionally, to ensure the oxidation effect, 200~400 sccm of argon gas can be added.

[0050] At the same time, it is also necessary to ensure that the pressure is low enough, preferably between 0 and 10 mTorr.

[0051] Furthermore, the overall oxidation time is controlled within 30-60 seconds.

[0052] S4. Completely remove the silicon oxide layers located on the substrate surface and the top surface of the gate, retaining the silicon oxide layer 603 on the gate sidewall, to obtain the following: Figure 6 The structure shown is as follows. Specifically, by dry etching the silicon oxide layer, the silicon oxide layer 601 on the substrate and the silicon oxide layer 602 on top of the gate can be removed, while the silicon oxide layer 603 on the gate sidewall is retained.

[0053] In this embodiment, the silicon oxide layers located on the substrate surface and the top surface of the gate are completely removed by photolithography and etching. Since the silicon oxide layer thickness on the substrate surfaces of the NMOS and PMOS is the same, it can be completely removed simultaneously during etching, leaving no silicon oxide layer residue on the top surface of the PMOS.

[0054] This part of the process involves conventional photoresist coating, exposure, and development, followed by dry etching to completely remove the silicon oxide layer on the substrate surface of the NMOS and PMOS source / drain regions. Dry etching is a micro / nano patterning transfer process that uses plasma or gaseous reactants to selectively remove exposed materials on a wafer through ion bombardment and chemical reaction in the absence of liquid chemicals.

[0055] In some embodiments, the parameters for dry etching specifically include: a reaction temperature of 30-50°C, a source power of 200-500W, a bias power of 100-200W, and a chamber pressure of 5-30 mTorr. S5. Perform subsequent metal silicide processes, including: depositing a metal silicide layer to obtain... Figure 7 The structure shown includes a metal silicide layer comprising a metal silicide 701 on the substrate and a metal silicide 702 on top of the gate.

[0056] The metal silicide layer can be a nickel silicide layer (NiSi) or other metal silicide layers.

[0057] The subsequent metal silicide process can be the same as the conventional process, and is not an improvement of this application, so it is not described in detail.

[0058] Furthermore, the aforementioned method for improving the partial absence of metal silicide in PMOS is mainly applied in logic processes following N / PMOSSAB with NiSi processing, such as 40nm~90nm low-power logic processes. Here, 40nm~90nm refers to the process dimensions.

[0059] Furthermore, this embodiment also provides a semiconductor device obtained by using the method described above for improving the partial absence of metal silicide in PMOS, such as an advanced process CMOS device, or other semiconductor devices that require metal silicide processes.

[0060] The core of this application lies in changing the substrate of the temporary silicon oxide layer of the silicide barrier layer by first forming a silicon nitride thin film and oxidizing it into a silicon oxide layer before depositing the temporary silicon oxide layer of the silicide barrier layer. This ensures that the SAB OX thickness of N / PMOS is consistent, and can be completely removed in subsequent processes. This ensures that there is no difference between N / PMOS in the metal silicide process, that is, it ensures that there will be no defects of missing metal silicide in PMOS.

[0061] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0062] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of a step / component can be combined into a new step / component to achieve the purpose of this application.

[0063] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for preparing metal silicides, characterized in that: A silicon nitride thin film is deposited on a substrate; the substrate includes a base, and an NMOS gate structure and a PMOS gate structure spaced apart on the base, wherein the base located on both sides of the NMOS gate structure and the PMOS gate structure are the NMOS source / drain region and the PMOS source / drain region, respectively; the silicon nitride thin film is deposited on the surface of the NMOS source / drain region and the PMOS source / drain region, the sidewall and the top surface of the NMOS gate structure and the PMOS gate structure; The silicon nitride thin film is oxidized into a first silicon oxide layer; A second silicon oxide layer is formed on the surface of the first silicon oxide layer. The first silicon oxide layer and the second silicon oxide layer together constitute a silicon oxide layer. At this time, the thickness of the silicon oxide layer on the surface of the NMOS source / drain region and the PMOS source / drain region is the same. Dry etching of the silicon oxide layer is used to preserve the silicon oxide layer located on the sidewalls of the NMOS gate structure and the PMOS gate structure. Then proceed with the subsequent metal silicide process.

2. The method for preparing metal silicides according to claim 1, characterized in that: Silicon nitride thin films were deposited on the substrate using plasma-enhanced chemical vapor deposition.

3. The method for preparing metal silicides according to claim 1, characterized in that: The thickness of the silicon nitride film is 5-20 Å.

4. The method for preparing metal silicides according to claim 1, characterized in that: The step of oxidizing the silicon nitride thin film into a first silicon oxide layer includes: High-density plasma chemical vapor deposition is used to oxidize silicon nitride thin films into a first silicon oxide layer by using high-density plasma and introducing reactive gases.

5. The method for preparing metal silicides according to claim 4, characterized in that: The reacting gases include oxygen or nitrous oxide.

6. The method for preparing metal silicides according to claim 4, characterized in that: During the process of oxidizing the silicon nitride thin film into the first silicon oxide layer, the power of the high-density plasma is above 5000W.

7. The method for preparing metal silicides according to claim 1, characterized in that: The reaction temperature for dry etching of silicon oxide layers is 30-50℃, the source power is 200-500W, the bias power is 100-200W, and the chamber pressure is 5-30mTorr.

8. The method for preparing metal silicides according to claim 1, characterized in that: Subsequent metal silicide processes include: depositing a metal silicide layer.

9. The method for preparing metal silicides according to any one of claims 1 to 8, characterized in that: The metal silicide layer is a nickel silicide layer.

10. A semiconductor device, characterized in that: It is obtained by the metal silicide preparation method according to any one of claims 1-9.

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