Semiconductor device and layout optimization method

Abstract

The invention discloses a semiconductor device and a layout optimization method. The semiconductor device comprises a semiconductor substrate; the active region is formed in the semiconductor substrate, and a gate structure is formed above the active region; the shallow trench isolation structure is formed in the semiconductor substrate, and the shallow trench isolation structure is used for defining the active region; the first pseudo active region is formed in the shallow trench isolation structure, and the first pseudo active region is of a strip-shaped or annular structure in an overlook angle; the second pseudo active region is formed on the outer side of the first pseudo active region, and the width of the first pseudo active region is smaller than that of the second pseudo active region. The semiconductor device can increase the density of the active region and avoid gate breakdown.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a layout optimization method. BACKGROUND

[0002] STI (Shallow Trench Isolation) technology realizes electrical and physical isolation by forming a trench filled with a dielectric layer between active regions of a semiconductor device, thereby effectively preventing current interference or leakage of adjacent transistors. Compared with junction isolation or LOCOS (Local Oxidation of Silicon) process, STI process has the advantages of small size and small leakage.

[0003] HVIC (High Voltage Integrated Circuit) is a special integrated circuit that integrates high-voltage devices (such as MOSFET or IGBT driving stages capable of withstanding hundreds of volts or even thousands of volts) and low-voltage control circuits (such as logic gates, level shifters, protection circuits, etc.) on the same chip. Some HVIC products have large STI structures in the design, resulting in a low AA (active area) density around some semiconductor devices. During the gate etching process, the plasma charges generated by etching will accumulate at both ends of the gate capacitor. For regions with low AA density, the gate dielectric layer per unit area needs to withstand more charges, and the AA corner tips are more likely to generate induced potential. The gate dielectric layer at the corner will arc after accumulating a large amount of charges, resulting in increased leakage and reduced device yield. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the detailed description section. The summary section of the present application does not mean to attempt to limit the key features and essential technical features of the claimed technical solutions, nor to determine the protection scope of the claimed technical solutions.

[0005] In view of the existing problems, the embodiment of the present application provides a semiconductor device, which comprises: a semiconductor substrate; an active region formed in the semiconductor substrate, a gate structure being formed above the active region; a shallow trench isolation structure formed in the semiconductor substrate, the shallow trench isolation structure being used to define the active region; a first pseudo-active region formed in the shallow trench isolation structure, the first pseudo-active region being a strip-shaped or ring-shaped structure in a top view. a second dummy active region formed outside the first dummy active region, the width of the first dummy active region being less than the width of the second dummy active region.

[0006] In one embodiment, the length of the first dummy active region is not less than twice the width of the first dummy active region.

[0007] In one embodiment, the width of the first dummy active region is 0.2um-0.5um.

[0008] In one embodiment, the minimum distance between the first dummy active region and the active region is 0.5um-1um.

[0009] In one embodiment, the minimum distance between the first dummy active region and the end of the gate structure is 0.5um-1um.

[0010] In one embodiment, the maximum distance between the first dummy active region and the active region is 3um-10um.

[0011] In one embodiment, the second dummy active region is a square structure in a top view.

[0012] In one embodiment, the distance between the first dummy active region and the second dummy active region is not less than 1um.

[0013] Another aspect of the embodiments of the present application provides a layout optimization method, which comprises: obtaining an original layout, the original layout comprising an active region pattern, a second dummy active region pattern and a shallow trench isolation pattern for defining the active region pattern; inserting a plurality of square third dummy active region patterns in the shallow trench isolation pattern, the distance between adjacent third dummy active region patterns being not greater than the width of the third dummy active region pattern, the width of the third dummy active region pattern being less than the width of the second dummy active region pattern; enlarging the width of the plurality of third dummy active region patterns so as to merge adjacent third dummy active region patterns to form a fourth dummy active region pattern in a strip or ring shape; reducing the width of the fourth dummy active region pattern to be equal to the width of the third dummy active region pattern to obtain a first dummy active region pattern in a strip or ring shape, the width of the first dummy active region being less than the width of the second dummy active region.

[0014] In one embodiment, after obtaining the first dummy active region pattern, the method further comprises: reducing the width of the first dummy active region pattern to eliminate the first dummy active region pattern with a width less than a preset width; Increase the width of the remaining first pseudo-active region pattern.

[0015] The semiconductor device and layout optimization method of this invention sets a strip-shaped or ring-shaped first pseudo-active region in the shallow trench isolation structure near the active region, which can reduce the accumulation of charge on the gate dielectric layer of the active region during the process, avoid premature breakdown of the gate dielectric layer, thereby improving the reliability of the device and reducing yield loss. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0017] In the attached image: Figure 1 A cross-sectional view of a semiconductor device in the related art is shown; Figure 2 It shows Figure 1 The image shows a computer-aided design (TCAD) simulation diagram of a semiconductor device. Figure 3 A cross-sectional view of a semiconductor device according to a specific embodiment of the present invention is shown; Figure 4A and Figure 4B A top view of a semiconductor device according to a specific embodiment of the present invention is shown; Figure 5 A computer-aided design (TCAD) simulation diagram of a semiconductor device according to an embodiment of the present invention is shown; Figure 6 A comparison diagram of the gate leakage state before and after adding the first pseudo-active region in an embodiment of the present invention is shown; Figure 7 A schematic flowchart of a layout optimization method according to an embodiment of the present invention is shown. Detailed Implementation

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0019] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0021] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] For a thorough understanding of the present application, reference will be made to the following detailed description taken in conjunction with the accompanying drawings, in which: Preferred embodiments of the present application will be described in detail below with reference to the following description and drawings. However, the present application can have other embodiments.

[0024] As shown in Figure 1 , a semiconductor substrate 100 is formed with a shallow trench isolation structure 102 and an active region 101, the shallow trench isolation structure 102 is used to define the active region 101, the active region 101 includes a well region and a source-drain region formed in the well region, a gate structure 103 is formed above the semiconductor substrate 100 and across the active region 101, and an interlayer dielectric layer 104 and a contact hole 105 in the interlayer dielectric layer 104 are formed. The large shallow trench isolation structure 102 reduces the density of the active region 101, so that the gate dielectric layer per unit area needs to bear more electric charge, and the active region corner tip is more prone to induced potential. The gate dielectric layer at the corner of the active region 101 near the shallow trench isolation structure 102 is prone to arc discharge after accumulating a large amount of electric charge, resulting in increased leakage current, thereby causing low yield. Figure 2 TCAD (computer-aided design) simulation diagram of the semiconductor device is shown Figure 1 , from which it can be seen that the gate dielectric layer at the corner of the active region 101 near the shallow trench isolation structure 102 is prone to leakage due to charge accumulation.

[0025] To solve the above problems, the embodiment of the present application proposes a semiconductor device and a layout optimization method. Next, first refer to Figures 3 to 6 The semiconductor device of the embodiment of the present application is described in detail, wherein, Figure 3 a sectional view of the semiconductor device of one specific embodiment of the present application is shown, Figure 4A and Figure 4B a top view of the semiconductor device of one specific embodiment of the present application is shown; Figure 5 a computer-aided design (TCAD) simulation diagram of the semiconductor device of the embodiment of the present application is shown; Figure 6 a comparison diagram of the front and rear gate leakage states of the first pseudo-active region added with the embodiment of the present application is shown.

[0026] First, refer to Figure 3 , the semiconductor device of the embodiment of the present application includes: a semiconductor substrate 300; an active region 301 formed in the semiconductor substrate 300, a gate structure 304 is formed above the active region 301; a shallow trench isolation structure 302 formed in the semiconductor substrate 300, the shallow trench isolation structure 302 is used to define the active region 301; a first pseudo-active region 303 formed between two adjacent shallow trench isolation structures 302, the first pseudo-active region 303 is a strip or ring structure in a top view. As shown in Figure 4A and Figure 4B , it also includes a second pseudo-active region 401 formed outside the first pseudo-active region 303, the width of the first pseudo-active region 303 is smaller than the width of the second pseudo-active region 401.

[0027] Exemplarily, the constituent material of the semiconductor substrate 300 can be undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc.

[0028] The semiconductor substrate 300 is formed with shallow trench isolation structures 302 and active areas 301, and the shallow trench isolation structures 302 are used to define the active areas 301. That is, the shallow trench isolation structures 302 formed in the semiconductor substrate 300 divide the semiconductor substrate 300 into a plurality of active areas 301, and the shallow trench isolation structures 302 are used to physically isolate adjacent active areas (AA) to prevent leakage between the active areas. The active areas 301 are regions on the semiconductor substrate 300 that allow transistors (including NMOS or PMOS) to be formed.

[0029] Exemplarily, in the process of manufacturing a semiconductor device, silicon nitride (Si3N4) and oxide are deposited on the semiconductor substrate 300 as a hard mask layer, and after the active area pattern is defined by photolithography, the semiconductor substrate is etched based on the hard mask layer to form a trench. Then, a chemical vapor deposition process is used to fill the trench with a dielectric material such as silicon oxide, and chemical mechanical polishing (CMP) is used to remove excess dielectric material until the hard mask layer is exposed, forming a flat surface. Finally, the hard mask layer is removed. At this time, the active areas 301 surrounded by the shallow trench isolation structures 302 have appeared on the semiconductor substrate 300.

[0030] It should be noted that the active areas defined by the shallow trench isolation structures 302 include both real active areas (i.e., regions where transistors are actually to be formed) and dummy active areas (Dummy AA). Hereinafter, the active areas 301 refer to real active areas. Exemplarily, after the shallow trench isolation structures 302 are formed, ion implantation is performed in the active areas 301 to form well regions. The well region refers to a large range of doped regions (such as a P-type well or an N-type well) formed in the semiconductor substrate 300. A well region can contain a plurality of active areas. For example, a large N-well can be provided with a plurality of active areas of PMOS transistors.

[0031] Next, a gate structure 304 is formed on the surface of the semiconductor substrate 300. Exemplarily, a silicon oxide layer is first grown on the surface of the semiconductor substrate 300 by thermal oxidation as a gate dielectric layer. Then, a polysilicon or metal gate material is deposited on the gate dielectric layer. Finally, a gate pattern is defined by photolithography, and the excess gate material is etched away to form the gate structure 304. Next, a gate sidewall is formed on both sides of the gate structure 304 to protect the edges of the gate and ensure that the source / drain implantation is a certain distance away from the gate. Then, high-dose, high-energy ion implantation is performed to form heavily doped source and drain regions. At this time, the gate and the gate sidewall themselves act as a mask to automatically define the implantation area, ensuring that the source / drain is self-aligned with the gate. After that, high-temperature rapid annealing (RTA) can also be performed to activate the impurities and diffuse them to a predetermined depth. At this point, a transistor structure is formed in the active region 301. Subsequently, an interlayer dielectric layer 305 covering the semiconductor substrate 300 and the gate structure can be formed, and a contact hole 306 connected to the gate structure 304 and the source / drain region can be formed in the interlayer dielectric layer 305, thereby being electrically connected to the transistor structure.

[0032] As for the dummy active region, it is a real active region that is intentionally added to meet the requirements of the manufacturing process and has no electrical function. The dummy active region itself does not constitute any transistor, and the only purpose is to improve the yield and reliability of chip manufacturing. Many steps in the chip manufacturing process, such as chemical mechanical polishing and etching, are highly dependent on the uniformity of the density and pattern distribution of the chip surface material. If the active regions in one area of the chip are very dense, while those in another area are very sparse, it will cause problems such as uneven CMP, uneven etching, and uneven stress. The dummy active region is born to solve the above problems. By uniformly inserting dummy active regions in the sparse area, the pattern density of the active regions on the entire chip surface can be made uniform and consistent, thereby ensuring the quality of processes such as CMP and etching.

[0033] The dummy active region of the embodiment of the present application includes a first dummy active region 303 and a second dummy active region 401. The second dummy active region 401 is a conventional dummy active region, and the first dummy active region 303 is a newly added dummy active region of the embodiment of the present application.

[0034] Exemplarily, the second dummy active regions 401 are mainly located at the chip edge and the large blank area. These areas originally have no circuit, and filling the second dummy active regions 401 can improve the global uniformity of the whole chip. The second dummy active regions 401 are in the shape of a square block and are designed as a densely arranged array, mainly for filling an area of any size with the highest efficiency, thereby providing a uniform and predictable pattern density. The number of square blocks of the same size that need to be inserted in a region to achieve the target density can be calculated using a design tool, and the corresponding pattern can be automatically generated. The square block-shaped second dummy active regions 401 can also ensure the photolithography resolution, etching uniformity and CMP uniformity, and improve the convenience of design and verification.

[0035] Generally, no dummy active region is arranged in the large shallow trench isolation structure surrounding the active region, which can cause the gate dielectric layer at the corner of the active region to be prematurely broken down. Therefore, in the embodiment of the present application, the first dummy active region 303 in the shape of a strip or a ring is inserted into the large shallow trench isolation structure surrounding the active region 301, so as to increase the active region density and reduce the risk of leakage.

[0036] Exemplarily, the width of the first dummy active region 303 is smaller than the width of the second dummy active region 401. The width of the first dummy active region 303 refers to the short side dimension of the first dummy active region 303, and the width of the second dummy active region 401 refers to the short side dimension of the second dummy active region 401. According to the conventional dummy active region insertion rule, the second dummy active region 401 cannot be inserted into the large shallow trench isolation structure 302 surrounding the active region, and the embodiment of the present application inserts the first dummy active region 303 in the shape of a strip or a ring with a smaller width into the shallow trench isolation structure 302, thereby solving the problem of too low local active region density. Moreover, through tests, the first dummy active region 303 in the shape of a strip or a ring can more effectively avoid gate breakdown than the square block-shaped dummy active region.

[0037] Exemplarily, the length of the first dummy active region 303 is not less than twice the width of the first dummy active region 303. The length of the first dummy active region 303 refers to the long side dimension of the first dummy active region 303. The first dummy active region pattern in the embodiment of the present application is obtained by merging a plurality of square block-shaped dummy active region patterns, and therefore the length of the first dummy active region 303 is not less than twice the width thereof.

[0038] In one embodiment, the width of the first dummy active region 303 is 0.2-0.5 um. Exemplarily, the width of the second dummy active region 401 is 1-4 um, i.e., the width of the second dummy active region 401 is greater than the width of the first dummy active region 303. In the top view, the first dummy active region 303 is in the shape of an elongated strip, and the second dummy active region 401 is in the shape of a larger square block.

[0039] In one embodiment, the minimum distance between the first dummy active region 303 and the active region 301 is 0.5-1um. That is, the distance between the side of the first dummy active region 303 close to the active region 301 and the side of the active region 301 close to the first dummy active region 303 is 0.5-1um. In this way, the first dummy active region 303 can be prevented from being connected to the active region pattern in the process of generating the pattern of the first dummy active region 303.

[0040] Further, the minimum distance between the first dummy active region 303 and the gate structure 304 is 0.5-1um. That is, the distance between the side of the first dummy active region 304 close to the end of the gate structure 304 and the end of the gate structure 304 is 0.5-1um. In this way, the first dummy active region 303 can be prevented from being connected to the gate structure pattern in the process of generating the pattern of the first dummy active region 303.

[0041] In one embodiment, the maximum distance between the first dummy active region 303 and the active region 301 is 3-10um. That is, the distance between the side of the first dummy active region 303 away from the active region 301 and the side of the active region 301 away from the first dummy active region 303 is 3-10um. In this way, a large blank area can be prevented from existing between the first dummy active region 303 and the active region 301.

[0042] In one embodiment, the distance between the first dummy active region 303 and the second dummy active region 401 is not less than 1um, so that the first dummy active region 303 can be prevented from being connected to the pattern of the second dummy active region 401 in the process of generating the pattern of the first dummy active region 303.

[0043] Referring to Figure 4A and Figure 4B , the second dummy active region 401 is located at the edge of the chip and is arranged in an array of square structures, and the first dummy active region 303 is close to the active region and is arranged in an elongated strip structure. The embodiment of the present application inserts the elongated first dummy active region 303 in a position where the conventional second dummy active region 401 is not allowed to be inserted, thereby increasing the active region density at this position.

[0044] Figure 5 A computer-aided design (TCAD) simulation diagram of the semiconductor device of the embodiment of the present application is shown. By comparison with Figure 2 It can be seen that the semiconductor device of the embodiment of the present application can reduce the probability of the gate dielectric layer being prematurely broken down at the corner of the active region.

[0045] Figure 6 A comparison diagram of the gate leakage state before and after the first dummy active region of the embodiment of the present application is added is shown. Specifically, Figure 6The gate leakage test figures of several different original chip layouts are shown, and the gate leakage test figures of the original chip layouts after adding the first dummy active region. It can be seen that the gate leakage of the array edge device and the ISO device is greatly improved, and the originally representative bright spot of the gate leakage disappears by using the GIB VC method to detect the gate leakage.

[0046] In summary, according to the semiconductor device provided by the embodiment of the present application, the strip-shaped first dummy active region is arranged in the shallow trench isolation structure close to the active region, so that the active region density can be increased, and the gate leakage of the active region corner can be avoided.

[0047] In another embodiment of the present application, an electronic device is also provided, which comprises the semiconductor device described above, and the semiconductor device can be prepared according to the method described above.

[0048] The electronic device of the embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present application has better performance because the semiconductor device described above is used.

[0049] The embodiment of the present application also provides a layout optimization method, as shown in the figure, the method comprises the following steps: Figure 7 In step S710, an original layout is obtained, the original layout comprises an active region pattern, a second dummy active region pattern and a shallow trench isolation pattern for defining the active region pattern; In step S720, a plurality of square third dummy active region patterns are inserted into the shallow trench isolation pattern, the distance between adjacent third dummy active region patterns is not greater than the width of the third dummy active region pattern, and the width of the third dummy active region pattern is smaller than the width of the second dummy active region pattern; In step S730, the width of the plurality of third dummy active region patterns is expanded to combine adjacent third dummy active region patterns, so as to form a strip-shaped or ring-shaped fourth dummy active region pattern; In step S740, the width of the fourth dummy active region pattern is reduced to be equal to the width of the third dummy active region pattern, so as to obtain a strip-shaped or ring-shaped first dummy active region pattern, and the width of the first dummy active region pattern is smaller than the width of the second dummy active region pattern.

[0050] ​Exemplarily, the third dummy active region pattern is a square with a width of 0.2-0.5 um. The third dummy active region patterns are arranged along the extension direction of the shallow trench isolation structure with a spacing of no more than the width of the third dummy active region pattern, i.e., the spacing is 0.2-0.5 um. In a preferred embodiment, the spacing of the third dummy active region patterns is equal to the width of the third dummy active region pattern.

[0051] In an embodiment, the third dummy active region pattern can be inserted based on the following constraints: the minimum distance between the third dummy active region pattern and the active region pattern is 0.5-1 um; the minimum distance between the third dummy active region pattern and the end of the gate structure pattern is 0.5-1 um; the maximum distance between the third dummy active region pattern and the active region pattern is 3-10 um; and the distance between the third dummy active region pattern and the second dummy active region pattern is no less than 1 um.

[0052] Next, the third dummy active region pattern is logically processed. Specifically, first, the width of the third dummy active region pattern is expanded so that adjacent third dummy active region patterns are merged to form a fourth dummy active region pattern in the shape of a strip or a ring. Exemplarily, the width of the third dummy active region pattern can be expanded to 2 times the original width, and the expanded width is consistent with the spacing of the third dummy active region patterns, and the expanded width is less than the distance between the third dummy active region pattern and the active region pattern, the gate structure pattern, or the second dummy active region pattern.

[0053] Next, the width of the fourth dummy active region pattern is reduced to be equal to the width of the third dummy active region pattern to obtain a first dummy active region pattern in the shape of a strip or a ring, thereby forming an elongated first dummy active region pattern with a width of 0.2-0.5 um.

[0054] Exemplarily, after the first dummy active region pattern is formed, the first dummy active region pattern is logically processed again, and the size of the first dummy active region pattern is first reduced and then expanded, the reduced size is 0.2-0.5 um, which is consistent with the width of the first dummy active region pattern, and the first dummy active region pattern with a width less than the above size is removed in the reduction process, and the first dummy active region pattern that is not removed is restored to the width in the expansion process, wherein the expanded size is consistent with the reduced size. Thus, the first dummy active region pattern that is too elongated can be removed to prevent peeling or delamination.

[0055] The layout optimization method of the embodiment of the present application can generate a first dummy active region pattern in the shape of a strip or a ring, and the semiconductor device generated based on the layout has the advantages described above.

[0056] The present application has been described by way of the above examples, but it should be understood that the above examples are for illustrative and explanatory purposes only, and are not intended to limit the present application to the scope of the described examples. Furthermore, those skilled in the art can understand that the present application is not limited to the above examples, and that various modifications and changes can be made to the present application according to the teachings of the present application, and that these modifications and changes all fall within the scope of the present application claimed. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; An active region is formed in the semiconductor substrate, and a gate structure is formed above the active region; A shallow trench isolation structure formed in the semiconductor substrate, the shallow trench isolation structure being used to define the active region; A first pseudo-active region is formed in the shallow trench isolation structure, and the first pseudo-active region is a strip-shaped or ring-shaped structure when viewed from a top angle; A second pseudo-active region is formed outside the first pseudo-active region, and the width of the first pseudo-active region is smaller than the width of the second pseudo-active region.

2. The semiconductor device as claimed in claim 1, characterized in that, The length of the first pseudo-active region is not less than twice the width of the first pseudo-active region.

3. The semiconductor device as described in claim 1, characterized in that, The width of the first pseudo-active region is 0.2um-0.5um.

4. The semiconductor device as claimed in claim 1, characterized in that, The minimum distance between the first pseudo-active region and the active region is 0.5um-1um.

5. The semiconductor device as claimed in claim 1, characterized in that, The minimum distance between the first pseudo-active region and the end of the gate structure is 0.5um-1um.

6. The semiconductor device as claimed in claim 1, characterized in that, The maximum distance between the first pseudo-active region and the active region is 3µm-10µm.

7. The semiconductor device as claimed in claim 1, characterized in that, The second pseudo-active region has a square structure when viewed from above.

8. The semiconductor device as claimed in claim 7, characterized in that, The distance between the first pseudo-active region and the second pseudo-active region is not less than 1 μm.

9. A layout optimization method, characterized in that, The method includes: Obtain the original layout, which includes an active region graphic, a second pseudo-active region graphic, and a shallow trench isolation graphic used to define the active region graphic; Multiple square third pseudo-active region patterns are inserted into the shallow trench isolation pattern. The spacing between adjacent third pseudo-active region patterns is no greater than the width of the third pseudo-active region pattern, and the width of the third pseudo-active region pattern is less than the width of the second pseudo-active region pattern. The width of the plurality of third pseudo-active region patterns is increased so that adjacent third pseudo-active region patterns are merged to form a strip or ring-shaped fourth pseudo-active region pattern. The width of the fourth pseudo-active region pattern is reduced to be equal to the width of the third pseudo-active region pattern to obtain a strip-shaped or ring-shaped first pseudo-active region pattern, wherein the width of the first pseudo-active region is smaller than the width of the second pseudo-active region.

10. The method as described in claim 9, characterized in that, After obtaining the first pseudo-active region pattern, the process also includes: Reduce the width of the first pseudo-active region pattern to eliminate the first pseudo-active region pattern whose width is less than a preset width; Increase the width of the remaining first pseudo-active region pattern.

Images