Magnetic memory element and manufacturing method thereof

Abstract

The invention discloses a magnetic memory device and a manufacturing method thereof, the magnetic memory device includes a memory cell structure including a bottom electrode, a magnetic tunnel junction stack on the bottom electrode, and a top electrode on the magnetic tunnel junction stack, and an upper portion of the top electrode includes an arcuate recess. An interconnect structure is disposed on the top electrode and fills the arcuate recess.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular, to a magnetic memory element and a method of fabricating the same. BACKGROUND

[0002] Magnetoresistive random access memory (MRAM) has been a new type of memory that has received much attention in recent years. MRAM integrates the advantages of various types of memory, such as access speed comparable to static random access memory (SRAM), non-volatility and low power consumption comparable to flash memory, high density and durability comparable to dynamic random access memory (DRAM), and can be integrated with current semiconductor back-end manufacturing processes, thus having the potential to become the main memory used in semiconductor chips.

[0003] MRAM includes a memory cell structure disposed between upper and lower interconnect structures, which includes a magnetic tunneling junction (MTJ). Unlike conventional memory that stores data by storing electric charges, MRAM operates by applying an external magnetic field to the MTJ to control the magnetization direction of the MTJ to obtain different tunneling magnetoresistive (TMR) to store digital data, such as a high resistance state representing a data value of 1 and a low resistance state representing a data value of 0. The difference between the high resistance state resistance value and the low resistance state resistance value and the ratio of the low resistance state resistance value is the TMR ratio. A higher TMR ratio can provide a larger read margin, improving the data read speed and reliability of the element. SUMMARY

[0004] The present application aims to provide a magnetic memory element and a method of fabricating the same, which can ensure that there is sufficient contact area and stable contact resistance between the top electrode of the memory cell structure and the interconnect structure, thereby achieving a more stable TMR and a higher TMR ratio, and improving the performance of the element.

[0005] One embodiment of the present application discloses a method for fabricating a magnetic memory element. A storage cell structure is formed on a substrate. The storage cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A dielectric layer is formed covering the substrate and the storage cell structure. A trench is formed in the dielectric layer, exposing an upper portion of the top electrode. An etch fabrication process is performed on the top electrode to form an arc-shaped recess in the upper portion of the top electrode, wherein the arc-shaped recess is lower than a bottom surface of the trench. A conductive material is formed to fill the trench and the arc-shaped recess.

[0006] Another embodiment of the present application discloses a magnetic memory element. A storage cell structure is formed on a substrate. The storage cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack, wherein an upper portion of the top electrode includes an arc-shaped recess. A wiring structure is formed on the top electrode and fills the arc-shaped recess. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 5 A schematic diagram of the steps of a method for fabricating a magnetic memory element according to one embodiment of the present application.

[0008] LEGEND

[0009] 10: substrate

[0010] 12: dielectric layer

[0011] 14: wiring structure

[0012] 16: dielectric layer

[0013] 18: wiring structure

[0014] 22: bottom electrode

[0015] 23: spin-orbit torque (SOT) layer

[0016] 24: magnetic tunnel junction (MTJ) stack

[0017] 26: cap layer

[0018] 28: top electrode

[0019] 32: spacer structure

[0020] 42: dielectric layer

[0021] 44: trench

[0022] 46: arc-shaped recess

[0023] 50: conductive material

[0024] 52: interconnect structure

[0025] 24a: free layer

[0026] 24b: tunnel barrier layer

[0027] 24c: fixed layer

[0028] 28a: lower portion

[0029] 28b: upper portion

[0030] 32a: first gap layer

[0031] 32b: second gap layer

[0032] 32c: top surface

[0033] 44a: bottom surface

[0034] 52a: contact bump

[0035] E1: etching fabrication process

[0036] E2: etching fabrication process

[0037] P1: contact

[0038] S1: straight sidewall

[0039] S2: tapered sidewall

[0040] W1: width

[0041] W2: width DETAILED DESCRIPTION

[0042] So that the general person skilled in the art familiar with the technical field of the present application can further understand the present application, the preferred embodiments of the present application are listed below, and the constitution content and the desired effect of the present application are described in detail with the help of the accompanying drawings.

[0043] The drawings of the present application are schematic drawings and are not drawn to scale, and the size of some components may be enlarged for clarity. If there are some common or similar features in the drawings, in order to facilitate drawing and description, similar features will usually be indicated by the same reference numerals. The spatially related descriptive words mentioned in the text, such as "under", "low", "below", "above", "on", "top", "bottom", and the like, and similar words, are understood by those skilled in the art as describing the relative position of one component or feature to another (or multiple) component or feature, and still comply with the spatially related description in the text when turned over at any angle (such as rotated by 90 degrees or other orientation).

[0044] In this specification, a "substrate" means any structure having a surface on which materials are deposited to form integrated circuit structures as taught by embodiments of the application. A "substrate" also means a semiconductor structure including materials deposited thereon in a fabrication process. When an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. The terms "comprises", "comprising", "includes", "including" and "contains", "containing" are open-ended terms that are used to describe the presence of a feature, object, element, or component, but do not exclude the presence of other features, objects, elements, or components. The terms "comprises", "comprising", "includes", "including", and "contains", "containing" are open-ended terms that are used to describe the presence of a feature, object, element, or component, but do not exclude the presence of other features, objects, elements, or components. The terms "a" or "an", or the terms "one or more", when used in the context of a feature, object, element, or component, means that a single or more of that feature, object, element, or component can be present. The terms "a" or "an", or the terms "one or more", when used in the context of a feature, object, element, or component, means that a single or more of that feature, object, element, or component can be present. Any two numerical values or directions can be approximated to within 20%, or within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of the stated values or directions.

[0045] Referring to Figures 1 to 5 , a schematic diagram of steps in a method of fabricating a magnetic memory element according to an embodiment of the application is shown. As shown in Figure 1 , a substrate 10 is provided, and at least one dielectric layer is formed on the substrate 10, and interconnect structures are disposed in the dielectric layer. Then, a plurality of memory cell structures MC are formed on the substrate 10, and spacer structures 32 are disposed on sidewalls of the memory cell structures MC.

[0046] The substrate 10 can be a silicon substrate, a silicon-on-insulator substrate, a Group III-V semiconductor substrate, or the like, but is not limited thereto. The substrate 10 can include fabricated semiconductor elements such as transistors, capacitors, resistors, inductors, or the like, which are not shown in the drawings for simplicity.

[0047] A dielectric layer 12 can be provided on the substrate 10, an interconnect structure 14 (e.g., a metal wire structure) formed in the dielectric layer 12, another dielectric layer 16 disposed on the dielectric layer 12, and an interconnect structure 18 (e.g., a contact plug) formed in the dielectric layer 16 and in direct contact with the interconnect structure 14. The dielectric layer 12 and the dielectric layer 16 can each include silicon oxide (SiO2) or a low-k dielectric material, where applicable low-k dielectric materials can include fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, a porous low-k dielectric material, or an organic polymer dielectric material, but are not limited thereto. The interconnect structure 14 and the interconnect structure 18 can each include a conductive metal material or a metal compound, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but are not limited thereto.

[0048] The memory cell structure MC is disposed on the dielectric layer 16, and the constituent film layers of the stack structure thereof can be adjusted according to the type of the magnetic memory element. In the present embodiment, the spin-orbit torques (SOT) type magnetic memory element is taken as an example, and the memory cell structure MC includes, in sequence from bottom to top, a bottom electrode 22 directly contacting the interconnect structure 18, a spin-orbit torques (SOT) layer 23 disposed on the bottom electrode 22, a magnetic tunnel junction stack 24 disposed on the SOT layer, a cap layer 26 disposed on the magnetic tunnel junction stack 24, and a top electrode 28 disposed on the cap layer 26. The materials of the bottom electrode 22 and the top electrode 28 can respectively include conductive metal materials or metal compounds, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof, but are not limited thereto. The SOT layer 23 can include heavy metal materials with strong spin-orbit effects, such as tantalum (Ta), tungsten (W), platinum (Pt), but is not limited thereto. The magnetic tunnel junction stack 24 mainly includes a free layer 24a, a fixed layer 24c, and a tunnel barrier layer 24b sandwiched between the free layer 24a and the fixed layer 24c. The free layer 24a and the fixed layer 24c respectively include ferromagnetic materials, such as iron (Fe), cobalt (Co), nickel (Ni), iron-nickel (FeNi), iron-cobalt (FeCo), cobalt-nickel (CoNi), iron-boron (FeB), iron-platinum (FePt), iron-palladium (FePd), cobalt-iron-boron (CoFeB), or combinations thereof, but are not limited thereto. The magnetization direction of the fixed layer 24c is pinned in a certain single direction by an adjacent anti-ferromagnetic reference layer (not shown in the figure), and the magnetization direction of the free layer 24a can be flipped by an external magnetic field to be parallel or anti-parallel to the magnetization direction of the fixed layer 24c. The tunnel barrier layer 24b contains insulating materials, such as magnesium oxide (MgO), aluminum oxide (AlO), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (TaO), molybdenum oxide (MoO), titanium oxide (TiO), tungsten oxide (WO), or combinations thereof, but is not limited thereto. The cap layer 26 can contain metals or metal oxides, such as aluminum (Al), magnesium (Mg), tantalum (Ta), ruthenium (Ru), magnesium oxide (MgO), aluminum oxide (AlO), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (TaO), molybdenum oxide (MoO), titanium oxide (TiO), tungsten oxide (WO), or combinations thereof, but is not limited thereto. The constituent film layers and the stacking order of the memory cell structure MC described above are only examples, and the present application is not limited thereto. Each of the constituent film layers can be a single material layer or a composite material layer with a thickness of about several angstroms to tens of nanometers (nm). to tens of nanometers (nm).

[0049] The spacer structure 32, which is disposed on the sidewalls of the memory cell structure MC, can include a single layer or multiple layers. In this embodiment, the spacer structure 32 includes a first spacer layer 32a disposed on the top surface of the bottom electrode 22 and covering the sidewalls of the SOT layer 23, the magnetic tunnel junction stack 24, the cap layer 26, and the top electrode 28, and a second spacer layer 32b disposed on the dielectric layer 16 and covering the sidewalls of the bottom electrode 22 and the first spacer layer 32a. The materials of the first spacer layer 32a and the second spacer layer 32b can include dielectric materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof, but are not limited thereto.

[0050] The fabrication steps of the memory cell structure MC include a sequential thin film deposition fabrication process to form the stack of materials of the memory cell structure MC on the dielectric layer 16, including a bottom electrode material layer, a SOT material layer, a magnetic tunnel junction material layer, a cap layer material layer, and a top electrode material layer in sequence from bottom to top, followed by an anneal process to promote good crystallization of the thin film of the magnetic tunnel junction to improve the quality of the junction and to determine the direction of magnetization. The anneal process can be at a temperature between about 350 °C and 450 °C for a time between about 30 minutes and 5 hours, but is not limited thereto. After the anneal process, an etch fabrication process is performed to remove excess portions of the stack of materials to pattern the stack of materials into the memory cell structure MC.

[0051] In some embodiments, the method of patterning the stack of layers includes multiple etching steps, and the step of forming the first spacer layer 32a of the spacer structure 32 is integrated between the etching steps. In some embodiments, the method of patterning the stack of layers includes using a patterned photoresist layer as an etching mask for a first etching step to remove part of the top electrode material layer until the surface of the capping layer material layer is exposed, resulting in the top electrode 28. Then, using the top electrode 28 as an etching mask for a second etching step to remove part of the capping layer material layer and the magnetic tunnel junction material layer until the surface of the SOT material layer is exposed, resulting in the capping layer 26 and the magnetic tunnel junction stack 24. Then, forming a first spacer material layer conformally covering the top surface and sidewalls of the top electrode 28, the sidewalls of the capping layer 26 and the magnetic tunnel junction stack 24, and the surface of the SOT material layer, followed by a third etching step to remove the first spacer material layer on the surface of the SOT material layer, resulting in the first spacer layer 32a covering the top surface and sidewalls of the top electrode 28, and the sidewalls of the capping layer 26 and the magnetic tunnel junction stack 24, and continuing to etch the SOT material layer and the bottom electrode material layer using the first spacer layer 32a as an etching mask until the surface of the dielectric layer 16 is exposed, resulting in the SOT layer 23 and the bottom electrode 22, completing the step of patterning the stack of layers to obtain the memory cell structure MC. In some embodiments, when the first spacer material layer on the top surface of the top electrode 28 is completely removed during the third etching step, the exposed top electrode 28 can also be used as a mask for etching during the etching of the SOT material layer and the bottom electrode material layer. After obtaining the memory cell structure MC and the first spacer layer 32a, then forming a second spacer material layer conformally covering the top surface and sidewalls of the memory cell structure MC and the surface of the dielectric layer 16, followed by a fourth etching step to remove the second spacer material layer on the surface of the dielectric layer 16, resulting in the second spacer layer 32b covering the sidewalls of the first spacer layer 32a, the SOT layer 23, and the bottom electrode 22. The first etching step, the second etching step, the third etching step, and the fourth etching step can each include reactive ion etching (RIE), ion beam etching (IBE), or a combination of the two, but are not limited thereto. In some embodiments, before forming the first spacer material layer, an oxidation fabrication process or a trimming etching fabrication process can be performed to oxidize or etch away the metal etching byproducts plated on the sidewalls of the magnetic tunnel junction stack 24 during the second etching step, avoiding the problem of metal etching byproducts conducting through the tunnel barrier layer 24b from the sidewalls to cause abnormal tunneling magnetoresistance. The first spacer layer 32a can protect the sidewalls of the magnetic tunnel junction stack 24 from damage and impurity diffusion contamination when etching the SOT material layer and the bottom electrode material layer.The above method of forming the memory cell structure MC and the spacer structure 32 in multiple etching steps is merely an example, and the present application is not limited thereto. In fact, the etching steps can be increased, omitted or combined according to the design of the memory cell structure MC and the method of forming the spacer structure 32.

[0052] It is noted that the top electrode 28 acts as an etching mask during the etching process, and thus is trimmed to have a bullet-shaped profile by the ion beam bombardment. As shown in Figure 1 the top electrode 28 can include a lower portion 28a having a straight sidewall S1 and an upper portion 28b having a tapered sidewall S2, wherein the tapered sidewall S2 is a curve having a varying included angle with the surface of the substrate 10. The upper end of the straight sidewall S1 and the lower end of the tapered sidewall S2 are connected at a junction P1. The thickness ratio of the lower portion 28a and the upper portion 28b can be adjusted by adjusting the etching fabrication process, such as adjusting the angle of the ion beam bombardment. In some embodiments, the lower portion 28a and the upper portion 28b each occupies about half of the height of the top electrode 28, i.e. the thickness ratio of the two portions is about 1:1. In other embodiments, the lower portion 28a can occupy more than half of the height of the top electrode 28.

[0053] Referring to Figure 2 , a dielectric layer 42 is then formed to cover the substrate 10 and the memory cell structure MC entirely, and then chemical mechanical polishing (CMP) is performed to planarize the surface of the dielectric layer 42 and polish the dielectric layer 42 to a predetermined thickness. At this time, the top of the memory cell structure MC is still covered by the dielectric layer 42 and is not exposed. The material of the dielectric layer 42 can include a low-k dielectric material such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric material or organic polymer dielectric material, but is not limited thereto.

[0054] Referring to Figure 3 , an etching fabrication process E1 is then performed to remove part of the dielectric layer 42 to form a trench 44 directly above the memory cell structure MC. The depth of the bottom surface 44a of the trench 44 is preferably controlled to be slightly lower than the top surface of the memory cell structure MC, so that the etching fabrication process E1 does not over-etch and damage the top electrode 28, and at the same time, the spacer structure 32 on the top surface of the memory cell structure MC can be exposed from the trench 44, so that the exposed part of the spacer structure 32 can be removed by selective etching (such as wet etching) in the subsequent process, and the upper portion 28b of the top electrode 28 and the top surface 32c of the spacer structure 32 are simultaneously exposed from the bottom surface 44a of the trench 44.

[0055] Referring toFigure 4 Next, an etching process E2, such as a wet etching process with etching selectivity to the material of the top electrode 28, is performed to isotropically etch and remove part of the top electrode 28, thereby forming an arc-shaped recess 46 in the upper portion 28b of the top electrode 28. The etching process E2 includes the use of an amine-based solvent, but is not limited thereto. The size of the arc-shaped recess 46 is controlled by the etching process E2, and the edge of the arc-shaped recess 46 is adjacent to the first gap layer 32a. According to a preferred embodiment of the present application, the opening width W2 of the arc-shaped recess 46 is smaller than the width W1 of the lower portion 28a, and the depth of the arc-shaped recess 46 is not greater than the thickness of the upper portion 28b, i.e., the lowest point P2 is not lower than the lower end of the tapered sidewall S2 of the upper portion 28b (i.e., the position of the junction P1).

[0056] Referring to Figure 5 Next, a conductive material 50 is formed to completely cover the dielectric layer 42 and fill the trench 44 and the arc-shaped recess 46, and then chemical mechanical polishing (CMP) is performed to remove the conductive material 50 on the dielectric layer 42, thereby obtaining an integrally formed interconnect structure 52. The conductive material 50 can include a metal material or a metal compound, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but is not limited thereto. The bottom surface of the interconnect structure 52 is in direct contact with the top surface 32c of the gap wall structure 32, and the interconnect structure 52 fills part of the arc-shaped recess 46 to form a contact bump 52a, which is in direct contact with and electrically connected to the top electrode 28 of the memory cell structure MC.

[0057] In summary, the present application mainly discloses a method for manufacturing a magnetic memory element. After a trench for an upper interconnect structure is defined in a dielectric layer, an etching process is additionally performed to form an arc-shaped recess in the upper portion of a top electrode, thereby increasing the contact area between the interconnect structure 52 and the top electrode 28, reducing the contact resistance, achieving a more stable tunneling magnetoresistance and a higher tunneling magnetoresistance change rate, and improving the element performance.

[0058] The above description is only preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be covered by the scope of the present application.

Claims

1. A method for fabricating a magnetic memory element, comprising: forming a memory cell structure on a substrate, the memory cell structure comprising: a bottom electrode; a magnetic tunnel junction stack on the bottom electrode; and a top electrode on the magnetic tunnel junction stack; forming a dielectric layer covering the substrate and the memory cell structure; forming a trench in the dielectric layer exposing an upper portion of the top electrode; performing an etching fabrication process on the top electrode to form an arc-shaped recess in the upper portion of the top electrode, wherein the arc-shaped recess is lower than a bottom surface of the trench; and forming a conductive material filling the trench and the arc-shaped recess.

2. The method for fabricating a magnetic memory element of claim 1, wherein the top electrode has a bullet-shaped cross-sectional shape.

3. The method for fabricating a magnetic memory element of claim 1, wherein the top electrode comprises: a lower portion on the magnetic tunnel junction stack and comprising straight sidewalls; and the upper portion on the lower portion and comprising tapered sidewalls.

4. The method for fabricating a magnetic memory element of claim 3, wherein a width of the arc-shaped recess is less than a width of the lower portion.

5. The method for fabricating a magnetic memory element of claim 3, wherein a lowest point of the arc-shaped recess is not lower than a lower end of the tapered sidewalls of the upper portion.

6. The method for fabricating a magnetic memory element of claim 3, wherein a thickness of the lower portion and the upper portion is 1 :

1.

7. The method for fabricating a magnetic memory element of claim 1, wherein the etching fabrication process is a wet etching fabrication process.

8. The method for fabricating a magnetic memory element of claim 1, wherein the etching fabrication process comprises using an amine-based solvent.

9. The method for fabricating a magnetic memory element of claim 1, further comprising, before forming the dielectric layer: forming a spacer structure on sidewalls of the memory cell structure, wherein a top surface of the spacer structure is exposed from the trench.

10. The method for fabricating a magnetic memory element of claim 9, wherein edges of the arc-shaped recess abut on the spacer structure.

11. A magnetic memory element, comprising: a memory cell structure disposed on a substrate, the memory cell structure comprising: a bottom electrode; a magnetic tunnel junction stack on the bottom electrode; and a top electrode on the magnetic tunnel junction stack, wherein an upper portion of the top electrode comprises an arc-shaped recess; and an interconnect structure disposed on the top electrode and filling the arc-shaped recess.

12. The magnetic memory element of claim 11, wherein the top electrode comprises: a lower portion on the magnetic tunnel junction stack and comprising straight sidewalls; and the upper portion on the lower portion and comprising tapered sidewalls.

13. The magnetic memory element of claim 12, wherein a width of the arc-shaped recess is less than a width of the lower portion.

14. The magnetic memory element of claim 12, wherein a lowest point of the arc-shaped recess is not lower than a lower end of the tapered sidewalls of the upper portion.

15. The magnetic memory element of claim 12, wherein a thickness of the lower portion and the upper portion is 1 :

1. ​ ​ 16. The magnetic memory element of claim 11, further comprising: a spacer structure on sidewalls of the memory cell structure, wherein a top surface of the spacer structure is in direct contact with a bottom surface of the interconnect structure.

17. The magnetic memory element of claim 16, wherein edges of the arcuate recess abut the spacer structure.

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