Ferroelectric memristor array and sequential sequence processing method adopting same

Abstract

The invention relates to a ferroelectric memristor array and a sequential sequence processing method adopting the ferroelectric memristor array, and the ferroelectric memristor array comprises a bottom array gating structure which is used for providing unit-by-unit addressing and suppressing an undercurrent path of a non-gated unit in the array when the array scale is expanded; the adjustable conductive channel structure is used for generating a continuous photoconductive effect which can be accumulated and attenuated along with time under optical excitation; the in-plane polarization regulation and control structure modifies the conductive degree of the semiconductor channel by regulating and controlling the surface potential barrier of the channel so as to form a non-volatile weight state; and the multi-physical-quantity coupled electrode structure is used as a unified channel for weight regulation and control, conductivity reading and photoelectric response. Compared with the prior art, the semiconductor channel potential barrier is dynamically regulated and controlled through in-plane polarization of the ferroelectric film, non-volatile multi-stage conductance weight is achieved, synaptic-like photoresponse and short-time memory characteristics are obtained through the continuous photoconduction effect of a semiconductor material, and the continuous light input natural accumulation and attenuation process is achieved.

Description

Technical Field

[0001] This invention relates to the field of memristor technology, and in particular to a ferroelectric memristor array and a timing sequence processing method using a ferroelectric memristor array. Background Technology

[0002] As artificial intelligence systems rapidly evolve towards real-time perception, low-power computing, and edge autonomy, devices need to be able to continuously acquire signals from dynamic environments and make judgments or predictions on a millisecond scale. For example, in applications such as fall warning, complex traffic condition analysis, drone obstacle avoidance, and human-computer interaction, the system must extract temporal evolution features from multiple consecutive frames of input and make decisions in an extremely short time. However, traditional time-series analysis methods based on digital processors, GPUs, or DSPs rely on massive data transfer and multi-level caching operations. The round-trip transmission of multiple frames of video or sensor sequences brings significant latency and energy consumption, making it difficult to meet the requirements of real-time prediction tasks on the edge.

[0003] To overcome this bottleneck, neuromorphic hardware proposes mimicking the "sense-while-process" mechanism of biological visual systems at the physical structure level, significantly reducing data transfer overhead by integrating storage and computation into the device. Memristors, due to their combined conductivity storage and vector multiplication-accumulation (MAC) capabilities, are widely used to construct artificial synaptic arrays to accelerate neural network inference. However, existing memristor arrays are primarily designed for processing static images or fixed input vectors, lacking native support for continuous time-series signals. Furthermore, because traditional crossbar arrays lack effective gating structures, crosstalk currents generate additional current paths in unselected cells, making array scaling difficult and leading to biased computation results.

[0004] To mitigate crosstalk, memristor structures incorporating ferroelectric materials have emerged in recent years. For example, ferroelectric polarization is introduced into the gate region of a transistor, enabling the device to possess both the switching control capability of a transistor and the non-volatile weighting characteristics generated by ferroelectric conductance modulation. These "transistor-like ferroelectric memristors" demonstrate a unity of programmability and gating capability on a single device, making it possible to construct addressable large-scale arrays. However, current research largely focuses on the storage mechanisms, polarization switching behavior, or basic synaptic characteristics of individual devices, with limited attention paid to techniques for coordinating ferroelectric weighting, photosensitive behavior, and timing characteristic processing at the array scale.

[0005] In the field of dynamic vision processing, the requirements for hardware architecture are even more stringent. Tasks such as fall prediction, motion trajectory extrapolation, and gesture sequence recognition all rely on the temporal correlation of inputs across multiple frames. Traditional implementations typically acquire images through optical sensors, and then backend algorithms extract features frame by frame and construct complex architectures such as recurrent neural networks, temporal convolutional models, or Transformers. These methods require continuous access to memory and the execution of numerous matrix operations, resulting in high latency, high power consumption, and difficulty in real-time deployment on edge devices.

[0006] Therefore, there is an urgent need for a new hardware architecture that can immediately complete the accumulation and decay in the time dimension when the sensing input arrives, and realize efficient temporal feature extraction and forward prediction locally, thereby avoiding redundant data movement and significantly improving real-time performance. Summary of the Invention

[0007] The purpose of this invention is to overcome the defects of the prior art by providing a ferroelectric memristor array and a timing sequence processing method using the ferroelectric memristor array. By dynamically controlling the semiconductor channel barrier through the in-plane polarization of the ferroelectric thin film, non-volatile multi-level conductance weighting is achieved. Furthermore, the continuous photoconductivity effect of the semiconductor material is used to obtain synaptic-like photoresponse and short-time memory characteristics, thus realizing the natural accumulation and attenuation process of continuous light input.

[0008] The objective of this invention can be achieved through the following technical solutions: According to a first aspect of the present invention, a ferroelectric memristor array is provided, comprising: The bottom array gate structure includes a bottom gate and a dielectric layer disposed on the substrate, which are used to provide cell-by-cell addressing and suppress the undercurrent path of unselected cells in the array when the array scale is expanded; The adjustable conductive channel structure includes a semiconductor channel disposed on the dielectric layer, which is used to generate a continuous photoconductive effect that can accumulate and decay over time under photoexcitation, and is used for short-term memory of continuous input frames. An in-plane polarization control structure includes a ferroelectric thin film covering the semiconductor channel, the ferroelectric thin film having a switchable in-plane polarization direction, modifying the conductivity of the semiconductor channel by controlling the channel surface barrier to form a non-volatile weighted state; and The electrode structure, which is coupled with multiple physical quantities, includes source and drain electrodes that are electrically in contact with the semiconductor channel and the ferroelectric thin film, and serves as a unified channel for weighting, conductivity readout, and photoelectric response.

[0009] Preferably, each ferroelectric memristor unit includes a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor channel layer, source and drain electrodes, and a ferroelectric layer arranged sequentially; wherein the semiconductor channel layer is made of a semiconductor material with a continuous photoconductivity effect.

[0010] Preferably, the semiconductor material with continuous photoconductivity includes indium oxide semiconductor, gallium oxide semiconductor, III-V compound semiconductor and two-dimensional material system; the oxide semiconductor includes ZnO, In2O3, IGZO, SnO2 and TiO2; the III-V compound semiconductor includes GaN, AlGaN, GaAs and AlGaAs; the two-dimensional material system includes MoS2, WS2 and WSe2.

[0011] Preferably, a multi-layer insulating structure is provided between the substrate and the ferroelectric layer to enable array-level point-to-point addressing in conjunction with a gate-controlled interconnect network.

[0012] Preferably, the insulating layer in the array is prepared by electron beam evaporation deposition of an oxide of a set thickness, the oxide including silicon oxide, aluminum oxide and hafnium oxide.

[0013] According to a second aspect of the present invention, a timing sequence processing method employing the aforementioned ferroelectric memristor array is provided, comprising: The weight corresponding to each ferroelectric memristor unit is written into the ferroelectric memristor array using electrical pulses. The conductance of each memristor unit is adjusted by electrical pulse programming to complete the preset configuration of the array. The array employs a parallel computing structure, where signals in each row and column are converged by current and weighted according to the conductance value of each storage cell to generate the output signal of the corresponding column. By utilizing stored historical information and current input timing signals, forward prediction is achieved by outputting a prediction of the future signal state.

[0014] Preferably, when multiple frames of light intensity of dynamic visual signals are projected onto the array, the conductance of each ferroelectric memristor unit changes with the cumulative light stimulation of the most recent frames, performing short-term memory of the input timing signal and realizing the cumulative processing of multi-frame information.

[0015] Preferably, the memory time constant of the ferroelectric memristor array is adjusted by setting different ferroelectric materials and device sizes to adapt to different prediction time range requirements.

[0016] Preferably, after obtaining the output results of the array at each time step, the method further includes: classifying and identifying the output results at each time step, and predicting the signal state at the next time step based on the internal state evolution of the array; wherein, the internal state of the array includes the non-volatile polarization state of each memory cell in the ferroelectric memristor array and the current photoconductivity excitation level, and the changing trend of the time series signal can be inferred using the internal state, thereby generating a forward prediction result.

[0017] Preferably, the weights corresponding to each ferroelectric memristor unit are obtained through training with a time-related dataset.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention dynamically controls the semiconductor channel barrier by in-plane polarization of ferroelectric thin film to achieve non-volatile multi-level conductivity weights, and obtains synaptic photoresponse and short-time memory characteristics by utilizing the continuous photoconductivity effect of ultrathin semiconductor material, so that the array can naturally complete the accumulation and attenuation process for continuous light input, thereby realizing the timing signal processing at the device layer.

[0019] (2) This invention combines the non-volatile control of carrier channels by ferroelectric polarization with the continuous photoconductivity effect of oxide semiconductors, enabling the device to simultaneously possess stable electrical and optical storage characteristics. The ferroelectric layer provides programmable and retainable electrical weights, while the long-lived photogenerated carriers generated by the semiconductor layer after illumination bear the burden of accumulation over time. Therefore, the entire array can complete electrical weight storage, optical signal accumulation, and temporal feature extraction within the same pixel, laying a complete physical foundation for realizing high-order visual processing.

[0020] (3) In the traditional memristor array construction process, the upper and lower insulating layers usually rely on atomic layer deposition of thick oxide films and etching to form vias. Since indium oxide is highly sensitive to etching and is easily damaged, while the present invention needs to keep the photosensitive channel region exposed, conventional processes cannot be used. To solve this key bottleneck, the present invention uses electron beam evaporation to deposit oxide as a local insulating layer, which not only achieves reliable cross-layer insulation, but also avoids etching damage to the channel material, ensuring the large-area manufacturability and high yield of the array.

[0021] (4) Traditionally, images are acquired through optical sensors, and then back-end algorithms extract features frame by frame and construct complex architectures such as recurrent neural networks, temporal convolutional models, or Transformers. This requires continuous access to memory and execution of a large number of matrix operations, resulting in high latency, high power consumption, and difficulty in real-time deployment on edge devices. In contrast, this invention is based on the tunable photoresponsivity of the device and the ability to retain light information across time steps due to the continuous photoconductivity effect of semiconductor materials. The light signal is directly accumulated in the array pixels and coupled with the pre-written ferroelectric weights. Temporal information fusion, feature extraction, and result inference can be completed without external preprocessing or software neural networks, thereby realizing true hardware-level in-situ dynamic visual recognition and early prediction. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a ferroelectric memristor array structure. Figure 2 This is a schematic diagram of a self-supporting field-effect transistor-type ferroelectric memristor structure, corresponding to... Figure 1 The area within the dashed box; Figure 3 This is the architecture of its hardware-based image recognition prediction algorithm.

[0023] Figure 4 This is the current-voltage response curve of the photomemristor.

[0024] Figure 5 This represents the current change of an opto-memristor under positive and negative electrical pulse stimulation.

[0025] Figure 6 This is the programmable number of times the opto-memristor is in the on and off states.

[0026] Figure 7 This is to accumulate photoconductivity by controlling the number of light pulses after polarization in an opto-memristor.

[0027] Figure 8 This is the accumulation of photoconductivity in an opto-memristor after polarization, based on the modulation of the optical pulse width.

[0028] Figure 9 This is the accumulation of photoconductivity in an opto-memristor after polarization, regulated by the frequency of the optical pulse.

[0029] Figure 10 To adjust the photoconductive relaxation time of the indium oxide / DIPAB memristor under different gate voltage switching conditions.

[0030] Figure 11 Simulation of prediction and recognition of the handwritten digit 1.

[0031] Symbol markings: 1-Ferroelectric memristor unit; 2-Electrode layer; 3-Insulating layer; 101-Ferroelectric layer; 102-Source / drain electrode; 103-Semiconductor channel layer; 104-Gate dielectric layer; 105-Gate electrode layer; 106-Substrate. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] Example This embodiment provides a ferroelectric memristor array, including: The bottom array gate structure includes a bottom gate and a dielectric layer disposed on the substrate, which are used to provide cell-by-cell addressing and suppress the undercurrent path of unselected cells in the array when the array scale is expanded; The adjustable conductive channel structure includes a semiconductor channel disposed on the dielectric layer, which is used to generate a continuous photoconductive effect that can accumulate and decay over time under photoexcitation, and is used for short-term memory of continuous input frames. An in-plane polarization control structure includes a ferroelectric thin film covering the semiconductor channel, the ferroelectric thin film having a switchable in-plane polarization direction, and the conductivity of the semiconductor channel is modified by controlling the channel surface barrier to form a non-volatile weighted state. The multi-physical coupling electrode structure includes source and drain electrodes that are electrically contacted with a semiconductor channel and a ferroelectric thin film, serving as a unified channel for weight control, conductivity readout, and photoelectric response. The array achieves array-level addressing through bottom gate gating, programmable conductivity weights through in-plane ferroelectric polarization, and forms short-term states that evolve over time through the continuous photoconductivity effect of the semiconductor channel. The three work together to enable the array to perform hardware-level processing on dynamic visual input, including multi-frame fusion, temporal feature extraction, and forward prediction.

[0034] like Figure 1 As shown, the ferroelectric memristor array in this embodiment is divided into ferroelectric memristor unit 1, electrode layer 2 and insulating layer 3.

[0035] like Figure 2 As shown, each ferroelectric memristor unit 1 includes a substrate 106, a gate electrode layer 105, a gate dielectric layer 104, a semiconductor channel layer 103, a source / drain electrode 102, and a ferroelectric layer 101 arranged sequentially.

[0036] In this embodiment, the source / drain electrodes 102 are made of metals such as gold, nickel, platinum, titanium, silver, copper, aluminum, and tungsten, as well as non-metallic electrode materials such as indium tin oxide and heavily doped semiconductors. Furthermore, the source / drain electrodes 102 are composed of a nickel / gold bimetallic layer.

[0037] In this embodiment, the ferroelectric layer 101 can be an inorganic ferroelectric material, including lead titanate, lead zirconate titanate, barium titanate, lithium niobate, strontium niobate, hafnium oxide, aluminum nitride, bismuth iron oxide, zirconium titanium oxide, etc., and doped materials mainly composed of the above materials; the ferroelectric material can be a polymeric ferroelectric material, including polyvinylidene fluoride, polyvinylidene fluoride-trifluoroethylene copolymer, etc.; the ferroelectric material can be a molecular ferroelectric material, including ketone acid, MDABCO-based perovskite molecular ferroelectric material, diisopropylamine salt, 2,4- The ferroelectric material can be a two-dimensional ferroelectric material including copper indium phosphosulfur, tin telluride, indium α-tin, tungsten telluride, etc.; the ferroelectric material can be an organic-inorganic hybrid perovskite ferroelectric material including methylammonium lead iodide perovskite, methylammonium lead bromide perovskite, methylammonium iron(II) halide perovskite, dication perovskite structural materials, etc. Further, the ferroelectric layer 101 is selected from the organic ferroelectric material diisopropylammonium bromide (DIPAB).

[0038] In this embodiment, the gate dielectric layer 104 is made of the following materials: inorganic gate dielectrics, including silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium dioxide, magnesium oxide, zinc sulfide, silicon nitride, silicon fluoride, barium oxide, calcium fluoride, boric acid, etc.; and organic gate dielectrics, including PI, PS, PE, PTFE, Nylon, PMMA, PET, PES, PEN, PC, PDMS, silicone, polyaniline, polythiophene, etc. In this embodiment, the gate dielectric layer 104 is an aluminum oxide thin film.

[0039] In this embodiment, the semiconductor channel layer 103 is fabricated using semiconductor materials with continuous photoconductivity, including indium oxide semiconductor, gallium oxide semiconductor, III-V compound semiconductor and two-dimensional material system. The oxide semiconductors include ZnO, In2O3, IGZO, SnO2 and TiO2, the III-V compound semiconductors include GaN, AlGaN, GaAs and AlGaAs; and the two-dimensional material system includes MoS2, WS2 and WSe2.

[0040] In this embodiment, a multilayer insulating structure is provided between the substrate 106 and the ferroelectric layer 101 to enable array-level point-to-point addressing in conjunction with a gate-controlled interconnect network. The insulating layer in the array is prepared by electron beam evaporation deposition of oxides of a predetermined thickness, including silicon oxide, aluminum oxide, and hafnium oxide.

[0041] This embodiment constructs a multilayer insulating structure between the substrate 106 and the ferroelectric layer 101, and combines it with a gate-controlled interconnect network to achieve array-level point-by-point addressing, thus fabricating a ferroelectric memristor array with active gating capability. This array effectively suppresses crosstalk currents in traditional cross-arrays in its physical structure, enabling stable operation of large-scale programmable cells.

[0042] By dynamically controlling the semiconductor channel barrier through in-plane polarization of ferroelectric thin films, non-volatile multi-level conductivity weights are achieved. Furthermore, the continuous photoconductivity (PPC) effect of ultrathin semiconductor materials is utilized to obtain synaptic-like photoresponse and short-time memory characteristics, enabling the array to naturally complete the accumulation and attenuation process for continuous light input.

[0043] The fabrication process of the ferroelectric memristor array includes: firstly, forming a bottom gate and an insulating layer 3 for point-by-point control on a substrate 106; then depositing and patterning an ultrathin semiconductor channel on the insulating layer 3 to make each ferroelectric memristor unit 1 independent of each other; next, constructing the row and column lines of the array as interconnection structures; finally, covering the channel region with a ferroelectric thin film and fabricating source and drain electrodes, so that the ferroelectric layer 3 can be written with weights and maintain good electrical contact with the channel, thereby giving the array the characteristics of low crosstalk, addressability and suitability for large-area integration.

[0044] The patterning process for forming array row-column interconnects and source-drain contact regions employs micro-nano fabrication techniques compatible with ferroelectric layers and ultra-thin semiconductor channels. By constructing high-resolution electrode patterns within the array region, electrical isolation between cells and consistency of the large-area array are ensured.

[0045] Specifically, the detailed preparation process includes the following steps: (1) Select silicon oxide as substrate 106 and perform pretreatment: place it in acetone, isopropanol and deionized water respectively for weak ultrasonic cleaning (15 minutes each), then blow it dry with nitrogen and dry it completely on a hot plate.

[0046] (2) The gate pattern is defined by ultraviolet lithography, and then a 40 nm thick tungsten film is deposited by magnetron sputtering to form the gate electrode layer 105.

[0047] (3) An atomic layer deposition process is applied to the gate electrode region to deposit an aluminum oxide thin film of about 30 nm as the gate dielectric layer 104.

[0048] (4) Continue to use atomic layer deposition to deposit an indium oxide thin film of about 2.3 nm on the surface of the dielectric layer to form a semiconductor channel layer 103.

[0049] (5) The positions of the source and drain electrodes are defined by ultraviolet lithography, and a nickel / gold bilayer metal of about 50 nm is deposited by metal thermal evaporation to form the source and drain electrodes 102.

[0050] (6) Photolithographic patterning is performed in the area where insulation isolation is required, and an electron beam evaporation is used to deposit a silicon oxide thin film of about 100 nm to form a local insulation structure in the array, namely the insulation layer 3.

[0051] (7) Photolithography is performed again and chromium / gold metal (thickness of about 120 nm) is deposited by metal thermal evaporation to prepare the interconnect electrodes and addressing electrodes of the array, namely electrode layer 2.

[0052] (8) Dissolve DIPAB in methanol to prepare a solution with a concentration of 15 mg / ml. After preheating the substrate at 65°C for 5 minutes, coat the solution by scraping. After the film is formed, anneal at 80°C for about 1 hour to make the obtained ferroelectric film dense and obtain stable ferroelectric properties.

[0053] In this embodiment, the polarization degree of ferroelectricity is used to regulate the conductivity / photoconductivity state of the channel region, and the gate is used to achieve another dimension of regulation of the channel conductivity / photoconductivity state. This regulation includes, but is not limited to, control path and turn-off. The gate includes a top gate, a bottom gate, and a device that controls both the top and bottom gates, thereby realizing multi-state storage of conductivity / photoconductivity states, multi-dimensional regulation, and integrated sensing, storage, and computing.

[0054] The ferroelectric memristor array constructed in this embodiment has programmable weights, short-time memory capability, array-level gating mechanism, and natural sensitivity to optical input, so as to directly complete multi-frame fusion, temporal inference and prediction functions at the hardware level.

[0055] This embodiment also provides a timing sequence processing method using a ferroelectric memristor array, the method comprising: The weights corresponding to each ferroelectric memristor unit are written into the ferroelectric memristor array using electrical pulses. The conductance of each memristor unit is adjusted by electrical pulse programming to complete the preset configuration of the array. The weights corresponding to each ferroelectric memristor unit are obtained by training with a time-related dataset. The array employs a parallel computing structure, where signals in each row and column are converged by current and weighted according to the conductance value of each storage cell to generate the output signal of the corresponding column. By utilizing stored historical information and current input timing signals, forward prediction is achieved by outputting a prediction of the future signal state.

[0056] In this embodiment, when multiple frames of light intensity of dynamic visual signals are projected onto the array, the conductance of each ferroelectric memristor unit changes with the cumulative light stimulation of the most recent frames, performing short-term memory of the input timing signal and realizing the cumulative processing of multi-frame information.

[0057] After obtaining the output results of the array at each time step, the method further includes: classifying and identifying the output results at each time step, and predicting the signal state at the next time step based on the internal state evolution of the array; wherein, the internal state of the array includes the non-volatile polarization state of each memory cell in the ferroelectric memristor array and the current photoconductivity excitation level, and the changing trend of the time series signal can be inferred using the internal state, thereby generating forward prediction results.

[0058] By employing a ferroelectric memristor array, multi-frame fusion, feature extraction, and forward prediction of trajectories or behaviors can be performed directly at the device layer, thereby improving image recognition accuracy and significantly reducing latency and power consumption.

[0059] In this embodiment, the ferroelectric memristor array and time sequence processing method can be used for the recognition and prediction of dynamic scenes, including but not limited to fall prediction, traffic trajectory prediction, and human-computer interaction behavior recognition. In these scenarios, external signals are input into the system in the form of video sequences or continuous sensor data. The system obtains the recognition result of the target behavior or state through multi-frame cumulative calculation and outputs the prediction signal of the future state in advance.

[0060] In this embodiment, the memory time constant of the ferroelectric memristor array is adjusted by setting different ferroelectric materials and device sizes to adapt to different prediction time range requirements. When the target application requires prediction over a longer time span, the ferroelectric materials and device sizes can be appropriately adjusted to extend the duration of the continuous photoconductive effect, thereby expanding the range of hardware short-term memory to meet the timing analysis needs in different scenarios.

[0061] Figure 3 This demonstrates the complete timing processing flow of the output layer from photoelectric mode to electrical mode. The left side shows the photoelectric mode: external dynamic light signals act on the array over time, and each pixel generates a corresponding photocurrent under illumination. This photocurrent, along with its preset photoconductivity state, determines the time-series photoelectric response. These responses are continuously recorded in a time-series manner in the two-dimensional array, forming a photoelectric feature matrix that evolves over time. The latter half shows the electrical mode: the electrical inference stage where the timing signals obtained from the photoelectric mode are directly input into the array. In this stage, the time-current trajectories of each pixel are further integrated, and matrix operations are performed with the preset matrix to output the final result.

[0062] Electrical tests were performed on the indium oxide memristor array fabricated in this example. A forward and reverse scan was applied to the memristor with a voltage amplitude of 4V, and the measured current response is shown in the attached figure. Figure 4As shown in the figure, when the voltage is less than 2 V, which is less than the coercive voltage of ferroelectricity, the memristor is in a high-resistivity state with a small current. When the voltage is greater than 2 V, the memristor becomes a low-resistivity state with a larger current, demonstrating the modulating effect of ferroelectric polarization on the conductance of the thin-layer silicon channel. Furthermore, multi-level conductance modulation can be achieved through ±4 V voltage pulses, exhibiting synaptic-like long-term peak power enhancement (LTP) and long-term peak power rejection (LTD) characteristics, as shown in the attached figure. Figure 5 The device's durability exceeds 10. 6 The next cycle, as shown in the appendix. Figure 6 Furthermore, the device exhibits a significant photoresponse to 405 nm violet light under zero bias (self-driven mode), and the photocurrent direction is correlated with the ferroelectric polarization direction. This electro-optic coupling allows the device to function simultaneously as a storage unit and a photosensitive synapse. Under repetitive light pulse excitation, the device exhibits a transition from short-term memory (STM) to long-term memory (LTM); the number of pulses, pulse width, and frequency can all modulate the accumulation of photoconductivity, as shown in the attached figure. Figure 7 , Figure 8 and Figure 9 As shown in the attached figure. Simultaneously, the applied gate voltage can also adjust the photoconductive relaxation time, thereby further expanding its application in timing processing, as illustrated in the attached figure. Figure 10 Furthermore, based on this entire column, digit prediction and recognition can be performed, with additional information provided. Figure 11 The demonstration shows a simulation of predictive recognition of the handwritten digit 1.

[0063] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A ferroelectric memristor array, characterized in that, include: The bottom array gate structure includes a bottom gate and a dielectric layer disposed on the substrate, which are used to provide cell-by-cell addressing and suppress the undercurrent path of unselected cells in the array when the array scale is expanded; The adjustable conductive channel structure includes a semiconductor channel disposed on the dielectric layer, which is used to generate a continuous photoconductive effect that can accumulate and decay over time under photoexcitation, and is used for short-term memory of continuous input frames. An in-plane polarization control structure includes a ferroelectric thin film covering the semiconductor channel, the ferroelectric thin film having a switchable in-plane polarization direction, and the conductivity of the semiconductor channel is modified by controlling the channel surface barrier to form a non-volatile weighted state. as well as The electrode structure, which is coupled with multiple physical quantities, includes source and drain electrodes that are electrically in contact with the semiconductor channel and the ferroelectric thin film, and serves as a unified channel for weighting, conductivity readout, and photoelectric response.

2. The ferroelectric memristor array according to claim 1, characterized in that, Each ferroelectric memristor unit includes a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor channel layer, source and drain electrodes, and a ferroelectric layer arranged sequentially; wherein the semiconductor channel layer is fabricated using a semiconductor material with a continuous photoconductivity effect.

3. A ferroelectric memristor array according to claim 2, characterized in that, The semiconductor materials with continuous photoconductivity include indium oxide semiconductors, gallium oxide semiconductors, III-V compound semiconductors, and two-dimensional material systems; the oxide semiconductors include ZnO, In2O3, IGZO, SnO2, and TiO2; the III-V compound semiconductors include GaN, AlGaN, GaAs, and AlGaAs; and the two-dimensional material systems include MoS2, WS2, and WSe2.

4. A ferroelectric memristor array according to claim 2, characterized in that, A multi-layer insulating structure is provided between the substrate and the ferroelectric layer to enable array-level point-to-point addressing in conjunction with a gate-controlled interconnect network.

5. A ferroelectric memristor array according to claim 4, characterized in that, The insulating layer in the array is prepared by electron beam evaporation deposition of an oxide of a set thickness, the oxide including silicon oxide, aluminum oxide and hafnium oxide.

6. A timing sequence processing method using the ferroelectric memristor array as described in claim 1, characterized in that, include: The weight corresponding to each ferroelectric memristor unit is written into the ferroelectric memristor array using electrical pulses. The conductance of each memristor unit is adjusted by electrical pulse programming to complete the preset configuration of the array. The array employs a parallel computing structure, where signals in each row and column are converged by current and weighted according to the conductance value of each storage cell to generate the output signal of the corresponding column. By utilizing stored historical information and current input timing signals, forward prediction is achieved by outputting a prediction of the future signal state.

7. The method according to claim 6, characterized in that, When multiple frames of light intensity from dynamic visual signals are projected onto the array, the conductance of each ferroelectric memristor unit changes with the cumulative light stimulation of the most recent frames, thus performing short-term memory of the input timing signal and realizing the cumulative processing of multi-frame information.

8. The method according to claim 6, characterized in that, The memory time constant of the ferroelectric memristor array can be adjusted by setting different ferroelectric materials and device sizes to adapt to different prediction time range requirements.

9. The method according to claim 6, characterized in that, After obtaining the output results of the array at each time step, the method further includes: classifying and identifying the output results at each time step, and predicting the signal state at the next time step based on the internal state evolution of the array; wherein, the internal state of the array includes the non-volatile polarization state of each memory cell in the ferroelectric memristor array and the current photoconductivity excitation level, and the changing trend of the time series signal can be inferred using the internal state, thereby generating forward prediction results.

10. The method according to claim 6, characterized in that, The weights corresponding to each ferroelectric memristor unit are obtained through training on a time-related dataset.

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