Method for improving wafer warping degree and furnace tube process
By forming a polycrystalline silicon layer and an insulating layer on the back of the wafer, and using different oxidation rates to generate stress differences, the problem of warpage variation in furnace tube processes is solved, thereby increasing the number of wafer cycles and wafer fabrication efficiency.
Patent Information
- Application Number
- CN202511719800.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-02-13
AI Technical Summary
In furnace tube processes, the warpage of the filler wafer changes due to repeated high-temperature treatments, affecting product yield and wafer fabrication efficiency. Existing technologies struggle to effectively control wafer warpage.
A polysilicon layer is formed on the back side of the wafer, and an insulating layer is formed on its surface. Different tensile stresses are generated by the different oxidation rates of the polysilicon layer and the insulating layer to adjust the warpage of the wafer.
By adjusting the warpage, the number of wafers that can be recycled is increased, manufacturing costs are reduced, and wafer fabrication efficiency is improved.
Smart Images
Figure CN121531941A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving wafer warpage and a furnace tube process. Background Technology
[0002] With the continuous development of semiconductor technology, the wafer fabrication process has become increasingly complex. The warpage of wafers, influenced by thermal and mechanical stresses, often exhibits and accumulates uncontrollable changes. When the warpage exceeds the process threshold, the risk of mechanical scratches on the equipment increases, preventing further wafer fabrication and resulting in direct economic losses while also impacting the efficiency of the FAB (Fabrication Equipment) plant. Therefore, it is necessary to control the wafer warpage in a timely manner during the fabrication process.
[0003] In furnace tube process technology, filler wafers are essential wafers placed above and below the product wafers within a wafer boat. Their function is to create a stable and balanced temperature atmosphere and to block falling particles, thus protecting the product. In furnace tube process modules, filler wafers are typically used multiple times, each cycle requiring multiple thermal treatments, followed by cleaning to remove the surface thin layer before entering the next cycle. These repeated high-temperature treatments inevitably cause changes in the warpage of the filler wafers, leading to reduced product yield or even product scrap. Summary of the Invention
[0004] The purpose of this invention is to provide a method and furnace tube process for improving wafer warpage, so as to adjust the warpage of the target wafer, increase the number of cycles of the target wafer, and reduce manufacturing costs.
[0005] To achieve the above objectives, one embodiment of the present invention provides a method for improving wafer warpage, comprising:
[0006] A target wafer is provided, including a first side and a second side arranged opposite to each other;
[0007] A polycrystalline silicon layer is formed and conformally covers the second surface;
[0008] An insulating layer is formed on the first surface and the polysilicon layer, the insulating layer comprising:
[0009] The second upper part is in direct contact with the target wafer.
[0010] The second lower half is disposed opposite to the second upper half and in direct contact with the polysilicon layer. The tensile stress of the second lower half on the target wafer is different from that of the second upper half on the target wafer.
[0011] Optionally, the first surface includes an arcuate profile that extends in a vertical direction toward the second surface.
[0012] Optionally, the step of forming the polycrystalline silicon layer includes:
[0013] A polycrystalline silicon material layer is formed on both the first and second surfaces of the target wafer;
[0014] Remove the polycrystalline silicon material layer on the first surface and retain the polycrystalline silicon material layer on the second surface.
[0015] Optionally, the deposition thickness of the polycrystalline silicon layer gradually increases with the gradual increase of the temperature of the subsequent heat treatment process to be performed.
[0016] Optionally, the temperature range of the subsequent thermal processing of the target wafer is 1000℃~1200℃, and the deposition thickness of the polycrystalline silicon layer is 600 angstroms~2000 angstroms.
[0017] Optionally, the insulating layer is a single-layer structure or a composite structure. The single-layer structure includes an oxide layer, and the composite structure includes an oxide layer and a nitride layer from bottom to top. The oxide layer is in direct contact with the first surface.
[0018] Optionally, the step of forming the insulating layer includes:
[0019] The thickness of the insulating layer is determined based on the temperature of the subsequent heat treatment process to be performed on the target wafer;
[0020] The target wafer is subjected to an oxidation process to oxidize a portion of the surface layer of the first side into the second upper half of the insulating layer, and to oxidize a portion of the surface layer of the polysilicon layer into the second lower half of the insulating layer.
[0021] Optionally, in the vertical direction, the thickness of the second lower half is N times the thickness of the second upper half, and N≥2.
[0022] Optionally, the oxide thickness of the insulating layer gradually increases with the gradual increase of the temperature of the subsequent heat treatment process.
[0023] Optionally, the oxidation process temperature gradually decreases as the temperature of the subsequent heat treatment process to be performed on the target wafer increases.
[0024] Optionally, the target wafer is a monitoring wafer or a filler wafer used in a furnace tube high-temperature process.
[0025] To achieve the above objectives, another embodiment of the present invention provides a furnace tube process, comprising:
[0026] A furnace tube is provided, and a target wafer is placed inside the crystal boat of the furnace tube;
[0027] A high-temperature process is performed on the target wafer, and the surface of the target wafer is cleaned and removed.
[0028] Determine whether the number of cycles of the high-temperature process performed on the target wafer has reached a first cycle threshold; if yes, perform the method described above for improving wafer warpage on the target wafer to adjust the warpage of the target wafer; if no, return to the step of performing the high-temperature process on the target wafer.
[0029] Optionally, after returning to the step of performing a high-temperature process on the target wafer, the method further includes:
[0030] Determine whether the number of cycles of the high-temperature process to be performed on the target wafer after the first cycle threshold has been reached has reached the second cycle threshold; if not, return to the step of performing the high-temperature process on the target wafer; if yes, determine that the target wafer is scrapped and remove it from the furnace tube.
[0031] Optionally, the second cycle threshold is M times the first cycle threshold, where M ≥ 1.5.
[0032] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:
[0033] In this invention, the target wafer includes a front side (first side) and a back side (second side) disposed opposite to each other. A polysilicon layer is first formed on the back side, and then an insulating layer is formed on the surface layer and the polysilicon layer of the first side. Since the oxidation rates of the polysilicon layer and the insulating layer are different, they can generate different tensile stresses on the first and second sides of the target wafer, thereby reducing the warping of the target wafer. Based on parameters such as the direction of warping, the warping of the target wafer can be adjusted (improved) by adjusting the process technology and process parameters for forming the polysilicon layer and the insulating layer, thereby reducing the manufacturing cost of semiconductor devices / products.
[0034] Secondly, when this invention is applied to furnace tube processes, a first cycle threshold can be set for the target wafer used as a monitoring wafer or filler wafer. Then, multiple high-temperature processes are performed on it. After the number of cycles of the target wafer reaches the first cycle threshold, the wafer warpage improvement method described above can be performed at least once. Then, the wafer is recycled until it reaches the second cycle threshold before it is determined to be scrapped. Since the wafer warpage improvement method of this invention can effectively adjust the warpage of the target wafer, it will not be scrapped when the target wafer reaches the first cycle threshold, thus increasing the number of cycles of the target wafer. Attached Figure Description
[0035] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0036] In the attached diagram:
[0037] Figure 1 This is an example diagram of a structure of a target wafer after warping, according to one embodiment of the present invention.
[0038] Figure 2 This is a flowchart illustrating a method for improving wafer warpage according to an embodiment of the present invention.
[0039] Figure 3 This is a graph comparing the number of cycles, warpage, and existing technology of a target wafer treated with the wafer warpage improvement method in one embodiment of the present invention in furnace tube processes.
[0040] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0041] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0042] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.
[0043] Furthermore, for ease of description, regional relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, regional relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the regional relative descriptive terms used herein may be interpreted accordingly.
[0044] In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.
[0045] As described in the background technology introduction, in current furnace tube process technology, filler wafers are essential wafers placed above and below the product wafer in a wafer boat. Their function is to create a stable and balanced temperature atmosphere field and to block falling particles, thus protecting the product. In furnace tube process modules, filler wafers are typically used more than fifteen times, with each cycle requiring approximately twenty thermal treatments. Afterward, they undergo cleaning to remove the surface thin layer before entering the next cycle. Repeated thermal processes can cause changes in the wafer warpage, typically manifesting as a central depression and edge warping, such as... Figure 1 As shown. Among them, in Figure 1 In the diagram, 100 is the reference numeral for the wafer, 100a is the reference numeral for the first side (front) of the wafer, and 100b is the reference numeral for the second side (back) of the wafer.
[0046] To address the aforementioned problems, this invention provides a method and furnace tube process for improving wafer warpage. Specifically, a polysilicon layer of controllable thickness is formed on the back side (second side, e.g., convex side) of the warped target wafer. Then, the target wafer undergoes high-temperature oxidation to convert at least a portion of the polysilicon on the surface silicon of the front side (first side, e.g., concave side) and the polysilicon layer on the back side into silicon dioxide. By utilizing the fact that the oxidation rate of the monocrystalline silicon exposed on the first side of the target wafer is lower than the oxidation rate of the polysilicon covering the second side, a stress difference is created simultaneously with the formation of an insulating layer, thereby improving warpage and increasing the number of cycles (referred to as cycle count) of the target wafer.
[0047] The following sections will provide a detailed description of the method for improving wafer warpage and the furnace tube process provided in the embodiments of the present invention.
[0048] Please see Figure 2, Figure 2 This is a flowchart illustrating a method for improving wafer warpage according to an embodiment of the present invention. Figure 2 As shown, the method for improving wafer warpage may include at least the following steps:
[0049] Step S101: Provide a target wafer, including a first side and a second side arranged opposite to each other.
[0050] Step S102: A polycrystalline silicon layer is formed and conformally covered on the second surface.
[0051] Step S103: Form an insulating layer located on the first surface and the polysilicon layer. The insulating layer includes a second upper half and a second lower half. The second upper half is in direct contact with the target wafer. The second lower half is disposed opposite to the second upper half and in direct contact with the polysilicon layer. The tensile stress of the second lower half on the target wafer is different from the tensile stress of the second upper half on the target wafer.
[0052] In step S101 above: a target wafer can be provided first, wherein the target wafer serves as a monitoring wafer or filler wafer located within the wafer boat in subsequent furnace tube processes to protect the wafers located within the wafer boat used for device formation. In one embodiment, the material of the target wafer can be any suitable substrate material well known to those skilled in the art, such as single-crystal silicon, but is not limited thereto. For example, the front side of the target wafer is referred to as the first side, and the back side of the target wafer is referred to as the second side, and the warped target wafer as a whole can appear as follows: Figure 1 As shown in the bowl shape, the surface profile of the first side of the target wafer can be an arc-shaped profile extending along a vertical direction (perpendicular to the first or second side of the target wafer) toward the second side of the target wafer (e.g., Figure 1 The target wafer shown is not limited to this; that is, the target wafer in the embodiments of the present invention may also have a contour structure after being subjected to different stresses, resulting in other warping shapes.
[0053] In step S102 above: the required thickness of the polysilicon layer can be determined first based on the temperature of the subsequent heat treatment process to be performed on the target wafer; then, using at least one of the deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition, a polysilicon material layer with controllable thickness and conformal coverage is formed on both the first and second surfaces of the target wafer; then, using at least one of the etching processes such as dry etching or wet etching, the polysilicon material layer on the first surface of the target wafer is removed, that is, only the polysilicon material layer on the second surface of the target wafer is retained (forming a polysilicon layer), that is, a polysilicon layer is formed on the surface of the target wafer where there is a protruding contour. In one embodiment, the material of the polysilicon layer may also be other conductive materials containing polysilicon, such as a mixture of doped or undoped polysilicon and monocrystalline silicon. This means that the material formed on the second surface of the target wafer has a faster oxidation rate than the material on the first surface of the target wafer (or, as can be understood, the material on the second surface of the target wafer experiences greater stress than the material on the first surface of the target wafer during heat treatment). Furthermore, the specific thickness of the polysilicon layer may be related to the process temperature of the subsequent fabrication process performed on the target wafer. For example, the deposition thickness of the polysilicon layer gradually increases with the increasing temperature of the subsequent heat treatment process. In one embodiment, the subsequent process performed on the target wafer may be, for example, a high-temperature oxidation process. When the process temperature of the high-temperature oxidation process is below 1000°C, the thickness of the polysilicon layer formed on the second surface of the target wafer in the vertical direction may be 600 angstroms. When the process temperature of the high-temperature oxidation process is between 1000°C and 1100°C, the thickness of the polysilicon layer formed on the second surface of the target wafer in the vertical direction may be 1000 angstroms. When the process temperature of the high-temperature oxidation process is above 1100°C, the thickness of the polysilicon layer formed on the second surface of the target wafer in the vertical direction may be 2000 angstroms.
[0054] It should be noted that in other embodiments, the deposition thickness of the polysilicon layer may also be related to the ambient temperature of the furnace tube and the process temperature of the multiple subsequent process processes to be performed on the wafer in the furnace tube. However, the relationship between the two is consistent with the relationship disclosed in the embodiments of the present invention, that is, both are within the protection scope of the present invention.
[0055] In step S103 above: based on the subsequent process temperature to be performed on the target wafer determined in step S102, the thickness of the insulating layer can be determined first; then, the target wafer (with a polysilicon layer formed on the second surface) is oxidized to convert a portion of the surface layer on the first surface of the target wafer into the second upper half of the insulating layer. This process involves high-temperature oxidation of the silicon substrate of the target wafer; simultaneously, a portion of the surface layer of the polysilicon layer on the second surface of the target wafer is oxidized to convert the second lower half of the insulating layer. This process involves high-temperature oxidation of the polysilicon layer. Thus, during the formation of the insulating layer in step S103, the first and second surfaces of the target wafer undergo high-temperature oxidation. Because the materials used in the oxidation process are different, the oxidation rates on the first and second surfaces of the target wafer are different. This difference in oxidation rate results in the insulation layer (e.g., silicon dioxide) formed on the second surface of the target wafer being thicker than the insulation layer formed on the first surface within the same time frame. The thicker insulation layer on the second surface undergoes rapid volume expansion during this oxidation process, generating stress within it that cannot be fully relaxed. This, in turn, generates higher stress on the second surface of the target wafer. Thus, different stresses, such as tensile stress, are generated on the first and second surfaces of the target wafer (i.e., there is a stress difference between the two surfaces of the target wafer). This stress difference is then used to improve the warpage of the target wafer.
[0056] In one embodiment, the insulating layer can be a single-layer structure comprising a single insulating material, such as a silicon dioxide layer, or a composite structure comprising multiple insulating materials, such as silicon dioxide and silicon nitride layers stacked sequentially from bottom to top, wherein the silicon dioxide in the composite structure can directly contact the first surface of the target wafer. Secondly, in the vertical direction, the thickness of the second lower half of the insulating layer (the portion located on the polysilicon layer) is N times the thickness of its second upper half (the portion located on the first surface of the target wafer), where N ≥ 2, and the specific value of N is related to the warpage of the target wafer; for example, the greater the warpage of the target wafer, the larger the value of N, i.e., the two are positively correlated. Furthermore, the oxide thickness of the insulating layer gradually increases with the increasing temperature of the subsequent heat treatment process to be performed; that is, the higher the temperature of the subsequent heat treatment process to be performed on the target wafer, the thicker the insulating layer (including the second upper half and the second lower half) in the vertical direction. In step S103, the process temperature for oxidizing the target wafer to form an insulating layer can gradually decrease as the temperature of the subsequent heat treatment process (e.g., high-temperature oxidation process) to be performed on the target wafer increases. That is, the higher the temperature of the subsequent heat treatment process to be performed on the target wafer, the lower the temperature of the oxidation process to form the insulating layer.
[0057] It should be noted that, in order to increase the density or porosity of the silicon dioxide insulating layer formed in this step, an appropriate amount of hydrogen (H2) can be added during the high-temperature oxidation process to accelerate the oxidation conversion rate, but this is not a limitation.
[0058] In addition, another embodiment of the present invention provides a furnace tube process, which may specifically include the following steps:
[0059] Step S100: Provide a furnace tube, wherein a target wafer is placed inside the crystal boat of the furnace tube.
[0060] Step S200: Perform a high-temperature process on the target wafer and clean and remove the surface layer of the target wafer.
[0061] Step S300: Determine whether the number of cycles of the high-temperature process performed on the target wafer has reached a first cycle threshold; if so, then perform the process on the target wafer. Figure 2 The method shown is to improve wafer warpage by adjusting the warpage of the target wafer; if not, return to continue performing the high-temperature process on the target wafer.
[0062] Step S400: Determine whether the number of cycles of the high-temperature process to be performed on the target wafer after reaching the first cycle threshold has reached the second cycle threshold; if not, return to continue executing the step of performing the high-temperature process on the target wafer; if yes, determine that the target wafer is scrapped and remove it from the furnace tube.
[0063] Wherein, the second cycle threshold is M times the first cycle threshold, and M ≥ 1.5.
[0064] In this embodiment, the number of cycles required for the warpage of the target wafer to reach a warpage threshold can be determined based on a pre-defined training relationship between the warpage of the target wafer and the number of cycles. This number of cycles is then used as the first cycle threshold, and the target wafer is subjected to at least one of the above-mentioned processes. Figure 2 The method shown for improving wafer warpage involves improving the warpage of the target wafer, which serves as a protective wafer, before proceeding with subsequent heat treatment processes such as high-temperature oxidation. This process continues until the number of cycles reaches a second cycle threshold. This allows for timely adjustment of the warpage of the target wafer and increases the number of cycles the target wafer can be used.
[0065] In other embodiments, the number of cycles after which the warpage of the target wafer reaches a warpage threshold can be determined based on a predetermined training relationship between the warpage of the target wafer and the number of cycles. This number of cycles is then used as the first cycle threshold, and the target wafer is subjected to at least one of the above-mentioned processes. Figure 2 The method for improving wafer warpage shown involves first improving the warpage of the target wafer, which serves as a protective wafer, before proceeding with subsequent heat treatment processes such as high-temperature oxidation. Then, the subsequent heat treatment processes, such as high-temperature oxidation, are performed until the second cycle threshold is reached. However, after each subsequent cycle, the target wafer can be re-executed at least once more. Figure 2 The method shown for improving wafer warpage involves performing warpage improvement at least once after each cycle of use of the target wafer, which is between a first cycle threshold and a second cycle threshold. This allows for timely adjustment of the warpage of the target wafer and increases the number of cycles of use of the target wafer to a greater extent.
[0066] Please refer to Figure 3 , Figure 3 This is a graph comparing the number of cycles, warpage, and prior art of a target wafer treated with the wafer warpage improvement method according to one embodiment of the present invention in furnace tube processes. Figure 3 As can be seen from the present invention Figure 2 The warpage of the target wafer after being treated by the method for improving wafer warpage provided in the illustrated embodiment can be greatly improved, and the number of times the target wafer can be recycled can be increased from 15 times in the prior art to 35 times.
[0067] In summary, the target wafer in this invention includes a front side (first side) and a back side (second side) arranged opposite to each other. A polysilicon layer is first formed on the back side, and then an insulating layer is formed on the surface layer and the polysilicon layer of the first side. Since the oxidation rates of the polysilicon layer and the insulating layer are different, they can generate different tensile stresses on the first and second sides of the target wafer, thereby reducing the warping of the target wafer. Based on parameters such as the direction of warping, the warping of the target wafer can be adjusted (improved) by adjusting the process technology and process parameters for forming the polysilicon layer and the insulating layer, thereby reducing the manufacturing cost of semiconductor devices / products.
[0068] Secondly, when this invention is applied to furnace tube processes, a first cycle threshold can be set for the target wafer used as a monitoring wafer or filler wafer. Then, multiple high-temperature processes are performed on it. After the number of cycles of the target wafer reaches the first cycle threshold, the wafer warpage improvement method described above can be performed at least once. Then, the wafer is recycled until it reaches the second cycle threshold before it is determined to be scrapped. Since the wafer warpage improvement method of this invention can effectively adjust the warpage of the target wafer, it will not be scrapped when the target wafer reaches the first cycle threshold, thus increasing the number of cycles of the target wafer.
[0069] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0070] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0071] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A method for improving wafer warpage, characterized in that, include: A target wafer is provided, including a first side and a second side arranged opposite to each other; A polycrystalline silicon layer is formed and conformally covers the second surface; An insulating layer is formed on the first surface and the polysilicon layer, the insulating layer comprising: The second upper part is in direct contact with the target wafer. The second lower half is disposed opposite to the second upper half and in direct contact with the polysilicon layer. The tensile stress of the second lower half on the target wafer is different from that of the second upper half on the target wafer.
2. The method for improving wafer warpage as described in claim 1, characterized in that, The first surface includes an arcuate profile that extends in a vertical direction toward the second surface.
3. The method for improving wafer warpage as described in claim 1, characterized in that, The steps for forming a polycrystalline silicon layer include: A polycrystalline silicon material layer is formed on both the first and second surfaces of the target wafer; Remove the polycrystalline silicon material layer on the first surface and retain the polycrystalline silicon material layer on the second surface.
4. The method for improving wafer warpage as described in claim 3, characterized in that, The thickness of the polycrystalline silicon material layer gradually increases with the increasing temperature of the subsequent heat treatment process.
5. The method for improving wafer warpage as described in claim 4, characterized in that, The temperature range of the subsequent thermal processing of the target wafer is 1000℃~1200℃, and the deposition thickness of the polycrystalline silicon layer is 600 angstroms~2000 angstroms.
6. The method for improving wafer warpage as described in claim 1, characterized in that, The insulating layer is a single-layer structure or a composite structure. The single-layer structure includes an oxide layer, and the composite structure includes an oxide layer and a nitride layer from bottom to top. The oxide layer is in direct contact with the first surface.
7. The method for improving wafer warpage as described in claim 3, characterized in that, The step of forming the insulating layer includes: The thickness of the insulating layer is determined based on the temperature of the subsequent heat treatment process to be performed on the target wafer; The target wafer is subjected to an oxidation process to oxidize the surface layer of the first side into the second upper half of the insulating layer, and to oxidize the surface layer of the polysilicon layer into the second lower half of the insulating layer.
8. The method for improving wafer warpage as described in claim 7, characterized in that, In the vertical direction, the thickness of the second lower half is N times the thickness of the second upper half, and N≥2.
9. The method for improving wafer warpage as described in claim 7, characterized in that, The oxide thickness of the insulating layer gradually increases with the increasing temperature of the subsequent heat treatment process.
10. The method for improving wafer warpage as described in claim 7, characterized in that, The process temperature of the oxidation treatment gradually decreases as the temperature of the subsequent heat treatment process to be performed on the target wafer increases.
11. The method for improving wafer warpage as described in claim 1, characterized in that, The target wafer is a monitoring wafer or filler wafer used in furnace tube high-temperature processes.
12. A furnace tube process, characterized in that, include: A furnace tube is provided, and a target wafer is placed inside the crystal boat of the furnace tube; A high-temperature process is performed on the target wafer, and the surface of the target wafer is cleaned and removed. Determine whether the number of cycles of the high-temperature process performed on the target wafer has reached a first cycle threshold; If yes, then the method for improving wafer warpage according to any one of claims 1 to 11 is performed on the target wafer to adjust the warpage of the target wafer; if no, then the process returns to the step of performing a high-temperature process on the target wafer.
13. The furnace tube process as described in claim 12, characterized in that, After returning to the step of performing a high-temperature process on the target wafer, the process further includes: Determine whether the number of cycles of the high-temperature process to be performed on the target wafer after the first cycle threshold has been reached has reached the second cycle threshold; if not, return to continue executing the step of performing the high-temperature process on the target wafer; if yes, determine that the target wafer is scrapped and remove it from the furnace tube.
14. The furnace tube process as described in claim 13, characterized in that, The second cycle threshold is M times the first cycle threshold, where M ≥ 1.5.