Lead frame package for integrated circuit insulation using integrated insulating layer

Abstract

The invention relates to a lead frame package using an integrated insulating layer for integrated circuit insulation. Example leadframe packages, methods of manufacturing leadframe packages, and electrical systems including leadframe packages are provided that utilize an integrated insulating layer to electrically insulate an integrated circuit within a leadframe package from one or more electrical components. An example lead frame package includes an integrated circuit substrate and an integrated circuit. The integrated insulating layer forms a first surface of the integrated circuit substrate. A plurality of conductive leads provide conductive paths between the second surface and the first surface of the integrated circuit substrate and form conductive traces within the integrated circuit substrate. The integrated insulating layer defines conductive wire bonding pads providing electrical connections with the plurality of conductive leads. Further, the integrated circuit is electrically isolated from the conductive trace by an integrated insulating layer, where the integrated circuit is positioned to determine an electromagnetic characteristic of the conductive trace.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to leadframe packages, and more particularly to integrating an insulating layer within an integrated circuit (IC) substrate of a leadframe package. BACKGROUND

[0002] Many electronic systems utilize printed circuit boards (PCBs) to support and connect various electrical components of the electrical system. The PCBs can generally receive surface mount and / or socketed electrical components, such as leadframe packages that include various integrated circuits (ICs) configured to perform various operations. Some leadframe packages require electrical insulation of the ICs from one or more electrical components within the leadframe package.

[0003] Applicants have discovered that there are numerous technical challenges and difficulties associated with electrically insulating the ICs from one or more electrical components within the leadframe package. Through effort, ingenuity, and innovation, Applicants have solved problems associated with electrical insulation of the ICs by developing solutions embodied in the present disclosure, which are described in detail below. SUMMARY

[0004] Various embodiments relate to an exemplary leadframe package, a method of manufacturing a leadframe package, and an electrical system including a leadframe package that utilizes an integrated insulating layer to electrically insulate an integrated circuit within the leadframe package from one or more electrical components. The exemplary leadframe package can include an integrated circuit substrate having a plurality of conductive leads, a conductive trace, and an integrated insulating layer, and an integrated circuit. The integrated circuit substrate includes at least a first surface and a second surface opposite the first surface. The plurality of conductive leads provide a conductive path between the second surface and the first surface, and the conductive trace is formed within the integrated circuit substrate. The integrated insulating layer forms the first surface of the integrated circuit substrate, and the integrated insulating layer defines a plurality of conductive wire bond pads associated with and providing electrical connections to the plurality of conductive leads. Further, the integrated circuit is electrically isolated from the conductive trace by the integrated insulating layer, wherein the integrated circuit is positioned to determine an electromagnetic property of the conductive trace, and wherein the integrated circuit is electrically connected to the plurality of conductive leads.

[0005] In some embodiments, the integrated circuit is configured to determine a current flowing through the conductive trace based at least in part on the electromagnetic property.

[0006] In some embodiments, a first portion of the conductive trace within an outer projection of the integrated circuit has a smaller cross-sectional area than a second portion of the conductive trace outside the outer projection of the integrated circuit.

[0007] In some embodiments, the first portion of the conductive trace is curved.

[0008] In some embodiments, the integrated insulating layer comprises a dielectric buildup film.

[0009] In some embodiments, the dielectric buildup film has a thickness between 40 and 60 microns.

[0010] In some embodiments, the dielectric buildup film is integrated with the integrated circuit substrate.

[0011] In some embodiments, the conductive wire bonding pads that provide electrical connections to the plurality of conductive leads are each less than 10,000 square microns.

[0012] In some embodiments, the conductive leads are formed by a copper connection in molding (C2iM) process.

[0013] In some embodiments, the integrated circuit is in a flip chip configuration such that electrical contact points on the integrated circuit are between the first surface of the integrated circuit substrate and the integrated circuit.

[0014] In some embodiments, electrical connections are established between the electrical contact points on the integrated circuit and the plurality of conductive wire bonding pads on the integrated circuit substrate.

[0015] In some embodiments, the leadframe package further comprises one or more adhesive connectors that adhere the integrated circuit to the first surface of the integrated circuit substrate.

[0016] In some embodiments, the integrated circuit is embedded in the leadframe package between the package molding and the integrated circuit substrate.

[0017] In some embodiments, the integrated circuit is embedded between the package molding and the integrated circuit substrate using a panel level packaging technique.

[0018] A method of manufacturing a leadframe package is also provided. In some embodiments, the method comprises forming an integrated circuit substrate comprising at least a first surface and a second surface opposite the first surface, the integrated circuit substrate defining a plurality of conductive leads providing a conductive path between the second surface and the first surface. The method further comprises forming conductive traces within the integrated circuit substrate. Additionally, the method comprises disposing an integrated insulating layer on the integrated circuit substrate forming a first surface of the integrated circuit substrate, the integrated insulating layer defining a plurality of conductive wire bonding pads associated with the plurality of conductive leads and providing electrical connections to the plurality of conductive leads. Further, the method comprises positioning an integrated circuit on the first surface of the integrated circuit substrate, wherein the integrated circuit is electrically isolated from the conductive traces by the integrated insulating layer, wherein the integrated circuit is positioned to determine electromagnetic properties of the conductive traces, and wherein the integrated circuit is electrically connected to the plurality of conductive leads.

[0019] In some embodiments, the integrated insulating layer comprises a dielectric build-up film.

[0020] In some embodiments, the integrated circuit is configured to determine the current flowing through the conductive trace based at least in part on the electromagnetic property.

[0021] In some embodiments, the integrated circuit substrate comprising the plurality of conductive leads and the conductive trace is formed by a copper connection by molding (C2iM) process.

[0022] In some embodiments, the integrated circuit is positioned such that a first portion of the conductive trace within a footprint of the integrated circuit has a smaller cross-sectional area than a second portion of the conductive trace outside the footprint of the integrated circuit.

[0023] An electrical system is also provided. In some embodiments, the electrical system comprises a leadframe package and a printed circuit board (PCB). The leadframe package comprises an integrated circuit substrate comprising at least a first surface and a second surface opposite the first surface. The integrated circuit substrate further comprises a plurality of conductive leads providing an electrically conductive path between the second surface and the first surface, a conductive trace formed within the integrated circuit substrate, and an integrated insulating layer forming the first surface of the integrated circuit substrate, the integrated insulating layer defining a plurality of conductive wire bond pads associated with the plurality of conductive leads and providing electrical connections to the plurality of conductive leads. The leadframe package further comprises an integrated circuit electrically isolated from the conductive trace by the integrated insulating layer, wherein the integrated circuit is positioned to determine an electromagnetic property of the conductive trace, and wherein the integrated circuit is electrically connected to the plurality of conductive leads. The electrical system further comprises a PCB comprising a current-carrying conductive path and a plurality of conductive contact surfaces, wherein the current-carrying conductive path is configured to interface with the conductive trace through two or more of the plurality of conductive surfaces. BRIEF DESCRIPTION OF DRAWINGS

[0024] Reference will now be made to the drawings. Components shown in the figures can or can not be present in certain embodiments described herein. Some embodiments can include fewer (or more) components than shown in the figures, according to example embodiments of the present disclosure.

[0025] Figure 1 An example leadframe package is illustrated, comprising an integrated circuit configured to measure an electromagnetic property of an electrically insulated conductive trace.

[0026] Figure 2 A top view of an example integrated circuit substrate and corresponding integrated circuit is illustrated, according to example embodiments of the present disclosure.

[0027] Figure 3A cross-sectional view of an example integrated circuit substrate and corresponding integrated circuit is illustrated in accordance with example embodiments of the present disclosure.

[0028] Figures 4A-4C A perspective view of multiple layers of an example integrated circuit substrate is illustrated in accordance with example embodiments of the present disclosure.

[0029] Figure 5 An example wire bond connection of an integrated circuit within a leadframe package is illustrated in accordance with example embodiments of the present disclosure.

[0030] Figure 6 A cross-sectional view of an example leadframe package is illustrated in accordance with example embodiments of the present disclosure.

[0031] Figure 7 A cross-sectional view of an example integrated circuit substrate including a reduced size conductive wire bond pad is illustrated in accordance with example embodiments of the present disclosure.

[0032] Figure 8 A perspective view of an example integrated circuit substrate including a reduced size conductive wire bond pad and corresponding integrated circuit is illustrated in accordance with example embodiments of the present disclosure.

[0033] Figures 9A-9B An integrated circuit substrate configured for an integrated circuit in a flip chip configuration is illustrated in accordance with example embodiments of the present disclosure.

[0034] Figure 10 A flip chip configured integrated circuit is illustrated in accordance with example embodiments of the present disclosure, the integrated circuit positioned to measure electromagnetic properties of a curved narrowed trace.

[0035] Figure 11 An embedded integrated circuit is illustrated in accordance with example embodiments of the present disclosure.

[0036] Figure 12 An example electrical system providing electrical isolation for a driver die is illustrated in accordance with example embodiments of the present disclosure.

[0037] Figure 13 An example process for manufacturing a leadframe package is shown in accordance with example embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the inventive subject matter described herein are shown. Indeed, embodiments of the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Throughout the following description, similar reference numerals can be used to describe similar elements throughout the several embodiments.

[0039] Various example embodiments address technical problems associated with electrically insulating an integrated circuit (IC) in a leadframe package from one or more electrically conductive components within an IC substrate of the leadframe package. As understood by one of skill in the art to which this disclosure pertains, there are a variety of example scenarios in which an electrical component of an IC substrate can need to be electrically insulated from an IC housed within a leadframe package.

[0040] Many electronic systems utilize PCBs to support and connect various electrical components of an electrical system. A PCB can include a rigid structure having a plurality of mounting regions configured to receive various electrical components. The PCB can also include electrically conductive traces or paths to enable electrical connections between various electrical components. The PCB can generally receive surface mount and / or socketed electrical components, including various ICs.

[0041] Generally, a leadframe package is a surface mount technology that provides structural support for an IC, protects it from environmental factors, and establishes electrical connections between a PCB and the IC without the need for through-holes. Electrically conductive surfaces (leads) on the bottom surface of the leadframe package are coupled with electrically conductive surfaces on the surface of the PCB. The leadframe package protects the electrical connections and electrical components of the IC from environmental factors, ensuring the reliability of the electrical system even under extreme conditions. Example leadframe packages include quad flat no-lead (QFN) packages and quad flat no-lead multiple row (QFNmr) packages.

[0042] As shown in Figure 1 Some leadframe packages 100 include an IC 104 configured to determine current flowing through an electrically conductive trace 108, as shown in Figure 1 The electrically conductive trace 108 is electrically coupled with the example leadframe package 100 through a plurality of electrically conductive leads 106, as shown in

[0043] As shown in Figure 1As shown in the middle, to determine the current flowing through the conductive trace 108 based on the magnetic field 112, the IC 104 must be electrically insulated from the conductive trace 108, including the narrowed trace 110, while still being able to measure one or more electromagnetic properties of the narrowed trace 110. In some previous examples, glass or insulating tape is placed on the surface of the leadframe package 100 between the IC 104 and the narrowed trace 110. However, glass can be thick and expensive. The thickness of the glass can adversely affect the sensitivity of the current-sensing IC 104. In addition, the thickness of the glass can increase the overall area occupied by the leadframe package 100. Further, the cost of using glass as an electrical insulating medium can be prohibitive. Insulating tape can crack and / or delaminate during operation of the IC 104. The cracking and / or delamination can create gaps between the narrowed trace 110 and the current-sensing IC 104. Such gaps can cause leakage current, which can adversely affect the ability of the IC 104 to accurately determine the electromagnetic properties of the narrowed trace 110.

[0044] The various example embodiments described herein provide an integrated insulating layer that is integrated as a top layer of the IC substrate of the leadframe package. The integrated insulating layer is a dielectric material, compound, or insulating film that is applied during the manufacture of the IC substrate. The integrated insulating layer provides an electrical insulating layer between the IC 104 and the narrowed trace 110. The integrated insulating layer can be applied to the top surface of the IC substrate of the leadframe package during the manufacture of the IC substrate. In addition, the integrated insulating layer enables conductive traces to pass through and / or along the integrated insulating layer. The integrated insulating layer provides the necessary insulation between the IC of the leadframe package and electronic components, such as the conductive trace 108 / narrowed trace 110.

[0045] In some embodiments, vias and / or traces can be formed through and / or along the integrated insulating layer. Accordingly, conductive wire bonding pads can be formed that are electrically connected to the plurality of conductive leads of the leadframe package, thereby providing a conductive path from the top surface of the IC substrate to the conductive leads. The conductive bonding wires of the leadframe package can connect the IC to the conductive wire bonding pads, thereby providing a conductive path from the IC to the conductive leads and to external electrical components of the electrical system.

[0046] One such integrated insulating layer can include a dielectric build-up film. The dielectric build-up film is an insulating film that is applied during the manufacture of the IC substrate. The dielectric build-up film can be applied through a vacuum lamination and curing process. The vacuum lamination and curing process enables the dielectric build-up film to adhere to the IC substrate. In addition, vias and / or openings can be formed using laser drilling. Further, conductive paths can be formed through electroplating. In some embodiments, the dielectric build-up film can include an ajinomoto build-up film (ABF).

[0047] As a result of the example embodiments described herein and in some examples, the integrated insulating layer forms an integral part of the IC substrate. Because the integrated insulating layer forms an integral part of the IC forming substrate, the integrated insulating layer does not delaminate to create a gap between the narrowed trace 110 and the IC. Further, the integrated insulating layer can reduce the thickness and cost of the insulating layer compared to a glass insulator. Eliminating the gap between the narrowed trace and the IC and reducing the space between the narrowed trace and the IC die, while still maintaining electrical insulation, enables higher sensitivity to the current flowing through the narrowed trace at the IC. Further, integrating the integrated insulating layer as a top layer of the IC substrate reduces manufacturing complexity and cost of manufacturing.

[0048] Referring now to Figure 2 , an example leadframe package 220 is provided. As shown in Figure 2 , the example leadframe package 220 includes an IC 104 positioned on an IC substrate 222. A top surface 222a of the IC substrate 222 is formed by an integrated insulating layer 224. The IC substrate 222 also includes a plurality of conductive wire bond pads 226 formed in a surface of the integrated insulating layer 224.

[0049] As shown in Figure 2 , the example leadframe package 220 includes an IC 104. The IC 104 (e.g., an IC die) is any block of semiconductor material that performs one or more functions using circuitry and / or electrical components. The IC 104 can include a processor, a reconfigurable architecture, passive electrical components, active electrical components, memory, communication circuitry, and / or any other electrical components necessary to perform the functionality of the IC 104. In one example embodiment, the IC 104 is configured to determine a current in a conductive component (e.g., a narrowed trace 110 as shown in Figure 1 ) proximate to the IC 104. In such embodiments, the IC 104 is configured to measure one or more electromagnetic properties of the conductive component while electrically insulated from the conductive component. For example, the IC 104 can determine a current in the conductive component based on changes in a magnetic field proximate to the conductive component using the Hall effect.

[0050] The IC 104 is also configured to receive and / or generate one or more electrical signals. The one or more electrical signals are transmitted through one or more conductive leads (e.g., lead wires 224 as shown in Figure 1The conductive leads 106) are transmitted between the IC 104 and the electrical system. The IC 104 can be electrically connected to the one or more conductive leads through a plurality of conductive wire bond pads 226. The conductive wire bond pads 226 are any electrically conductive material located at the top surface 222a of the IC substrate 222 that provide an electrically conductive path to the one or more conductive leads of the leadframe package 220. The IC 104 can include a plurality of electrical contact points configured to interface with the one or more conductive wire bond pads 226. The IC 104 can be electrically connected to the conductive wire bond pads 226 via conductive bond wires.

[0051] As Figure 2 As further shown in FIG. 1, the leadframe package includes an IC substrate 222. The IC substrate 222 defines an interface between the IC 104 of the leadframe package 220 and an underlying circuit board (e.g., printed circuit board). For example, the IC substrate 222 can define a plurality of electrically conductive paths between the conductive leads and the one or more conductive wire bond pads 226. In some embodiments, the IC substrate 222 can define an electrically conductive path of a current-carrying conductive trace through the IC substrate 222. For example, the IC substrate 222 can define a narrowed trace proximate to the IC 104 such that the IC 104 can determine one or more electromagnetic properties of the conductive trace without electrical contact. In some embodiments, as described further with respect to FIG. 2, the IC substrate 222 can be formed using a copper-circuit-in-mold (C2iM) process or a molded interconnect substrate (MIS) process. Figure 3 As further described, the IC substrate 222 can be formed using a copper-circuit-in-mold (C2iM) process or a molded interconnect substrate (MIS) process.

[0052] As Figure 2 As further shown in FIG. 1, the top surface 222a of the IC substrate 222 is defined by an integrated insulating layer 224. The integrated insulating layer 224 is a dielectric, compound, film, or other material applied during the manufacture of the IC substrate 222 as an insulating of the top surface 222a of the IC substrate 222. The integrated insulating layer 224 provides an electrically insulating layer between the IC 104 and the narrowed trace 110. The insulating material, including the integrated insulating layer 224, can include any non-conductive material configured to insulate the electrically conductive paths of the IC substrate 222 from the IC 104. For example, a molding material, an epoxy, a resin, a polymeric plastic, a dielectric build-up film, or other similar material. The integrated insulating layer 224 can be applied by any process used to manufacture the IC substrate 222, such as a copper-circuit-in-mold (C2iM) process or a molded interconnect substrate (MIS) process.

[0053] Further, the integrated insulating layer 224 enables the conductive trace to pass through the integrated insulating layer 224 and / or enables the definition of an electrically conductive surface (e.g., the conductive wire bond pads 226) on the integrated insulating layer 224. The integrated insulating layer 224 insulates the IC 104 of the leadframe package 220 from any underlying electronic components, such as the conductive leads 106, the one or more conductive wire bond pads 226, and / or the conductive traces of the IC substrate 222. Figure 1The integrated insulating layer 224 provides the necessary insulation between the conductive traces 108 / narrowed traces 110 as shown in FIG. 3. Because the integrated insulating layer 224 is formed as an integral part of the IC substrate 222, the integrated insulating layer 224 does not delaminate or allow a gap to form between the underlying conductive components and the IC 104.

[0054] In some embodiments, the integrated insulating layer 224 can include a dielectric build-up film. A dielectric build-up film is an insulating film applied to the top surface 222a of the IC substrate 222 during the manufacture of the IC substrate 222. The dielectric build-up film provides an electrically insulating layer between the IC 104 and the narrowed traces 110. The dielectric build-up film can be applied using a vacuum lamination and curing process. The vacuum lamination and curing process enables the dielectric build-up film to bond to the IC substrate 222. In some embodiments, the dielectric build-up film includes an ABF build-up film. In some embodiments, the dielectric build-up film includes a ShinEtsu build-up film.

[0055] Referring now to FIG. 4, Figure 3 a cross-section of an example IC substrate 222 and corresponding IC 104 is provided. As shown in Figure 3 , the example IC substrate 222 includes a dielectric material 330 formed to insulate conductive paths (e.g., conductive leads 106, narrowed traces 110). As further shown in Figure 3 , the integrated insulating layer 224 forms the top surface 222a of the IC substrate 222. The conductive wire bond pads 226 are formed in the integrated insulating layer 224, providing a conductive path from the top surface 222a of the IC substrate 222 to the conductive leads 106 at the bottom surface 222b of the IC substrate 222. Further, the IC 104 is positioned on the integrated insulating layer 224 of the IC substrate 222 and above the current carrying narrowed traces 110 formed below the integrated insulating layer 224 of the IC substrate 222.

[0056] As shown in Figure 3 , the IC substrate 222 includes a layer of dielectric material 330 that electrically insulates the conductive paths. The dielectric material 330 includes any non-conductive material configured to provide structure to the IC substrate 222 and insulate various conductive paths that pass through the IC substrate 222. The dielectric material 330 can be an epoxy, a resin, a polymer plastic, or other similar material.

[0057] In some embodiments, the IC substrate 222 and the integrated insulating layer 224 can be formed using a molded copper connection process (C2iM). In such embodiments, the dielectric material 330 comprises a glass-fiber free epoxy molding compound. The IC substrate 222 can be formed in layers comprising the dielectric material 330 and / or the conductive material of the interconnects. For example, the conductive material can be placed on a metal carrier plating. The conductive material can then be encapsulated (molded) with the dielectric material 330. The dielectric material 330 can then be ground to expose portions of the layers of dielectric material 330. These steps can be repeated, forming interconnect paths of the conductive material between the layers. As shown in Figure 3

[0058] In some embodiments, the IC substrate 222 and the integrated insulating layer 224 can be formed using a molded interconnect substrate (MIS) process. The MIS process can include forming the IC substrate 222 using a pre-molded structure having one or more layers. Each layer is pre-configured with a copper plating or interconnect to provide electrical connections within the package (e.g., the conductive lead 106, the narrowed trace 110). Each layer is then encapsulated (molded) with the dielectric material 330. The dielectric material 330 can then be etched to expose portions of the layers of dielectric material 330. These steps can be repeated to form interconnect paths of the conductive material between the layers of the IC substrate 220.

[0059] As further shown in Figure 3 The integrated insulating layer 224 is formed as a top surface of the IC substrate 222. The integrated insulating layer 224 provides an insulating layer between the IC 104 and the underlying narrowed trace 110. The thickness of the integrated insulating layer 224 affects the insulating properties of the integrated insulating layer 224. For example, a thicker integrated insulating layer 224 can provide insulation at higher voltages. However, the thickness of the integrated insulating layer 224 also affects the sensitivity of current measurements made by the IC 104 due to the separation between the narrowed trace 110 and the IC 104. For example, a thicker integrated insulating layer 224 can reduce the sensitivity of current measurements at the IC 104. In embodiments that include a dielectric build-up film as the integrated insulating layer 224, the thickness of the integrated insulating layer 224 is between 40 microns and 60 microns; more preferably between 45 microns and 55 microns; and most preferably between 48 and 52 microns. A thicker integrated insulating layer 224 can provide electrical insulation at higher voltages.

[0060] ​In cases where the integrated insulating layer 224 includes a dielectric build-up film, the dielectric build-up film can be attached to the surface of the IC substrate 222 using a lamination process (e.g., vacuum lamination). Once attached, the conductive path can be continued and / or completed by laser-drilling an opening or path through the dielectric build-up film and then filling the opening or path with a conductive material using electroplating. This process can be used to form the conductive wire bond pad 226 in the surface of the dielectric build-up film.

[0061] As further shown in Figure 3 , the IC 104 is positioned proximate to the constricted trace 110, opposite the integrated insulating layer 224. In some embodiments, the IC 104 can be configured to measure the current flowing through the constricted trace 110 based on one or more electromagnetic properties measured by the IC 104. As such, the IC 104 is placed in close proximity to the constricted trace 110. For example, as shown in Figure 3 , the constricted trace 110 lies within the outer perimeter projection of the IC 104 relative to the top surface 222a of the IC substrate 222 in at least one direction. Further, the constricted trace 110 is in contact with the surface of the integrated insulating layer 224 directly opposite the IC 104.

[0062] Referring now to Figures 4A-4B , the following example layers of an example IC substrate are provided: a first layer 440a, a second layer 440b, and a third layer 440c.

[0063] As shown in Figure 4A , the first layer 440a of the IC substrate includes a plurality of conductive leads 106a defined within a dielectric material 330 and a conductive trace 442a. The plurality of conductive leads 106a provide a conductive path between the IC of the leadframe package and an underlying circuit board. The conductive leads 106a enable the sending and receiving of electrical signals between the IC and various electrical components interconnected by the underlying circuit board.

[0064] The conductive trace 442a is also configured to interface with the underlying circuit board. In one non-limiting example, the conductive trace 442a can be configured to interface with a current-carrying conductive wire. The conductive trace 442a can enable the transmission of current through the IC substrate of the leadframe package such that the IC can determine the current flowing through the current-carrying conductive wire based on one or more electromagnetic properties measured by the IC.

[0065] As shown in Figure 4BAs shown, the second layer 440b is positioned in physical contact with the first layer 440a. The second layer 440b is positioned such that the conductive lead 106a of the first layer 440a is in electrical contact with the conductive lead 106b of the second layer 440b. Furthermore, the conductive trace 442a of the first layer 440a is in electrical contact with the conductive trace 442b of the second layer 440b. The conductive portion of the second layer 440b also forms a narrowed trace 110 of the conductive trace 442b. The cross-sectional area of ​​the narrowed trace 110 is smaller than that of the conductive traces 442a / 442b. Therefore, the current flowing through the conductive traces 442a / 442b is forced through the narrowed trace 110. Forcing the current through the narrowed trace 110 allows the IC to more accurately determine its electromagnetic characteristics.

[0066] like Figure 4C As shown, the third layer 440c includes an integrated insulating layer 224 that substantially covers the surface of the third layer 440c. Furthermore, a plurality of conductive line bonding pads 226 corresponding to the conductive leads 106a / 106b of the first layer 440a and the second layer 440b are formed in the integrated insulating layer 224. The third layer 440c is positioned to physically contact the second layer 440b on the surface of the second layer 440b opposite to the first layer 440a. The third layer 440c is positioned such that the conductive leads 106b of the second layer 440b are in electrical contact with the conductive line bonding pads 226 of the third layer 440c. The integrated insulating layer 224 provides electrical insulation between the top surface of the third layer 440c and the underlying narrowed traces 110 and conductive traces 442a / 442b. Furthermore, the conductive line bonding pads 226 provide electrical connections between the IC and external electrical components via the conductive leads 106a / 1106b.

[0067] Now for reference Figure 5 An example conductive bond line 550 is provided to provide electrical connections between multiple conductive bond pads 226 and electrical contacts 552 on IC 104. For example... Figure 5 As further shown, the integrated insulating layer 224 provides an insulating barrier between IC 104 and the electrical components below.

[0068] like Figure 5 As shown, the conductive bonding wire 550 provides an electrical connection between a plurality of conductive wire bonding pads 226 and electrical contacts 552 on the IC 104. The conductive bonding wire 550 can be any conductive material forming a conductive path from the conductive lead through the conductive wire bonding pads 226 to the electrical contacts 552 on the IC 104. The conductive bonding wire 550 facilitates the transmission of electrical signals between the IC 104 and the conductive lead and provides electrical connectivity to external electrical systems. The conductive bonding wire 550 can include aluminum, copper, silver, gold, or other similar conductive materials. In some embodiments, the conductive bonding wire 550 can be attached using ball bonding or wedge bonding techniques.

[0069] Referring now to Figure 6 , an example leadframe package 660 is provided. As shown in Figure 6 , the example leadframe package 660 includes an IC substrate 222 that includes a narrowed trace 110 and a conductive lead 106. A top surface of the IC substrate 222 is defined by an integrated insulating layer 224 of an insulating layer formed between the IC 104 and the narrowed trace 110. The integrated insulating layer 224 also defines a conductive wire bond pad 226 that forms a conductive path between the top surface of the IC substrate 222 and the conductive lead 106. A conductive bond wire 550 provides an electrical connection between the IC 104 and the conductive lead 106. As further shown in Figure 6 , the IC 104 and the conductive bond wire 550 are encapsulated in a package molding 662. The conductive paths (e.g., the narrowed trace 110, the conductive lead 106) are attached to a printed circuit board (PCB) 664 by a conductive bond 666.

[0070] As shown in Figure 6 , the example leadframe package 660 includes a package molding 662. The package molding 662 includes any non-conductive material configured to protect the IC 104 within the leadframe package 660 from the surrounding environment. For example, in some embodiments, the IC 104 can be located on an electrical system in a harsh environment (e.g., high temperatures, low temperatures, exposure to dirt, water, dust, sand, etc.). The leadframe package 660 can be used to protect the IC 104 located in a portion of an automobile (e.g., an engine, a chassis, a drivetrain, etc.). As shown in Figure 6 , the package molding 662 is formed to define an outer boundary of the leadframe package 660. The package molding 662 can include a resin, a polymer plastic, or other insulating material.

[0071] As further shown in Figure 6 , the example leadframe package 660 is electrically coupled to the PCB 664 by the conductive bond 666. The PCB 664 is a structure that includes laminated layers of conductive and insulating material, providing a rigid structure and electrical connections between various electrical components of a circuit (e.g., the leadframe package 660). The PCB 664 can utilize copper or similar conductors to form electrical paths between electrical components that comprise a circuit. The conductive layers can be accompanied by one or more insulating layers. The insulating layers can be composed of an insulating material, such as fiberglass. The PCB 664 can enable integration of one or more electrical components through surface mount technology. Surface mount technology provides for direct attachment of electrical components to a surface of the PCB 664. Surface mount technology enables increased automation in the manufacture of circuits utilizing the PCB 664. Additionally, surface mount technology reduces costs and improves the quality and reliability of circuits.

[0072] The PCB 664 can include a plurality of conductive surfaces configured to interface with the conductive leads 106 of the leadframe package 660. The conductive surfaces can be configured to provide electrical connections to one or more electrical paths on the PCB 664. The conductive surfaces can include copper or other similar conductive material. The conductive surfaces can be configured to align with the conductive leads 106 of the leadframe package 660. The conductive leads 106 of the leadframe package 660 can be attached to the conductive surfaces of the PCB 664 with conductive bonds 666, such as solder.

[0073] Referring now to Figure 7 , a cross-sectional view of an example IC substrate 222 and corresponding IC 104 is provided. As shown in Figure 7 , the example IC substrate 222 includes a dielectric material 330 separating the conductive leads 106 from the narrowed traces 110. The top layer of the IC substrate 222 is defined by the integrated insulating layer 224 forming conductive wire bond pads 770. The IC 104 is attached to the IC substrate 222 by a die attach film 772. As shown in Figure 7 , the IC 104 is electrically separated from the narrowed traces 110 by the integrated insulating layer 224.

[0074] As shown in Figure 7 , the size of the conductive wire bond pads 770 formed by the integrated insulating layer 224 is reduced compared to the conductive wire bond pads 226. The reduced size conductive wire bond pads 770 can provide better isolation between the IC 104 and underlying electrical components because there is less exposed conductive material. The reduced size conductive wire bond pads 770 can further save costs because less conductive material is needed on the top surface of the IC substrate 222. However, the reduced size conductive wire bond pads 770 can require longer conductive wire bonds to reach the conductive surface provided by the conductive wire bond pads 770. In some embodiments, the size of the conductive wire bond pads 770 can be reduced such that the surface area exposed at the surface of the integrated insulating layer 224 is minimized. For example, in the case where gold wire with a diameter of 0.8 mm is used as the conductive leads 106, a conductive wire bond pad 770 of 100 microns by 80 microns can be used.

[0075] Referring now to Figure 8 , a perspective view of an example IC substrate 222 and corresponding IC 104 having reduced size conductive wire bond pads 770 is provided. As shown in Figure 7As shown, the top layer of the IC substrate 222 is defined by an integrated insulating layer 224 forming a plurality of reduced-size conductive line bonding pads 770. The reduced-size conductive line bonding pads 770 provide more adequate isolation between the conductive portions of the IC substrate 222 and the IC 104. Furthermore, the reduced-size conductive line bonding pads 770 reduce the amount of conductive material required at the integrated insulating layer 224. However, longer conductive bonding lines may be required to reach the conductive surface provided by the conductive line bonding pads 770.

[0076] Now for reference Figures 9A-9B An example IC substrate 222 is provided, which is designed to support ICs with flip-chip configurations. Figure 9A The layer of the IC substrate 222 beneath the integrated insulating layer 224 is shown. (See diagram.) Figure 9A As shown, the conductive leads 106 of the example IC substrate 222 are moved to align with the electrical contacts of the flip-chip configured IC. Figure 9A As further shown, the conductive trace 442 (including the narrowed trace 110) is further defined in the dielectric material 330.

[0077] Figure 9B The top layer of an example IC substrate 222 designed to support a flip-chip configuration is shown. Figure 9B As shown, the integrated insulating layer 224 defines the top layer of the IC substrate 222, thereby providing an electrical insulating layer between the conductive trace 444 / narrow trace 110 and the IC located on the integrated insulating layer 224. Figure 9B As further shown, the integrated insulating layer 224 defines a plurality of conductive pads 990, which are configured to interact with... Figure 9A The conductive leads 106 shown are aligned with the electrical contacts on the flip-chip configured IC.

[0078] The flip-chip configured IC is flipped upside down, so that the electrical contacts on the top of the IC are positioned to contact the integrated insulating layer 224. In some embodiments, the flip-chip configured IC can provide a more accurate readout of the electromagnetic characteristics of the conductive trace 442. For example, when the IC is in a flip-chip configuration, the sensing element of the IC can be closer to the conductive trace 442 and the narrowed trace 110.

[0079] like Figure 9B As further illustrated, in some embodiments, the IC substrate 222 may also include an adhesive connector 992. The adhesive connector 992 is included at any contact point between the IC substrate 222 and the IC, thereby providing structural stability to the IC, particularly in flip-chip configurations. Figure 9BAs shown in

[0080] Referring now to Figure 10 , a perspective view of an example IC substrate 222 is shown including a curved narrowed trace 1010. As shown in Figure 10 , the integrated insulating layer 224, the conductive leads 106, and the IC 104 are transparent, thereby exposing the layers of the IC substrate 222 that are located beneath the integrated insulating layer 224. The IC substrate 222 includes a conductive trace 442 that includes a curved narrowed trace 1010 that is located within a projection of an outer perimeter of the IC 104. The IC substrate 222 also includes a plurality of conductive leads 106 that terminate at a plurality of conductive pads 990 at a top surface of the IC substrate 222.

[0081] As shown in Figure 10 , the example IC substrate 222 includes a plurality of conductive leads 106. The conductive leads 106 are designed for an IC 104 that is employed in a flip-chip configuration. For example, the conductive paths are defined in the IC substrate 222 such that the ends of the conductive leads 106 terminate at conductive pads 990 that are aligned with electrical contact points of the IC 104.

[0082] As further shown in Figure 10 , the conductive trace 442 includes a curved narrowed trace 1010. The curved narrowed trace 1010 is designed to concentrate the current flowing through the conductive trace 442 in a conductive portion having a smaller cross-sectional area. By restricting the current flowing through the conductive trace 442 to a conductive portion having a smaller cross-sectional area, the current can be brought into closer proximity to the sensing elements of the IC 104. Furthermore, by curving the curved narrowed trace 1010, the portion of the conductive trace 442 that is narrowed can be isolated within a projection of an outer perimeter of the IC 104 on the IC substrate 222. By isolating and narrowing the curved narrowed trace 1010 of the conductive trace 442, the current flowing through the conductive trace 442 is concentrated near the active area of the IC 104. Concentrating the current near the accurate area can generate more accurate measurements of the electromagnetic properties of the conductive trace 442.

[0083] Although the integrated insulating layer 224 is transparent in Figure 10 , the integrated insulating layer 224 provides electrical isolation between the curved narrowed trace 1010 of the IC substrate 222 and the IC 104.

[0084] Referring now to Figure 11, example embodiments of a leadframe package 1100 are provided in which an IC 104 is embedded between an IC substrate 1122 and a panel material 1102 (e.g., a molding compound). As shown in Figure 11 , example IC substrate 1122 includes an IC 104 on the panel material 1102. Example IC substrate 1122 also includes an integrated insulating layer 224 that covers the IC 104 and provides an insulating layer between the IC 104 and the narrowed traces 110. The IC substrate 1122 includes a dielectric material 330 for insulating conductive paths (e.g., conductive traces 108, conductive traces 442, narrowed traces 110) within the IC substrate 1122.

[0085] Panel-level packaging techniques can be used to manufacture leadframe packages 1100 such as shown in Figure 11 Panel-level packaging techniques enable the simultaneous manufacture of multiple leadframe packages 1100. As shown in Figure 11 , multiple ICs 104 can be positioned on the panel material 1102 or molding compound. Subsequently, an integrated insulating layer 224 can be disposed on top of the ICs 104, forming an electrically insulating barrier. Conductive paths (e.g., conductive traces 108, conductive traces 442, narrowed traces 110) can be formed through the IC substrate 1122, with one or more of the conductive paths terminating at conductive pads on the top surface of the leadframe package 1100. Once manufactured, the leadframe packages 1100 with embedded ICs 104 can undergo a singulation process in which individual leadframe packages 1100 are separated.

[0086] Referring now to Figure 12 , additional embodiments of a leadframe package 1200 according to example embodiments of the present disclosure are provided. As shown in Figure 12 , example leadframe package 1200 includes a driver die 1202 and a power die 1204. The driver die 1202 is attached to an IC substrate 222 by a die attach film 772. The power die 1204 is attached to the IC substrate 222 by a hybrid adhesive 1206. Further, the top layer of the IC substrate 222 in contact with the driver die 1202 includes an integrated insulating layer 224.

[0087] As shown in Figure 12As shown in FIG. 12, in some embodiments, it can be desirable to electrically insulate a portion of the IC substrate 222 (e.g., a portion of the IC substrate 222 proximate to the drive die 1202). In such embodiments, a portion of the top surface of the IC substrate 222 can be defined by an integrated insulating layer 224. In such cases, the integrated insulating layer 224 provides electrical insulation between the drive die 1202 and the underlying layers of the IC substrate 222. Insulating the drive die 1202 from the power die 1204 prevents an electrical short from occurring between the high current power die 1204 and the low current drive die 1202.

[0088] Referring now to Figure 13 An example process flow 1300 for manufacturing a leadframe package according to example embodiments of the present disclosure is provided. At block 1302, an integrated circuit substrate (e.g., IC substrate 222) is formed, the substrate including at least a first surface (e.g., top surface 222a) and a second surface (e.g., bottom surface 222b) opposite the first surface, the integrated circuit substrate defining a plurality of conductive leads (e.g., conductive leads 106) to provide a conductive path between the second surface and the first surface.

[0089] The IC substrate can include a dielectric material that defines a conductive path between the conductive leads and the first surface of the IC substrate. Such a conductive path can provide an electrical connection from the first surface of the IC substrate to an external electrical component, system, processor, etc. by interfacing with the conductive leads. For example, a PCB can include corresponding conductive surfaces positioned in alignment with the conductive leads of the IC substrate. By coupling the conductive leads with the conductive surfaces of the PCB, electrical signals can be transmitted to electrical components interconnected with the PCB.

[0090] At block 1304, a conductive trace (e.g., conductive trace 442, narrowed trace 110, curved narrowed trace 1010) is formed within the integrated circuit substrate. The conductive trace can interface with a PCB or other circuitry through one or more of the conductive leads and corresponding conductive surfaces. The conductive trace can include a narrowed portion within the IC substrate. The narrowed portion includes a conductive trace of a smaller cross-sectional area. For example, the narrowed portion can include only the layers of the upper portion of the IC substrate. The narrowed portion can be configured to concentrate electrical current in a portion of the IC substrate, for example, to enable detection of one or more electromagnetic properties of the conductive trace.

[0091] At block 1306, an integrated insulating layer (e.g., integrated insulating layer 224) is disposed on the integrated circuit substrate, thereby forming a first surface of the integrated circuit substrate, the integrated insulating layer defining a plurality of conductive wire bonding pads (e.g., conductive wire bonding pads 226) associated with and providing electrical connections to the plurality of conductive leads. The integrated insulating layer includes an insulating material, a dielectric compound, and / or a dielectric build-up film applied to the top surface of the IC substrate during fabrication of the IC substrate. The integrated insulating layer provides an electrically insulating layer for the IC substrate, including conductive paths (e.g., narrowed traces) within the IC substrate. Further, the conductive wire bonding pads (e.g., conductive wire bonding pads 226) are defined on the integrated insulating layer to enable electrical connections with one or more conductive leads. Because the integrated insulating layer forms as an integral part of the IC substrate, the integrated insulating layer does not delaminate or cause a gap to form between the underlying conductive components and the IC of the leadframe package. In some embodiments, the integrated insulating layer includes a dielectric build-up film, such as an Ajinomoto build-up film (ABF) or a Henkel build-up film.

[0092] At block 1308, an integrated circuit (e.g., IC 104) is positioned on the first surface of the integrated circuit substrate, wherein the integrated circuit is electrically isolated from the conductive traces by the integrated insulating layer, wherein the integrated circuit is positioned to determine electromagnetic properties of the conductive traces, and wherein the integrated circuit is in electrical connection with the plurality of conductive leads.

[0093] As described herein, the integrated insulating layer can define one or more conductive wire bonding pads that provide electrical connections between the top surface of the IC substrate and one or more conductive leads exposed at the bottom surface of the IC substrate. The leadframe package includes electrical connections between electrical contact points on the IC and the conductive wire bonding pads. In some embodiments, a conductive bonding wire can form the electrical connection between the IC and the conductive wire bonding pads. In some embodiments, the integrated insulating layer can define conductive pads at or near the perimeter of the IC, thereby enabling the IC to be attached to the conductive pads in a flip-chip configuration. The integrated insulating layer also provides electrical insulation between the IC and the underlying conductive paths (e.g., conductive traces and narrowed trace portions). Electrically isolating the IC from the conductive traces enables the IC to determine electromagnetic properties of the conductive traces without electrical contact. For example, the IC can determine current flowing through the conductive traces by measuring changes in the magnetic field around the conductive traces.

[0094] While this detailed description has set forth some embodiments of the application, the appended claims encompass other embodiments of the application which are within the purview of various modifications and improvements as described above and as will occur to those skilled in the art. For example, those skilled in the art will recognize that the principles can be applied to any integrated circuit in a leadframe package that benefits from electrical insulation from a portion of the leadframe package.

[0095] In the appended claims, unless the specific terms “means for…” or “steps for…” are used in a given claim, the claims are not intended to be interpreted in accordance with paragraph 6 of 35 U.SC 112.

[0096] The use of broad terms such as “comprising,” “including,” and “having” should be understood to provide support for narrower terms such as “consisting of,” “substantially consisting of,” and “truly consisting of.” The use of terms such as “optionally,” “may,” “perhaps,” and “possibly” with respect to any element of an embodiment means that the element is not essential, or alternatively, that the element is required, both of which are within the scope of the embodiment(s). Furthermore, references to examples are provided for illustrative purposes only and are not intended to be exclusive.

Claims

1. A leadframe package comprising: an integrated circuit substrate comprising at least a first surface and a second surface opposite the first surface, the integrated circuit substrate further comprising: a plurality of conductive leads providing an electrically conductive path between the second surface and the first surface; a conductive trace formed within the integrated circuit substrate; and an integrated insulating layer forming the first surface of the integrated circuit substrate, the integrated insulating layer defining a plurality of conductive wire bond pads associated with and providing electrical connections to the plurality of conductive leads; and an integrated circuit electrically isolated from the conductive trace by the integrated insulating layer, wherein the integrated circuit is positioned to determine an electromagnetic property of the conductive trace, and wherein the integrated circuit is electrically connected to the plurality of conductive leads.

2. The leadframe package of claim 1, wherein the integrated circuit is configured to determine a current flowing through the conductive trace based at least in part on the electromagnetic property.

3. The leadframe package of claim 1, wherein a first portion of the conductive trace within a projection of an outer periphery of the integrated circuit has a smaller cross-sectional area than a second portion of the conductive trace outside the projection of the outer periphery of the integrated circuit.

4. The leadframe package of claim 3, wherein the first portion of the conductive trace is curved.

5. The leadframe package of claim 1, wherein the integrated insulating layer comprises a dielectric build-up film.

6. The leadframe package of claim 5, wherein a thickness of the dielectric build-up film is between 40 and 60 microns.

7. The leadframe package of claim 1, wherein the dielectric build-up film is integrated with the integrated circuit substrate.

8. The leadframe package of claim 1, wherein each conductive wire bond pad providing an electrical connection to the plurality of conductive leads is less than 10,000 square microns.

9. The leadframe package of claim 1, wherein the conductive leads are formed by a molded copper connection (C2iM) process.

10. The leadframe package of claim 1, wherein the integrated circuit is in a flip-chip configuration such that electrical contact points on the integrated circuit are between the first surface of the integrated circuit substrate and the integrated circuit.

11. The leadframe package of claim 10, wherein electrical connections are established between the electrical contact points on the integrated circuit and the plurality of conductive wire bond pads on the integrated circuit substrate.

12. The leadframe package of claim 11, further comprising one or more adhesive connectors bonding the integrated circuit to the first surface of the integrated circuit substrate.

13. The leadframe package of claim 1, wherein the integrated circuit is embedded in the leadframe package between a package mold and the integrated circuit substrate.

14. The leadframe package of claim 13, wherein the integrated circuit is embedded between the package mold and the integrated circuit substrate using a panel-level packaging technique.

15. A method of manufacturing a leadframe package comprising: forming an integrated circuit substrate comprising at least a first surface and a second surface opposite the first surface, the integrated circuit substrate defining a plurality of conductive leads providing an electrically conductive path between the second surface and the first surface; forming a conductive trace within an integrated circuit substrate; disposing an integrated insulating layer on the integrated circuit substrate, the integrated insulating layer forming a first surface of the integrated circuit substrate, the integrated insulating layer defining a plurality of conductive wire bond pads, the plurality of conductive wire bond pads being associated with and providing electrical connection to the plurality of conductive leads; and positioning an integrated circuit on the first surface of the integrated circuit substrate, wherein the integrated circuit is electrically isolated from the conductive trace by the integrated insulating layer, wherein the integrated circuit is positioned to determine an electromagnetic property of the conductive trace, and wherein the integrated circuit is electrically connected to the plurality of conductive leads.

16. The method of claim 15, wherein the integrated insulating layer comprises a dielectric build-up film.

17. The method of claim 15, wherein the integrated circuit is configured to determine a current flowing through the conductive trace based at least in part on the electromagnetic property.

18. The method of claim 15, wherein the integrated circuit substrate including the plurality of conductive leads and the conductive trace is formed by a molded copper connection (C2iM) process.

19. The method of claim 15, wherein the integrated circuit is positioned such that a first portion of the conductive trace within a projection of a periphery of the integrated circuit has a smaller cross-sectional area than a second portion of the conductive trace outside the projection of the periphery of the integrated circuit.

20. An electrical system comprising: a leadframe package comprising: an integrated circuit substrate comprising at least a first surface and a second surface opposite the first surface, the integrated circuit substrate further comprising: a plurality of conductive leads providing a conductive path between the second surface and the first surface; a conductive trace formed within the integrated circuit substrate; and an integrated insulating layer forming the first surface of the integrated circuit substrate, the integrated insulating layer defining a plurality of conductive wire bond pads, the plurality of conductive wire bond pads being associated with and providing electrical connection to the plurality of conductive leads; and an integrated circuit electrically isolated from the conductive trace by the integrated insulating layer, wherein the integrated circuit is positioned to determine an electromagnetic property of the conductive trace, and wherein the integrated circuit is electrically connected to the plurality of conductive leads; and a printed circuit board (PCB) comprising a current-carrying conductive path and a plurality of conductive contact surfaces, wherein the current-carrying conductive path is configured to interface with the conductive trace through two or more of the plurality of conductive surfaces.

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