Molded power semiconductor package for enhanced thermal handling

Abstract

The invention relates to a molded power semiconductor package for enhanced thermal operation. A semiconductor device includes: a die carrier; a first semiconductor die including at least a first load electrode and a second load electrode, where the first semiconductor die is mounted on the die carrier, where the first load electrode is electrically connected to the die carrier; a first set of external connections electrically and thermally connected to the die carrier; and a second set of external connections spaced apart from the die carrier and electrically connected to the second load electrode, where a total lead size of the second set of external connections is greater than a total lead size of the first set of external connections.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The current rating in a TO package is limited by chip technology or drain pad area. When the current rating is extended beyond a certain point (typically ~150A in TO 247), wider leads are required.

[0003] For solar energy applications, high lead / pin lengths are typically required. In the following description, the terms "pin," "lead," and "connector" may be used synonymously.

[0004] When the current carrying capacity limit is exceeded, ohmic heating of the pins will lead to new overheating conditions, i.e., the pin temperature exceeds the allowable temperature. Furthermore, the pin temperature may exceed the allowable temperature of the board material (e.g., FR4) at the board connection point. This effect is most pronounced at the source lead because there is no direct cooling connection to a possible heatsink. Typically, the source pins inside the package are cooled via leads into the board, while the drain pins are cooled via a heatsink (i.e., via drain pads).

[0005] Therefore, enhanced cooling of the source connection is usually required. Summary of the Invention

[0006] According to a first aspect of this disclosure, a semiconductor device of the aforementioned type is provided, wherein the total wire size of the second set of external connectors is greater than the total wire size of the first set of external connectors.

[0007] To ensure a certain current carrying capacity for each conductive element in the load current path of a semiconductor device, a minimum conductor size, i.e., a minimum conductive cross-section, is required throughout the entire load current path. However, when the semiconductor device is switched on, all components in the load current path heat up due to their own ohmic resistance. Therefore, heat energy is generated throughout the load current path that needs to be dissipated into the surrounding environment. However, there are significant differences in thermal conductivity along the load current path. In particular, the thermal conductivity on the source side is typically lower than that on the drain side. This is because the isolation characteristics on the source side differ from those on the drain side. Therefore, the effective temperature on the source side (i.e., at the external source lead) is higher than the effective temperature on the drain side (i.e., at the external drain lead).

[0008] By designing an asymmetrical number of leads with equal lead sizes, additional source leads can be introduced, which can be connected to an isolated heatsink because no electrical contact is required. Therefore, the lead size at the source connection is larger than the lead size at the drain connection. Specifically, the lead size of each connector in the first set of external connectors is equal to the lead size of each connector in the second set of external connectors. However, the total lead size (i.e., the total conductive cross-section of the second set of external connectors) is greater than the total conductive cross-section of the first set of external connectors. This allows for better thermal management of the source pillars and allows for a higher overall current carrying capacity in the discrete package.

[0009] An asymmetrical lead ratio, i.e., an unequal number of source and drain leads, allows for thermal decoupling. For example, a two-pin input (drain) and a three-pin output (source) allow individual contact with a single pin without reducing the current carrying capacity of the load current path.

[0010] Additional pins can be used, for example, to contact an isolation heatsink on a printed circuit board (PCB). Therefore, the heat flux is dispersed, i.e., distributed among multiple source pins. For example, four pins to two pins reduce the thermal load by 50%, and three pins to two pins reduce the thermal load by 33%.

[0011] In one embodiment, the semiconductor device includes an encapsulation that encapsulates at least a portion of a first semiconductor die and at least a proximal end of each external connector, such that the distal ends of the external connectors of both the first set of external connectors and the second set of external connectors protrude from the encapsulation.

[0012] Since the proximal ends of both the second and first sets of external connectors are buried within the encapsulation, the heat generated by the ohmic resistance within the proximal portion of each set of external connectors cannot be effectively dissipated because the encapsulation acts as an insulator. Therefore, the heat generated at the proximal portion of the external connectors needs to be guided out of the encapsulation via the external connector itself toward its distal end. Specifically, at the second set of external connectors, which could be source connections, there is no available direct connection to the die pads that can be used as heat sinks. Furthermore, the external source connections are heated by possible internal connections that transfer heat from the source electrode to the source connections. That is, regarding the portion of the load current path from the source electrode of the semiconductor die toward the distal end of the external source connections, there is no possibility of further cooling other than the external connectors themselves. By providing asymmetrical conductor dimensions along the load current path, i.e., increased conductor dimensions at the external source connections, heat transfer from inside the encapsulation to the outside of the encapsulation is enhanced.

[0013] As a result of the above, a molded power semiconductor package with an asymmetric pin / lead layout is provided for thermally enhanced operation.

[0014] In this embodiment, the die carrier is a lead frame, which includes a first portion forming the die pads. The die carrier can be a lead frame made of a monolithic ground metal. However, the die carrier can also be ceramic, or AMB, or DCB, or an isolation metal substrate (IMS), or any other interposer. Additionally, any isolation technology, such as FullPak, advanced isolation, or thermal interface material (TIM) sheets, can be applied to the opposite sides of the die carrier. The die carrier can also contact or be attached to the thermal interface material (TIM).

[0015] In one embodiment, the second set of external connectors includes at least one additional connector, relative to the first set of external connectors.

[0016] Specifically, at least one additional connector is a thermal connector used to facilitate heat transfer from the interior of the encapsulation to the surrounding environment. By providing the additional connector, an asymmetrical pin count is provided. The pin dimensions are the same, but the additional pins enlarge the wire size at the source connection compared to the wire size at the drain connection.

[0017] In one embodiment, the semiconductor device includes lead posts attached to a second set of external connectors, the lead posts and the second set of external connectors forming an integral component. The second set of external connectors can be attached to the lead posts, which integrate all connectors into a single integral component. Thus, the lead posts can act as heat sinks.

[0018] In this embodiment, the first set of external connectors is an integral part of the first portion of the leadframe. The drain lead can be formed by grounding together with the first portion of the leadframe, and thus can be thermally and electrically connected integrally with the die pad. Therefore, the drain pin is cooled via the drain pad connection. In particular, the drain lead can be cooled via a heatsink that can be coupled to the leadframe. The first set of external connectors can have a downward setting toward the die carrier, such that the drain lead is through-hole and at the same height as the source lead.

[0019] In this embodiment, the semiconductor device is a single-in-line package (SIP), wherein the first set of external connectors and the second set of external connectors are laterally spaced apart by a distance greater than the distance between the external connectors in the first set of external connectors and the distance between the external connectors in the second set of external connectors.

[0020] In a single-in-line package, all external connectors are arranged in a row on a common side (i.e., the common portion of the package's circumferential surface). That is, all leads project substantially in the same direction and substantially parallel to each other onto the same surface of the package body. In this embodiment, the source and drain leads need to be spaced apart to maintain a gap distance based on voltage difference. Specifically, the drain leads may be arranged on a first side of the common portion of the circumferential surface, and the source leads and possible control leads may be arranged on a second, opposite side of the common portion of the circumferential surface. The drain leads are spaced apart from the group of source leads and possible control leads, thus forming an asymmetrical through-hole pin layout at the package body.

[0021] A pocket can be arranged in the circumferential surface between the first set of external connectors and the second set of external connectors of the encapsulation to enhance the required creepage distance along the surface between the drain and source connectors of the mold body.

[0022] In this embodiment, the outermost surface of the die carrier is exposed from the encapsulation. Exposed portions of the die carrier may be formed to facilitate thermal bonding with other devices. These exposed portions of the die carrier may also be referred to as exposed die pads.

[0023] Specifically, the outermost surface of the die carrier can be configured to attach to a heat sink. A thermal interface material can be disposed on the exposed outermost surface of the die carrier to connect the semiconductor device to the heat sink.

[0024] In this embodiment, the lateral dimension of each connector in the first set of external connectors is equal to the lateral extension of each connector in the second set of external connectors. That is, the connectors can have equal dimensions. The connectors can also have the same conductive cross-section, i.e., wire size. With equal connector dimensions, attachment to a second-level device (e.g., a printed circuit board) is convenient because only one size of the second-level connector (e.g., a through-hole on a PCB) is required. This reduces manufacturing effort on the customer side.

[0025] In an embodiment, at least one additional connector is configured to attach to a heat sink, such as to a copper-plated insulating area on a printed circuit board (PCB). Because the additional pin is not required for electrical purposes—that is, not for carrying drain-source current—it can be used as a pin term. This means that the additional pin is used only for thermal purposes and can therefore be used to connect to a heat sink to cool the source connection.

[0026] In one embodiment, the die carrier includes a second portion forming a tie-bar, wherein the second portion is arranged on the opposite side relative to the external connector. The tie-bar is arranged on the side of the lead frame opposite to the side of the attachment pin. The tie-bar holds the array of lead frames in place during the manufacturing process. Specifically, the tie-bar is a connection between the lead frames during the manufacturing process to provide mechanical stability. It prevents rotation of the lead frames during the manufacturing process and thus misalignment between the lead frames and the semiconductor die.

[0027] In an embodiment, the semiconductor device includes a second semiconductor die attached to a die carrier, wherein the second semiconductor die is electrically and thermally connected to lead posts via internal electrical connections, wherein the internal electrical connections are formed, for example, by wire bonding, wedge bonding, pin bonding, or clamping. In particular, materials such as Al, Cu, or Ag can be used for the internal electrical connections. The second semiconductor die can be a diode or a second transistor. Combinations of transistor dies and dies or several transistors are possible. For example, the first and second semiconductor dies can also form a half-bridge arrangement.

[0028] In the embodiments, the first semiconductor die is one of MOSFET, IGBT, JFET, SFET, bipolar transistor, or GaNHEMT; and the second semiconductor die is a diode.

[0029] In one embodiment, the lead post includes a first portion and a second portion, with an external connector from a second set of external connectors attached to the first portion, and the second portion extending between the second set of external connectors and the first set of external connectors. An internal electrical connector is attached from a second semiconductor die to the second portion. Therefore, the lead post is subdivided into two portions, each for attaching an internal electrical connector from a corresponding semiconductor die.

[0030] In one embodiment, the external connector in the second set of external connectors is attached to the lead post via a trapezoidal interconnect portion with a mold lock. The trapezoidal shape of the interconnect portion and the reduction in effective via size reduce the effective conductive cross-section at the interconnect portion. Conversely, a circular mold lock may be necessary to mitigate the delamination effect between the external connector and the molding compound at the circumferential surface of the molding compound.

[0031] In this embodiment, the second portions of the lead posts are staggered to maintain the maximum possible wire size toward the interconnect portion. By staggering the second portions of the lead posts, the effective conductive cross-section as seen by the input current is increased. Therefore, a larger heat-dissipating surface with a heat dissipation effect can be facilitated.

[0032] In addition, the semiconductor device may include an overcurrent protection circuit (OCP-IC) and / or a gate driver circuit. Both the OCP-IC and the gate driver may be attached to the lead frame along with the first and second semiconductor dies. Additional external electrical connections for controlling the respective ICs may be located in appropriate positions.

[0033] In one embodiment, the first semiconductor die includes a control electrode and a third set of external connectors, wherein the third set of external connectors includes at least one control connector connected to the control electrode of the first semiconductor die, and wherein the third set of external connectors is laterally separated from the first set of external connectors by a second set of external connectors.

[0034] According to a second aspect of this disclosure, a single-in-line package (SIP) is provided, wherein a set of external drain connections, a set of external source connections, and a set of external control connections are arranged along a respective circumferential package surface, such that the external connections are arranged asymmetrically, wherein the total lead size of the set of external source connections is greater than the total lead size of the set of external drain connections. The external connections may be arranged asymmetrically in the following senses: asymmetrical lead count, asymmetrical lead layout along one edge of the SIP, and / or asymmetrical lead size along the load current path (particularly with respect to the external source and drain connections).

[0035] According to a third aspect of this disclosure, a system is provided that includes a first semiconductor device and a second semiconductor device according to a first or second aspect of this disclosure, wherein the first semiconductor device and the second semiconductor device are electrically connected in parallel and arranged such that the exposed outermost surfaces of each die carrier of the semiconductor device are arranged in the same plane.

[0036] In an embodiment of the third aspect of this disclosure, the system further includes a common heat sink to which the exposed outermost surface of each die carrier of the first semiconductor device and the second semiconductor device is thermally coupled. Attached Figure Description

[0037] An exemplary embodiment of this disclosure is described with reference to the following figures:

[0038] Figure 1a and Figure 1b A semiconductor device according to this disclosure is shown.

[0039] Figure 2a An internal view of a semiconductor device according to this disclosure is shown.

[0040] Figure 2b It shows Figure 2a An extended view of the lead post.

[0041] Figure 3a and Figure 3b A cross-sectional view of a semiconductor device according to this disclosure is shown.

[0042] Figure 4 A schematic diagram of a connection scheme for an external connector of a semiconductor device according to the present disclosure is shown. Detailed Implementation

[0043] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples in which the invention can be practiced. It should be understood that, unless otherwise specifically stated, the features and principles described with respect to the various examples can be combined with each other. In the claims, the designation of certain elements as "first element," "second element," "third element," etc., should not be construed as enumeration. Rather, such designation is only used to address different "elements." That is, for example, the presence of a "third element" does not require the presence of "first element" and "second element." The wire as described herein may be a single conductive element or may comprise at least two separate conductive elements connected in series and / or in parallel. The wire may comprise metallic and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The wire may have a resistivity independent of the direction of the current flowing through it. The semiconductor body as described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included in a semiconductor chip. The semiconductor body has electrically connected pads and includes at least one semiconductor element having electrodes. The pads are electrically connected to the electrodes, which includes the pads being electrodes and vice versa.

[0044] refer to Figure 1a The image shows a semiconductor device 1. The semiconductor device 1 includes a mold body 2 formed of an encapsulant. The semiconductor device 1 is a single-in-line package, meaning that all external connectors protrude from the mold body at a common surface of the semiconductor device 1, which is a circumferential surface.

[0045] Semiconductor device 1 includes a first set of external connectors 3. The first set of external connectors 3 are drain connectors of semiconductor device 1. Furthermore, semiconductor device 1 includes a second set of external connectors 4. The second set of external connectors 4 are source connectors of semiconductor device 1. Additionally, semiconductor device 1 includes a third set of external connectors 5.

[0046] External connectors are manifested as leads or pins protruding from the mold body 2 and configured to couple the circuit system from the interior of the mold body to another external device (not shown).

[0047] The second set of external connectors 4 is laterally spaced from the first set of external connectors 3 to maintain the required gap distance between different voltage domains of the external connectors. In particular, the gap distance is greater than the distance between the leads of the first set of external connectors 3 and the distance between the leads of the second set of external connectors 4.

[0048] In order to increase the creepage distance along the surface between the first set of external connectors 3 and the second set of external connectors 4 along the mold body 2, the recess / notch 6 is arranged in the circumferential surface between the first set of external connectors 3 and the second set of external connectors 4.

[0049] The second set of external connectors 4 includes three leads, while the first set of external connectors 3 includes only two leads. Therefore, the drain and source connectors have an asymmetrical pin count. Consequently, the current carrying capacity of the second set of external connectors 4 is greater than that of the first set of external connectors 3. As a further result, the current carrying capacity is not constant along the load current path.

[0050] The leads of the first set of external connectors 3 and the leads of the second set of external connectors 4 have the same spacing, that is, the same spacing between them.

[0051] The third set of external connectors 5 is arranged adjacent to the second set of external connectors 4. The third set of external connectors 5 is a control connector that connects to the control circuit system inside the mold body 2. For example, the control connector 5 can be connected to the gate electrode or gate driver circuit of a semiconductor die inside the mold body 2.

[0052] The cross-section of the lead wire of the first set of fixed external connectors 3 is equal to the cross-section of the lead wire of the second set of external connectors 4.

[0053] Figure 1b Shown from the rear view Figure 1a Semiconductor device 1. Pin layout and Figure 1a The same as in the previous section. On the back side, the exposed portion of the die carrier 7 (i.e., the exposed die pad 7a) is visible. The exposed die pad 7a forms a flat surface with the outermost portion of the mold body 2. Thus, the semiconductor device 1 is configured to be attached to the planar heat sink by abutting the exposed die pad 7a against the corresponding surface of the heat sink.

[0054] Figure 2a An internal view of a semiconductor device 1 according to an embodiment of the present disclosure is shown.

[0055] Semiconductor device 1 includes an encapsulation forming a mold body 2. Inside the encapsulation, a lead frame 8 is provided, including a first portion forming a die pad 7a. A first semiconductor die 9 is attached to the lead frame 8. The first semiconductor die 9 includes a first load electrode 9a (not visible) serving as a drain electrode. The first semiconductor die 9 is attached to the die pad 7a by a die-attach adhesive (e.g., soft soldering). The first semiconductor die 9 also includes a second load electrode 10 serving as a source electrode. Furthermore, the first semiconductor die 9 includes at least one control electrode 11, which may be a gate or a temperature sensing electrode.

[0056] The semiconductor device 1 also includes a second semiconductor die 12. The second semiconductor die 12 is a diode and also has first and second load electrodes 13, wherein the first load electrode is coupled to a die pad 7a, and wherein the second load electrode 13 is disposed on the uppermost surface of the second semiconductor die 12 opposite to the first load electrode (not visible).

[0057] The first set of external connectors 3, namely the external drain connectors, forms an integral component with the die pad 7a. The first set of external connectors 3 is electrically connected to the first load electrode 9a of the first semiconductor die 9 and the first load electrode of the second semiconductor die 12.

[0058] The first mold lock 14 is located at the connection portion of the first set of external connectors 3. Furthermore, the semiconductor device 1 includes lead posts 15. The lead posts 15 and the second set of external connectors 4 form an integral component. The following describes the process in conjunction with... Figure 2b Describe lead post 15 in more detail.

[0059] The second load electrode 10 of the first semiconductor die 9 is electrically connected to the first portion 16 of the lead post 15 via a first set of internal electrical connections 17 (e.g., bonding wires).

[0060] The second load electrode 13 of the second semiconductor die 12 is electrically coupled to the second portion 18 of the lead post 15 via a second set of internal electrical connections 19 (e.g., bonding wires).

[0061] At least one control electrode 11 is electrically connected to a third set of external connectors 5 via a third set of internal electrical connectors 20.

[0062] The mold body 2 includes a circumferential surface 21. All electrical connectors protrude from a first portion 22 of the circumferential surface 21, thereby forming a single in-line package (SIP). Opposite to the first portion 22 of the circumferential surface 21, a second portion 23 of the circumferential surface 21 is provided. The second portion 23 of the circumferential surface 21 includes stepped recesses 24. The recesses 24 are located at the outer corners of the mold body 2. The second portion of the lead frame forming tie rod 25 protrudes from the surface portion of each recess 24. The tie rod 25 is an integral part of the ground metal of the lead frame 8.

[0063] A second mold lock 26 is provided at the outermost part of the second part of the lead frame 8.

[0064] The first set of external connectors 3 includes two leads. The leads of the first set of external connectors are spaced apart by a first distance d. The first distance d can also be referred to as the lead pitch.

[0065] The second set of external connectors 4 includes three leads. Therefore, the second set of external connectors 4 includes more leads than the first set of external connectors 3. The leads of the second set of external connectors 4 are also spaced apart from each other by a first distance d. However, the first set of external connectors 3 and the second set of external connectors 4 are spaced apart by a larger distance D. The larger distance D is the gap distance between the external source connection and the external drain connection of the semiconductor device 1. The gap distance D is greater than the first distance d. In order to increase the creepage distance between the external source connection and the external drain connection, a notch 6 is provided in the circumferential surface 21 of the mold body 2.

[0066] The leads of the first set of external connectors 3 and the leads of the second set of external connectors 4 have the same cross-section, i.e., the same width and thickness, and are made of the same material. Therefore, each lead in the first set of external connectors 3 and the second set of external connectors 4 has the same conductor size, i.e., the same conductive cross-section.

[0067] Because the second set of external connectors 4 includes at least one more lead than the first set of external connectors, the total effective conductor size of the second set of external connectors 4 is greater than the total effective conductor size of the first set of external connectors 3. The external source connector has a larger conductor size than the external drain connector.

[0068] Figure 2b It shows Figure 2a Extended view of lead post 15.

[0069] The first portion 16 of the lead post 15 is integral with the second set of external connectors 4. At the first portion 16 of the lead post 15, a first set of internal electrical connectors 17 (i.e., first bonding wires) are electrically attached to the lead post 15. Each lead of the second set of external connectors 4 is integrally attached to the first portion 16 of the lead post via an interconnect portion 27. The interconnect portion 27 has a trapezoidal shape. That is, starting from each lead, the cross-section of the lead widens towards the first portion 16 of the lead post 15. The interconnect portion 27 includes a third mold lock 28. Due to the shape of the interconnect portion 27, despite the third mold lock 28, the electrically effective (i.e., conductive) cross-section of the lead remains constant throughout the interconnect portion 27.

[0070] The second portion 18 of the lead post 15 extends away from the second set of external connectors 4. The second portion 18 of the lead post 15 includes a stepped portion extending away from the second set of external connectors 4. At the second portion 18 of the lead post 15, the second set of internal electrical connectors 19 are electrically coupled to the lead post 15.

[0071] Figure 3a and Figure 3b A cross-sectional view of a semiconductor device 1 according to the present disclosure is shown.

[0072] exist Figure 3a In the process, a first amount of heat energy W1 is generated along the drain side of the load current path (i.e., the current path between the external drain connector 3 and the first semiconductor die 9). The first semiconductor die 9 is coupled to the die carrier 7 via its first load electrode 9a. As a result, the first semiconductor die 9, the die carrier 7, and the external drain connector 3 become hot. However, the heat energy W1 is dissipated to the surrounding environment via the die pads 7a exposed on the back side of the semiconductor device 1. That is, the first part of the heat energy W1 is dissipated into the surrounding environment. cool,dp It is led out from semiconductor device 1 through die pad 7a, wherein the second part W cool,D It is led out from the semiconductor device 1 via the external drain connector 3. As a result, the external drain connector 3 has a relatively low temperature because the first part of the heat energy W1 generated on the drain side of the load current path is W cool,dp The exposed die pad 7a dissipates heat. Since the external drain connector 3 forms an integral part of the lead frame 8 and therefore has a good thermal connection to the die pad 7a, the external drain connector 3 is cooled via the die pad 7a.

[0073] exist Figure 3b In the process, a second amount of heat energy W2 is generated along the source side of the load current path (i.e., the current path between the external source connector 3 and the first semiconductor die 9). The load current is constant along the load current path, that is, it is constant along the path from the external drain connector 3 through the semiconductor die 9 to the external source connector 4.

[0074] Because almost all the source sides of the semiconductor die and the load current path are encapsulated by the molding compound, the heat energy W2 cannot be effectively conducted to the outside of the semiconductor device 1. That is, although the amount of heat energy generated is roughly the same (W1 = W2), less cooling occurs on the source side of the load current path than on the drain side of the load current path.

[0075] Therefore, only a portion of the source-side load current path allows heat energy to be drawn from semiconductor device 1, i.e., dissipated into the surrounding environment. This portion is the second set of external connectors 4, i.e., the external source connectors. Heat energy W cool,SThe transfer of heat is achieved by the source leads. Since the leads of the second set of external connectors 4 are electrically and thermally connected to the first set of internal electrical connectors 17 via their connected lead posts 15, the corresponding portion 16 of the lead post 15 will receive even more heat. First, it receives heat generated by its own ohmic resistance. Second, it receives an additional amount of heat from the first set of internal electrical connectors 17 via thermal convection. Therefore, the second set of external connectors 4 becomes hot through ohmic resistance and convection, and is well isolated from the surrounding environment, at least at its proximal end, by being buried within the molding compound. This results in a higher temperature at the source connector compared to the drain connector.

[0076] It should be noted that, Figure 3b In the diagram, the first set of external connectors 3 and the second set of external connectors 4 are shown stacked vertically. However, this is only for better supervision. In a single in-line package (SIP), all connectors are arranged in a row, adjacent to each other.

[0077] Figure 4 A schematic diagram of the second-stage interconnection scheme for semiconductor device 1 is shown. Semiconductor device 1, which may be THD or SMD, is mounted on a printed circuit board (PCB) 29. A first set of external connectors 3 are connected to a first portion 30 of the PCB 29, which may be the drain portion. A second set of external connectors 4 includes three leads, wherein a first lead 31 is connected to a second portion 32 of the PCB, and a second lead 33 is connected to a third portion 34 of the PCB.

[0078] The second portion 32 of the PCB serves as an isolation section for a heat sink. The second portion 32 of the PCB can be an isolation copper-plated area on the PCB 29. To connect to the second portion 32 of the PCB, the shape of the first lead 31 can differ from that of the second lead 33. For example, the first lead 31 can include a step, a downsloping arrangement, a J-shape, a gull-wing shape, or can be bent in any suitable form.

[0079] List of reference numerals

[0080] 1. Semiconductor devices

[0081] 2. Mold body

[0082] 3. First set of external connectors

[0083] 4. Second set of external connectors

[0084] 5. Third set of external connectors

[0085] 6. Notches / recesses

[0086] 7. Core Carrier

[0087] 7a. Die pads

[0088] 8. Lead Wire Frame

[0089] 9. First Semiconductor Die

[0090] 9a. First load electrode

[0091] 10. Second load electrode / source electrode

[0092] 11. Control Electrode

[0093] 12. Second semiconductor die

[0094] 13. Second load electrode of the second semiconductor die

[0095] 14. First mold lock

[0096] 15. Lead post

[0097] 16. The first part of the lead post

[0098] 17. First internal electrical connection

[0099] 18. The second part of the lead post

[0100] 19. Second internal electrical connection

[0101] 20. Third internal electrical connection

[0102] 21. Circumferential surface of the mold body

[0103] 22. The first part of the circumferential surface

[0104] 23. The second part of the circumferential surface

[0105] 24. Stepped recess

[0106] 25. Tie rod

[0107] 26. Second mold lock

[0108] 27. Interconnection section

[0109] 28. Third mold lock

[0110] 29. PCB

[0111] 30. The first part of the PCB

[0112] 31. First lead / hot pin of the second set of external connectors

[0113] 32. The second part of the PCB

[0114] 33. The second lead of the second set of external connectors

[0115] 34. The third part of the PCB

Claims

1. A semiconductor device (1), comprising: Core carrier (7); A first semiconductor die (9) includes at least a first load electrode (9a) and a second load electrode (10), wherein the first semiconductor die (9) is mounted on the die carrier (7), and wherein the first load electrode (9a) is electrically connected to the die carrier (7). The first set of external connectors (3) are electrically and thermally connected to the core carrier (7); The second set of external connectors (4) is spaced apart from the core carrier (7) and electrically connected to the second load electrode (10); The total wire size of the second set of external connectors (4) is greater than the total wire size of the first set of external connectors (3).

2. The semiconductor device (1) according to claim 1 further includes an encapsulation that encapsulates at least a portion of the first semiconductor die (9) and at least the proximal end of each of the external connectors, such that the distal ends of the external connectors of both the first set of external connectors (3) and the second set of external connectors (4) protrude from the encapsulation.

3. The semiconductor device (1) according to claim 1 or 2, wherein, The die carrier (7) is a lead frame (8), which includes a first part forming the die pad (7a).

4. The semiconductor device (1) according to any of the preceding claims, wherein, The second set of external connectors (4) includes at least one additional connector, relative to the first set of external connectors (3).

5. The semiconductor device (1) according to claim 4, wherein, The at least one additional connector is a thermal connector used to facilitate heat transfer from the interior of the encapsulation to the surrounding environment.

6. The semiconductor device (1) according to any of the preceding claims further includes a lead post (15) attached to the second set of external connectors (4), the lead post (15) and the second set of external connectors (4) forming an integral component.

7. The semiconductor device (1) according to claim 3, wherein, The first set of external connectors (3) and the first part of the lead frame (8) are an integral part.

8. The semiconductor device (1) according to any of the preceding claims, wherein, The semiconductor device (1) is a single in-line package (SIP), wherein the first group of external connectors (3) and the second group of external connectors (4) are laterally spaced apart by a distance greater than the distance between the external connectors in the first group of external connectors (3) and the distance between the external connectors in the second group of external connectors (4).

9. The semiconductor device (1) according to claim 2, wherein, The outermost surface of the core carrier (7) is exposed from the encapsulation.

10. The semiconductor device (1) according to claim 9, wherein, The outermost surface of the die carrier (7) is configured to be attached to a heat sink.

11. The semiconductor device (1) according to any of the preceding claims, wherein, The first set of external connectors (3) has a downward orientation toward the core carrier (7).

12. The semiconductor device (1) according to any of the preceding claims, wherein, The cross-section of each connector in the first group of external connectors (3) is equal to the cross-section of each connector in the second group of external connectors (4).

13. The semiconductor device (1) according to claim 4, wherein, The at least one additional connector is configured to be attached to a heat sink, wherein the heat sink includes a copper-plated insulating area on a printed circuit board (29).

14. The semiconductor device (1) according to claim 2, wherein, The second set of external connectors (4) is spaced apart from the first set of external connectors (3), and wherein a notch (6) is arranged in the circumferential surface (21) of the encapsulation between the first set of external connectors and the second set of external connectors.

15. The semiconductor device (1) according to claim 1, wherein, The core carrier (7) includes a second portion forming a tie rod (25), wherein the second portion is arranged on the opposite side relative to the external connector.

16. The semiconductor device (1) according to claim 6, further comprising a second semiconductor die (12) attached to the die carrier (7), wherein, The second semiconductor die (12) is electrically and thermally connected to the lead post (15) via an internal electrical connector (19), wherein the internal electrical connector (19) is formed by one of wire bonding, wedge bonding, nail head bonding, or clamping.

17. The semiconductor device (1) according to claim 16, wherein, The lead post (15) includes: a first portion (16) to which an external connector of the second set of external connectors (4) is attached; and a second portion (18) extending between the second set of external connectors (3) and the first set of external connectors (4), wherein an internal electrical connector (19) is attached from the second semiconductor die (12) to the second portion.

18. The semiconductor device (1) according to claim 6, wherein, The external connector in the second set of external connectors (4) is attached to the lead post (15) via a trapezoidal interconnection portion (27) having a mold lock (28).

19. The semiconductor device (1) according to claim 17 or 18, wherein, The second portion (18) of the lead post (15) is staggered to maintain the maximum possible wire size toward the interconnect portion (27).

20. The semiconductor device (1) according to any of the preceding claims, wherein, The first semiconductor die (9) is one of MOSFET, IGBT, JFET, SFET, bipolar transistor, or GaN HEMT; and the second semiconductor die (12) is a diode.

21. The semiconductor device (1) according to any of the preceding claims further includes an overcurrent protection circuit (OCP-IC) and / or a gate driver circuit.

22. The semiconductor device (1) according to any of the preceding claims, wherein, The first semiconductor die (9) further includes: a control electrode (11); and a third set of external connectors (5), wherein the third set of external connectors (5) includes at least one control connector (20) connected to the control electrode (11) of the first semiconductor die (9), and wherein the third set of external connectors (5) is laterally separated from the first set of external connectors (3) by the second set of external connectors (4).

23. A single in-line package (SIP), comprising: A set of external drain connectors (3), a set of external source connectors (4), and a set of external control connectors (5). The set of external drain connectors (3), the set of external source connectors (4), and the set of external control connectors (5) are arranged along their respective circumferential packaging surfaces, resulting in an asymmetrical arrangement of the external connectors. The total wire size of the set of external source connectors is greater than the total wire size of the set of external drain connectors.

24. A system comprising two semiconductor devices (1) according to any one of claims 1-22, wherein, Two semiconductor devices (1) are electrically connected in parallel and are arranged such that the exposed outermost surfaces of the die carriers of each of the two semiconductor devices are arranged in the same plane.

25. The system of claim 24, further comprising a common heat sink, wherein the exposed outermost surface of each die carrier of the two semiconductor devices is thermally coupled to the common heat sink.

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