Package and method of forming same

Abstract

The embodiment of the invention provides a packaging piece and a manufacturing method thereof. The package includes a semiconductor die, an insulating layer encapsulation, and a redistribution structure. The redistribution circuit structure includes a dielectric layer and a stacked via structure embedded in the dielectric layer. The stacked via structure includes a first via plug, a first diffusion layer including a plurality of first dopants, a second via plug, and a second diffusion layer including a plurality of second dopants. The first via plug includes a plurality of first dopants dispersed within a first metallic material of the first via plug, and the second via plug includes a plurality of second dopants dispersed within a second metallic material of the second via plug.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a package with a redistribution structure and a method of forming the same. BACKGROUND

[0002] During a packaging process of a semiconductor die, a redistribution structure including a metal wiring pattern, a pad, and a via is formed for wiring and interconnecting the die and / or semiconductor devices in a package. SUMMARY

[0003] A package of an embodiment of the present disclosure includes a molded structure including a first semiconductor die and a second semiconductor die laterally surrounded by an insulating encapsulant, and a redistribution structure disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die, wherein the redistribution structure includes a dielectric layer and a stacked via structure in the dielectric layer, wherein the stacked via structure includes a first diffusion layer including a first dopant, wherein the first dopant includes silver, zinc, or manganese, a first via plug disposed on the first diffusion layer, wherein the first via plug includes a first metal material and the first dopant dispersed within the first metal material, a second diffusion layer disposed on the first via plug, wherein the second diffusion layer includes a second dopant, and a second via plug disposed on the second diffusion layer, wherein the second via plug includes a second metal material and the second dopant dispersed within the second metal material, and the second metal material includes copper.

[0004] A package of an embodiment of the present disclosure includes a semiconductor die, an insulating encapsulant laterally surrounding the semiconductor die, and a redistribution structure disposed on the semiconductor die and the insulating encapsulant and electrically connected to the semiconductor die, wherein the redistribution structure includes a first dielectric layer having a first opening extending through the first dielectric layer, a first diffusion layer disposed on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant, a first conductive via plug disposed on the first diffusion layer, wherein the first conductive via plug includes the first dopant dispersed therein, a second dielectric layer disposed on the first dielectric layer and having a second opening exposing the first conductive via plug, a second diffusion layer disposed on the second dielectric layer and covering the second opening, wherein the second diffusion layer includes a second dopant, a second conductive via plug disposed on the second diffusion layer, wherein the second conductive via plug includes the second dopant dispersed therein, and a third dielectric layer disposed on the second dielectric layer and partially covering the second conductive via plug.

[0005] A method of forming a package includes providing a semiconductor die, forming an insulative encapsulation surrounding the semiconductor die, and forming a redistribution structure over the insulative encapsulation and on the semiconductor die, where forming the redistribution structure includes forming a first dielectric layer having a first opening extending through the first dielectric layer, forming a first diffusion layer on the first dielectric layer and covering the first opening, where the first diffusion layer includes a first dopant, forming a first conductive via plug on the first diffusion layer over the first dielectric layer, where the first conductive via plug fills in the first opening with the first diffusion layer in between, and the first conductive via plug includes the first dopant dispersed therein, forming a second dielectric layer on the first dielectric layer and having a second opening exposing the first conductive via plug, forming a second diffusion layer on the second dielectric layer and covering the second opening and the exposed first conductive via plug, where the second diffusion layer includes a second dopant, forming a second conductive via plug on the second diffusion layer over the second dielectric layer, where the second conductive via plug fills in the second opening with the second diffusion layer in between the first conductive via plug and the second conductive via plug, and the second conductive via plug includes the second dopant dispersed therein, and forming a third dielectric layer on the second dielectric layer and partially covering the second conductive via plug. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that various features can not be to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the clarity of discussion.

[0007] Figures 1-6 is a schematic cross-sectional view of various stages of a manufacturing method of forming a semiconductor package structure in accordance with some example embodiments of the present disclosure.

[0008] Figures 7A-7F is a schematic enlarged cross-sectional view of various stages in a manufacturing method for forming a stacked via in a redistribution structure in accordance with some example embodiments of the present disclosure.

[0009] Figure 8 is a schematic cross-sectional view of a portion of a semiconductor package structure having a stacked via in accordance with example embodiments of the present disclosure.

[0010] Figure 9 A portion of a stacked via and wiring pattern in a redistribution structure in accordance with embodiments of the present disclosure is schematically illustrated.

[0011] Figure 10is a schematic cross-sectional view illustrating a package structure with a stacked via according to some example embodiments of this disclosure. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed directly contacting one another, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be directly contacting one another. Additionally, the present disclosure can repeat certain

[0013] Furthermore, spatial or directional terms, such as "below," "lower," "bottom," "above," "upper," and the like, can be used herein for describing the relative positioning and / or location of one element or feature to another element(s) or feature(s) as shown in the figures. Unless otherwise noted specifically herein, these spatial or directional terms are not intended to imply the relative positioning and / or location of the devices in use or operation. Devices can be otherwise oriented (rotated 90 degrees or located in other orientations) and the spatial or directional descriptions used herein can be interpreted accordingly.

[0014] Additionally, for the sake of convenience, the terms "first," "second," "third," "fourth," and the like can be used herein to describe a variety of elements or features, and can not necessarily be interpreted as limiting terms or used to indicate a chronological or sequential priority with respect to one another. Furthermore, the terms "comprise," "include," and / or "contain" and / or any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, includes and / or contains a list of elements is not necessarily limited to those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0015] Other features and processes can also be included. For example, test structures can be included to assist in verifying testing of the 3D package or 3DIC device. The test structures can include, for example, test pads formed on the redistribution layer or substrate that allow for the use of probes and / or probe cards, etc. to test the 3D package or 3DIC. Verification testing can be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0016] Figures 1-6 is a schematic cross-sectional view illustrating a package structure with a stacked via according to some example embodiments of this disclosure. Figures 7A-7Fare schematic enlarged cross-sectional views of various stages in a fabrication method for forming a stacked via in a rewiring structure according to some example embodiments of this disclosure.

[0017] With reference to Figure 1 A semiconductor die 10D is provided. The semiconductor die 10D can be an integrated circuit die formed from a semiconductor wafer. In some embodiments, the semiconductor die 10D includes a semiconductor substrate 110 and a plurality of semiconductor devices 115 formed from, on, or in the semiconductor substrate 110. For example, the semiconductor substrate 110 can include a doped or undoped bulk silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 110 can include other semiconductor materials, such as germanium, compound semiconductor materials (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP). In some embodiments, the semiconductor substrate 110 can be or include a multilayer or graded substrate. For example, the plurality of semiconductor devices 115 are formed within a device layer 116 over the semiconductor substrate 110. In some embodiments, the device layer 116 is formed with the plurality of semiconductor devices 115, the plurality of semiconductor devices 115 including active devices (e.g., transistors, diodes, etc.) and, optionally, passive devices (e.g., capacitors, resistors, inductors, etc.).

[0018] Also see Figure 1semiconductor die 10D further includes an interconnect structure 120 on the device layer 116, a plurality of conductive pads 128 connected with the interconnect structure 120, a passivation layer 130 covering the plurality of conductive pads 128 and the interconnect structure 120, a plurality of conductive pillars 132 disposed on the plurality of conductive pads 128, and a protection layer 134 covering the plurality of conductive pillars 132 and the passivation layer 130. In some embodiments, the interconnect structure 120 includes a plurality of metallization patterns 124 embedded within a dielectric material 122. For example, the plurality of metallization patterns 124 including a plurality of metal lines and a plurality of vias are embedded within the dielectric material 122 formed as one or more low-k dielectric layers. The interconnect structure 120 is electrically interconnected with the plurality of semiconductor devices 115 in the device layer 116 to form an integrated circuit, and electrically connects the plurality of semiconductor devices 115 in the device layer 116 with the plurality of conductive pads 128 and the plurality of conductive pillars 132. In some embodiments, the passivation layer 130 is formed on the interconnect structure 120 over the semiconductor substrate 110 and has a plurality of contact openings exposing the plurality of conductive pads 128. For example, the plurality of conductive pads 128 can be or include aluminum pads, copper pads, or other suitable metal or metal pads, and the passivation layer 130 can be or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed from other suitable dielectric materials. In some embodiments, the plurality of conductive pillars 132 are formed on the plurality of conductive pads 128 by plating. In some embodiments, the plurality of conductive pillars 132 include metal pillars, such as copper pillars or copper alloy pillars. The plurality of conductive pillars 132 can be used as die connections. For example, the protection layer 134 formed on the passivation layer 130 can include multiple layers and at least include a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed from other suitable polymers. The protection layer 134 is formed on the passivation layer 130 and completely covers the plurality of conductive pillars 132.

[0019] In some embodiments, the semiconductor die 10D can be or include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radiofrequency (RF) die, an optoelectronic die, or a sensor die. In some embodiments, the semiconductor die 10D can be a stacked structure containing multiple semiconductor dies, such as a hybrid memory cube (HMC) die or a high bandwidth memory (HBM) die.

[0020] In some embodiments, the semiconductor die 10D is a known good die (KGD) that is tested by the chip and only the KGD is subsequently processed. In the following figures, the detailed construction of the semiconductor devices formed in the device layer 116 and the interconnect structure 120 will be omitted for simplicity.

[0021] In some embodiments, referring to FIG. 1, the semiconductor die 10D is a KGD that is tested by the chip and only the KGD is subsequently processed. In the following figures, the detailed construction of the semiconductor devices formed in the device layer 116 and the interconnect structure 120 will be omitted for simplicity. Figure 2A carrier 102 having a debonding layer 104 coated thereon is provided. In some embodiments, the carrier 102 includes any suitable carrier for a manufacturing method of an integrated fan-out (InFO) package structure. In some embodiments, the carrier 102 is a glass carrier or a temporary carrier. In some embodiments, the debonding layer 104 is formed of any material suitable for bonding and debonding the carrier 102 with the above-mentioned assembly or any die disposed thereon. In some embodiments, the debonding layer 104 includes a light-to-heat-conversion (LTHC) debonding coating film that can be debonded from the carrier 102 at room temperature by applying laser irradiation. In some embodiments, the debonding layer 104 includes an ultra-violet (UV) glue that loses its adhesive property when exposed to UV light. In certain embodiments, the debonding layer 104 can be dispensed as a liquid and cured, or can be a lamination film laminated onto the carrier 102.

[0022] Referring to Figure 2 After the debonding layer 104 is provided on the carrier 102, a plurality of semiconductor dies 10D is provided and placed on the carrier 102. In some embodiments, the plurality of semiconductor dies 10D is picked up and placed on the carrier 102. In some embodiments, the plurality of semiconductor dies 10D is arranged side-by-side and placed with their back surfaces facing the debonding layer 104 such that the back surfaces of the plurality of semiconductor dies 10D are attached to the debonding layer 104. In the embodiments described herein, the manufacturing process is directed to a die-first and face-up wafer-level packaging process.

[0023] Referring to Figure 3 An insulating encapsulant 150 is formed over the top surface of the carrier 102, completely covering and filling between the plurality of semiconductor dies 10D to encapsulate the plurality of semiconductor dies 10D to form a molded structure 15M. In some embodiments, the insulating encapsulant 150 includes a resin material such as an epoxy resin, a phenol resin, a silicon-containing resin, or a combination thereof, and a filler including a silica filler or a metal oxide filler. In some embodiments, the method of forming the insulating encapsulant 150 includes forming an insulating resin material (not shown) over the debonding layer 104 on the carrier 102 by a molding process (e.g., transfer molding, compression molding, or over molding) to completely cover and encapsulate the plurality of semiconductor dies 10D. In some embodiments, the insulating encapsulant 150 completely covers the top surfaces and sidewalls of the plurality of semiconductor dies 10D. Referring to Figure 1 andFigure 3 In some embodiments, the conductive pillars 132 of the plurality of semiconductor dies 10D are covered by the protective layer 134 such that the conductive pillars 132 of the plurality of semiconductor dies 10D are not exposed and are well protected by the protective layer 134.

[0024] Referring to Figure 4 In some embodiments, a planarization process is performed to partially remove the insulative encapsulation 150 of the molded structure 15M to become a reconstituted wafer 15M’. In some embodiments, during the planarization process, the insulative encapsulation 150 is partially removed and the protective layer 134 is partially removed until the tops of the plurality of conductive pillars 132 are exposed. In some embodiments, the planarization process includes performing a mechanical grinding process and / or a chemical mechanical polishing (CMP) process. In some embodiments, after the planarization process, the conductive pillars 132 of the plurality of semiconductor dies 10D are exposed from the polished protective layer 134 and the polished insulative encapsulation 150. After performing the planarization process, the plurality of active surfaces 10DA of the plurality of semiconductor dies 10D are coplanar and flush with a top surface 150T of the polished insulative encapsulation 150. That is, the plurality of conductive pillars 132 are exposed from the active surfaces 10DA of the plurality of semiconductor dies 10D.

[0025] Referring to Figure 5 and Figure 6 A redistribution line structure 160 is formed over the top surface of the reconstituted wafer 15M’ and a plurality of bump connectors 170 are formed on the redistribution line structure 160. In some embodiments, the plurality of bump connectors 170 are or include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, ENEP IG (electroless nickel-electroless palladium-immersion gold technique) formed bumps, or the like.

[0026] In some embodiments, the redistribution line structure 160 is disposed on the plurality of semiconductor dies 10D and spread over the polished insulative encapsulation 150 that laterally surrounds the plurality of semiconductor dies 10D over the carrier 102. In some embodiments, the redistribution line structure 160 includes alternating dielectric layers 161, 163, 165, 167, 169 and conductive layers 162, 164, 166, 168, and the conductive layers 162, 164, 166, 168 are sandwiched between the dielectric layers 161, 163, 165, 167, 169. The conductive layers 162, 164, 166, 168 can be referred to as redistribution line layers and contain a plurality of metallization patterns. Here, the redistribution line structure 160 is shown as an example with four layers of metallization patterns sandwiched between five dielectric layers. However, it is understood that more or less dielectric layers and metallization patterns can be formed in the redistribution line structure 160. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0027] In some embodiments, with reference to Figure 5 Formation of the redistribution line structure 160 begins with deposition of the dielectric layer 161 over the reconstituted wafer 15M' in some embodiments. The material of the dielectric layer 161 includes polyimide (PI), epoxy, acrylic, phenol formaldehyde, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymeric dielectric material, in some embodiments. For example, the dielectric layer 161 can be formed by suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or a combination thereof. In some embodiments, the material of the dielectric layer 161 includes a photosensitive polymeric material that can be directly patterned using a photolithographic mask. After the dielectric layer 161 is formed, a conductive layer 162 is then formed over the dielectric layer 161. In some embodiments, the conductive layer 162 is formed to have a plurality of metallization patterns including routing lines 162L and vias 162V1 and 162V2. With reference to Figure 5, a routing line 162L (e.g., a wire or trace) is located on and extends along a top surface of the dielectric layer 161, while vias 162V1 and 162V2 extend through the dielectric layer 161 to physically contact and electrically couple to respective conductive pillars 132 (die attach) of the plurality of semiconductor dies 10D. In some embodiments, a seed layer (not shown) and a diffusion layer 1622 are formed directly below and cover a bottom surface of the conductive layer 162, as Figure 5 shown in a partial enlarged view of the upper portion. In addition, the conductive layer 162 is formed to have dopants 1623 dispersed therein.

[0028] The formation of the re-wiring line structure will be described in more detail by way of the formation method shown in Figures 7A-7F .

[0029] Figures 7A-7F A cross-sectional view showing a portion of a re-wiring line structure 760 in accordance with some embodiments is shown. In the illustrated embodiment, the re-wiring line structure 760 formed on a semiconductor die 70D can be implemented as a portion of the re-wiring line structure 160 formed on a semiconductor die 10D within a reconstituted wafer 15M' (see Figure 5 and Figure 6 ). The semiconductor die 70D is similar to the semiconductor die 10D shown above with reference to Figure 1 , like features are labeled with like reference numerals, and like features are not repeated described herein. For example, the semiconductor die 70D includes a plurality of conductive pillars 72 exposed from a protective layer 74.

[0030] Referring to Figure 7A , in some embodiments, a dielectric layer 761 is formed on the semiconductor die 70D. In some embodiments, the material of the dielectric layer 761 includes a photo-sensitive polymer material that can be directly patterned using a photoresist mask. In one embodiment, the dielectric layer 761 is formed via spin coating, deposition, or lamination. The dielectric layer 761 is then patterned to form a plurality of openings S1 (only one is shown) to at least expose the plurality of conductive pillars 72 of the semiconductor die 70D. When the dielectric layer 761 is made of a photosensitive material such as PBO or PI, the patterning can include performing any acceptable process such as exposing the dielectric layer 761 and then developing to remove the unexposed portions to form the plurality of openings S1. In some embodiments, a baking process can optionally be performed before or after the exposure. Alternatively, the dielectric layer 761 can be patterned by etching with a photoresist pattern using, for example, anisotropic etching. In some embodiments, an annealing process is performed on the dielectric layer 761, and the annealing process is performed at a temperature higher than 200 degrees Celsius. In one embodiment, the annealing process is performed at a temperature of about 230 degrees Celsius for a time period of about 2 to 6 hours.

[0031] Referring Figure 7A In some embodiments, a seed layer 750 is formed on the dielectric layer 761 with the opening S1. In some embodiments, the seed layer 750 is formed on the dielectric layer 761 and in the opening to cover the bottom surface of the opening S1. In some embodiments, the seed layer 750 is a single metal layer or a composite layer including multiple sub-layers formed of different metals or materials of metals. In some embodiments, the material of the metal of the seed layer 750 includes silver, copper, antimony, titanium, alloys thereof, or combinations thereof. In one embodiment, the seed layer 750 includes a titanium layer as a diffusion barrier layer and a copper layer on the titanium layer. The seed layer 750 can be formed using, for example, physical vapor deposition (PVD) or sputtering. In some embodiments, the seed layer 750 or the remaining seed pattern 750’ is quite thin in thickness, and it is acceptable that the seed layer does not remain as a continuous layer. Referring Figure 7A Due to the profile of the opening S1, the seed layer 750 covers the top surface of the dielectric layer 761 and the bottom surface of the opening S1 without covering the sidewall of the opening S1. In some other embodiments, the seed layer 750 not only covers the dielectric layer 761 but also conformally covers the opening S1.

[0032] Referring Figure 7A And Figure 7B In some embodiments, a photoresist pattern 755 with multiple openings S2 (only one is shown) is then formed on the seed layer 750. For example, the photoresist pattern 755 is formed by spin coating, curing and then patterning by exposure. In some embodiments, the photoresist pattern 755 is formed by a process such as a lift-off process. Figure 7A In the middle, the photoresist pattern 755 is disposed directly on the seed layer 750, covering the seed layer 750 but exposing the opening S1 and partially exposing the seed layer 750 around the opening S1. In some embodiments, the opening S2 includes a trench opening S2T and a hole opening S2H connected with the trench opening S2T. In some embodiments, the hole opening S2H is connected with the underlying opening S1 to form a via plug opening. The pattern of the photoresist pattern 755 and the dielectric layer 761 corresponds to the pattern of the metallization pattern to be formed. For example, the location and profile of the via plug opening correspond to the via plug to be formed.

[0033] Referring Figure 7BA diffusion layer 752 is formed in the openings S2 and S1 and on the exposed seed layer 750. In some embodiments, the diffusion layer 752 is formed on the seed layer 750 exposed by the openings S2 and conformally covers the openings S1 (on the seed layer 750 directly on the sidewalls of the openings S1 and on the bottom surface of the openings S1). In some embodiments, the diffusion layer 752 formed can be conformal to the profile of the openings S1 and uniformly covers the bottom surface of the openings S2. For example, the diffusion layer 752 can be formed by plating using the exposed portions of the seed layer 750 as seeds, such that the diffusion layer 752 is formed on the seed layer 750 exposed by the openings S2 and extends along the sidewalls of the openings S1 and over the seed layer 750 on the bottom surface of the openings S1, but the diffusion layer 752 does not extend onto the sidewalls of the openings S2 or onto the top surface of the photoresist pattern 755. In some embodiments, the diffusion layer 752 is formed by plating, such as electroplating or electrochemical plating, etc.

[0034] In some embodiments, the diffusion layer 752 includes or is made of a metal layer, and the material of the metal layer includes silver (Ag), manganese (Mn), zinc (Zn), an alloy thereof, or a combination thereof. The diffusion layer 752 includes metal atoms that can readily diffuse into a subsequently formed metal or metal feature (i.e., a conductive layer). In some embodiments, the diffusion layer 752 can be used as a source of dopant (i.e., a dopant supply layer) to dope a subsequently formed conductive layer. That is, the diffusion layer 752 contains dopants. The thickness of the diffusion layer 752 can be adjusted according to the size or thickness of the subsequently formed feature or layer, and is adjusted to be thick enough to provide sufficient dopants or metal atoms to the feature or layer. In some embodiments, the diffusion layer 752 is formed to have a substantially uniform thickness. In some embodiments, the thickness T1 of the diffusion layer 752 can range from about 0.01 microns to about 1.0 microns, or from about 0.1 microns to about 0.5 microns. In other embodiments, the diffusion layer 752 on the seed layer 752 on the dielectric layer 761 can be thicker than the diffusion layer 752 on the sidewalls of the openings S1 and not thinner (about the same) than the diffusion layer 752 on the bottom surface of the openings S1.

[0035] Referring to Figure 7C A conductive layer 740 is formed on the diffusion layer 752, inside the pattern of the photoresist pattern 755 (e.g., inside the openings S2), and fills the openings S1 and S2. In some embodiments, the conductive layer 740 is formed by plating a metal material (not shown) over the photoresist pattern 755 that covers the photoresist pattern 755, fills the openings S1 and S2, and covers the diffusion layer 752 on the seed layer 750, and then removing the excess metal material. For example, the excess metal material on top of the photoresist pattern 755 is removed by etching, and the conductive layer 740 is planarized and flush with the top surface of the photoresist pattern 755.

[0036] refer to Figure 7C In some embodiments, the conductive layer 740 includes a metallization pattern formed as routing traces (or routing lines) 744 in the trench opening S2T and a via plug 742 formed inside the via plug opening (the hole opening S2H that engages with opening S1). In some embodiments, the metal material of the conductive layer 740 is formed by plating, such as electroplating or electrochemical plating. The metal material may include, for example, aluminum, titanium, copper, nickel, tungsten, cobalt, and / or alloys thereof. In some embodiments, the conductive layer 740 fills openings S1 and S2, and the thickness of the conductive layer 740 may range from about 0.5 micrometers to about 10 micrometers, depending on the thickness of the photoresist pattern 755 and the dielectric layer 761. In some embodiments, the bulk thickness T2 of the via plug 742 of the conductive layer 740 ranges from about 1.5 micrometers to about 6 micrometers. Reference Figure 7C In some embodiments, the thickness T1 of the diffusion layer 752 may range from about 1% to about 20% of the thickness T2 relative to the bulk thickness T2 of the via plug 742 of the conductive layer 740, provided that the diffusion layer 752 can provide sufficient dopant or doped atoms. In one embodiment, the thickness T1 is greater than 1% of the thickness T2 and less than or equal to 15% of the thickness T2.

[0037] refer to Figure 7C During the formation of the conductive layer 740, dopant 741 diffuses from the diffusion layer 752 into the conductive layer 740. That is, the conductive layer 740 is formed with embedded dopant 741. In some embodiments, dopant 741 is or includes metal atoms initially contained within the metallic material of the diffusion layer 752, and dopant 741 may exist in the conductive layer 740 as a single solid metal atom or in the form of tiny dies or particles. For example, the metallic material of the conductive layer 740 is like a solid solution in which metal atoms (dopant 741) are dispersed. It is understood that dopant 741 present at the atomic scale (indicated by small circles in the figure) may not be visible to the naked eye but can be detected by microscopic examination. In some embodiments, the conductive layer 740 is formed with dopant 741 contained therein, and the average content of dopant 741 is from about 5 at% (atomic percentage) to about 11 at% relative to the total number of atoms in the entire conductive layer 740.

[0038] For example, the concentration of dopants 741 (e.g., metal atoms) in the diffusion layer 752 is much higher than the concentration of dopants 741 in the conductive layer 740. This is because the diffusion layer 752 can be formed of a bulk metal material that includes dopants or metal atoms, and some of the metal atoms can diffuse out of the diffusion layer 752 and move into the conductive layer 740 through thermally driven atomic diffusion. In some embodiments, the concentration of dopants 741 in the conductive layer 740 can gradually decrease from the interface (contact surface) between the conductive layer 740 and the diffusion layer 752. That is, more dopants 741 are located in the region of the conductive layer 740 that is close to the interface (contact surface) between the conductive layer 740 and the diffusion layer 752, and less dopants 741 are located in the region of the conductive layer 740 that is far from the interface (contact surface) between the conductive layer 740 and the diffusion layer 752.

[0039] In some embodiments, the material of the diffusion layer 752 includes silver (Ag), manganese (Mn), or zinc (Zn), and the dopants 741 include Ag atoms, Mn atoms, or Zn atoms. In some embodiments, the material of the diffusion layer 752 includes silver, or the diffusion layer 752 includes a silver layer, and the dopants 741 include Ag atoms, solo atoms, or clusters of atoms. Due to the presence of the diffusion layer 752, for example, in the case of an electrochemical plating (ECP) process to form the conductive layer 740, copper is co-plated with the metal atoms (e.g., Ag atoms) diffused out of the diffusion layer 752, such that the plated copper is formed to have a smaller crystal grain size and a larger fraction of the copper is formed to have a preferred crystal orientation, e.g., Cu(111), as compared to copper formed by the same plating process in the absence of the diffusion layer 752.

[0040] Referring to Figure 7D The photoresist pattern 755 is removed by a suitable etching process using plasma (using oxygen plasma) and / or an acceptable ashing or stripping process. When the photoresist pattern 755 is removed, the portion of the seed layer 750 underlying the photoresist pattern 755 is removed by the same process, or by using an additional etching process, e.g., a wet etching or a dry etching, to form the seed pattern 750'. Here, the photoresist pattern 755 and the portion of the seed layer 750 on which the conductive material is not formed are removed.

[0041] From Figure 7DAs can be seen in the schematic three-dimensional view of the upper portion, the stack 753 of the conductive layer 740, the underlying diffusion layer 752, and the seed pattern 750’ is inverted, with the diffusion layer 752 covering the entire bottom surface of the conductive layer 740 (including the bottom surface of the routing trace 744 and the bottom surface of the via plug 742), and the seed pattern 750’ covering the bottom surface of the protruding portion 742V of the via plug 742, the bottom surface of the lip portion 742L of the via plug 742, and the bottom surface of the routing trace 744.

[0042] In some embodiments, after the photoresist pattern 755 is removed, the stack 753 (or combination) of the conductive layer 740, the underlying diffusion layer 752, and the seed pattern 750’ remains as a metallization pattern disposed on the dielectric layer 761 and contacts (both physically and electrically) the conductive pillar 72 of the semiconductor die 70D. In some embodiments, the thickness of the diffusion layer 752 is thick enough such that the diffusion layer 752 remains on the bottom surface of the conductive layer 740 even though some of the metallic material of the diffusion layer 752 is consumed or diffused out of the diffusion layer 752.

[0043] Reference is made to Figure 7E In some embodiments, a dielectric layer 763 is formed on the dielectric layer 761, covering the conductive layer 740, and is formed with a plurality of openings S3 (only one is shown) that expose portions of the conductive layer 740. The material and formation method of the dielectric layer 763 can be the same as or similar to that of the dielectric layer 761, which will not be repeated here. In some embodiments, during the formation of the dielectric layer 763, an annealing process is performed at a temperature of about 230 degrees Celsius for about 2 to 6 hours to set the dielectric layer 763. During the annealing process, the conductive layer 740 and the underlying diffusion layer 752 are also annealed, and more dopants 741 diffuse from the diffusion layer 752 into the conductive layer 740, further increasing the dopant content in the conductive layer 740 (especially in the via plug 742). In some embodiments, after the annealing process, the content of the dopants 741 is about 7 at% to about 12 at% relative to the total number of atoms of the entire conductive layer 740.

[0044] With such an annealing process, more of the conductive layer 740 forms in a preferred crystal orientation, resulting in further reduction in transistor core size and increased grain boundaries in the metal material of the conductive layer 740. When the metal material of the conductive layer 740 forms with smaller transistor core size or increased grain boundaries, the resistance to dislocation increases, and the conductive layer 740 provides higher mechanical strength (including higher hardness and higher toughness) and higher Young’s modulus. Due to the presence of the diffusion layer 752, when the conductive layer 740 is formed with copper as an example, during the annealing process, more and more of the copper will transform (change) to a primary crystal orientation, such as Cu(l l l), and the transistor core size of the copper can be further reduced. In some embodiments, the diffusion layer 752 remains on the bottom surface of the conductive layer 740 after the annealing process.

[0045] Referring to Figure 7E , the opening S3 penetrates the dielectric layer 763 to expose the via plug 742 of the conductive layer 740. After the dielectric layer 763 is formed, referring to Figure 7F , another seed layer 731 is formed on the dielectric layer 763 around the opening S3 and covers the exposed surface of the via plug 742, followed by conformally forming another diffusion layer 732 on the opening S3 and covering the seed layer 731. In some embodiments, the diffusion layer 732 covers the seed layer 731 on the dielectric layer 763 around the opening S3, the sidewall of the opening S3, and the seed layer 731 on the via plug 742. In some embodiments, another conductive layer 730 including a metallization pattern is formed on the diffusion layer 732 on the dielectric layer 763 and fills in the opening S3. The conductive layer 730 includes a via plug 734 that fills in the opening S3 and sits on the via plug 742. Referring to Figure 7F , the via plug 734 on the diffusion layer 732 disposed directly on the seed layer 731 extends through the dielectric layer 763 to physically and electrically connect to the underlying via plug 742. The seed layer 731 and the diffusion layer 732 can be formed using similar materials and methods as the seed layer 750 / seed pattern 750’ and the diffusion layer 752, the details of which will not be repeated. In addition, the conductive layer 730 can be formed using similar materials and methods as the conductive layer 740, but with a different metallization pattern, which will not be repeated here.

[0046] In some embodiments, the material of the conductive layer 730 is different from the material of the conductive layer 740, and the material of the seed layer 731 and the diffusion layer 732 is different from the material of the seed layer 750 and the diffusion layer 752.

[0047] Referring to Figure 7FIn some embodiments, a conductive layer 730 embedded with a dopant 731 is formed after a diffusion layer 732 is pre-formed. In some embodiments, the dopant 731 is or includes metal atoms initially contained within the metallic material of the diffusion layer 732, and the dopant 731 may exist in the conductive layer 730 as a single metal atom or in the form of tiny dies or particles. Although Figure 7F Although not shown, the conductive layer 730 may be formed with other metallization patterns, such as wires or traces extending along the main surface of the dielectric layer 763.

[0048] In some embodiments, by adjusting the thickness of the diffusion layer 732 relative to the via plug 734, more or less dopant 731 is contained within the via plug 734 compared to the via plug 742. In some embodiments, the content of dopant 741 in the conductive layer 740 (via plug 742 and routing trace 744) differs from the content of dopant 731 in the conductive layer 730 (via plug 734).

[0049] Return to reference Figure 5 and Figure 6 ,according to Figures 7A-7F The exemplary process steps and formation method shown involve forming diffusion layers 1622, 1642, and 1662 within the redistributed circuit structure 160, prior to the formation of conductive layers 162, 164, and 166. The subsequently formed conductive layers 162, 164, and 166 are directly formed on the diffusion layers 1622, 1642, and 1662, and contain dispersed dopants (e.g., [missing information]). Figure 5 (Dopant 1623 in the enlarged view). Here, since the dopant may be invisible and will not be shown in some figures for simplicity, it can be understood that the dopant provided by the diffusion layer is diffused and dispersed into the subsequently formed conductive layer and / or its metallic features. Here, for simplicity, the seed layer or seed pattern is not shown in the figures.

[0050] In some embodiments, a conductive layer 168 is formed without an underlying diffusion layer, thus forming a layer that is doped. Depending on the product design, one or more conductive layers may be formed without a pre-formed diffusion layer, and doped conductive layers may be formed. Doped conductive layers can exhibit greater mechanical strength (higher hardness, higher toughness, and higher modulus) compared to conductive layers formed without doping. The metal materials of the via plugs 162V1 / 162V2 and other via plugs in conductive layers 162, 164, and 166 have smaller transistor die sizes, resulting in greater mechanical strength compared to via plugs in doped conductive layers. As a result, redistribution circuit structures with doped conductive layers (especially stacked via plugs) will be more reliable and withstand more demanding processing conditions, and production yields will be correspondingly improved.

[0051] Figure 8 This is a schematic cross-sectional view of a portion of a semiconductor package structure having stacked through-holes according to an exemplary embodiment of the present disclosure. Figures 7A-7F The exemplary process steps and forming methods shown will form a redistributed circuit structure. (Reference) Figure 8 The redistribution circuit structure 860 is shown as an example having four metallization patterns 862, 864, 866, and 868 (four conductive layers) sandwiched between five dielectric layers 861, 863, 865, 867, and 869. In some embodiments, the redistribution circuit structure 860 is formed on a molding structure 850 having semiconductor dies 810 and 820 laterally encapsulated by an insulating molding compound 830. In one embodiment, the molding compound 830 is made of epoxy resin, phenolic resin, or silicone-containing resin, and filler particles, such as silica particles.

[0052] Metalized pattern 862, metalized pattern 864, metalized pattern 866, metalized pattern 868 can be formed using similar materials and methods as described in the preceding paragraph for forming conductive layer 730, conductive layer 740 having a metalized pattern, and are not repeated here. In some embodiments, the material of dielectric layer 861, dielectric layer 863, dielectric layer 865, dielectric layer 867, dielectric layer 869 comprises a polymeric material, such as a photosensitive polymeric material that can be directly patterned using a photolithographic mask. Dielectric layer 861, dielectric layer 863, dielectric layer 865, dielectric layer 867, dielectric layer 869 can be formed using the same or similar materials and formation methods as described in the preceding paragraph for dielectric layer 761, dielectric layer 763. Similarly, the formation of dielectric layer 861, dielectric layer 863, dielectric layer 865, dielectric layer 867, dielectric layer 869 can involve performing one or more annealing processes, and the annealing processes can be performed at a temperature of about 230 degrees Celsius for a time of about 2 to 6 hours.

[0053] Referring to Figure 8 In the stack structure of metalized pattern 862, metalized pattern 864, metalized pattern 866, metalized pattern 868, a stack structure SV1 of via plug 862V, via plug 864V, via plug 866V, and via plug 868V (stacked vias) is electrically connected to semiconductor die 810 below, while a stack structure SV2 of via plug 862V, via plug 864V, and via plug 866V (stacked vias) is electrically connected to semiconductor die 820 below. In some embodiments, semiconductor die 810 is electrically connected to a plurality of bump connectors 880 (only one shown) through stack structure SV1 and routing trace 868L of metalized pattern 868, while semiconductor die 820 is electrically connected to bump connector 880 through routing trace 866L, routing trace 868L, via plug 868V, and stack structure SV2. In some embodiments, bump connector 880 comprises a C4 bump. Further reference is made to Figure 8 In some embodiments, via plug 862V, via plug 864V, via plug 866V, and via plug 868V have sloped sidewalls. In some embodiments, at least one via plug 868V is laterally displaced relative to stack structure SV2 of via plug 862V, via plug 864V, and via plug 868V (stacked vias). In some embodiments, via plug 862V, via plug 864V, via plug 866V, and via plug 868V in stack structure SV1 or stack structure SV2 are vertically stacked on top of each other.

[0054] As Figure 8As shown, the metallization pattern 862, the metallization pattern 864, the metallization pattern 866, the metallization pattern 868 are formed with the diffusion layer 8622, the diffusion layer 8642, the diffusion layer 8662, the diffusion layer 8682 covering the bottom surface thereof and sandwiched between the bottom surface thereof and the underlying seed layer 8621, the seed layer 8641, the seed layer 8661, the seed layer 8681, respectively. The seed layer 8621, the seed layer 8641, the seed layer 8661, the seed layer 8681 and the diffusion layer 8622, the diffusion layer 8642, the diffusion layer 8662, the diffusion layer 8682 can be formed using similar materials and methods as the seed layer 731, the seed layer 750 and the diffusion layer 732, the diffusion layer 752. Similarly, the metallization pattern 862, the metallization pattern 864, the metallization pattern 866, the metallization pattern 868 are formed with the dopant 8623, the dopant 8643, the dopant 8663, the dopant 8683 dispersed therein. With the diffusion layer 8622, the diffusion layer 8642, the diffusion layer 8662, the diffusion layer 8682 and the dopant 8623, the dopant 8643, the dopant 8663, the dopant 8683 dispersed therein directly below, the metal material of the metallization pattern 862, the metallization pattern 864, the metallization pattern 866, the metallization pattern 868 is formed with a predominant crystal orientation, resulting in further reduction of the grain size of the crystal and increase of the crystal grain boundaries formed therein. The metal material of the via plug 862V, the via plug 864V, the via plug 866V, the via plug 868V has a smaller grain size compared to the via plug without the dopant, resulting in a stronger mechanical strength. As a result, the formed metallization pattern 862, the metallization pattern 864, the metallization pattern 866, the metallization pattern 868 (particularly the via plug 862V, the via plug 864V, the via plug 866V, the via plug 868V) are formed with a higher mechanical strength and a higher Young's modulus, and with very few or no voids therein. As a result, a reliable stack structure of the redistribution line structure (particularly the stacked via or the stacked via plug) can be formed even after undergoing multiple thermal cycles with very little or no cracking.

[0055] By forming metallization patterns 862, 864, 866, and 868 with dopants 8623, 8643, 8663, and 8683, respectively, stronger and harder through-hole plugs 862V, 864V, 866V, and 868V are formed. As described above, the redistribution structure 860 is more robust regardless of whether the through-hole plugs are stacked or interleaved. Therefore, due to fewer defects caused by strain in the redistribution structure 860, the redistribution structure becomes more reliable and durable, improving its process window and design flexibility. Consequently, better wiring efficiency and reliability can be achieved for packages or semiconductor devices including such redistribution structures.

[0056] Figure 9 A portion of the stacked vias and wiring patterns in a redistributed wiring structure according to an embodiment of this disclosure is schematically shown. See also Figure 9 As can be seen, the stacked through-hole plugs V1, V2, and V3 form a diffusion layer DB that covers the bottom surfaces of through-hole plugs V1, V2, and V3 respectively, but does not cover the top surfaces of through-hole plugs V1, V2, and V3. For example... Figure 9 As shown, the diffusion layer DB is located between and sandwiched between through-hole plugs V1 and V2, and between through-hole plugs V2 and V3. That is, the diffusion layer DB between through-hole plugs V1 and V2 physically separates through-hole plugs V1 and V2, and the diffusion layer DB between through-hole plugs V2 and V3 physically separates through-hole plugs V2 and V3. Furthermore, the routing trace R1 has a diffusion layer DB formed on its bottom surface. In some embodiments, the stacked through-hole plugs V1, V2, and V3 are electrically connected to each other.

[0057] Compared to through-hole plugs formed by plating without a diffusion layer or dopants, copper through-hole plugs with a silver layer (as a diffusion layer on their bottom surface) exhibit the following advantages: when the thickness of the diffusion layer is approximately 15% of the thickness of the through-hole plug body and the content of dopants (such as Ag / Ag atoms) in the through-hole plug is approximately 7 at% (atomic percentage), the copper transistor core size is reduced by approximately 30%, the hardness of the through-hole plug increases by 20% (1.2 times), the toughness increases by approximately 32%, and the modulus (Young's modulus) increases by approximately 8% to 10%, if measured using an indentation test.

[0058] Figure 10 This is a schematic cross-sectional view illustrating a package structure with stacked through-holes according to some exemplary embodiments of the present disclosure.

[0059] Reference is made to Figure 10 In some embodiments, a package structure 18 is shown, which includes at least one package unit 90 mounted and bonded to a circuit substrate 9S by a plurality of bump connectors 94. In some embodiments, the package unit 90 includes a first semiconductor die 90D1 and a second semiconductor die 90D2 laterally surrounded by an insulating encapsulation 92, a redistribution line structure 96 formed on the first semiconductor die 90D1 and the second semiconductor die 90D2 and extending over the encapsulation 92, and a plurality of bump connectors 94 on the redistribution line structure 96. In some embodiments, the first semiconductor die 90D1 and the second semiconductor die 90D2 are different types of dies or perform different functions. In some embodiments, the first semiconductor die 90D1 can include one or more of an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless application chip (such as a Bluetooth chip or a radio frequency chip), a voltage regulation chip, or a system on chip (SoC). In some embodiments, the second semiconductor die 90D2 includes one or more memory chips, such as a high bandwidth memory (HBM) chip, a dynamic random access memory (DRAM) chip, or a static random access memory (SRAM) chip. In Figure 10 In some embodiments, two dies are shown as exemplary dies of the package structure, but it should be understood that multiple dies or two or more types of dies or different types of dies can be included within the package structure. In certain embodiments, die and chip can be used interchangeably.

[0060] In some embodiments, the first semiconductor die 90D1 and the second semiconductor die 90D2 (facing down, active surface facing the redistribution line structure 96) are bonded to the redistribution line structure 96 by a plurality of die connectors 902 of the first semiconductor die 90D1 and the second semiconductor die 90D2. In addition, an underfill 95 is filled between the circuit substrate 9S and the redistribution line structure 96 and around the plurality of bump connectors 94. In some embodiments, the underfill 95 fills the gap between the package unit 90 and the circuit substrate 9S, and the underfill 95 can overflow to partially cover the sidewalls of the redistribution line structure 96. In some embodiments, the first semiconductor die 90D1, the second semiconductor die 90D2, the redistribution line structure 96 are substantially the same or similar to the corresponding elements described in the above paragraphs, and detailed description will be skipped. As shown in FIG. 1C, the package unit 90 is mounted on the circuit substrate 9S by the plurality of bump connectors 94, and the underfill 95 is filled between the circuit substrate 9S and the redistribution line structure 96 and around the plurality of bump connectors 94. Figure 10As shown, the circuit substrate 9S can provide for double-sided electrical connections and further electrical connections through the plurality of conductive balls 98. In some embodiments, the circuit substrate 9S is a printed circuit board (PCB), a flexible PCB, or any suitable laminated circuit substrate. In some embodiments, the conductive balls 98 have a size (diameter) larger than the size (diameter) of the bump connections 94, as exemplified by the circular bumps. Through these conductive connections and the redistribution line structure, the semiconductor dies 90D1, 90D2 of finer pitch are electrically connected to the circuit substrate 9S of larger pitch.

[0061] In accordance with Figures 7A-7F As shown in the exemplary process steps and formation methods, the redistribution line structure 96 is formed with three conductive layers 962, 964, 966 sandwiched between four dielectric layers 961, 963, 965, 967 (as a three-level metallization pattern). Through the same or similar formation processes, the conductive layers 962, 964, 966 are formed with diffusion layers 9622, 9642, 9662 located directly below and having dopants therein. Here, for simplicity, the seed layers or seed patterns are not shown in the figures. As shown in the partial enlarged view of Figure 10 As shown in the partial enlarged view of Figure 10 As shown in the partial enlarged view of Figure 10 Although not shown in In some embodiments, the metallization patterns of the conductive layers 962, 964, 966 include at least via plugs 962V, 964V, 966V. Thus, by forming the conductive layers (with metal materials) containing dopants, the metallization patterns including the via plugs 962V, 964V, 966V are formed to have higher mechanical strength and higher Young's modulus. As such, the package structure formed with such a redistribution line structure will become more reliable and provide excellent electrical performance. For a package with such a redistribution line structure, there are few or no cracks formed in the redistribution line structure (particularly the stacked vias or stacked via plugs of the redistribution line structure), so that reliable and satisfactory electrical interconnections and wiring can be achieved.

[0062] According to the above exemplary embodiments, a package structure can be suitably formed after a process of fabricating an integrated fan-out (InFO) wafer-level package structure. More than one or more redistribution layers (RDLs) can be provided in the package structure, or can be arranged on the front and back surfaces of the die or wafer for signal redistribution between multiple dies or chips. The structures and / or processes of the present disclosure are not limited to the exemplary embodiments. According to the above exemplary embodiments, the layout and configuration of the redistribution layer structure can be suitably formed within the wafer-level package structure. In addition, the package structure can also include additional dies or sub-package units disposed above or below the die, and another redistribution layer structure or layer can be formed to electrically connect the additional dies or sub-package units. The structures and / or processes of the present disclosure are not limited to the exemplary embodiments.

[0063] Due to the presence of dopants within the conductive metallization pattern of the redistribution layer structure, the redistribution layer structure has stronger mechanical strength, and reliable electrical connections are provided through such redistribution layer structure. By forming the diffusion layer before the metal material of the conductive metallization pattern in the redistribution layer structure, dopants are formed in the conductive metallization pattern, which enhances mechanical properties and structural integrity. By forming such a redistribution layer structure, the stacked structure of the via plug has higher mechanical strength and fewer cracks, thereby improving the reliability of the package structure.

[0064] The present disclosure is not limited by the type or number of semiconductor packages connected to the circuit substrate. It is clear that different types of semiconductor package units can be used to produce a semiconductor device package structure including the circuit substrate disclosed herein, and all such semiconductor devices are intended to fall within the scope of the present specification and claims. For example, a chip-on-wafer-on-substrate (CoWoS) structure, a three-dimensional integrated circuit (3DIC) structure, a chip-on-wafer (CoW) package, a package-on-package (PoP) structure can be used individually or in combination as a semiconductor package unit.

[0065] According to some embodiments, a package includes a molded structure having a first semiconductor die and a second semiconductor die laterally surrounded by an insulative encapsulation, and a redistribution structure disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die. The redistribution structure includes a dielectric layer and a stacked via structure embedded in the dielectric layer. The stacked via structure includes a first via plug, a first diffusion layer including a first dopant, a second via plug, and a second diffusion layer including a second dopant. The first via plug is disposed on the first diffusion layer. The first via plug includes the first dopant dispersed within a first metallic material of the first via plug, and a first surface of the first via plug is covered by the first diffusion layer. The second diffusion layer is disposed on the second via plug. The second via plug disposed on the second diffusion layer includes the second dopant dispersed within a second metallic material of the second via plug. The second metallic material includes copper. According to some embodiments, a package includes a molded structure and a redistribution structure. The molded structure includes a first semiconductor die and a second semiconductor die laterally surrounded by an insulative encapsulation. The redistribution structure includes a dielectric layer and a stacked via structure embedded in the dielectric layer. The redistribution structure is disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die, wherein the redistribution structure includes a dielectric layer and a stacked via structure in the dielectric layer. The stacked via structure includes a first diffusion layer including a first dopant, wherein the first dopant includes silver, zinc, or manganese; a first via plug disposed on the first diffusion layer, wherein the first via plug includes a first metallic material and the first dopant dispersed within the first metallic material; a second diffusion layer disposed on the first via plug, wherein the second diffusion layer includes a second dopant; and a second via plug disposed on the second diffusion layer, wherein the second via plug includes a second metallic material and the second dopant dispersed within the second metallic material, and the second metallic material includes copper. In some embodiments, the copper in the second metallic material has a predominant crystal orientation of Cu(111). In some embodiments, the redistribution structure includes a first routing trace embedded in the dielectric layer, the first routing trace connected to the first via plug, and the first routing trace lined with the first diffusion layer covering a surface of the first routing trace. In some embodiments, the redistribution structure includes a second routing trace embedded in the dielectric layer, the second routing trace connected to the second via plug, and the second routing trace lined with the second diffusion layer covering a surface of the second routing trace. In some embodiments, the first routing trace includes the first dopant, and the second routing trace includes the second dopant. In some embodiments, the first metallic material includes copper, and the first dopant in the first via plug is at or less than 12 at% and greater than 5 at%.In some embodiments, the second dopant includes silver, zinc, or manganese, and the content of the second dopant in the second via plug is about 12 at% or less and greater than 5 at%.

[0066] According to some embodiments, a package structure includes a semiconductor die, an insulative encapsulation laterally surrounding the semiconductor die, and a redistribution line structure disposed on and extending over the semiconductor die and the insulative encapsulation. The redistribution line structure is electrically connected with the semiconductor die. The redistribution line structure includes first, second, and third dielectric layers, first and second diffusion layers, and first and second conductive via plugs. The first diffusion layer is disposed on and covers a first opening of the first dielectric layer. The first diffusion layer includes a first dopant. The first dopant comprises silver, zinc, or manganese. The first conductive via plug is disposed on the first diffusion layer and fills the first opening with the first diffusion layer sandwiched therebetween. The first conductive via plug includes the first dopant dispersed therein. The second dielectric layer is disposed on the first dielectric layer and has a second opening exposing the first conductive via plug. The second diffusion layer is disposed on the second dielectric layer and covers the second opening and the exposed first conductive via plug. The second diffusion layer includes a second dopant. The second conductive via plug is disposed on the second diffusion layer and fills in the second opening with the second diffusion layer sandwiched between the first and second conductive via plugs. The second conductive via plug includes the second dopant dispersed therein. The third dielectric layer is disposed on the second dielectric layer and partially covers the second conductive via plug. According to some embodiments, a package includes a semiconductor die; an insulative encapsulation laterally surrounding the semiconductor die; and a redistribution line structure disposed on and electrically connected with the semiconductor die. The redistribution line structure includes a first dielectric layer having a first opening extending through the first dielectric layer; a first diffusion layer disposed on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; a first conductive via plug disposed on the first diffusion layer, wherein the first conductive via plug includes the first dopant dispersed therein; a second dielectric layer disposed on the first dielectric layer and having a second opening exposing the first conductive via plug; a second diffusion layer disposed on the second dielectric layer and covering the second opening, wherein the second diffusion layer includes a second dopant; a second conductive via plug disposed on the second diffusion layer, wherein the second conductive via plug includes the second dopant dispersed therein; and a third dielectric layer disposed on the second dielectric layer and partially covering the second conductive via plug. In some embodiments, a material of the first diffusion layer includes silver, zinc, or manganese, and a material of the second diffusion layer includes silver, zinc, or manganese. In some embodiments, the first conductive via plug includes copper, the first dopant includes silver, and a content of the first dopant in the first conductive via plug is about 12 at% or less and greater than 5 at%. In some embodiments, the second conductive via plug includes copper, the second dopant includes silver, and a content of the second dopant in the second conductive via plug is about 12 at% or less and greater than 5 at%.In some embodiments, the first dopant in the first conductive via plug is present in a different amount than the second dopant in the second conductive via plug. In some embodiments, the package further includes a third conductive via plug disposed on the third dielectric layer and directly on the second conductive via plug, wherein the third conductive via plug does not include a dopant. In some embodiments, the first conductive via plug is made of a first metal material of a first transistor die size, the second conductive via plug is made of a second metal material of a second transistor die size, the third conductive via plug is made of a third metal material of a third transistor die size, and the first transistor die size is substantially the same as the second transistor die size and smaller than the third transistor die size. In some embodiments, the package further includes a circuit substrate and a plurality of connectors disposed on the redistribution structure, wherein the circuit substrate is electrically connected to the redistribution structure and the semiconductor die through the plurality of connectors.

[0067] According to some embodiments, a method of fabricating a package structure is provided. After providing a semiconductor die, an insulative encapsulation is formed around the semiconductor die. A redistribution structure is formed over the insulative encapsulation and on the semiconductor die. The forming of the redistribution structure includes forming a first dielectric layer having a first opening extending through the first dielectric layer, and forming a first diffusion layer on the first dielectric layer and covering the first opening. The first diffusion layer includes a first dopant. Subsequently, a first conductive via plug is formed on the first diffusion layer over the first dielectric layer, fills in the first opening, and the first diffusion layer is sandwiched therebetween, and the first conductive via plug includes the first dopant dispersed therein. After forming a second dielectric layer on the first dielectric layer and having a second opening exposing the first conductive via plug, a second diffusion layer is formed on the second dielectric layer and covering the second opening and the exposed first conductive via plug. The second diffusion layer includes a second dopant. A second conductive via plug is formed on the second diffusion layer over the second dielectric layer, fills in the second opening, and the second diffusion layer is between the first and second conductive via plugs. The second conductive via plug includes the second dopant dispersed therein. A third dielectric layer is then formed on the second dielectric layer and partially covering the second conductive via plug. According to some embodiments, a method of forming a package includes providing a semiconductor die, forming an insulative encapsulation around the semiconductor die, and forming a redistribution structure over the insulative encapsulation and on the semiconductor die. The forming of the redistribution structure includes forming a first dielectric layer having a first opening extending through the first dielectric layer, forming a first diffusion layer on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant, forming a first conductive via plug on the first diffusion layer over the first dielectric layer, wherein the first conductive via plug fills in the first opening and is sandwiched with the first diffusion layer therebetween, and the first conductive via plug includes the first dopant dispersed therein, forming a second dielectric layer on the first dielectric layer and having a second opening exposing the first conductive via plug, forming a second diffusion layer on the second dielectric layer and covering the second opening and the exposed first conductive via plug, wherein the second diffusion layer includes a second dopant, forming a second conductive via plug on the second diffusion layer over the second dielectric layer, wherein the second conductive via plug fills in the second opening and the second diffusion layer is between the first and second conductive via plugs, and the second conductive via plug includes the second dopant dispersed therein, and forming a third dielectric layer on the second dielectric layer and partially covering the second conductive via plug. In some embodiments, the forming of the first diffusion layer includes performing an electrochemical plating process to form a silver layer, and the first dopant includes silver.In some embodiments, forming the first conductive via plug includes performing copper electrochemical plating to add silver as the first dopant into the first conductive via plug. In some embodiments, forming the second diffusion layer includes performing an electrochemical plating process to form a layer of silver, and the second dopant includes silver. In some embodiments, forming the second conductive via plug includes performing copper electrochemical plating to add silver as the second dopant into the second conductive via plug.

[0068] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A package, characterized by Comprising: a molded structure including a first semiconductor die and a second semiconductor die laterally surrounded by an insulating encapsulation; and a redistribution line structure disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die, wherein the redistribution line structure includes a dielectric layer and a stacked via structure in the dielectric layer, wherein the stacked via structure includes: a first diffusion layer including a first dopant, wherein the first dopant includes silver, zinc, or manganese; a first via plug disposed on the first diffusion layer, wherein the first via plug includes a first metallic material and the first dopant dispersed within the first metallic material; a second diffusion layer disposed on the first via plug, wherein the second diffusion layer includes a second dopant; and a second via plug disposed on the second diffusion layer, wherein the second via plug includes a second metallic material and the second dopant dispersed within the second metallic material, and the second metallic material includes copper. The copper in the second metallic material has a primary crystal orientation of Cu(111).

2. The package of claim 1, wherein, The redistribution line structure includes a first routing trace embedded in the dielectric layer, the first routing trace connected to the first via plug, and the first routing trace lined with the first diffusion layer covering a surface of the first routing trace.

3. The package of claim 1, wherein, The first metallic material includes copper, and the first dopant in the first via plug has a content equal to or less than 12 at% and greater than 5 at%.

4. The package of claim 1, wherein, Comprising:

5. A package, characterized by a semiconductor die; an insulating encapsulation laterally surrounding the semiconductor die; and a redistribution line structure disposed on the semiconductor die and the insulating encapsulation and electrically connected to the semiconductor die, wherein the redistribution line structure includes: a first dielectric layer having a first opening extending through the first dielectric layer; a first diffusion layer disposed on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; a first conductive via plug disposed on the first diffusion layer, wherein the first conductive via plug includes the first dopant dispersed therein; a second dielectric layer disposed on the first dielectric layer and having a second opening exposing the first conductive via plug; a second diffusion layer disposed on the second dielectric layer and covering the second opening, wherein the second diffusion layer includes a second dopant; a second conductive via plug disposed on the second diffusion layer, wherein the second conductive via plug includes the second dopant dispersed therein; and a third dielectric layer disposed on the second dielectric layer and partially covering the second conductive via plug. The first diffusion layer includes silver, zinc, or manganese, and the second diffusion layer includes silver, zinc, or manganese.

6. The package of claim 5, wherein, The first conductive via plug includes copper, the first dopant includes silver, and the first dopant in the first conductive via plug has a content equal to or less than 12 at% and greater than 5 at%.

7. The package of claim 5, wherein, ​ 8. The package of claim 5, wherein, A third conductive via plug disposed on the third dielectric layer and directly on the second conductive via plug, wherein the third conductive via plug does not contain a dopant.

9. A method of forming a package, characterized by, Comprising: providing a semiconductor die; forming an insulating encapsulation around the semiconductor die; and forming a redistribution structure over the insulating encapsulation and on the semiconductor die, wherein forming the redistribution structure comprises: forming a first dielectric layer having a first opening extending through the first dielectric layer; forming a first diffusion layer on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; forming a first conductive via plug on the first diffusion layer over the first dielectric layer, wherein the first conductive via plug fills in the first opening with the first diffusion layer in between, and the first conductive via plug includes the first dopant dispersed therein; forming a second dielectric layer on the first dielectric layer and having a second opening exposing the first conductive via plug; forming a second diffusion layer on the second dielectric layer and covering the second opening and the exposed first conductive via plug, wherein the second diffusion layer includes a second dopant; forming a second conductive via plug on the second diffusion layer over the second dielectric layer, wherein the second conductive via plug fills in the second opening, and the second diffusion layer is between the first conductive via plug and the second conductive via plug, and the second conductive via plug includes the second dopant dispersed therein; and forming a third dielectric layer on the second dielectric layer and partially covering the second conductive via plug.

10. The method of forming a package of claim 9, wherein, forming the first diffusion layer includes performing an electrochemical plating process to form a silver layer, and the first dopant includes silver.

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