Embedded frame, embedded substrate, preparation method of embedded substrate, power supply device and electronic equipment

Abstract

The embodiment of the invention discloses an embedded frame, an embedded substrate, a power supply device, electronic equipment and a preparation method of the embedded substrate. The embedded frame comprises a core holding body, a first wiring layer and a first insulating layer; the core holding body comprises two side plate surfaces which are oppositely arranged, the first wiring layer is arranged on one side plate surface of the core holding body, and the first insulating layer covers the outside of the first wiring layer; the embedded frame is provided with an embedded groove in which an electronic component can be embedded, and the embedded groove penetrates through the core holding body, the first wiring layer and the first insulating layer. According to the arrangement, based on the insulating layer arranged outside the wiring layer, insulation protection on the wiring layer can be constructed, the surface of the embedded frame is free of copper, when layer adding is further pressed after elements are mounted, foreign matter can be effectively prevented from making contact with the wiring layer through the insulating layer, the interlayer short circuit risk is effectively avoided, and the effect of improving warping of the embedded substrate is achieved. And on the whole, the method has relatively good reliability so as to meet the application requirements of different high-integration and high-density scenes.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronic component packaging, and in particular to a buried frame, an embedded substrate, a power supply device, an electronic device, and a preparation method of the embedded substrate. BACKGROUND

[0002] The embedded substrate technology can embed electronic components in the buried frame of the substrate, such as but not limited to chips, resistors, capacitors, inductors, and the like, and realize interconnection through peripheral circuits to form a high-integration and high-density functional module. In a general embedded substrate process, a buried groove is first formed in the buried frame of the surface wiring, and then the components are attached, and subsequent processes such as substrate build-up are performed. Between the component attachment and the build-up station, if the environment or device foreign matter falls on the surface wiring of the buried frame, it is easy to cause interlayer short circuit after laminated build-up, that is, based on the existence of foreign matter, the short circuit between the surface wiring of the buried frame and the outer build-up wiring is caused. In particular, the small foreign matter cannot be effectively detected during product electrical testing, resulting in a reliability risk in the terminal product, which has a great impact. SUMMARY

[0003] Embodiments of the present application provide a buried frame, an embedded substrate, a preparation method of the embedded substrate, a power supply device, and an electronic device, which avoid the short circuit risk of the embedded substrate and improve the reliability through optimization of the buried frame structure.

[0004] The first aspect of the embodiments of the present application provides a buried frame for embedding electronic components, specifically comprising a core retaining body, a first wiring layer, and a first insulating layer; wherein the core retaining body comprises two side plate surfaces arranged oppositely, the first wiring layer is arranged on one side plate surface of the core retaining body, and the first insulating layer is arranged outside the first wiring layer; the buried frame is provided with a buried groove for embedding electronic components, and the buried groove penetrates the core retaining body, the first wiring layer, and the first insulating layer. In this way, based on the insulating layer arranged outside the wiring layer, the insulating protection of the wiring layer can be constructed, that is, there is no copper on the surface of the buried frame, and after attaching the components and further build-up, the insulating layer can effectively prevent the foreign matter from contacting the wiring layer, thereby effectively avoiding the interlayer short circuit risk. Overall, it has good reliability to meet the application requirements of different high-integration and high-density scenarios.

[0005] In addition, based on the insulating layer arranged outside the buried frame, the warping of the embedded substrate can also be improved.

[0006] Exemplarily, the core retaining body can be a core plate. In actual application, the core plate can be made of organic material or glass material.

[0007] Other exemplarily, the core retaining body can also be formed by filling material.

[0008] Based on the first aspect, the embodiments of the present application further provide a first implementation of the first aspect: the embedded frame further comprises a second wiring layer and a second insulating layer, wherein the second wiring layer is arranged on the other side plate surface of the core holding body, the second insulating layer covers the outside of the second wiring layer, and the embedded groove penetrates through the second wiring layer and the second insulating layer. In this way, the needs of different application scenarios can be met, and good adaptability is achieved.

[0009] For example, in actual application, for electronic components with double-sided PINs, the interconnection wiring of the corresponding side can be conveniently constructed.

[0010] Exemplarily, the first insulating layer and the second insulating layer can be made of Ajinomoto Build-up Film (ABF) material or Prepreg (PP) material.

[0011] Based on the first implementation of the first aspect, the embodiments of the present application further provide a second implementation of the first aspect: the thickness of the first insulating layer and the thickness of the second insulating layer are the same or different. In this way, the warping of the embedded substrate can be further improved.

[0012] In actual application, for application scenarios of product asymmetric structure, the thickness of the first insulating layer and / or the second insulating layer can be adjusted for processing. For example, the asymmetric arrangement of the embedded substrate surface-mounted device, etc. can be limited by reducing or increasing the thickness of the first insulating layer and the second insulating layer, thereby reversing the warping trend. In this way, on the basis of effectively preventing foreign matter from contacting the wiring layer, the warping problem of the embedded substrate product can be flexibly improved. Overall, the application reliability and good adaptability are taken into account.

[0013] Based on the first implementation of the first aspect or the second implementation of the first aspect, the embodiments of the present application further provide a third implementation of the first aspect: the core holding body is provided with a through structure, and the first wiring layer and the second wiring layer are interconnected through the through structure. In this way, the line interconnection of the corresponding double-layer wiring layer can be realized as needed, and a functional circuit meeting different needs is constructed.

[0014] Exemplarily, the through structure includes a via hole with a copper-plated end face, a via hole without a copper-plated end face, or an X-shaped hole.

[0015] In actual application, the number and position of the through structure can be configured according to the functional needs of the product, so as to establish a corresponding interconnection relationship between the first wiring layer and the second wiring layer.

[0016] For the case that multiple conductive structures are arranged on the embedded frame, a combination of different structural forms of conductive structures can be adopted, for example, but not limited to, any combination of PTH holes without Cap copper, PTH holes with Cap copper, and X-shaped holes.

[0017] Based on the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, the fourth implementation of the first aspect is provided in the embodiments of the present application: the first insulating layer is arranged as one layer or multiple layers, and the second insulating layer is arranged as one layer or multiple layers. In actual application, it can be determined according to actual process conditions, and better processability is achieved.

[0018] The second aspect of the embodiments of the present application provides an embedded substrate, which comprises an embedded frame, a build-up layer, and an electronic component. The embedded frame is as described above, the electronic component is embedded in the embedded groove of the embedded frame, the build-up layer is arranged on the embedded frame, and the circuit layer of the build-up layer is electrically connected with the pin of the electronic component. Based on the embedded frame without copper on the surface, technical support is provided to avoid the risk of short circuit of the embedded substrate. In actual application, for smaller foreign matters that cannot be effectively detected during product electrical measurement, the hidden danger of terminal product reliability can also be avoided, and the product reliability is effectively improved.

[0019] Based on the second aspect, the first implementation of the second aspect is provided in the embodiments of the present application: the thickness of the embedded frame is greater than or equal to the thickness of the electronic component. In this way, the electronic component embedded in the embedded groove will not be exposed to the embedded frame, that is, it can be completely placed in the corresponding embedded groove, and the risk of subsequent lamination process can be further avoided.

[0020] The third aspect of the embodiments of the present application provides a power supply device, which comprises a chip and an inductor. The chip forms an embedded package by using the embedded substrate as described above, and the inductor is surface-mounted on the embedded substrate. Exemplarily, the inductor can be surface-mounted on the front surface of the embedded substrate, or surface-mounted on the back surface of the embedded substrate.

[0021] Based on the third aspect, the first implementation of the third aspect is provided in the embodiments of the present application: the power supply device further comprises multiple electronic components, a part of the multiple electronic components and the chip form an embedded package by using the embedded substrate, and another part of the multiple electronic components are surface-mounted on the embedded substrate with the inductor. In this way, the configuration can be flexibly performed according to the functional needs of the product, and better designability is achieved.

[0022] The fourth aspect of the embodiments of the present application provides an electronic device, which comprises a circuit board and a power supply device. The power supply device is arranged on the circuit board, and the power supply device is as described above.

[0023] In practical applications, this electronic device can be a server, computer, or high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, this electronic device can also be a switch, router, or edge device, etc.

[0024] The fifth aspect of this application provides a method for preparing an embedded substrate, comprising: providing an embedded frame as described above; mounting electronic components such that the electronic components are placed in the embedded grooves of the embedded frame; filling and pressing with an embedded filler material to fix the electronic components to the embedded frame; and fabricating an add-on layer on the outside of the embedded substrate.

[0025] In practical applications, an adhesive film can be applied to one side of the embedding frame to house electronic components within the embedding groove and fix them to the adhesive film. The adhesive film can then be removed after the electronic components are pressed and fixed to the embedding frame using the embedding filler material.

[0026] Based on the fifth aspect, the present application also provides a first implementation of the fifth aspect: the preparation of the embedded frame includes: preparing a core holder and forming a surface copper layer on the board surface of the core holder; patterning the surface copper layer to form a wiring layer of the embedded frame; laminating an insulating layer on the outside of the wiring layer; and opening an embedded groove, wherein the embedded groove penetrates the core holder, the wiring layer and the insulating layer.

[0027] Based on the first embodiment of the fifth aspect, this application also provides a second embodiment of the fifth aspect: the patterned surface copper layer forms a wiring layer of the embedded frame, including: patterning the surface copper layers located on both sides of the core retainer to form a first wiring layer and a second wiring layer of the embedded frame respectively, and preparing a conductive structure electrically connected to the first wiring layer and the second wiring layer.

[0028] Based on the first embodiment of the fifth aspect, this application also provides a second embodiment of the fifth aspect: the conductive structure includes a through hole with copper plating on the end face, a through hole without copper plating on the end face, or an X-shaped hole. Attached Figure Description

[0029] Figure 1 A cross-sectional schematic diagram of an embedded frame provided for an embodiment of this application;

[0030] Figure 2 for Figure 1 A schematic diagram of the manufacturing process of the embedded frame shown in the figure;

[0031] Figure 3 This application provides a cross-sectional view of an embedded substrate architecture.

[0032] Figure 4 A cross-sectional schematic diagram of another embedded frame provided in an embodiment of this application;

[0033] Figure 5 For Figure 4 Process flow diagram of the process of embedding the frame shown in FIG. 1;

[0034] Figure 6 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided;

[0035] Figure 7 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided;

[0036] Figure 8 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided;

[0037] Figure 9 For Figure 8 Process flow diagram of the process of embedding the frame shown in FIG. 1;

[0038] Figure 10 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided;

[0039] Figure 11 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided;

[0040] Figure 12 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided;

[0041] Figure 13 Another architecture cross-sectional view of the embedded substrate provided by the embodiments of the present application is provided; DETAILED DESCRIPTION

[0042] The embodiments of the present application provide an embedded substrate implementation scheme that can improve reliability, which can be applied to different high integration and high density application scenarios.

[0043] The embedded substrate technology is used to embed electronic components in the embedding frame of the substrate, which can shorten the link path between components, reduce transmission loss, improve product integration, and reduce module size. Taking the embedded substrate of the power chip packaging module as an example, a typical embedded substrate architecture can embed components such as chips, capacitors, and / or resistors in the embedding frame, and the embedding frame surface is stacked with an increase layer, which can be used to realize the interconnection between electronic components and the connection with external circuits. Generally, the process of the embedded substrate opens an embedding groove on the embedding frame, the surface of the embedding frame has a wiring, and then the components are mounted and the increase layer is compressed. Between the component mounting station and the increase layer compression station, if the environment or equipment foreign matter falls on the embedding frame of the surface wiring, based on the existence of the foreign matter, it is easy to cause interlayer short circuit after laminating the increase layer. For smaller foreign matter, it is often not possible to effectively detect during product electrical measurement, resulting in potential reliability risks in the terminal product, thereby causing greater impact.

[0044] Based on this, the application provides an embedded frame of an embedded substrate, which is used for embedding electronic components. The embedded frame comprises a core holding body, a first wiring layer and a first insulating layer. The core holding body comprises two oppositely arranged side plate surfaces. The first wiring layer is arranged on one side plate surface of the core holding body. The first insulating layer is arranged on the outside of the first wiring layer. The embedded groove of the embedded frame penetrates the core holding body, the first wiring layer and the first insulating layer. In this way, based on the insulating layer arranged on the outside of the wiring layer, the insulating protection of the wiring layer can be formed. After the components are attached, the insulating layer can effectively prevent foreign matters from contacting the wiring layer, thereby effectively avoiding the risk of interlayer short circuit. Overall, the embedded frame has good reliability, thereby meeting the application requirements of different high integration and high density scenes.

[0045] In order to better understand the technical solutions and technical effects of the application, without losing generality, specific embodiments will be described in detail below in combination with the drawings. Please refer to Figure 1 , which is a cross-sectional schematic view of an embedded frame provided by an embodiment of the application.

[0046] As Figure 1 indicated, the core holding body 11 of the embedded frame 10 can be made of a core plate, for example but not limited to, a core plate made of an organic material or a glass material.

[0047] In this embodiment, the wiring layer 12, i.e., the first wiring layer 121 and the second wiring layer 122, is arranged on the two side plate surfaces of the core holding body 11. Specifically, the first wiring layer 121 is arranged on one side plate surface of the core holding body 11, and the second wiring layer 122 is arranged on the other side plate surface of the core holding body 11.

[0048] In a specific implementation, based on the first wiring layer 121 and the second wiring layer 122, the electronic components (not shown in the figure) embedded in the embedded groove 15 can be electrically connected with the wiring layers on the corresponding side, so as to realize the interconnection between the electronic components (not shown in the figure) and the external circuit, thereby constructing the corresponding functional circuit. In other specific implementations, based on the first wiring layer 121 and the second wiring layer 122, the interconnection between the electronic components (not shown in the figure) can also be realized.

[0049] The insulating layer 13, i.e., the first insulating layer 131 and the second insulating layer 132, is arranged on the outside of the wiring layer 12. Specifically, the first insulating layer 131 is arranged on the outside of the first wiring layer 121, and the second insulating layer 132 is arranged on the outside of the second wiring layer 122. In this way, the wiring layer 12 on the corresponding side can be protected from foreign matters. That is, compared with the traditional embedded frame, the surface of the embedded frame 10 provided by the application is copper-free, which can effectively avoid the risk of interlayer short circuit caused by foreign matters.

[0050] In a specific implementation, the insulating layer 13 can be made of ABF material or PP material. It can be understood that the material selection of the insulating layer can be determined according to the overall design requirements of the product, as long as it can effectively block the influence of foreign matters and effectively avoid the risk of possible interlayer short circuit.

[0051] In other specific implementations, the first insulating layer 131 covering the outside of the first wiring layer 121 can be set as one layer or multiple layers as needed. Similarly, the second insulating layer 132 covering the outside of the second wiring layer 122 can also be set as one layer or multiple layers as needed. The embodiments of the present application are not limited.

[0052] The first wiring layer 121 and the second wiring layer 122 can be interconnected through the conductive structure 14 penetrating the core holding body 11. Figure 1 In a specific implementation, a Plating Through Hole (PTH) with a Cap copper on the end face is used as a conductive structure 14. A copper layer is plated on the sidewall of the hole, so that the hole wall of the PTH hole has conductivity, and the conductive structure 14 for interconnecting the first wiring layer 121 and the second wiring layer 122 is formed on the end face of the through hole, and the first wiring layer 121 and the second wiring layer 122 on both sides of the embedded frame 10 are respectively electrically connected.

[0053] In actual application, based on the PTH hole with Cap copper as the conductive structure, the welding performance can be further enhanced while improving the current-carrying capacity.

[0054] To clearly show the conductive structure 14, Figure 1 In a specific implementation, a PTH hole with Cap copper is exemplarily shown. Of course, the number of the conductive structure 14 is not limited to one shown in the figure, and the number can be configured according to the functional requirements of the product to establish the corresponding interconnection relationship between the first wiring layer 121 and the second wiring layer 122. The embodiments of the present application are not limited.

[0055] The embedded groove 15 for embedding electronic components is provided through the embedded frame. In other words, the embedded groove 15 is provided through the first insulating layer 131, the first wiring layer 121, the core holding body 11, the second wiring layer 122 and the second insulating layer 132. Before the electronic component is mounted, the surface of the embedded frame 10 is copper-free, which is an intermediate architecture product of the embedded frame process, and is protected by the two-side insulating layer 13 and is not affected by foreign matters that may be generated in the process of use of the environment or equipment.

[0056] To clearly show the basic structure of the embedded groove 15, Figure 1Only one embedding groove 15 is exemplarily shown. It should be noted that in different application scenarios, the embedding groove can be configured in terms of position, number and size according to product functional requirements to embed one or more electronic components in an embedding frame and realize corresponding interconnection relationship through the first wiring layer 121 and the second wiring layer 122. The embodiments of the present application are not limited.

[0057] The process of the embedding frame 10 will be described below in conjunction with Figure 2 Brief description Figure 1 The process of the embedding frame 10 will be described below in conjunction with

[0058] In step S201, a core plate is prepared as the core holding body 11. In a specific implementation, based on the core plate, a copper layer can be prepared on the two side surfaces of the core holding body 1 to form the wiring layer 12.

[0059] In step S202, the wiring layer is patterned and formed, and the through-structure 14 is prepared. In a specific implementation, the first wiring layer 121 and the second wiring layer 122 on the two sides of the core holding body 11 can be formed respectively. Here, the through-structure 14 is a PTH hole with CAP copper, which is electrically connected to the first wiring layer 121 and the second wiring layer 122 respectively through the PTH hole with CAP copper, and realizes the interconnection between the two.

[0060] In step S203, the insulation layer is laminated. In a specific implementation, the first insulation layer 131 and the second insulation layer 132 can be respectively laminated outside the first wiring layer 121 and the second wiring layer 122. Here, the material of the insulation layer can be ABF or PP.

[0061] In step S204, the embedding groove 15 is opened. In a specific implementation, UV Laser (ultraviolet laser), CO2laser (carbon dioxide laser) or other mechanical processing can be used to groove the embedding frame 10. Thus, the embedding frame 10 without copper on the surface is prepared.

[0062] Based on the insulation layer arranged outside the embedding frame, in the subsequent process of embedding the substrate, in addition to effectively blocking the contact between foreign matters and the wiring layer, the effect of improving the warping of the embedded substrate is achieved. Please see Figure 3 , which is a schematic cross-sectional view of an embedded substrate provided by an embodiment of the present application. Figure 3 The embedded substrate 100 shown in Figure 1 is constructed by the embedding frame 10 shown in

[0063] The embedded substrate 100 includes the embedded frame 10, the build-up layer 20 and the electronic component 30. The electronic component 30 is embedded in the embedded groove 15 of the embedded frame 10. For example, the electronic component 30 can be a chip of a power module, or other components such as resistors or capacitors. The build-up layer 20 includes the build-up wiring layer 21 and the dielectric layer 22. The pin of the electronic component 30 can be electrically connected to the build-up wiring layer 21 through the blind via hole 211 in the corresponding side build-up layer 20.

[0064] In the embodiment, the first build-up layer 201 is stacked on one side of the first insulating layer 131, and the second build-up layer 202 is stacked on one side of the second insulating layer 132. For the embedded substrate 100, based on the arrangement of the external insulating layer 12 of the embedded frame 10, the overall rigidity of the architecture is enhanced, which can improve the warping problem of the embedded substrate 100 to a certain extent, for example, but not limited to, the deformation caused by the operation heat of the component or the assembly process, etc., reduce the influence of the warping stress, and further improve the application reliability.

[0065] For example, as shown in FIG. 1, the embedded substrate 100 includes the embedded frame 10, the first insulating layer 131, the second insulating layer 132, the build-up layer 20 and the electronic component 30. The embedded frame 10 includes the embedded groove 15 and the embedded frame 10 is arranged on the first insulating layer 131. The electronic component 30 is embedded in the embedded groove 15 of the embedded frame 10. The build-up layer 20 includes the build-up wiring layer 21 and the dielectric layer 22. The pin of the electronic component 30 can be electrically connected to the build-up wiring layer 21 through the blind via hole 211 in the corresponding side build-up layer 20. Figure 1 As shown in FIG. 1, the thickness of the first insulating layer 131 is t1, and the thickness of the second insulating layer 132 is t2. In specific implementation, the thickness t1 of the first insulating layer 131 and the thickness t2 of the second insulating layer 132 can be the same or different, to further improve the warping of the embedded substrate 100. In particular, for the application scenario of the asymmetric structure of the product, the thickness of the first insulating layer 131 and / or the second insulating layer 132 can be adjusted for processing. For example, the asymmetric arrangement of the surface-mounted device of the embedded substrate causes the overall embedded substrate 100 to have a warping of the upper middle part, which can be limited in the reverse direction by reducing the thickness t1 of the first insulating layer 131 or increasing the thickness t2 of the second insulating layer 132. On the basis of effectively preventing foreign matters from contacting the wiring layer, the warping problem of the embedded substrate product can be flexibly improved. Overall, the application reliability and good adaptability are taken into account.

[0066] In specific implementation, the material of the dielectric layer 22 of the build-up layer 20 can be the same as or different from the material of the insulating layer 12. The material can be determined according to the overall design requirement of the product, which is not limited in the embodiments of the present application.

[0067] Specifically, as shown in FIG. 1, the embedded substrate 100 includes the embedded frame 10, the first insulating layer 131, the second insulating layer 132, the build-up layer 20 and the electronic component 30. The embedded frame 10 includes the embedded groove 15 and the embedded frame 10 is arranged on the first insulating layer 131. The electronic component 30 is embedded in the embedded groove 15 of the embedded frame 10. The build-up layer 20 includes the build-up wiring layer 21 and the dielectric layer 22. The pin of the electronic component 30 can be electrically connected to the build-up wiring layer 21 through the blind via hole 211 in the corresponding side build-up layer 20. Figure 3 As shown in FIG. 1, the electronic component 30 is a single-sided pin (PIN) component, and the pin thereof can be electrically connected to the build-up wiring layer 21 of the second build-up layer 202 through the blind via hole 211.

[0068] In other specific implementations, the electronic component can also be a double-sided PIN-out component (not shown in the figure) and is electrically connected to the build-up wiring layer 21 of the build-up layer on both sides of the embedded frame 10. The specific implementation can be selected according to the overall design requirements of the product.

[0069] Optionally, the thickness of the embedded frame 10 is not less than the thickness of the electronic component 30, that is, the thickness of the embedded frame 10 is greater than or equal to the thickness of the electronic component 30. In this way, it can be ensured that the electronic component 30 embedded in the corresponding embedded groove 15 is not exposed, that is, it is completely placed in the embedded groove 15. In this way, the risk of subsequent lamination processes can be further avoided.

[0070] In addition, the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 can be electrically connected to the first wiring layer 121 and the second wiring layer 122 of the embedded frame 10 on the corresponding side through the interlayer via structure 212. It should be understood that the interlayer via structure shown in the figure is only an exemplary schematic, and in different product application scenarios, it can be configured according to actual functional needs. The embodiments of the present application are not limited.

[0071] For the embedded frame 10 with double-sided wiring layers 12, the via structure for interconnecting the first wiring layer 121 and the second wiring layer 122 can also adopt other structural forms.

[0072] Please refer to Figure 4 , which is a cross-sectional schematic view of another embedded frame provided by the embodiments of the present application. In order to clearly show the differences and connections between the embedded frame described in Figure 1 and the embedded frame described in the present embodiment, the same functional components or structures are shown in the figure with the same reference signs.

[0073] As Figure 4 shown, the embedded frame 10 uses a Capless copper PTH hole as another via structure 14a, and a copper layer is plated on the sidewall of the hole, so that the hole wall of the PTH hole has conductivity, forming a via structure 14a for interconnecting the first wiring layer 121 and the second wiring layer 122.

[0074] Other functional components and connection relationships can be consistent with the embedded frame described in Figure 1 . Here, further description is omitted.

[0075] The process of the embedded frame 10 described in Figure 5 will be briefly described below. Figure 4

[0076] In step S501, a core plate is prepared as a core holding body 11.

[0077] ​Step S502, patterned to form the wiring layer, and prepare the interlayer conductive structure 14a. Here, the conductive structure 14a is a CAP-free copper PTH hole.

[0078] Step S503, laminated to form the insulating layer.

[0079] Step S504, open the embedded slot 15. Thus, the surface copper-free embedded frame 10 is made.

[0080] The above steps S501, S503 and S504 can refer to the same steps S201, S203 and S204 in Figure 2 .

[0081] In addition, please refer to the embedded substrate 100 shown in Figure 6 and Figure 7 , Figure 6 and Figure 7 , which are all based on the embedded frame 10 shown in Figure 4 . In order to clearly show the differences and connections between the embodiments and the embedded substrate described in Figure 3 , the same functional components or structures are shown with the same reference signs in the figures.

[0082] Please refer to Figure 6 , the embedded substrate 100 includes the embedded frame 10, the build-up layer 20 and the electronic component 30 shown in Figure 4 . The electronic component 30 is embedded in the embedded slot 15 of the embedded frame 10. The build-up layer 20 includes the build-up wiring layer 21 and the dielectric layer 22 formed by pressing. The first build-up layer 201 is stacked on one side of the first insulating layer 131, and the second build-up layer 202 is stacked on one side of the second insulating layer 132.

[0083] In this embodiment, the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 can be electrically connected through the via hole 212a. In a specific implementation, the via hole 212a can be connected with the conductive structure on the embedded frame 10, such as but not limited to the vertical interconnection shown in the figure, and the electrical connection between the two can also be established through an independently formed via hole. The present application does not limit the embodiment.

[0084] In other possible implementations, the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 can also be electrically connected through the interlayer conductive structure such as the blind hole (not shown in the figure) between the first wiring layer 121 and the second wiring layer 122 of the embedded frame 10 on the corresponding side. In different product application scenarios, the configuration can be made according to the actual functional needs. The present application does not limit the embodiment.

[0085] Figure 6The via 212a shown is a PTH via without cap copper. For other specific implementations, please refer to [link / reference]. Figure 7 The first augmentation layer 201 and the second augmentation layer 202 of the embedded substrate 100 are electrically connected through a through-hole 212b, which is a PTH hole with cap copper.

[0086] It should be understood that the interconnect structure of the added-layer wiring layer 21 can be selected according to product design and process conditions, such as, but not limited to, any combination of conduction structures such as PTH vias without cap copper, PTH vias without cap copper, and X-shaped vias (not shown in the figure), and the embodiments of this application are not limited.

[0087] for Figure 6 and Figure 7 The embedded substrate shown, along with its other functional components and connections, can be compared with... Figure 3 The description of the embedded substrate is consistent. Further details will not be provided here.

[0088] For the embedded frame 10 with double-sided wiring layers 12, please also refer to Figure 8 This figure is a cross-sectional schematic diagram of another embedded frame provided in an embodiment of this application. To clearly illustrate the implementation scheme and... Figure 1 The differences and connections between the embedded frames described, and the same functional components or structures are illustrated in the figure with the same markings.

[0089] like Figure 8 As shown, the embedded frame 10 uses X-shaped holes as another conductive structure 14b. Copper is filled into the X-shaped openings to form the conductive structure 14b, thereby realizing the interconnection between the first wiring layer 121 and the second wiring layer 122. This can further improve the interlayer current carrying capacity and high thermal conductivity, and make the architecture design more flexible.

[0090] Other functional components and connections can be related to Figure 1 The embedded framework described is consistent. Further details will not be provided here.

[0091] The following is combined Figure 9 Brief description Figure 8 The process of embedding the frame 10 described in the document.

[0092] Step S901: Prepare the core plate as the core retainer 11.

[0093] Step S902 involves patterning a wiring layer and fabricating an interlayer conductive structure 14b. Here, the conductive structure 14b is an X-shaped via.

[0094] Step S903: Lamination to form an insulating layer.

[0095] Step S904, the embedded groove 15 is opened. Thus, the surface copper-free embedded frame 10 is made.

[0096] The above steps S901, S903 and S904 can refer to the steps S201, S203 and S204 in Figure 2 .

[0097] It can be understood that, for the sake of clear illustration of the conductive structure 14a and the conductive structure 14b, Figure 4 , an exemplary PTH hole with Cap copper is schematically shown, Figure 8 , an exemplary X-shaped hole is schematically shown. The number of the conductive structures can be configured according to the functional requirements of the product to establish the corresponding interconnection relationship between the first wiring layer 121 and the second wiring layer 122. The embodiments of the present application are not limited.

[0098] In addition, for the case that the embedded frame 10 is provided with a plurality of conductive structures, in other possible specific implementations, a combination of different structure forms of conductive structures can be used, for example, but not limited to, any combination of PTH holes without Cap copper, PTH holes with Cap copper and X-shaped holes (not shown in the figure).

[0099] The embedded frame described in the foregoing embodiments is provided with the wiring layer 12 on both sides. In other implementations, the embedded frame can be provided with the wiring layer on one side surface of the core holding body 11 and the corresponding insulating layer on the other side surface. Please refer to Figure 10 , which is a cross-sectional view of another embedded frame provided by the embodiments of the present application. In order to clearly show the differences and connections between the embedded frame of the present embodiment and the embedded frame described in Figure 1 , the same functional components or structures are schematically shown with the same reference numerals in the figure.

[0100] As shown in Figure 10 , the embedded frame 10 includes a core holding body 11 made of a core plate, and is provided with a wiring layer 12 (121) and an insulating layer 13 (131) on one side surface of the core holding body 11. Similarly, based on the provision of the insulating layer, the contact of foreign matter with the wiring layer can be blocked, and the risk of short circuit can be avoided.

[0101] The other functional components and connection relationships can be consistent with the embedded frame described in Figure 1 . Here, further description is omitted.

[0102] The foregoing embodiments all use a core plate as the core holding body 11. In other specific implementations, a filling material can also be used to form the core holding body. That is, a coreless frame structure, which is simple in process and can reasonably control the manufacturing cost.

[0103] For the embedded substrate described in the foregoing embodiments, the following will be described in combination withFigure 11 Briefly describe the preparation method.

[0104] Step S1101, provide the embedded frame 10 described in the foregoing Figure 1 , Figure 4 , Figure 8 Or Figure 10 In a specific implementation, for the embedded frame 10 described in Figure 1 , for example but not limited to, prepared by adopting the process described in Figure 2 ; for the embedded frame 10 described in Figure 4 , for example but not limited to, prepared by adopting the process described in Figure 5 ; for the embedded frame 10 described in Figure 8 , for example but not limited to, prepared by adopting the process described in Figure 9 ; for the embedded frame 10 described in Figure 10 , please refer to the corresponding process steps in Figure 2 , Figure 5 Or Figure 9 .

[0105] Step S1102, paste electronic components 30. Specifically, an adhesive film can be attached to one side surface of the embedded frame 10 to embed the electronic components in the embedded groove and attach and fix them to the adhesive film.

[0106] Step S1103, filling and pressing. In a specific implementation, an embedded filling material can be used to press and fill the gap between the electronic components and the embedded groove. The adhesive film can be removed after the electronic components are fixed to the embedded frame 10. Here, the embedded filling material can be ABF, or selected according to actual process conditions.

[0107] Step S1104, making and forming the increment layer. In a specific implementation, the aforementioned embedded filling material can form a dielectric layer of the increment layer in conjunction with the insulating layer of the embedded frame 10 while filling the gap. On this basis, the surface copper of the increment layer wiring layer is prepared, and the increment layer wiring layer is made and formed by surface patterning.

[0108] In addition, for the case of having multiple outer layer increments, they can be sequentially pressed and formed according to specific process conditions. At the same time, a solder resist layer is formed on the surface of the wiring layer of the outermost increment layer, and the surface of the outer metal is processed. In other possible implementation schemes, the number of layers of each outer increment layer can be determined according to the overall design requirements of the product, and the corresponding process procedures are formulated. The embodiments of the present application are not limited.

[0109] The embedded substrate architecture scheme described in the foregoing embodiments can be widely applied to the packaging structure of different functional modules. In actual application, the above technical advantages are particularly significant in the power module architecture scenario. Please refer to Figure 12Fig. 1 is a schematic diagram of a power supply device according to an embodiment of the present application.

[0110] As shown in Figure 12 , the power supply device 1000 includes an inductor 200 and a chip, and further includes a capacitor element and a resistor element (not shown in the figure) to construct a corresponding functional circuit. The chip can be formed into a buried package using the embedded substrate 100 architecture described in Figure 3 , Figure 6 or Figure 7 . The inductor 200 can be surface-mounted on the surface of the embedded substrate 100.

[0111] In a specific implementation, the capacitor element and the resistor element can be embedded in the embedded substrate 100 together with the chip, or can be surface-mounted on the embedded substrate 100 together with the inductor 200 (not shown in the figure). The embodiments of the present application are not limited in this regard. In use, the reliability of the embedded substrate can meet the performance requirements of the power supply device.

[0112] It should be understood that other functional configurations of the power supply device are not the core of the present application, and can be implemented by those skilled in the art based on the prior art, so this document will not be described here.

[0113] In addition to the aforementioned embedded substrate, the present embodiment also provides an electronic device, please refer to Figure 13 , Fig. 2 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application.

[0114] As shown in Figure 13 , the electronic device 10000 includes a housing 3000 and a circuit board 2000 disposed in the housing 3000, and the circuit board 2000 is provided with a power supply device 1000 as described in the foregoing embodiments. Based on the high reliability of the power supply device 1000, it can be widely used in different high-density application scenarios.

[0115] In a specific implementation, the electronic device can be a server, a computer, or a high-performance computing cluster, for a high-power, high-integration, and super-large data center server. In addition, the electronic device can also be a switch, a router, or an edge device, and the embodiments of the present application are not limited in this regard.

[0116] It should be understood that other functional configurations of the electronic device are not the core of the present application, and can be implemented by those skilled in the art based on the prior art, so this document will not be described here.

[0117] The above is only a preferred embodiment of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. An embedded frame for embedding electronic components, characterized in that, The embedded frame comprises a core holding body, a first wiring layer and a first insulating layer; the core holding body comprises two oppositely arranged side plate surfaces, the first wiring layer is arranged on one side plate surface of the core holding body, and the first insulating layer is arranged outside the first wiring layer; the embedded frame is provided with an embedded groove, and the embedded groove penetrates through the core holding body, the first wiring layer and the first insulating layer.

2. The flush frame of claim 1, wherein, The embedded frame further comprises a second wiring layer and a second insulating layer, the second wiring layer is arranged on the other side plate surface of the core holding body, the second insulating layer is arranged outside the second wiring layer, and the embedded groove further penetrates through the second wiring layer and the second insulating layer.

3. The flush frame of claim 2, wherein, The thickness of the first insulating layer and the thickness of the second insulating layer are the same or different.

4. The flush frame of claim 2 or 3, wherein, The core holding body is provided with a conductive structure, and the first wiring layer and the second wiring layer are interconnected through the conductive structure.

5. The flush frame of claim 4, wherein, The conductive structure comprises a through hole with copper plating on an end surface, a through hole without copper plating on an end surface or an X-shaped hole.

6. The flush-mount frame of any of claims 2-5, wherein, The first insulating layer is arranged as one layer or multiple layers, and the second insulating layer is arranged as one layer or multiple layers.

7. The flush-mount frame of any of claims 1-6, wherein, The core holding body is a core plate.

8. An embedded substrate, characterized by, The embedded frame comprises an embedded frame, a build-up layer and an electronic component, the embedded frame is the embedded frame according to any one of claims 1 to 7, the electronic component is embedded in the embedded groove of the embedded frame, the build-up layer is arranged on the embedded frame, and a circuit layer of the build-up layer is electrically connected with a pin of the electronic component.

9. The embedded substrate of claim 8, wherein, The thickness of the embedded frame is greater than or equal to the thickness of the electronic component.

10. A power supply device characterized by comprising: The embedded frame comprises a chip and an inductor, the chip forms an embedded package by using the embedded substrate according to claim 8 or 9, and the inductor is attached to the embedded substrate.

11. The power supply device according to claim 10, wherein The power supply device further comprises a plurality of electronic components, a part of the plurality of electronic components and the chip form an embedded package by using the embedded substrate, and another part of the plurality of electronic components and the inductor are attached to the embedded substrate.

12. An electronic device, comprising: The power supply device comprises a circuit board and a power supply device, the power supply device is arranged on the circuit board, and the power supply device is the power supply device according to claim 10 or 11.

13. A method of manufacturing a buried substrate, characterized by, The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises:

14. The method of claim 13, wherein The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises:

15. 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The method of claim 15, wherein The conductive structure includes a via plated with copper on an end face, a via not plated with copper on an end face, or an X-shaped hole.

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