Packaging structure, manufacturing method thereof and electronic device
By using conductive connection structures on the interconnect substrate and lead-out structures in the sub-package structure in the packaging structure, the problem that traditional packaging technology cannot meet high-speed data transmission is solved, and a low-cost, high-yield high-speed interconnect effect is achieved.
Patent Information
- Application Number
- CN202411080886.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-07
- Publication Date
- 2026-02-13
AI Technical Summary
Traditional packaging technologies cannot meet the demands of high-speed data transmission and also suffer from problems such as high processing difficulty and high cost.
Electrical connections between two adjacent sub-package structures are achieved by using conductive connection structures on the interconnect substrate and lead-out structures of the sub-package structure. Interconnect lines are fabricated using substrate technology, with line widths reaching approximately 10 micrometers, thus avoiding the use of silicon interposers.
High-speed interconnection was achieved, which reduced processing difficulty and cost and improved yield.
Smart Images
Figure CN121532040A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to a packaging structure, a manufacturing method of the packaging structure, and an electronic device. BACKGROUND
[0002] Integrated circuit (IC) chips are widely used in various electronic devices, and can be packaged by semiconductor packaging technology. The semiconductor packaging technology can integrate multiple chips together to provide more powerful functions.
[0003] With the continuous advancement of integrated circuit technology, the integration of chips is continuously improved, and the data transmission speed between chips is also getting faster and faster. This poses a challenge to traditional packaging technology, as traditional packaging technology cannot meet the needs of high-speed data transmission. In order to realize high-speed interconnection between chips and improve system performance, there is an urgent need for a packaging structure that can realize high-speed data transmission, has high product yield, and is low in cost. SUMMARY
[0004] Embodiments of the present disclosure provide a packaging structure, a manufacturing method of the packaging structure, and an electronic device. The packaging structure can use the conductive connection structure on the interconnection substrate and the lead-out structure of the sub-packaging structure to realize the electrical connection between the two chips of the two adjacent sub-packaging structures, thereby providing a high-speed interconnection scheme, and having the advantages of low processing difficulty, high yield, and low cost.
[0005] At least one embodiment of the present disclosure provides a packaging structure, comprising: a main board; a plurality of sub-packaging structures on the main board; and an interconnection substrate comprising a carrier substrate and a conductive connection structure, each of the sub-packaging structures comprising a packaging substrate and a chip, the packaging substrate comprising a lead-out structure, the lead-out structure comprising a first lead-out pad, a second lead-out pad, and a conductive lead-out wire electrically connecting the first lead-out pad and the second lead-out pad, a conductive connecting piece of the chip being connected to the first lead-out pad, the conductive connection structure comprising a first interconnection pad, a second interconnection pad, and an interconnection wire electrically connecting the first interconnection pad and the second interconnection pad, two second lead-out pads of two lead-out structures of two adjacent sub-packaging structures being respectively electrically connected to the first interconnection pad and the second interconnection pad of the conductive connection structure, so that two chips of two adjacent sub-packaging structures are electrically connected to each other.
[0006] The packaging structure manufacturing method provided by the embodiment of the present disclosure comprises the following steps: forming a lead-out structure on a packaging substrate, the lead-out structure comprising a first lead-out pad, a second lead-out pad and a conductive lead-out wire electrically connecting the first lead-out pad and the second lead-out pad; mounting a chip on the packaging substrate, so that a conductive connecting piece of the chip is electrically connected with the first lead-out pad; forming a sub-packaging structure by the packaging substrate and the chip; forming an interconnection substrate by a substrate process, the interconnection substrate comprising a bearing substrate and a conductive connecting structure, the conductive structure comprising a first interconnection pad, a second interconnection pad and an interconnection wire electrically connecting the first interconnection pad and the second interconnection pad; assembling a plurality of the sub-packaging structures on a mainboard; and electrically connecting the two second lead-out pads of the two lead-out structures of the two adjacent sub-packaging structures with the first interconnection pad and the second interconnection pad of the conductive connecting structure respectively, so that the two chips of the two adjacent sub-packaging structures are electrically connected with each other.
[0007] The electronic device provided by the embodiment of the present disclosure comprises the packaging structure provided by any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.
[0009] Figure 1 A structural schematic diagram of a packaging structure provided by an embodiment of the present disclosure;
[0010] Figure 2 A planar schematic diagram of a packaging structure provided by an embodiment of the present disclosure;
[0011] Figure 3 A structural schematic diagram of another packaging structure provided by an embodiment of the present disclosure;
[0012] Figure 4 A structural schematic diagram of another packaging structure provided by an embodiment of the present disclosure;
[0013] Figure 5 A structural schematic diagram of another packaging structure provided by an embodiment of the present disclosure;
[0014] Figure 6 A flow schematic diagram of a packaging structure manufacturing method provided by an embodiment of the present disclosure;
[0015] Figures 7A-7G A step schematic diagram of a packaging structure manufacturing method provided by an embodiment of the present disclosure; and
[0016] Figure 8 A schematic diagram of an electronic device is provided for an embodiment of the present disclosure. DETAILED DESCRIPTION
[0017] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.
[0018] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms “comprise”, “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.
[0019] The features “parallel”, “perpendicular” and “same” and the like used in the embodiments of the present disclosure include the strict sense of “parallel”, “perpendicular”, “same” and the like, and the cases of “approximately parallel”, “approximately perpendicular”, “approximately same” and the like containing certain errors, which are determined by a person of ordinary skill in the art within an acceptable deviation range for a specific value considering measurement and errors related to measurement of a specific quantity (for example, limitations of a measurement system). For example, “approximately” can mean within one or more standard deviations, or within 10% or 5% of the value. When the quantity of a component is not specifically indicated in the following embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. “At least one” means one or more, and “multiple” means at least two. “Same layer” in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, one patterning process). Here, “same layer” does not always mean that the thicknesses of the multiple film layers are the same or the heights of the multiple film layers in a cross-sectional view are the same.
[0020] Currently, there are some packaging solutions for multi-chip interconnection, such as 2.5D silicon interposer solutions and 3D packaging solutions. The 2.5D silicon interposer solutions include CoWoS-S, CoWoS-R, CoWoS-L, InFo, etc. The 3D packaging solutions include SOIC, etc. These packaging solutions can improve the interconnection density between chips, but these solutions are processed on a silicon substrate, and there are problems of high processing difficulty and high cost.
[0021] On the other hand, if the interconnection between chips is realized by a traditional PCB packaging solution, the minimum size of the line width on the mainboard is about 40 microns, so the interconnection density is low, which cannot meet the demand of high-speed data transmission.
[0022] To this end, the packaging structure provided by the embodiments of the present disclosure includes a mainboard, a plurality of sub-packaging structures on the mainboard, and an interconnection substrate. The interconnection substrate includes a bearing substrate and a conductive connection structure. Each sub-packaging structure includes a packaging substrate and a chip. The packaging substrate includes a lead-out structure, and the lead-out structure includes a first lead-out pad, a second lead-out pad, and a conductive lead-out wire electrically connecting the first lead-out pad and the second lead-out pad. The conductive connection member of the chip is connected to the first lead-out pad. The conductive connection structure includes a first interconnection pad, a second interconnection pad, and an interconnection wire electrically connecting the first interconnection pad and the second interconnection pad. The two second lead-out pads of the two lead-out structures of the two adjacent sub-packaging structures are respectively electrically connected to the first interconnection pad and the second interconnection pad of the conductive connection structure, so that the two chips of the two adjacent sub-packaging structures are electrically connected to each other. Thus, the packaging structure can realize the electrical connection between the two chips of the two adjacent sub-packaging structures by using the conductive connection structure on the interconnection substrate and the lead-out structure of the sub-packaging structure, thereby providing a high-speed interconnection solution, and having the advantages of low processing difficulty, high yield, and low cost.
[0023] This disclosure also provides a method for manufacturing a package structure, comprising: forming a lead-out structure on a package substrate, the lead-out structure including a first lead-out pad, a second lead-out pad, and a conductive lead connecting the first lead-out pad and the second lead-out pad; mounting a chip on the package substrate such that the conductive connector of the chip is electrically connected to the first lead-out pad; forming a sub-package structure by combining the package substrate and the chip; forming an interconnect substrate using a substrate process, the interconnect substrate including a carrier substrate and a conductive connection structure, the conductive structure including a first interconnect pad, a second interconnect pad, and an interconnect connecting the first interconnect pad and the second interconnect pad; assembling multiple sub-package structures on a motherboard; and electrically connecting two second lead-out pads of two lead-out structures of two adjacent sub-package structures to the first interconnect pad and the second interconnect pad of the conductive connection structure, respectively, so that the two chips of the two adjacent sub-package structures are electrically connected to each other. Therefore, this method for manufacturing a package structure can utilize the conductive connection structure on the interconnect substrate and the lead-out structure of the sub-package structure to achieve electrical connection between the two chips of two adjacent sub-package structures, thereby providing a high-speed interconnect solution with advantages such as low processing difficulty, high yield, and low cost.
[0024] This disclosure also provides an electronic device including the above-described packaging structure. Therefore, this electronic device can also achieve high-speed interconnection between chips and has advantages such as low processing difficulty, high yield, and low cost.
[0025] The packaging structure, the manufacturing method of the packaging structure, and the electronic device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0026] Figure 1 This is a schematic diagram of a packaging structure provided in one embodiment of the present disclosure. Figure 1 As shown, the package structure 100 includes a motherboard 110, a plurality of sub-package structures 120 located on the motherboard 110, and an interconnect substrate 130. The interconnect substrate 130 includes a carrier substrate 132 and a conductive connection structure 135. Each sub-package structure 120 includes a package substrate 122 and a chip 124. The package substrate 122 includes a lead-out structure 125, which includes a first lead-out pad 125A, a second lead-out pad 125B, and a conductive lead 125C electrically connecting the first lead-out pad 125A and the second lead-out pad 125B. The conductive connector 1245 of the chip 124 is connected to the first lead-out pad 125A, so that the lead-out structure 125 can connect the flip-chip 125 to other structures.
[0027] like Figure 1As shown, the conductive connection structure 135 includes a first interconnect pad 135A, a second interconnect pad 135B, and an interconnect line 135C electrically connecting the first interconnect pad 135A and the second interconnect pad 135B. The two second lead-out pads 125B of the two lead-out structures 125 of two adjacent sub-package structures 120 are respectively electrically connected to the first interconnect pad 135A and the second interconnect pad 135B of the conductive connection structure 135, thereby being electrically connected through the interconnect line 135C, enabling the two chips of the two adjacent sub-package structures to be electrically connected to each other. It should be noted that although... Figure 1 The interconnect substrate shown only illustrates one conductive connection structure, but the interconnect substrate provided in the embodiments of this disclosure includes multiple densely arranged conductive connection structures, thereby enabling high-speed data transmission.
[0028] In the packaging structure provided in this embodiment, the two second lead pads of the two lead-out structures of two adjacent sub-package structures are electrically connected to the first interconnect pad and the second interconnect pad of the conductive connection structure, respectively, so that the two chips of the two adjacent sub-package structures are electrically connected to each other. Thus, this packaging structure can utilize the conductive connection structure on the interconnect substrate and the lead-out structures of the sub-package structures to achieve electrical connection between the two chips of the two adjacent sub-package structures. Since the interconnect substrate is fabricated using substrate technology (e.g., SAP, mSAP), the linewidth of the interconnect lines in the conductive connection structure can be around 10 micrometers, such as 9 micrometers or 10 micrometers. Therefore, high-density interconnect lines can be set on the interconnect substrate, thereby achieving high-speed interconnection between chips. Furthermore, since the interconnect substrate uses substrate technology and does not require the fabrication of a silicon interposer, it also has advantages such as low processing difficulty, high yield, and low cost.
[0029] For example, the material of the substrate 132 may include resin, and the material of the conductive connection structure 135 may include copper. Of course, embodiments of this disclosure include, but are not limited to, these.
[0030] In some examples, the interconnect substrate 130 includes multiple conductive connection structures 135, and the linewidth of the interconnect 135C is less than 40 micrometers. Thus, the interconnect substrate can achieve a dense arrangement of multiple conductive connection structures, thereby enabling high-speed data transmission.
[0031] In some examples, the linewidth of interconnect 135C ranges from 8 to 20 micrometers, such as 9 or 10 micrometers. This allows the interconnect substrate to achieve higher data transmission speeds.
[0032] In some examples, such as Figure 1As shown, in each sub-package structure 120, the orthographic projection of the first lead-out pad 125A on the package substrate 122 overlaps with the orthographic projection of the chip 124 on the package substrate 122, and the orthographic projection of the second lead-out pad 125B on the package substrate 122 is spaced apart from the orthographic projection of the chip 124 on the package substrate 122, thereby leading out the conductive connector 1245 of the flip-chip 124.
[0033] In some examples, such as Figure 1 As shown, the interconnect substrate 130 is located on the side of the plurality of sub-package structures 120 away from the motherboard 110. With this configuration, the package structure can achieve high-speed interconnection by placing the interconnect substrate on two adjacent sub-package structures and electrically connecting the corresponding pads, thereby further reducing the process complexity.
[0034] In some examples, such as Figure 1 As shown, the packaging structure 100 includes two sub-packaging structures 120 and an interconnect substrate 130. The two sub-packaging structures 120 can be a first sub-packaging structure 120A and a second sub-packaging structure 120B. The first sub-packaging structure 120A includes a first chip 124A, and the second sub-packaging structure 120B includes a second chip 124B. The first chip 124A is connected to the first interconnect pad 135A of the conductive connection structure 135 of the interconnect substrate 130 through the lead-out structure 125 of the first sub-packaging structure 120A. The second chip 124B is connected to the second interconnect pad 135B of the conductive connection structure 135 of the interconnect substrate 130 through the lead-out structure 125 of the second sub-packaging structure 120B. Thus, the first chip 124A and the second chip 125B can achieve high-speed interconnection through the two lead-out structures 125 and the interconnect substrate 130.
[0035] In some examples, such as Figure 1 As shown, each sub-package structure 120 also includes a vertical conductive structure 127, which electrically connects the second lead pad 125B to the first interconnect pad 135A or the second interconnect pad 135B of the corresponding conductive connection structure 135. Therefore, this package structure can further reduce manufacturing complexity through the vertical conductive structure. It should be noted that when a vertical conductive structure is provided, the upper surface of the sub-package structure can expose the vertical conductive structure, thus requiring only the interconnect substrate to be placed on the vertical conductive structure to complete high-speed interconnection, thereby reducing manufacturing complexity.
[0036] For example, such as Figure 1 As shown, the height of the upper surface of the vertical conductive structure 127 is greater than the height of the chip 124, thus ensuring that the chip 124 does not interfere with the connection between the vertical conductive structure 127 and the interconnect substrate 130. It should be noted that the aforementioned height is relative to the height of the motherboard.
[0037] In some examples, as shown in Figure 1 Each sub-packaging structure 120 further includes an encapsulation layer 128 on the packaging substrate 122, which encapsulates at least the conductive connecting member 1245 of the chip 124, and the vertical conductive structure 127 is at least partially located in the encapsulation layer 128. In this way, the encapsulation layer can improve the warpage of the packaging substrate, and also protect the conductive connecting member of the chip.
[0038] For example, the encapsulation layer 128 can be an epoxy molding compound (EMC). Of course, embodiments of the present disclosure include but are not limited to this, and the encapsulation layer can also be other materials.
[0039] In some examples, as shown in Figure 1 The encapsulation layer 128 encapsulates the chip 124 away from the upper surface of the packaging substrate 122.
[0040] In some examples, as shown in Figure 1 The conductive connecting member 1245 of the chip 124 can be a conductive bump.
[0041] In some examples, as shown in Figure 1 The vertical conductive structure 127 can be a conductive metal ball, such as a copper ball. Of course, embodiments of the present disclosure include but are not limited to this, and the vertical conductive structure can also be a conductive metal column or a conductive metal needle.
[0042] In some examples, as shown in Figure 1 Each sub-packaging structure 120 further includes a plurality of conductive terminals 129 on the side of the packaging substrate 122 away from the chip 124, and each sub-packaging structure 120 is electrically connected to the main board 110 through the plurality of conductive terminals 129.
[0043] For example, the main board 110 can be a PCB circuit board, and of course, embodiments of the present disclosure include but are not limited to this, and the main board can also be other suitable circuit boards.
[0044] Figure 2 A plan view of a packaging structure according to an embodiment of the present disclosure is shown in Figure 2 A plurality of sub-packaging structures 120 are arranged in a first direction X and a second direction Y, and the packaging structure 100 includes a plurality of interconnection substrates 130, including a first interconnection substrate 130A and a second interconnection substrate 130B; two adjacent sub-packaging structures 120 in the first direction X are electrically connected through the first interconnection substrate 130A, and two adjacent sub-packaging structures 120 in the second direction Y are electrically connected through the second interconnection substrate 130B. In this way, the packaging structure can achieve the interconnection of a plurality of sub-packaging structures while improving the arrangement density of the sub-packaging structures.
[0045] For example, the first direction X intersects with the second direction Y; or, for another example, the first direction X and the second direction Y are perpendicular to each other.
[0046] For example, such as Figure 2 As shown, six sub-package structures 120 are arranged in an array along a first direction and a second direction. The package structure 100 includes four first interconnect substrates 130A and three second interconnect substrates 130B. Of course, the specific number is not limited in the embodiments disclosed herein.
[0047] Figure 3 This is a schematic diagram of another packaging structure provided in an embodiment of this disclosure. For example... Figure 3 As shown, the package structure 100 includes a motherboard 110, a plurality of sub-package structures 120 located on the motherboard 110, and an interconnect substrate 130. The interconnect substrate 130 includes a carrier substrate 132 and a conductive connection structure 135; for example, the material of the carrier substrate 132 may include resin, and the material of the conductive connection structure 135 may include copper. Each sub-package structure 120 includes a package substrate 122 and a chip 124. The package substrate 122 includes a lead-out structure 125, which includes a first lead-out pad 125A, a second lead-out pad 125B, and a conductive lead 125C electrically connecting the first lead-out pad 125A and the second lead-out pad 125B. The conductive connector 1245 of the chip 124 is connected to the first lead-out pad 125A, so that the lead-out structure 125 can connect the flip-chip 125 to other structures.
[0048] like Figure 3 As shown, the conductive connection structure 135 includes a first interconnect pad 135A, a second interconnect pad 135B, and an interconnect line 135C that electrically connects the first interconnect pad 135A and the second interconnect pad 135B. The two second lead-out pads 125B of the two lead-out structures 125 of the two adjacent sub-package structures 120 are electrically connected to the first interconnect pad 135A and the second interconnect pad 135B of the conductive connection structure 135, respectively, and are electrically connected through the interconnect line 135C, so that the two chips of the two adjacent sub-package structures are electrically connected to each other.
[0049] In the packaging structure provided in this embodiment, the two second lead pads of the two lead-out structures of two adjacent sub-package structures are electrically connected to the first interconnect pad and the second interconnect pad of the conductive connection structure, respectively, so that the two chips of the two adjacent sub-package structures are electrically connected to each other. Thus, this packaging structure can utilize the conductive connection structure on the interconnect substrate and the lead-out structures of the sub-package structures to achieve electrical connection between the two chips of the two adjacent sub-package structures. Since the interconnect substrate is fabricated using substrate technology (e.g., SAP, mSAP), the linewidth of the interconnect lines in the conductive connection structure can be around 10 micrometers, such as 9 micrometers or 10 micrometers. Therefore, high-density interconnect lines can be set on the interconnect substrate, thereby achieving high-speed interconnection between chips. Furthermore, since the interconnect substrate uses substrate technology and does not require the fabrication of a silicon interposer, it also has advantages such as low processing difficulty, high yield, and low cost.
[0050] In some examples, such as Figure 3 As shown, each sub-package structure 120 further includes a vertical conductive structure 127 and an encapsulation layer 128. The vertical conductive structure 127 electrically connects the second lead pad 125B to the first interconnect pad 135A or the second interconnect pad 135B of the corresponding conductive connection structure 135. The encapsulation layer 128 is located on the package substrate 122 and at least encapsulates the conductive connectors 1245 of the chip 124. The vertical conductive structure 127 is at least partially located within the encapsulation layer 128. Thus, this package structure can further reduce the manufacturing process difficulty through the vertical conductive structure, improve the warpage of the package substrate through the encapsulation layer, and protect the conductive connectors of the chip.
[0051] In some examples, such as Figure 3 As shown, the encapsulation layer 128 exposes the upper surface of the chip 124 away from the packaging substrate 122, thereby improving heat dissipation performance.
[0052] Figure 4 This is a schematic diagram of another packaging structure provided in one embodiment of the present disclosure. Figure 1 and Figure 3 The packaging structure shown is different, such as Figure 4 As shown, each sub-package structure 120 does not have the aforementioned encapsulation layer, but instead has a reinforcing ring 126 surrounding the chip 124; the vertical conductive structure 127 is located on the side of the reinforcing ring 126 away from the chip 124. Therefore, the reinforcing ring 126 can improve the warpage of the package substrate 122, and the use of the reinforcing ring 126 can also improve the heat dissipation performance of this package structure. It should be noted that... Figure 4 The omitted structural reference numerals can be found in the accompanying drawings. Figure 1 and Figure 3 .
[0053] Figure 5A structure diagram of another packaging structure provided by an embodiment of the present disclosure is shown. Different from the packaging structure shown in Figure 1 and Figure 3 , as shown in Figure 5 , each sub-packaging structure 120 is not provided with the encapsulation layer and the reinforcing ring, and the vertical conductive structure 127 adopts a conductive pin. Thus, the packaging structure can provide a vertical conductive structure. Figure 5 The omitted part structure is marked with reference numerals, which can be referred to Figure 1 and Figure 3 .
[0054] Figure 6 A flowchart of a manufacturing method of a packaging structure provided by an embodiment of the present disclosure is shown. As shown in Figure 6 , the manufacturing method of the packaging structure includes the following steps S101-S106:
[0055] Step S101: forming a lead-out structure on a packaging substrate, the lead-out structure including a first lead-out pad, a second lead-out pad, and a conductive lead-out wire electrically connecting the first lead-out pad and the second lead-out pad.
[0056] Step S102: mounting a chip on the packaging substrate, so that the conductive connecting piece of the chip is electrically connected with the first lead-out pad.
[0057] Step S103: forming a sub-packaging structure with the packaging substrate and the chip.
[0058] Step S104: forming an interconnection substrate by a substrate process, including a carrier substrate and a conductive connecting structure, the conductive structure including a first interconnection pad, a second interconnection pad, and an interconnection wire electrically connecting the first interconnection pad and the second interconnection pad.
[0059] Step S105: assembling a plurality of sub-packaging structures on a mainboard.
[0060] Step S106: electrically connecting the two second lead-out pads of the two lead-out structures of the two adjacent sub-packaging structures with the first interconnection pad and the second interconnection pad of the conductive connecting structure respectively, so that the two chips of the two adjacent sub-packaging structures are electrically connected with each other.
[0061] In the manufacturing method of the package structure provided in this disclosure, the two second lead pads of the two lead-out structures of two adjacent sub-package structures are electrically connected to the first interconnect pad and the second interconnect pad of the conductive connection structure, respectively, so that the two chips of the two adjacent sub-package structures are electrically connected to each other. Thus, this packaging structure manufacturing method can utilize the conductive connection structure on the interconnect substrate and the lead-out structures of the sub-package structures to achieve electrical connection between the two chips of the two adjacent sub-package structures. Since the interconnect substrate is fabricated using substrate technology (e.g., SAP, mSAP), the linewidth of the interconnect lines in the conductive connection structure can be around 10 micrometers, such as 9 micrometers or 10 micrometers. Therefore, high-density interconnect lines can be set on the interconnect substrate, thereby achieving high-speed interconnection between chips. Furthermore, since the interconnect substrate uses substrate technology and does not require the fabrication of a silicon interposer, it also has advantages such as low processing difficulty, high yield, and low cost.
[0062] In some examples, multiple sub-package structures are arrayed along a first direction and a second direction on the motherboard. The manufacturing method further includes forming multiple interconnect substrates, including a first interconnect substrate and a second interconnect substrate; two adjacent sub-package structures in the first direction are electrically connected through the first interconnect substrate, and two adjacent sub-package structures in the second direction are electrically connected through the second interconnect substrate. Thus, this packaging structure manufacturing method can improve the arrangement density of sub-package structures while achieving interconnection of multiple sub-package structures.
[0063] In some examples, forming a subpackage structure from the packaging substrate and the chip further includes placing a vertical conductive structure on the second lead pad, the vertical conductive structure being configured to electrically connect the second lead pad to a first interconnect pad or a second interconnect pad of a corresponding conductive connection structure. Thus, the manufacturing method of this package structure can further reduce the process complexity through the vertical conductive structure.
[0064] In some examples, forming a sub-package structure from the packaging substrate and the chip further includes forming an encapsulation layer on the packaging substrate that encapsulates at least the conductive interconnects of the chip, with the vertical conductive structure at least partially located within the encapsulation layer. Thus, the encapsulation layer can both mitigate warpage of the packaging substrate and protect the conductive interconnects of the chip.
[0065] Figures 7A-7G This is a schematic diagram illustrating the steps of a method for manufacturing a packaging structure according to an embodiment of the present disclosure.
[0066] like Figure 7A As shown, a lead-out structure 125 is formed on the packaging substrate 122. The lead-out structure 125 includes a first lead-out pad 125A, a second lead-out pad 125B, and a conductive lead 125C electrically connecting the first lead-out pad 125A and the second lead-out pad 125B. It should be noted that, although...Figure 7A Two lead-out structures 125 are shown on the package substrate 122 shown, but embodiments of this disclosure include, but are not limited to, these. The number of lead-out structures may be determined based on the position of the sub-package structure and the number of adjacent sub-package structures.
[0067] For example, such as Figure 7A As shown, one end of the conductive lead 125C is connected to the first lead pad 125A, and the other end is connected to the second lead pad 125B.
[0068] like Figure 7B As shown, a chip 124 is mounted on a packaging substrate 122, such that the conductive connector 1245 of the chip 124 is electrically connected to the first lead-out pad 125A, thereby the lead-out structure 125 can lead out the conductive connector 1245 of the chip 124.
[0069] like Figure 7C As shown, a vertical conductive structure 127 is placed on the second lead-out pad 125B. The vertical conductive structure 127 is configured to electrically connect the second lead-out pad 125B to either the first interconnect pad 135A or the second interconnect pad 135B of the subsequent conductive connection structure 135. Therefore, the manufacturing method of this package structure can further reduce the process difficulty through the vertical conductive structure. It should be noted that when the vertical conductive structure is provided, the upper surface of the sub-package structure can expose the vertical conductive structure, thus requiring only the interconnect substrate to be overlapped on the vertical conductive structure to complete high-speed interconnection, thereby reducing the process difficulty.
[0070] For example, such as Figure 7C As shown, the height of the upper surface of the vertical conductive structure 127 is greater than the height of the chip 124, thus ensuring that the chip 124 does not interfere with the connection between the vertical conductive structure 127 and the interconnect substrate 130. It should be noted that the aforementioned height is relative to the height of the motherboard.
[0071] like Figure 7D As shown, an encapsulation layer 128 is formed on the packaging substrate 122 to encapsulate at least the conductive connector 1245 of the chip 124, and the vertical conductive structure 127 is at least partially located within the encapsulation layer 128. Thus, the encapsulation layer 128 can improve the warpage of the packaging substrate 122 and protect the conductive connector 1245 of the chip 124.
[0072] For example, such as Figure 7D As shown, the encapsulation layer 128 covers the upper surface of the chip 124, that is, encapsulates the upper surface of the chip 124, and exposes the upper surface of the vertical conductive structure 127, thereby facilitating connection with the conductive connection structure.
[0073] like Figure 7E As shown, multiple sub-package structures 120 are assembled on the motherboard 110.
[0074] For example, each sub-package structure 120 further includes a plurality of conductive terminals 129 located on the side of the package substrate 122 away from the chip 124, and each sub-package structure 120 is electrically connected to the main board 110 through the plurality of conductive terminals 129.
[0075] As shown in Figure 7F The interconnection substrate 130 is formed by a substrate process, including a carrier substrate 132 and a conductive connection structure 135, and the conductive connection structure 135 includes a first interconnection pad 135A, a second interconnection pad 135B, and an interconnection line 135C electrically connecting the first interconnection pad 135A and the second interconnection pad 135B.
[0076] As shown in Figure 7G The two second lead-out pads 125B of the two lead-out structures 125 of the two adjacent sub-package structures 120 are respectively electrically connected to the first interconnection pad 135A and the second interconnection pad 135B of the conductive connection structure 130, so that the two chips 124 of the two adjacent sub-package structures 120 are electrically connected to each other.
[0077] In the manufacturing method of the package structure provided in the embodiments of the present disclosure, the two second lead-out pads of the two lead-out structures of the two adjacent sub-package structures are respectively electrically connected to the first interconnection pad and the second interconnection pad of the conductive connection structure, so that the two chips of the two adjacent sub-package structures are electrically connected to each other. Thus, the manufacturing method of the package structure can use the conductive connection structure on the interconnection substrate and the lead-out structure of the sub-package structure to realize the electrical connection between the two chips of the two adjacent sub-package structures. Since the interconnection substrate is made by a substrate process (such as SAP, mSAP), the line width of the interconnection line in the conductive connection structure can be about 10 microns, for example, 9 microns or 10 microns, so that a high-density interconnection line can be arranged on the interconnection substrate, thereby realizing high-speed interconnection between the chips. On the other hand, since the interconnection substrate is made by a substrate process, it does not need to be made by a silicon interposer, so it also has the advantages of low processing difficulty, high yield, and low cost.
[0078] In some examples, the interconnection substrate 130 includes a plurality of conductive connection structures 135, and the line width of the interconnection line 135C is less than 40 microns. Thus, the interconnection substrate can realize a dense arrangement of a plurality of conductive connection structures, thereby realizing high-speed data transmission.
[0079] In some examples, the line width of the interconnection line 135C is in the range of 8-20 microns, for example, 9 microns or 10 microns. Thus, the interconnection substrate can realize a higher data transmission speed.
[0080] In some examples, as shown in Figure 7GAs shown, in each sub-package structure 120, the orthographic projection of the first lead-out pad 125A on the package substrate 122 overlaps with the orthographic projection of the chip 124 on the package substrate 122, and the orthographic projection of the second lead-out pad 125B on the package substrate 122 is spaced apart from the orthographic projection of the chip 124 on the package substrate 122, thereby leading out the conductive connector 1245 of the flip-chip 124.
[0081] In some examples, such as Figure 7G As shown, the interconnect substrate 130 is located on the side of the plurality of sub-package structures 120 away from the motherboard 110. With this configuration, the package structure can achieve high-speed interconnection by placing the interconnect substrate on two adjacent sub-package structures and electrically connecting the corresponding pads, thereby further reducing the process complexity.
[0082] Figure 8 This is a schematic diagram of an electronic device provided according to an embodiment of the present disclosure. Figure 8 As shown, the electronic device 500 includes the packaging structure 100 described in any of the above-mentioned embodiments. Therefore, the electronic device 500 can also achieve high-speed interconnection between chips, and has advantages such as low processing difficulty, high yield, and low cost.
[0083] For example, the aforementioned electronic devices include, but are not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (such as in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers.
[0084] The following points need to be explained:
[0085] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.
[0086] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.
[0087] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.
Claims
1. A packaging structure, comprising: Motherboard; Multiple sub-package structures are located on the motherboard; as well as Interconnect substrate, including carrier substrate and conductive connection structure, Each of the sub-package structures includes a packaging substrate and a chip. The packaging substrate includes a lead-out structure, which includes a first lead-out pad, a second lead-out pad, and a conductive lead connecting the first lead-out pad and the second lead-out pad. The conductive connector of the chip is connected to the first lead-out pad. The conductive connection structure includes a first interconnect pad, a second interconnect pad, and an interconnect line that electrically connects the first interconnect pad and the second interconnect pad. The two second lead pads of the two lead-out structures of the two adjacent sub-package structures are electrically connected to the first interconnect pad and the second interconnect pad of the conductive connection structure, respectively, so that the two chips of the two adjacent sub-package structures are electrically connected to each other.
2. The packaging structure according to claim 1, wherein, In each of the sub-package structures, the orthographic projection of the first lead pad on the package substrate overlaps with the orthographic projection of the chip on the package substrate, and the orthographic projection of the second lead pad on the package substrate and the orthographic projection of the chip on the package substrate are spaced apart.
3. The packaging structure according to claim 1, wherein, The interconnect substrate is located on the side of the plurality of sub-package structures away from the motherboard.
4. The packaging structure according to claim 1, wherein, The interconnect substrate includes a plurality of the conductive connection structures, and the linewidth of the interconnect is less than 40 micrometers.
5. The packaging structure according to claim 4, wherein, The linewidth of the interconnect ranges from 8 to 20 micrometers.
6. The packaging structure according to any one of claims 1-5, wherein, The plurality of sub-package structures are arranged in an array along a first direction and a second direction. Each package structure includes a plurality of interconnect substrates, including a first interconnect substrate and a second interconnect substrate. Two adjacent sub-package structures in the first direction are electrically connected through the first interconnect substrate, and two adjacent sub-package structures in the second direction are electrically connected through the second interconnect substrate.
7. The packaging structure according to any one of claims 1-5, wherein, Each of the sub-package structures further includes: Vertical conductive structure The vertical conductive structure electrically connects the second lead-out pad to the first interconnect pad or the second interconnect pad of the corresponding conductive connection structure.
8. The packaging structure according to claim 7, wherein, Each of the sub-package structures further includes: An encapsulation layer, located on the packaging substrate, encapsulates at least the conductive connectors of the chip. The vertical conductive structure is at least partially located within the encapsulation layer.
9. The packaging structure according to claim 8, wherein, The encapsulation layer encapsulates the chip on the upper surface away from the packaging substrate.
10. The packaging structure according to claim 8, wherein, The encapsulation layer exposes the upper surface of the chip away from the packaging substrate.
11. The packaging structure according to claim 7, wherein, Each of the sub-package structures further includes: A reinforcing ring is arranged around the chip. The vertical conductive structure is located on the side of the reinforcing ring away from the chip.
12. The packaging structure according to claim 6, wherein, The vertical conductive structure includes a conductive metal ball or a conductive needle.
13. The packaging structure according to any one of claims 1-5, wherein, Each of the sub-package structures further includes: Multiple conductive terminals are located on the side of the packaging substrate away from the chip. Each of the sub-package structures is electrically connected to the motherboard through the plurality of conductive terminals.
14. A method for manufacturing a packaging structure, comprising: An exit structure is formed on a packaging substrate, the exit structure including a first exit pad, a second exit pad, and a conductive lead electrically connecting the first exit pad and the second exit pad; A chip is mounted on the packaging substrate such that the conductive connector of the chip is electrically connected to the first lead-out pad. The packaging substrate and the chip are formed into a sub-package structure; An interconnect substrate is formed using a substrate process. The interconnect substrate includes a carrier substrate and a conductive connection structure. The conductive structure includes a first interconnect pad, a second interconnect pad, and an interconnect line that electrically connects the first interconnect pad and the second interconnect pad. The multiple sub-package structures are assembled on the motherboard; as well as The two second lead pads of the two lead-out structures of the two adjacent sub-package structures are electrically connected to the first interconnect pad and the second interconnect pad of the conductive connection structure, respectively, so that the two chips of the two adjacent sub-package structures are electrically connected to each other.
15. The method for manufacturing the packaging structure according to claim 12, wherein, On the motherboard, the plurality of sub-package structures are arranged in an array along a first direction and a second direction, and the manufacturing method further includes: A plurality of interconnect substrates are formed, the plurality of interconnect substrates including a first interconnect substrate and a second interconnect substrate; Two adjacent sub-package structures in the first direction are electrically connected through the first interconnect substrate, and two adjacent sub-package structures in the second direction are electrically connected through the second interconnect substrate.
16. The method for manufacturing the packaging structure according to claim 12, wherein, The process of forming a sub-package structure from the packaging substrate and the chip further includes: A vertical conductive structure is placed on the second lead-out pad. The vertical conductive structure is configured to electrically connect the second lead-out pad to the first interconnect pad or the second interconnect pad of the corresponding conductive connection structure.
17. The method for manufacturing the packaging structure according to claim 16, wherein, The process of forming a sub-package structure from the packaging substrate and the chip further includes: An encapsulation layer is formed on the packaging substrate to at least encapsulate the conductive connectors of the chip. The vertical conductive structure is at least partially located within the encapsulation layer.
18. An electronic device comprising a packaging structure according to any one of claims 1-13.