Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining the region feature information of a target bonding region of a circuit substrate and a semiconductor laminated structure; determining a target pattern of a first curing characteristic layer based on the regional characteristic information; forming the target pattern on the target bonding area as a current limiting frame; forming a second curing characteristic layer as a filling layer in the current limiting frame; aligning and placing the semiconductor laminated structure on the filling layer, and applying a bonding pressure; and carrying out curing under the bonding pressure. When pressure is applied, the high-viscosity first layer can accurately guide and limit transverse flowing of the low-viscosity second layer, finally, a uniform and low-stress reliable bonding interface is formed through synergistic curing, and the problems of uneven filling, stress concentration and poor reliability in a traditional method are solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating a semiconductor device. Background Technology

[0002] In the semiconductor packaging field, especially in the chip-to-substrate bonding process, the precise application of liquid or paste-like packaging materials (hereinafter collectively referred to as "adhesives") is crucial to determining device reliability, performance, and yield. Traditional mainstream processes, such as underfill or non-contact coating (NCF), rely on capillary flow or pressure spreading of the adhesive within the narrow gap between the chip and the substrate. However, the flow behavior of the adhesive in this confined space is subject to complex coupling effects from various factors, making it difficult to predict and control precisely. This directly results in the process being extremely sensitive to the initial coating amount and environmental fluctuations, easily leading to defects such as filling voids, edge overflow, or localized thickness unevenness. These defects not only introduce localized thermal resistance and mechanical weak points but may also cause electrical short circuits. Summary of the Invention

[0003] The purpose of this application is to provide a method for fabricating a semiconductor device to solve the above-mentioned technical problems.

[0004] In a first aspect, the present invention provides a method for fabricating a semiconductor device, comprising the following steps: Obtain regional feature information of the target bonding region of the circuit substrate and semiconductor stacked structure; determine the target pattern of the first curing feature layer based on the regional feature information; wherein the viscosity of the first curing feature layer is higher than that of the second curing feature layer; The target pattern is formed on the target bonding region as a current-limiting frame; within the current-limiting frame, the second curing characteristic layer is formed as a filler layer; The semiconductor stack structure is aligned and placed on the filler layer, and bonding pressure is applied to cause the second curing characteristic layer to generate controlled lateral flow under the restriction and guidance of the first curing characteristic layer. The bonding pressure is used for curing, so that the first curing characteristic layer and the second curing characteristic layer are cured to form a bonding interface.

[0005] In an optional implementation, the regional feature information includes one or more of the following: the area and shape of the target bonding region, the thickness of the semiconductor stack, the wiring density of the circuit board in the target bonding region, and the thermomechanical stress distribution information pre-calibrated through simulation or experiment.

[0006] In an optional implementation, the target pattern is a closed ring, a grid, or a dot matrix; wherein, when the regional feature information indicates that the target bonding region is an edge stress-sensitive area, the target pattern is determined to be a closed ring; when it indicates a large central area, it is determined to be a grid; when it indicates the presence of local high intensity or high heat dissipation requirements, it is determined to be a dot matrix reinforced at the corresponding location.

[0007] In an optional implementation, forming the target pattern as a current-limiting framework on the target bonding region includes: A first curable material is applied and partially pre-cured to form a gel state, resulting in a first curable property layer; the partial pre-curing is controlled to achieve a curing degree of 50% to 90% for the flow-limiting frame.

[0008] In an optional embodiment, the ratio ρ of the coating volume of the second curing feature layer to the theoretical cavity volume defined by the flow-limiting frame and the target bonding gap satisfies: 0.9 ≤ ρ ≤ 1.1.

[0009] In an optional implementation, the theoretical cavity volume is determined based on the bonding region area, the target bonding gap, the top projected area of ​​the current-limiting frame, the initial height of the current-limiting frame, and the effective occupancy coefficient of the frame calibrated experimentally.

[0010] In an optional implementation, the step of applying bonding pressure includes: first increasing the pressure to a maximum value at a first rate to allow the semiconductor stacked structures to contact rapidly; then adjusting and maintaining the pressure at an optimized value to promote uniform distribution of the controlled lateral flow.

[0011] In an optional embodiment, the step of applying bonding pressure further includes real-time monitoring of the flow or distribution state of the second cured characteristic layer using a sensor, and dynamically fine-tuning the bonding pressure or the temperature of the circuit board based on the monitoring results.

[0012] In an optional embodiment, curing is performed under the bonding pressure to ensure that the second curable layer reaches a fully cured state before the first curable layer.

[0013] In an optional embodiment, curing is achieved by a thermal field, wherein the complete curing temperature of the second curing feature layer is lower than that of the first curing feature layer; or, curing is achieved by a light field, wherein the photoinitiator contained in the second curing feature layer and the first curing feature layer has a different main absorption wavelength of ultraviolet light.

[0014] This method acquires regional feature information and dynamically determines the target pattern of the current-limiting frame accordingly. This allows the subsequently formed bilayer structure with high and low viscosity differences to be specifically adapted to the physical properties of different bonding regions. Thus, when pressure is applied, the high-viscosity first layer can accurately guide and restrict the lateral flow of the low-viscosity second layer. Finally, through synergistic curing, a uniform and low-stress reliable bonding interface is formed. This achieves a leap from a "general solution" to "adaptive and precise control" in the encapsulation process, fundamentally solving the problems of uneven filling, stress concentration, and poor reliability caused by fixed solutions in traditional methods. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the electronic device structure provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0018] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 1 As shown, the method may include the following steps: S110, acquire the regional feature information of the target bonding region of the circuit substrate and the semiconductor stacked structure; based on the regional feature information, determine the target pattern of the first curing characteristic layer; wherein, the viscosity of the first curing characteristic layer is higher than that of the second curing characteristic layer.

[0019] The regional feature information can be a set of parameters characterizing the geometric, physical, and mechanical properties of the target bonding region, used to guide the design of the current-limiting frame. The regional feature information may include one or more of the following: the area and shape of the target bonding region, the thickness of the semiconductor stack-up structure, the wiring density of the circuit board in the target bonding region, and the thermomechanical stress distribution information pre-calibrated through simulation or experimentation.

[0020] The target pattern can be a closed ring, a grid, or a dot matrix. When the regional feature information indicates that the target bonding area is an edge stress-sensitive area, the target pattern is determined to be a closed ring, which can limit the excessive flow of the filler layer to the edge, enhance edge support, and alleviate stress concentration. When it indicates a large central area, a grid pattern is determined, which divides the large area into small areas, guides the lateral flow of the filler layer to be evenly distributed, and avoids air bubbles in the center due to insufficient flow. When it indicates that there is a local high strength or high heat dissipation requirement, a dot matrix pattern is determined by reinforcing the corresponding position, which provides local high support strength or heat conduction channels through the dot matrix.

[0021] The target bonding region is the interface area between the circuit substrate and the semiconductor stack structure to be bonded, which is the core area where the two are bonded through the curing of the characteristic layer.

[0022] The first curing property layer is a curable material layer used to form the flow-limiting framework. It has a higher viscosity than the second curing property layer and provides structural support and flow restriction functions.

[0023] The planar distribution of the first curing property layer of the target pattern in the target bonding region is used to limit the flow range of the second curing property layer.

[0024] The planar area of ​​the bonding interface can be extracted through optical scanning or design drawings, reflecting the overall size of the bonding area.

[0025] The geometric profile of the bonding region affects stress distribution and flow path design.

[0026] The greater the total thickness of the semiconductor stack, the higher the stack stiffness, and the more sensitive it is to the pressure distribution of the filler layer during bonding.

[0027] The higher the ratio of line width to spacing within the target bonding area, the higher the local mechanical strength and heat dissipation requirements, and it is necessary to avoid the compression of the wiring by the flow of the filler layer.

[0028] Thermomechanical stress distribution information can be obtained through finite element simulation (such as ANSYS) or experiments (such as strain gauge measurement) to identify characteristic areas such as "edge stress sensitive areas" and "large area central areas".

[0029] S120, a target pattern is formed on the target bonding region as a current-limiting frame; within the current-limiting frame, a second curing property layer is formed as a filler layer.

[0030] A first curable material can be coated and partially pre-cured to form a gel state, resulting in a first curable characteristic layer. The partial pre-curing is controlled to achieve a curing degree of 50% to 90% for the flow-limiting frame. The ratio ρ of the coating volume of the second curable characteristic layer to the theoretical cavity volume defined by the flow-limiting frame pattern and the target bonding gap satisfies: 0.9 ≤ ρ ≤ 1.1. Where ρ < 0.9 easily leads to voids, and ρ > 1.1 easily leads to overflow and contamination.

[0031] The theoretical cavity volume is determined based on the bonding region area, the target bonding gap, the top projected area of ​​the current-limiting frame, the initial height of the current-limiting frame, and the effective occupancy coefficient of the frame calibrated experimentally.

[0032] Theoretical volume of cavity It can be determined based on the following formula: ; By introducing the effective occupancy coefficient of the frame Correct the actual volume occupied by the frame, so that The calculations are more accurate. Area of ​​the target bonding region; The projected area of ​​the top of the current-limiting frame; For the target bonding gap; This is the initial height of the rate-limiting frame; This is the effective occupancy coefficient of the frame.

[0033] The target bonding gap is the designed thickness of the second cured feature layer after bonding, which is determined by the flatness requirements of the semiconductor stack and the substrate.

[0034] The effective occupancy factor of the frame is used to characterize the ratio (dimensionless) of the actual volume occupied by the current-limiting frame to the initial volume under bonding pressure. It can be calibrated experimentally, taking into account the frame compression or expansion effect.

[0035] The first curable material can be a modified epoxy resin with a viscosity of 5000~10000 cP. The target pattern is formed by inkjet printing or stencil printing, followed by partial pre-curing. The curing temperature (60~80℃) and time (5~15min) can be controlled to achieve a curing degree of 50%~90%.

[0036] At 50% curing degree, the material is a soft gel (elastic modulus 1~10 MPa), and at 90% curing degree, it is a hard gel (elastic modulus 10~50 MPa). It can maintain the shape of the target pattern to restrict flow, and can also undergo slight deformation under bonding pressure to adapt to uneven interfaces.

[0037] S130, the semiconductor stack structure is aligned and placed on the filler layer, and bonding pressure is applied to cause the second curing feature layer to generate controlled lateral flow under the restriction and guidance of the first curing feature layer.

[0038] The pressure can be increased to its maximum value at the first rate to allow the semiconductor stacked structure to contact quickly; then the pressure can be adjusted and maintained at the optimized value to promote controlled lateral flow to achieve uniform distribution.

[0039] Bonding pressure is the vertical pressure applied to the semiconductor stack structure, used to drive the lateral flow of the second cured feature layer and maintain interfacial contact.

[0040] Controlled lateral flow refers to the uniform flow of the second cured feature layer along the direction parallel to the bonding interface under the constraint of the flow-limiting framework, avoiding local accumulation or voids.

[0041] The first stage (rapid contact) involves increasing the pressure to its maximum value (0.8-1.2 MPa) at a first rate (0.5-2 MPa / s), enabling the semiconductor stacked structure to fully contact the filling layer within 0.5-2 seconds, thus avoiding localized flow caused by slow contact.

[0042] The second stage (pressure holding flow): The pressure is adjusted to the optimized value (0.1~0.5 MPa) and held for 10~30 s. Under low pressure, the viscosity of the filler layer decreases. Due to the heat generated by the pressure or the thinning of the material by shear, there is sufficient time for it to flow laterally to a uniform distribution.

[0043] In some embodiments, the flow or distribution state of the second cured characteristic layer can be monitored in real time by a sensor, and the bonding pressure or the temperature of the circuit board can be dynamically fine-tuned based on the monitoring results.

[0044] Data can be acquired in real time using the following sensors: Displacement sensors monitor the vertical displacement of semiconductor stacked structures, reflecting changes in the thickness of the filler layer; An optical interferometer monitors the amount of overflow at the edge of the filler layer, reflecting the lateral flow velocity; Infrared thermal imagers monitor the temperature distribution of the filler layer, reflecting the viscosity uniformity.

[0045] If the displacement of a certain area is less than 0.8 × the average displacement (insufficient flow), increase the pressure in that area by ΔP = 0.05~0.1 MPa, or increase the temperature by ΔT = 5~10℃ (to reduce viscosity); if the overflow is greater than 10% of the design value (excessive flow), reduce the pressure or lower the temperature.

[0046] Flow uniformity control: The flow direction is guided by the geometric parameters of the flow-limiting frame (such as annular width, grid cell size, and lattice density), and the flow distance is controlled by the holding time, which ultimately reduces the uniformity error of the filler layer thickness.

[0047] S140 is cured under bonding pressure, so that the first curing property layer and the second curing property layer are cured to form a bonding interface.

[0048] Among them, curing under bonding pressure is used to ensure that the second curing property layer reaches a fully cured state before the first curing property layer.

[0049] After the first and second curing characteristic layers are fully cured, the overall interface formed with the circuit board and semiconductor stacked structure must have high bonding strength and low thermal resistance.

[0050] When fully cured, the material has a cross-linking degree of ≥95% and its mechanical properties (such as elastic modulus and strength) reach the design value.

[0051] It is necessary to ensure that the second curing characteristic layer (filler layer) reaches a fully cured state before the first curing characteristic layer (flow-limiting frame). This is because the filler layer cures first, which can fix the interface shape and provide initial bonding strength, and prevent the frame from curing first, which would restrict the flow of the filler layer and cause uneven distribution.

[0052] In some embodiments, curing can be achieved by a thermal field, where the complete curing temperature of the second curing feature layer is lower than that of the first curing feature layer; or, curing can also be achieved by a light field, where the photoinitiators contained in the second curing feature layer and the first curing feature layer have different main absorption wavelengths for ultraviolet light.

[0053] For light field curing: The second curing characteristic layer contains photoinitiator A (main absorption wavelength λ). A =365±10 nm), the first curing characteristic layer contains photoinitiator B (main absorption wavelength λ). B =405±10 nm), selective curing is achieved by switching the wavelength of the ultraviolet light source.

[0054] First with λ A Light intensity 50~100 mW / cm 2 The time is 30-60 seconds to allow the filler layer to cure, and then λ is used. B Light intensity, 80~150 mW / cm 2 The curing time is 60~120 s to solidify the frame and avoid synchronous curing caused by wavelength overlap.

[0055] Maintaining bonding pressure during the curing process ensures close contact between the filler layer and the substrate and stack, preventing interface gaps caused by curing shrinkage.

[0056] In some embodiments, the first curable material can be a polymer prepolymer system with photosensitive or thermosensitive curing properties, such as modified epoxy acrylate or silicone-containing polyimide precursors. A key requirement is that the material can form a stable gel state after partial curing. High-precision screen printing or inkjet printing techniques can be used to coat the material onto the bonding area of ​​the circuit board in a predetermined pattern. The second curable material can be a low-viscosity, low-shrinkage, high-wetting liquid prepolymer, such as hydrogenated siloxane or aliphatic acrylate.

[0057] In some embodiments, the coating volume of the second curing property layer It can be calculated based on the following formula: ; in, The fill factor is determined based on the complexity of the pattern; for simple circular patterns: ; Complex meshes: .

[0058] The coefficient of thermal expansion of the material; This refers to the process temperature; Room temperature; K represents the expected applied pressure; K is the bulk modulus of the material.

[0059] Bonding pressure Control can be achieved based on the following formula: ; in, This represents the greatest pressure in the first phase. Optimize the pressure for the second phase; This is the time constant for the first stage; This is the decay constant for the second stage; This is the pressure oscillation period; This refers to the phase switching time; This is the total pressure holding time.

[0060] This allows for rapid pressurization in the first stage, ensuring quick chip contact and initiation of flow; the second stage applies slightly oscillating pressure to promote bubble removal and thickness uniformity; the oscillation phase breaks down the internal structure of the liquid, reducing apparent viscosity.

[0061] In some embodiments, a gradient curing process in which the filler layer is cured first and the current-limiting frame is cured later can be achieved by precisely controlling the curing energy input sequence, thereby locking in a smooth interface while minimizing internal stress.

[0062] This method acquires regional feature information and dynamically determines the target pattern of the current-limiting frame accordingly. This allows the subsequently formed bilayer structure with high and low viscosity differences to be specifically adapted to the physical properties of different bonding regions. Thus, when pressure is applied, the high-viscosity first layer can accurately guide and restrict the lateral flow of the low-viscosity second layer. Finally, through synergistic curing, a uniform and low-stress reliable bonding interface is formed. This achieves a leap from a "general solution" to "adaptive and precise control" in the encapsulation process, fundamentally solving the problems of uneven filling, stress concentration, and poor reliability caused by fixed solutions in traditional methods.

[0063] See Figure 2 As shown, the electronic device 200 provided in this application embodiment includes at least: a processor 201, a memory 202, and a computer program stored in the memory 202 and executable on the processor 201. When the processor 201 executes the computer program, it implements the method provided in this application embodiment.

[0064] The electronic device 200 provided in this application embodiment may further include a bus 203 connecting different components (including processor 201 and memory 202). The bus 203 represents one or more types of bus structures, including memory bus, peripheral bus, local area bus, etc.

[0065] Memory 202 may include readable storage media in the form of volatile memory, such as random access memory (RAM) 2021 and / or cache memory 2022, and may further include read-only memory (ROM) 2023. Memory 202 may also include a program tool 2025 having a set (at least one) of program modules 2024, including but not limited to an operating subsystem, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0066] Processor 201 can be a single processing element or a collective term for multiple processing elements. For example, processor 201 can be a central processing unit (CPU) or one or more integrated circuits configured to implement the methods provided in the embodiments of this application. Specifically, processor 201 can be a general-purpose processor, including but not limited to CPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0067] Electronic device 200 can communicate with one or more external devices 204 (e.g., keyboard, remote control, etc.), and also with one or more devices that enable a user to interact with electronic device 200 (e.g., mobile phone, computer, etc.), and / or with any device that enables electronic device 200 to communicate with one or more other electronic devices 200 (e.g., router, modem, etc.). This communication can be performed through input / output (I / O) interface 205. Furthermore, electronic device 200 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) through network adapter 206. Figure 2 As shown, network adapter 206 communicates with other modules of electronic device 200 via bus 203. It should be understood that, although... Figure 2 As not shown, other hardware and / or software modules may be used in conjunction with electronic device 200, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, Redundant Arrays of Independent Disks (RAID) subsystems, tape drives, and data backup storage subsystems.

[0068] It should be noted that, Figure 2 The electronic device 200 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0069] The computer-readable storage medium provided in the embodiments of this application is described below. The computer-readable storage medium provided in the embodiments of this application stores computer instructions, which, when executed by a processor, implement the methods provided in the embodiments of this application. Specifically, the computer instructions may be built into or installed in a processor, so that the processor can implement the methods provided in the embodiments of this application by executing the built-in or installed computer instructions.

[0070] Furthermore, the method provided in this application embodiment can also be implemented as a computer program product, which includes program code that implements the method provided in this application embodiment when run on a processor.

[0071] The computer program product provided in this application embodiment may employ one or more computer-readable storage media. The computer-readable storage media may be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. Specifically, more specific examples (a non-exhaustive list) of computer-readable storage media include: electrical connections having one or more wires, portable disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM), optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0072] The computer program product provided in this application embodiment can be a CD-ROM and include program code, and can also run on electronic devices such as computers. However, the computer program product provided in this application embodiment is not limited thereto. In this application embodiment, the computer-readable storage medium can be any tangible medium that contains or stores program code, which can be used by or in conjunction with an instruction execution system, device, or apparatus.

[0073] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0074] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0075] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0076] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Obtain the regional feature information of the target bonding region between the circuit substrate and the semiconductor stacked structure; Based on the regional feature information, a target pattern for the first curing property layer is determined; wherein the viscosity of the first curing property layer is higher than that of the second curing property layer. The target pattern is formed on the target bonding region as a current-limiting frame; within the current-limiting frame, the second curing characteristic layer is formed as a filler layer; The semiconductor stack structure is aligned and placed on the filler layer, and bonding pressure is applied to cause the second curing characteristic layer to generate controlled lateral flow under the restriction and guidance of the first curing characteristic layer. The bonding pressure is used for curing, so that the first curing characteristic layer and the second curing characteristic layer are cured to form a bonding interface.

2. The preparation method according to claim 1, characterized in that, The regional feature information includes one or more of the following: the area and shape of the target bonding region, the thickness of the semiconductor stack structure, the wiring density of the circuit board in the target bonding region, and the thermomechanical stress distribution information calibrated in advance through simulation or experiment.

3. The preparation method according to claim 1 or 2, characterized in that, The target pattern can be a closed ring, a grid, or a dot matrix; wherein, when the regional feature information indicates that the target bonding region is an edge stress sensitive area, the target pattern is determined to be a closed ring; when it indicates a large central area, it is determined to be a grid; when it indicates the presence of local high strength or high heat dissipation requirements, it is determined to be a dot matrix pattern reinforced at the corresponding position.

4. The preparation method according to claim 1, characterized in that, Forming the target pattern as a current-limiting framework on the target bonding region includes: A first curable material is applied and partially pre-cured to form a gel state, resulting in a first curable property layer; the partial pre-curing is controlled to achieve a curing degree of 50% to 90% for the flow-limiting frame.

5. The preparation method according to claim 1, characterized in that, The ratio ρ of the coating volume of the second curing characteristic layer to the theoretical cavity volume defined by the flow-limiting frame and the target bonding gap satisfies: 0.9 ≤ ρ ≤ 1.

1.

6. The preparation method according to claim 5, characterized in that, The theoretical volume of the cavity is determined based on the bonding region area, the target bonding gap, the top projected area of ​​the current-limiting frame, the initial height of the current-limiting frame, and the effective occupancy coefficient of the frame calibrated through experiments.

7. The preparation method according to claim 1, characterized in that, The step of applying bonding pressure includes: first, increasing the pressure to a maximum value at a first rate to allow the semiconductor stacked structure to contact quickly; then adjusting and maintaining the pressure at an optimized value to promote the controlled lateral flow to achieve uniform distribution.

8. The preparation method according to claim 7, characterized in that, The step of applying bonding pressure also includes real-time monitoring of the flow or distribution state of the second cured characteristic layer using sensors, and dynamic fine-tuning of the bonding pressure or the temperature of the circuit board based on the monitoring results.

9. The preparation method according to claim 1, characterized in that, Curing is performed under the bonding pressure to ensure that the second curing property layer reaches complete curing before the first curing property layer.

10. The preparation method according to claim 9, characterized in that, Curing is achieved through a thermal field, wherein the complete curing temperature of the second curing feature layer is lower than that of the first curing feature layer; or, curing is achieved through a light field, wherein the photoinitiator contained in the second curing feature layer and the first curing feature layer has different main absorption wavelengths for ultraviolet light.

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