Board-level packaging method and product thereof

Abstract

The invention discloses a board-level packaging method. The method comprises the following steps: preparing a chip with a first rewiring layer; mounting the chip or the chip and the support material on a carrier plate, performing plastic packaging, then removing the carrier plate, and exposing the first rewiring layer; manufacturing a second rewiring layer, an electroplating metal circuit layer and a supporting frame on the first rewiring layer; and after a plurality of rewiring layers are manufactured as required, electroplating a lead frame or manufacturing solder ball bumps, and finally cutting into single packaging bodies. According to the invention, the solid support material with high modulus and low thermal expansion coefficient is embedded in the second rewiring layer, so that a local stress suppression skeleton is constructed in the packaging structure, and free shrinkage and expansion of the polymer dielectric layer in the subsequent thermal process are effectively restrained. Therefore, thermal stress generated by mismatch of thermal expansion coefficients is greatly offset, the overall bending deformation of the packaging body is fundamentally inhibited from the interior of the structure, and the overall rigidity and the anti-warping capability of the packaging body are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a board-level packaging method and its products. Background Technology

[0002] As the semiconductor industry moves towards "beyond Moore's Law," packaging technology has become crucial for improving chip performance, achieving high-density integration, and reducing costs. Panel-level packaging technology, based on the manufacturing process of printed circuit boards, expands the carrier in the process from traditional circular wafers to large-size rectangular substrates. This allows for the parallel packaging of thousands of individual chips in a single process, significantly improving production efficiency. It boasts economies of scale and cost advantages far exceeding traditional wafer-level packaging, making it a cutting-edge industry trend and a hot research topic.

[0003] However, panel-level packaging technology faces several severe challenges in large-scale industrial applications, among which package warpage is one of the most critical and intractable problems. Mismatches in the coefficients of thermal expansion exist between various materials in the packaging structure, and large-size panels undergoing high-temperature processes can lead to cumulative deformation. Package warpage caused by these factors results in a series of process and reliability issues, such as photolithography focusing failure, difficulties in wafer transfer, and poor solder ball coplanarity, severely restricting the yield of panel-level packaging technology. Summary of the Invention

[0004] To address the problems in the prior art, the present invention aims to provide a board-level packaging method and its products.

[0005] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: A board-level packaging method includes the following steps: Step 1: Fabricate a wafer or chip with a first redistribution layer; Step 2: Mount the wafer or chip obtained in Step 1, or the wafer or chip obtained in Step 1 and the support material onto the carrier board, encapsulate it, and then remove the carrier board to expose the first rewiring layer. Step 3: Fabricate a second rewiring layer, an electroplated metal circuit layer, and a support frame on the first rewiring layer; Step 4: After fabricating multiple redistribution layers as needed according to Step 3, electroplat the lead frame or fabricate solder ball bumps, and finally cut it into a single package.

[0006] Furthermore, in step one, the step of fabricating the chip with the first redistribution layer includes: First, a seed layer is sputtered onto the wafer, then metal lines are electroplated onto the seed layer, and then a dielectric layer is prepared on the metal lines to form the first redistribution layer. Finally, the wafer with the first redistribution layer is selectively diced into individual chips.

[0007] Furthermore, the seed layer comprises a titanium layer and a copper layer, formed by physical vapor deposition.

[0008] Furthermore, the thickness of the metal line is 5~35μm, and it is formed by electroplating.

[0009] Furthermore, the thickness of the dielectric layer is 10~40μm.

[0010] Furthermore, in step two, the chip obtained in step one, or the chip obtained in step one and the support material, are both mounted onto the carrier board using temporary bonding adhesive, with a molding thickness of 60~350μm.

[0011] Furthermore, in step three, a second rerouting layer is fabricated on top of the first rerouting layer in one go.

[0012] The present invention also discloses a board-level packaging structure prepared by a board-level packaging method, characterized in that it includes a molding compound, wherein a wafer or chip, or a wafer or chip and a support material are disposed within the molding compound, a first redistribution layer is disposed on the molding compound, a second redistribution layer is disposed on the first redistribution layer, a solid support material is embedded in the second redistribution layer, multiple redistribution layers are fabricated on the second redistribution layer as needed, and lead frames or solder ball bumps are disposed on the redistribution layers.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention constructs a local stress-suppressing skeleton within the package structure by embedding a high-modulus, low-thermal-expansion-coefficient solid support material within the second redistribution layer, thereby enhancing the overall stiffness and anti-warping capability of the package. The Young's modulus and tensile strength of the solid support material are much higher than those of the surrounding polymer dielectric layer, while its thermal expansion coefficient is closer to that of silicon chips and metal wires. This effectively constrains the free contraction and expansion of the polymer dielectric layer during subsequent thermal processes, thereby significantly offsetting the thermal stress caused by the mismatch in thermal expansion coefficients and suppressing the overall bending deformation of the package from the root cause within the structure. Attached Figure Description

[0014] Figure 1-2 This is a structural schematic diagram of step one of the present invention; Figure 3-4 This is a schematic diagram of the structure of step two of the present invention; Figure 5 This is a schematic diagram of step three in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of step three of the present invention; Figure 7-8 This is a schematic diagram of step four in Embodiment 1 of the present invention; Figure 9-10This is a schematic diagram of step four in Embodiment 2 of the present invention; Figure 11 This is a schematic diagram of the structure of Embodiment 3 of the present invention. Detailed Implementation

[0015] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0016] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0017] like Figure 1-11 As shown, this invention discloses a board-level packaging method, comprising the following steps: Step 1: As Figure 1-2 As shown, firstly, a seed layer is sputtered onto wafer 1 using physical vapor deposition. The seed layer may include a titanium layer and a copper layer. Then, metal lines 2 are electroplated onto the seed layer using an electroplating process. The material can be copper, tungsten, silver, etc., with a thickness of 5-35 μm. Next, a dielectric layer 3 of 10-40 μm is formed on the metal lines using a lamination or coating exposure and development process. The dielectric layer 3 can be a dry film, or it can be composed of a dry film and an organic polymer (including but not limited to polyimide, photosensitive polyimide, benzocyclobutene, etc.). This forms the first redistribution layer, which includes the seed layer, metal lines 2, and dielectric layer 3. The wafer 1, after the first redistribution layer is formed, is then diced into individual chips 4, or it may not be diced. Step Two: As Figure 3-4 As shown, the first redistribution layer of wafer 1 or chip 4 can be mounted onto a carrier board 6 with temporary bonding adhesive 5. The wafer 1 or chip 4 is encapsulated using molding compound 7 through compression molding or liquid encapsulation. The molding compound 7 includes, but is not limited to, epoxy molding compound or dry film, and the encapsulation thickness is 60~350μm. After encapsulation, the bonding is removed, the carrier board 6 is removed, and the residual temporary bonding adhesive 5 is cleaned to expose the first redistribution layer 4 for subsequent process fabrication. Alternatively, wafer 1 or chip 4 and support material 15 can be mounted onto carrier 6 with temporary bonding adhesive 5. Wafer 1 or chip 4 can be encapsulated using molding compound 7 through compression molding or liquid encapsulation. The molding compound 7 includes, but is not limited to, epoxy molding compound or dry film, and the encapsulation thickness is 60~350μm. After encapsulation, the bonding is removed, carrier 6 is removed, and residual temporary bonding adhesive 5 is cleaned to expose the first redistribution layer 4 for subsequent process fabrication. Step 3: Fabricate the second rewiring layer 8 on the first rewiring layer. The polymer dielectric layer of this second rewiring layer 8 is fabricated in a single step using a traditional method rather than a layered approach. Figure 6 As shown. After the coating or lamination process, the solid support material 10 is embedded into the uncured dielectric material, and the desired functional pattern opening is retained using a coating exposure or laser drilling process, followed by curing and molding. In this step, the height of the solid support material 10 is slightly lower than the target thickness of the polymer dielectric layer. The solid support material 10 includes, but is not limited to, solid materials with high modulus and low coefficient of thermal expansion, such as insulating carbon fiber frames, glass, ceramics, or electroplated special metal frames. If the solid support material 10 is an electroplated special metal frame, it needs to be formed together with the metal circuit layer 16 during the electroplating stage after the polymer dielectric layer has cured. The polymer dielectric layer is fabricated in a single step using a traditional method rather than a layered approach, retaining the desired functional and non-functional openings, and then electroplating the metal circuit layer 16 and the support frame 12. Figure 7 As shown; Step 4: After fabricating multiple redistribution layers as needed according to Step 3, the electroplated lead frame 13 serves as the solder pads for connection between the package and the external environment, such as... Figure 7-8 As shown, it is finally cut into individual packages. Alternatively, solder ball bumps 14 can be fabricated using processes such as ball reflow soldering to connect the package to the outside. Figure 9-10 As shown, it is finally cut into individual packages.

[0018] The present invention also discloses a semiconductor package structure prepared by a board-level packaging method, including a molding compound 7, in which a wafer 1 or a chip 4 is disposed, or a wafer 1 or a chip 4 and a support material 15 are disposed, a first redistribution layer is disposed on the molding compound 7, a second redistribution layer is disposed on the first redistribution layer, a solid support material 10 is embedded in the second redistribution layer, multiple redistribution layers are fabricated on the second redistribution layer as needed, and lead frames 13 or solder ball bumps 14 are disposed on the redistribution layers.

[0019] Example 1 like Figure 1-8 As shown, a board-level packaging method includes the following steps: Step 1: As Figure 1-2 As shown, firstly, a seed layer, consisting of a titanium layer and a copper layer, is sputtered onto wafer 1 using physical vapor deposition. Then, a 35μm thick metal circuit 2, made of tungsten, is electroplated onto the seed layer. Next, a 40μm thick dielectric layer 3, a dry film, is formed on the metal circuit using a lamination process. This completes the first redistribution layer, which includes the seed layer, metal circuit 2, and dielectric layer 3. The wafer with the first redistribution layer is then diced into individual chips 4. Step Two: As Figure 3-4 As shown, the first redistribution layer of chip 4 is mounted onto a carrier board 6 with temporary bonding adhesive 5. Chip 4 is encapsulated using liquid encapsulation with molding compound 7. The molding compound 7 is an epoxy molding compound with an encapsulation thickness of 350 μm. After encapsulation, the bonding is removed, the carrier board 6 is removed, and the residual temporary bonding adhesive 5 is cleaned to expose the first redistribution layer for subsequent processing. Step 3: Fabricate a second redistribution layer 8 on the first redistribution layer. The polymer dielectric layer of the second redistribution layer 8 is fabricated as follows: The polymer dielectric layer is fabricated in a single step using traditional methods rather than in layers. After the coating process, a solid support material 10 is embedded into the uncured dielectric material. The desired functional patterns are then created using coating exposure or laser drilling techniques, followed by curing. The height of the solid support material 10 is slightly lower than the target thickness of the polymer dielectric layer; The solid support material 10 is an electroplated metal frame, which needs to be formed together with the metal circuit layer 16 during the electroplating stage after the polymer dielectric layer has been cured and formed. The polymer dielectric layer is fabricated in one step in a traditional way rather than in layers and stages, retaining the desired functional and non-functional openings, the electroplated metal circuit layer 16 and the support frame 12; Step 4: After fabricating multiple redistribution layers as needed according to Step 3, the electroplated lead frame 13 serves as the solder pads for connection between the package and the external environment, such as... Figure 7-8 As shown, it is finally cut into individual packages.

[0020] This embodiment also discloses a semiconductor package structure prepared by a board-level packaging method, including a molding compound 7, a chip 4 disposed in the molding compound 7, a first redistribution layer disposed on the molding compound 7, a second redistribution layer disposed on the first redistribution layer, a solid support material 10 embedded in the second redistribution layer, multiple redistribution layers fabricated on the second redistribution layer as needed, and a lead frame 13 disposed on the redistribution layer.

[0021] Example 2 The difference between this embodiment and Embodiment 1 is that in step four of this embodiment, after fabricating multiple redistribution layers as needed according to step three, solder ball bumps 14 are created using a ball-mounting reflow soldering process to connect the package to the outside. Finally, it is cut into single packages, as shown below. Figure 9-10 As shown.

[0022] This embodiment also discloses a semiconductor package structure prepared by a board-level packaging method, including a molding compound 7, a chip 4 disposed in the molding compound 7, a first redistribution layer disposed on the molding compound 7, a second redistribution layer disposed on the first redistribution layer, a solid support material 10 embedded in the second redistribution layer, multiple redistribution layers fabricated on the second redistribution layer as needed, and solder ball bumps 14 disposed on the redistribution layers.

[0023] The rest is the same as in Example 1.

[0024] Example 3 The difference between this embodiment and embodiment 1 is that in step two of this embodiment, the chip 4 and the support material 15 are jointly mounted on the carrier board 6 with temporary bonding adhesive 5, and the remaining steps are the same as in embodiment 1.

[0025] This embodiment also discloses a semiconductor package structure prepared by a board-level packaging method, including a molding compound 7, a chip 4 and a support material 15 disposed within the molding compound 7, a first redistribution layer disposed on the molding compound 7, a second redistribution layer disposed on the first redistribution layer, a solid support material 10 embedded in the second redistribution layer, multiple redistribution layers fabricated on the second redistribution layer as needed, and solder ball bumps 14 disposed on the redistribution layers, such as... Figure 11 As shown.

[0026] The rest is the same as in Example 1.

[0027] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0028] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A board-level packaging method, characterized in that, Includes the following steps: Step 1: Fabricate a wafer or chip with a first redistribution layer; Step 2: Mount the wafer or chip obtained in Step 1, or the wafer or chip obtained in Step 1 and the support material onto the carrier board, encapsulate it, and then remove the carrier board to expose the first rewiring layer. Step 3: Fabricate a second rewiring layer, an electroplated metal circuit layer, and a support frame on the first rewiring layer; Step 4: After fabricating multiple redistribution layers as needed according to Step 3, electroplat the lead frame or fabricate solder ball bumps, and finally cut it into a single package.

2. The board-level packaging method according to claim 1, characterized in that, Step one, the steps for fabricating a chip with a first redistribution layer, include: First, a seed layer is sputtered onto the wafer, then metal lines are electroplated onto the seed layer, and then a dielectric layer is prepared on the metal lines to form the first redistribution layer. Finally, the wafer with the first redistribution layer is selectively diced into individual chips.

3. The board-level packaging method according to claim 2, characterized in that, The seed layer comprises a titanium layer and a copper layer, and is formed by physical vapor deposition.

4. The board-level packaging method according to claim 2, characterized in that, The thickness of the metal lines is 5~35μm, and they are formed by electroplating.

5. A board-level packaging method according to claim 2, characterized in that, The thickness of the dielectric layer is 10~40μm.

6. The board-level packaging method according to claim 1, characterized in that, In step two, the chip obtained in step one, or the chip obtained in step one and the support material, are both mounted onto the carrier board using temporary bonding adhesive, with a molding thickness of 60~350μm.

7. A board-level packaging method according to claim 1, characterized in that, In step three, the second rerouting layer is created in one go on the first rerouting layer.

8. The board-level packaging structure prepared by the board-level packaging method according to any one of claims 1-7, characterized in that, The device includes a molding compound containing a wafer or chip, or a wafer or chip and a support material. A first redistribution layer is disposed on the molding compound, and a second redistribution layer is disposed on the first redistribution layer. A solid support material is embedded in the second redistribution layer. Multiple redistribution layers are fabricated on the second redistribution layer as needed, and lead frames or solder ball bumps are disposed on the redistribution layers.

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