Alpha mixing for power and display optimization

Abstract

Aspects presented herein relate to methods and apparatus for image processing, including devices, such as a GPU or DPU. In some embodiments, a device may obtain a first indication of an image comprising a set of pixels associated with a color format, the color format comprising a set of color channels, where each pixel in a subset of pixels comprises at least one first value of at least one first channel different from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises a second value of the second channel equal to other pixels in the subset of pixels. The apparatus may also configure a second value for each pixel in the subset of pixels based on the set of pixels. Further, the device may output a second indication of the image including the configured second value for each pixel in the subset of pixels.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to processing systems, and more specifically to one or more techniques for image processing. BACKGROUND

[0002] Computing devices often perform graphics and / or display processing (e.g., with a graphics processing unit (GPU), central processing unit (CPU), display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. A GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. A central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are often capable of executing multiple applications concurrently, each of which can require utilization of the GPU during execution. A display processor is configured to convert digital information received from the CPU into analog values and can issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display can utilize a GPU and / or a display processor.

[0003] A GPU of a device can be configured to perform processes in a graphics processing pipeline. Further, a display processor or display processing unit (DPU) can be configured to perform processes of display processing. However, as wireless communication and smaller handheld devices have emerged, there is an increasing demand for improved graphics or display processing. SUMMARY

[0004] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0005] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus can be a graphics processing unit (GPU), a display processing unit (DPU), or any apparatus that can perform image processing. The apparatus can obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels in the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels. The apparatus can further configure the second value of each pixel in the subset of pixels based on the set of pixels. Additionally, the apparatus can downsample the second value of the second channel of each pixel in the subset of pixels. The apparatus can further perform a subsampling process on the second value of each pixel in the subset of pixels, wherein the subsampling process is associated with a reduced sampling rate in a horizontal direction and a vertical direction. Moreover, the apparatus can adjust the reduced sampling rate in the horizontal direction and the vertical direction in order to match a bit alignment of the set of pixels. The apparatus can further output a second indication of the image comprising the configured second value of each pixel in the subset of pixels.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system.

[0008] Figure 2 an example graphics processing unit (GPU) is illustrated.

[0009] Figure 3 an example display framework including a display processor and a display is illustrated.

[0010] Figure 4 is a diagram illustrating an example mask layer for display processing.

[0011] Figure 5 is a diagram illustrating an example layer compositing scheme for display processing.

[0012] Figure 6 includes a diagram illustrating an example visual effect problem for a display device.

[0013] Figure 7 is a diagram illustrating an example set of pixels.

[0014] Figure 8 This is a diagram illustrating an example downsampling or subsampling process for a pixel.

[0015] Figure 9 This is a flowchart illustrating an example of communication between the GPU, DPU, and memory.

[0016] Figure 10 This is a flowchart of an example method for image processing.

[0017] Figure 11 This is a flowchart of an example method for image processing. Detailed Implementation

[0018] Certain types of color formats or (e.g., floating point (FP) formats or FP16 formats) can address the aforementioned visual issues (e.g., display flicker issues). However, these types of color formats or FP formats (e.g., FP16 formats) can have significant power consumption and memory consumption that can be detrimental to a device. Other types of color formats (e.g., red (R) green (G) blue (B) alpha (A) (RGBA) RGBA10101010 formats) can be potentially helpful, but can present challenges for compatibility with operating systems (OSs) and / or rendering engines. Further, some types of color formats (e.g., RGBA10101010 formats) can have too many bits (e.g., too many bits allocated for alpha (A) values) that can consume too much power. That is, for some frame buffer targets (e.g., frame buffer targets for RGBA1010102 formats), 2-bit alpha values can not be sufficient, while other frame buffer targets (e.g., frame buffer targets for RGBA10101010 formats or FP16 formats) can need additional bits and have power issues. As indicated herein, increasing the amount of bits utilized (e.g., bits allocated for alpha (A) values) can improve the overall visual quality of a display device, but also increase the overall power consumption at the display device. Further, reducing the amount of bits utilized for color formats (e.g., bits allocated for alpha (A) values) can reduce the overall power consumption at the display device, but reduce the overall visual quality of the display device. Aspects of the present disclosure can provide a balanced and efficient approach to utilizing each bit in different color formats for a display device. For example, aspects presented herein can efficiently utilize each bit in certain types of color formats (e.g., RGBA formats including RGBA pixels). Additionally, aspects of the present disclosure can effectively balance performance and power consumption at a device when displaying certain types of color formats. For example, aspects of the present disclosure can balance performance and power consumption at a device when utilizing certain types of display formats (e.g., high dynamic range (HDR) video playback) with certain types of display features (e.g., dimming features). That is, aspects presented herein can utilize a type of color format (e.g., a 10-bit RGBA format or a RGBA1010102 format) that includes a down-sampled channel or a spatially sub-sampled channel (e.g., an alpha channel). By doing so, aspects presented herein can provide visual / power optimization for color / pixel blending (e.g., alpha blending).

[0019] Aspects of the disclosure can include a number of benefits or advantages. For example, aspects presented herein can also efficiently utilize each bit in certain types of color formats (e.g., RGBA format including RGBA pixels). That is, aspects presented herein can optimize the use of each bit of each RGBA pixel. Aspects presented herein can also provide an efficient balance between power usage and visual quality. For example, when utilizing certain types of display formats (e.g., HDR video playback) and certain types of display features (e.g., dimming features), aspects of the disclosure can balance performance and power consumption at a device. Moreover, aspects presented herein can satisfy certain types of buffer alignment conditions (e.g., GPU / CPU / DSP buffer alignment conditions). Additionally, aspects presented herein can utilize a novel spatial subsampling approach for the alpha channel in certain color formats (e.g., RGBA format). This can be helpful in handling alpha values for certain color formats (e.g., RGBA format).

[0020] Various aspects of systems, apparatuses, computer program products, and methods will be more fully described in the following detailed description, taken in conjunction with the accompanying drawings. However, the disclosure can be embodied in many different forms and should not be construed as limited to the particular aspects set forth throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using, in addition to or in place of the aspects set forth herein, other structures, functionalities, or structures and functionalities disclosed herein. Any aspect disclosed herein can be embodied by one or more elements of a claim.

[0021] While various aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. While some potential benefits and advantages of aspects of the disclosure are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the appended drawings and description hereinafter. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

[0022] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

[0023] For example, an element, or any portion of an element, or any combination of elements can be implemented as a “processing system” that includes one or more processors (which can also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SOC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described herein. One or more processors in the processing system can execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term “application” can refer to software. As described herein, one or more techniques can refer to an application, i.e., software, configured to perform one or more functions. In such examples, an application can be stored on a memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware, such as a processor, described herein can be configured to execute the application. For example, an application can be described as including code that, when executed by hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware can access the code from memory and execute the code accessed from memory to perform one or more techniques described herein. In some examples, components are identified in the present disclosure. In such examples, a component can be hardware, software, or a combination thereof. Components can be individual components or subcomponents of a single component.

[0024] Accordingly, in one or more examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise a random-access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), compact disk ROM (CD-ROM), diskette, a hard disk drive, magnetic tape, other magnetic medium, a solid-state drive, a flash memory card, a postal disk, postal compact diskette, other optical medium, any other medium that can be used to store desired computer instructions or data structures in a form that can be accessed by a computer, or any suitable combination of the foregoing. A "computer-readable medium," as used herein, is not "a computer" itself, but is a medium that a computer accesses.

[0025] Generally, the present disclosure describes techniques with graphics processing pipelines in a single device or multiple devices, improving rendering of graphics content and / or reducing load on processing units (i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU). For example, the present disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout the present disclosure.

[0026] As used herein, examples of the term "content" can refer to "graphics content," "images," and vice versa. This is true regardless of whether the terms are used as an adjective, noun, or other part of speech. In some examples, as used herein, the term "graphics content" can refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphics content" can refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphics content" can refer to content produced by a graphics processing unit.

[0027] In some examples, as used herein, the term“display content” can refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term“display content” can refer to content generated by a display processing unit. Graphics content can be processed to become display content. For example, a graphics processing unit can output graphics content, such as a frame, to a buffer, which can be referred to as a frame buffer. A display processing unit can read graphics content, such as one or more frames, from the buffer and perform one or more display processing techniques on the display processing unit to generate display content. For example, a display processing unit can be configured to perform compositing on one or more render layers to generate a frame. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers together into a single frame. A display processing unit can be configured to perform scaling, such as zooming in or out, on a frame. In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form the frame, i.e., the frame includes two or more layers, and the frame including the two or more layers can subsequently be blended.

[0028] Figure 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 can include one or more components or circuits to perform the various functions described herein. In some examples, one or more components of the device 104 can be components of a SOC. The device 104 can include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the device 104 can include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 can include several components, e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to a display 131 can refer to one or more displays 131. For example, the display 131 can include a single display or multiple displays. The display 131 can include a first display and a second display. The first display can be a left eye display and the second display can be a right eye display. In some examples, the first display and the second display can receive different frames for presentation on the first display and the second display. In other examples, the first display and the second display can receive the same frames for presentation on the first display and the second display. In further examples, the results of graphics processing can not be displayed on the device, e.g., the first display and the second display can not receive any frames for presentation thereon. Rather, the frames or graphics processing results can be passed to another device. In some aspects, this situation is referred to as split rendering.

[0029] The processing unit 120 can include internal memory 121. The processing unit 120 can be configured to perform graphics processing, such as in the graphics processing pipeline 107. The content encoder / decoder 122 can include internal memory 123. In some examples, the device 104 can include a display processor, such as the display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 prior to presentation by one or more displays 131. The display processor 127 can be configured to perform display processing. For example, the display processor 127 can be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 can be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 can include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0030] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, can be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 can be configured to read from and / or write to the external memory, such as system memory 124. The processing unit 120 and the content encoder / decoder 122 can be communicatively coupled to the system memory 124 by a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 can be communicatively coupled to each other via the bus or a different connection.

[0031] The content encoder / decoder 122 can be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 can be configured to store received encoded or decoded graphics content. The content encoder / decoder 122 can be configured to receive encoded or decoded graphics content, for example, from the system memory 124 and / or the communication interface 126, in the form of encoded pixel data. The content encoder / decoder 122 can be configured to encode or decode any graphics content.

[0032] The internal memory 121 or system memory 124 can include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 121 or system memory 124 can include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data medium, or an optical storage medium, or any other type of memory.

[0033] According to some examples, the internal memory 121 or system memory 124 can be a non-transitory storage medium. The term “non-transitory” can indicate that the storage medium is not embodied in a carrier wave or a propagating signal. However, the term “non-transitory” should not be interpreted to mean that the internal memory 121 or system memory 124 is non-removable or that its contents are static. For example, the system memory 124 can be removed from the device 104 and moved to another device. As another example, the system memory 124 can be non-removable from the device 104.

[0034] The processing unit 120 can be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 can be integrated into a motherboard of the device 104. In some examples, the processing unit 120 can be present on a graphics card that is installed in a port of the motherboard of the device 104, or can be otherwise incorporated into a peripheral device that is configured to interoperate with the device 104. The processing unit 120 can include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic circuitry, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combination thereof. If the technology is implemented partially in software, the processing unit 120 can store instructions for the software in a suitable, non-transitory computer-readable storage medium (e.g., the internal memory 121) and execute the instructions in hardware to perform the technology of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered one or more processors.

[0035] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into a motherboard of the device 104. The content encoder / decoder 122 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder / decoder 122 can store instructions for the software in a suitable, non-transitory computer-readable storage medium (e.g., the internal memory 123) and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing (including hardware, software, a combination of hardware and software, etc.) can be considered one or more processors.

[0036] In some aspects, the content generation system 100 can include a communication interface 126. The communication interface 126 can include a receiver 128 and a transmitter 130. The receiver 128 can be configured to perform any of the receiving functions described herein with respect to the device 104. In addition, the receiver 128 can be configured to receive information from another device, such as eye or head positioning information, rendering commands, or position information. The transmitter 130 can be configured to perform any of the transmitting functions described herein with respect to the device 104. For example, the transmitter 130 can be configured to transmit information to another device, which can include a request for content. The receiver 128 and the transmitter 130 can be combined into a transceiver 132. In such examples, the transceiver 132 can be configured to perform any of the receiving functions and / or transmitting functions described herein with respect to the device 104.

[0037] Referring again to Figure 1In certain aspects, processing unit 120 can include a downsample component 198 configured to obtain a first indication of an image comprising a set of pixels, where the set of pixels is associated with a color format comprising a set of color channels, where the set of color channels comprises at least a first channel and a second channel, where each pixel in the set of pixels comprises at least a first value of the at least first channel and a second value of the second channel, where each pixel in a subset of pixels in the set of pixels comprises a different at least first value than other pixels in the subset of pixels, and where each pixel in the subset of pixels comprises an equal second value than other pixels in the subset of pixels. Downsample component 198 can be further configured to configure the second value of each pixel in the subset of pixels based on the set of pixels. Downsample component 198 can be further configured to downsample the second value of the second channel of each pixel in the subset of pixels. Downsample component 198 can be further configured to perform a sub-sampling process on the second value of each pixel in the subset of pixels, where the sub-sampling process is associated with a reduced sampling rate in a horizontal direction and a vertical direction. Downsample component 198 can be further configured to adjust the reduced sampling rate in the horizontal direction and the vertical direction in order to match a bit alignment of the set of pixels. Downsample component 198 can be further configured to output a second indication of an image comprising the configured second value of each pixel in the subset of pixels. Although the following description can focus on display processing, the concepts described herein can be applicable to other similar processing techniques.

[0038] As described herein, a device, such as device 104, can refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device can be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), an end product, an appliance, a telephone, a smartphone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smartwatch, an augmented reality device, or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediary network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein can be described as being performed by a particular component (e.g., a GPU), but in further implementations can be performed using other components (e.g., a CPU) that are consistent with the disclosed implementations.

[0039] A GPU can process various types of data or data packets within its pipeline. For example, in some aspects, a GPU can process two types of data or data packets, such as context register packets and draw call data. Context register packets can be a collection of global state information, such as information about global registers, shaders, or constant data, which can regulate how the graphics context will be handled. For example, a context register packet may include information about the color format. In some aspects of a context register packet, there may be bits indicating which workload belongs to the context register. Furthermore, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, context registers can define multiple states of the GPU.

[0040] Context states can be used to determine how individual processing units (e.g., vertex extractors (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate and / or in which mode a processing unit operates. For this purpose, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in the pipeline based on the context register definitions of modes or states. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Because these modes or states can change, the GPU may need to modify the corresponding context. Additionally, the workload corresponding to a mode or state may follow the changed mode or state.

[0041] Figure 2 Example GPU 200 is illustrated according to one or more technologies according to this disclosure. For example... Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, a level 2 (L2) cache (UCHE) 238, and system memory 240. Although Figure 2 The GPU 200 shown includes processing units 220 to 238, but the GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and any combination or order of processing units may be used in the GPU according to this disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0042] like Figure 2As shown, the GPU can utilize a CP (e.g., CP 210) or hardware accelerator to parse the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). Subsequently, the CP 210 can transmit the context register packets 260 or draw call packets 212 through separate paths to processing units or blocks in the GPU. Further, the command buffer 250 can alternate different states of context registers and draw calls. For example, the command buffer can be structured in the following manner: context registers for context N, draw calls for context N, context registers for context N+1, and draw calls for context N+1.

[0043] A GPU can render images in a number of different ways. In some cases, a GPU can use render and / or binning rendering to render an image. In a binning rendering GPU, an image can be divided or partitioned into different sections or bins. After dividing the image, each section or bin can be rendered separately. A binning rendering GPU can divide a computer graphics image into a grid format such that each portion of the grid (i.e., a bin) is rendered separately. In some aspects, during a binning pass, an image can be divided into different bins or tiles. In some aspects, during a binning pass, a visibility stream can be constructed in which visible primitives or draw calls can be identified. In contrast to binning rendering, direct rendering does not divide a frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs can allow for both binning rendering and direct rendering.

[0044] Figure 3 is a block diagram 300 illustrating an example display framework including, for example, a processing unit 120, a system memory 124, a display processor 127, and a display 131 as can be identified in the device 104.

[0045] A GPU can be included in a device that provides content for visual presentation on a display. For example, a processing unit 120 can include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which can be a computer workstation, a mobile phone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of the GPU 310 can be controlled based on one or more graphics processing commands provided by a CPU 315. The CPU 315 can be configured to execute multiple applications concurrently. In some cases, each of the multiple applications executed concurrently can utilize the GPU 310 simultaneously. Processing techniques can be performed via the processing unit 120 to output frames over a physical or wireless communication channel.

[0046] System memory 124, which can be executed by processing unit 120, can include user space 320 and kernel space 325. User space 320 (sometimes referred to as “application space”) can include software applications and / or application frameworks. For example, software applications can include an operating system, a media application, a graphics application, a workspace application, etc. Application frameworks can include frameworks used by one or more software applications, such as libraries, services (e.g., a display service, an input service, etc.), application program interfaces (APIs), etc. Kernel space 325 can further include display driver 330. Display driver 330 can be configured to control display processor 127. For example, display driver 330 can cause display processor 127 to compose frames and send data for the frames to a display.

[0047] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 can be configured to manipulate functionality of display 131 (e.g., based on input received from display driver 330). Display control block 335 can also be configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 can additionally or alternatively perform post-processing of image data provided based on execution of system memory 124 by processing unit 120.

[0048] Display interface 340 can be configured to cause display 131 to display image frames. Display interface 340 can output image data to display 131 according to an interface protocol, such as, for example, MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface). That is, display 131 can be configured according to the MIPI DSI standard. The MIPI DSI standard supports a video mode and a command mode. In examples where display 131 operates in the video mode, display processor 127 can continuously refresh graphical content of display 131. For example, the entire graphical content can be refreshed (e.g., line-by-line) at each refresh period. In examples where display 131 operates in the command mode, display processor 127 can write graphical content for a frame to buffer 350.

[0049] In some such examples, display processor 127 can not continuously refresh graphical content of display 131. Rather, display processor 127 can use a vertical sync (Vsync) pulse to coordinate rendering and consumption of graphical content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 can output new graphical content to buffer 350. Thus, generation of a Vsync pulse can indicate that current graphical content has been rendered at buffer 350.

[0050] Based on the display controller 345, the display client 355, and the buffer 350, a frame is displayed at the display 131. The display controller 345 can receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 can output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 can represent local memory to the display 131. In some examples, the display controller 345 can output image data received from the display interface 340 directly to the display client 355.

[0051] The display client 355 can be associated with a touch panel that senses interactions between a user and the display 131. When a user interacts with the display 131, one or more sensors in the touch panel can output a signal to the display controller 345 that indicates which of the one or more sensors has sensor activity, a duration of the sensor activity, a pressure applied to the one or more sensors, and the like. The display controller 345 can use the sensor output to determine a manner in which the user interacts with the display 131. The display 131 can further be associated with / include other devices that operate in conjunction with the display client 355, such as a camera, a microphone, and / or a speaker.

[0052] Some processing techniques of the device 104 can be performed through three stages (e.g., Stage 1: a render stage; Stage 2: a composition stage; and Stage 3: a display / deliver stage). However, other processing techniques can combine the composition stage and the display / deliver stage into a single stage, such that the processing techniques can be performed based on two stages in total (e.g., Stage 1: a render stage; and Stage 2: a composition / display / deliver stage). During the render stage, the GPU 310 can process the content buffer based on execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stage, pixel elements can be assembled to form a frame that is delivered to a physical display panel / subsystem (e.g., the display 131) that displays the frame.

[0053] Instructions executed by the CPU (e.g., software instructions) or instructions executed by the display processor can cause the CPU or the display processor to search for and / or generate a composition strategy for composing a frame based on dynamic priorities and runtime statistics associated with one or more composition strategy groups. A frame to be displayed by a physical display device, such as a display panel, can include multiple layers. In addition, composition of the frame can be based on combining the multiple layers into the frame (e.g., based on a frame buffer). After the multiple layers are combined into the frame, the frame can be provided to the display panel for display on the display panel. The process of combining each of the multiple layers into the frame can be referred to as composition, frame composition, composition process, composition processing, and the like.

[0054] A frame composition process or composition strategy can correspond to techniques for composing different layers of a plurality of layers into a single frame. The plurality of layers can be stored in a double data rate (DDR) memory. Each layer of the plurality of layers can further correspond to a separate buffer. A compositor or hardware compositor (HWC) associated with a block or function can determine the input of each layer / buffer and perform a frame composition process to generate an output indicative of a composed frame. That is, the input can be layers and the output can be a frame composition process for composing a frame to be displayed on a display panel.

[0055] Some aspects of display processing can utilize different types of mask layers, e.g., shape mask layers. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of a mask layer can correspond to an area of a display, but an entire mask layer can delineate a portion of the content that is actually displayed at the display or panel. For example, a mask layer can include a top portion and a bottom portion of a display area, but a middle portion of the mask layer can be empty. In some examples, there can be multiple mask layers to represent different portions of a display area. Additionally, for certain portions of a display area, the content of different mask layers can overlap one another. Thus, a mask layer can represent a portion of a display area that can or can not overlap other mask layers.

[0056] Figure 4 is a diagram 400 illustrating example mask layers for display processing. More specifically, the diagram 400 depicts one type of mask layer that can represent portions of a display panel. As Figure 4 shown, the diagram 400 includes a mask layer 402 that includes a top region 410 and a bottom region 420. The top region 410 includes region 411, region 412, region 413, and region 414, and the bottom region 420 includes region 421, region 422, region 423, and region 424. As Figure 4 depicted, the mask layer 402 can represent different regions that are displayed on a display panel.

[0057] Some types of displays can use a certain type of mask layer (e.g., shape mask layer) to reshape display frames. For example, a mask layer can reshape display frames to provide a more optimized visual shape at a display panel (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.). These types of mask layers (e.g., shape mask layers) can be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software) or by hardware (e.g., display processing unit (DPU) hardware). Additionally, these mask layers can be processed by other specific types of hardware logic modules (e.g., modules in a display driver integrated circuit (DDIC) or bridge chip). In some aspects, these types of mask layers (e.g., shape mask layers) can be based on a certain unit, such as a pixel. That is, the shape generation base unit of a shape mask layer can be a single pixel.

[0058] Some aspects of display processing can utilize a frame buffer to cache or store the composition output of a GPU. For example, after composition at a GPU, display layers can be cached or stored in a frame buffer. In some aspects, a composition hardware (HW) or software (SW) stack can use a frame buffer target to cache the composition output (e.g., GPU composition output or CPU composition output). The cached composition output can then be passed to another processor (e.g., a DPU) as an input layer. A frame buffer can have multiple different color formats, such as a red (R) green (G) blue (B) alpha (A) (RGBA) format (e.g., a RGBA8888 format). Additionally, a frame buffer can have a certain size (e.g., a 32-bit triple buffer). For example, at the beginning of a display / graphic subsystem design, a frame buffer can be created as a RGBA8888 format and a 32-bit triple buffer. In some instances, if a frame layer does not use a certain composition (e.g., GPU or client composition), the frame buffer can be ignored. Additionally, layers (e.g., frame layers or display layers associated with display processing) can be directly fetched and composed. For example, a DPU or hardware compositor can directly fetch a layer and then compose the layer.

[0059] Figure 5 is a diagram 500 illustrating an example of a layer composition scheme for display processing. More specifically, the diagram 500 depicts layer composition of display layers, where certain layers (e.g., layers of a certain composition) are cached in a frame buffer and some layers are directly fetched and composed by a DPU. As shown, the diagram 500 includes a layer 510, a layer 511, a layer 512, a layer 513, a frame buffer 530 (e.g., a RGBA8888 format frame buffer), a DPU 540, and a display 550. Figure 5 Figure 5 ​Layers that are synthesized at the GPU (i.e., layers associated with GPU synthesis) can be cached or stored in a frame buffer. For example, layer 510, layer 511, and layer 512 can be synthesized at the GPU and then cached / stored at frame buffer 530. Alternatively, layers that are not synthesized at the GPU (i.e., layers associated with non-GPU synthesis) can be directly fetched and synthesized at the DPU. For example, layer 513 can be directly fetched and synthesized at DPU 540. That is, layer 510, layer 511, and layer 512 can be of one type of synthesis (e.g., GPU synthesis), while layer 513 can be of another type of synthesis (non-GPU synthesis). After being cached / stored in frame buffer 530, layer 510, layer 511, and layer 512 can be communicated to DPU 540. Further, after processing at DPU 540, layer 510-513 can be communicated to display 550.

[0060] In some aspects, certain types of frame buffers (e.g., single format 32-bit RGBA8888 frame buffers) can correspond to reduced display quality (e.g., poor synthesis performance, poor power performance, poor color management, and / or poor visual quality). For example, certain types of frame buffer synthesis (e.g., single format 32-bit RGBA8888 frame buffer synthesis) can not be able to match certain power / performance specifications of certain displays (e.g., high frame rate, high layer complexity, frame geometry, standard dynamic range (SDR) / high dynamic range (HDR)), such as color management and mobile system performance / power specifications of certain displays. Some types of layer formats (e.g., floating point 16-bit (FP16) format, integer 12-bit (INT12) format, integer 10-bit (INT10) format) can lose details (e.g., color and geometry details) of certain types of synthesis (e.g., 32-bit RGBA8888 GPU synthesis). For example, if 4 bytes are maintained and 32-bit buffer alignment is not changed (e.g., RGBA1010102 buffer), an alpha channel (e.g., 2-bit alpha channel) can not be sufficient to maintain a certain level of detail. Additionally, if a direct change is made to the frame buffer (e.g., changed to a RGBA FP16161616 8-byte format), the power / performance cost can be high. In some aspects, if a frame buffer is marked as SDR, it can not be able to meet HDR layer synthesis specifications. Also, if a frame buffer is marked as HDR, it can not be able to meet SDR layer synthesis specifications, as well as result in poor power / performance.

[0061] High dynamic range (HDR) content is high definition content such as improves the quality of a display signal when compared to standard dynamic range (SDR) content. For example, HDR uses a higher dynamic color range than normal (e.g., SDR) content. HDR content helps change the way luminance and color of a video / image are represented in a signal. HDR also allows brighter and more detailed highlights, as well as darker, more detailed shadows, and a wider array of colors. That is, HDR content allows for higher light level variations within a scene or image. For example, HDR allows compatible displays to receive higher quality image sources, but the content cannot improve inherent characteristics of the display device (e.g., brightness, contrast, and color). Thus, HDR content can look different depending on the type of display used.

[0062] Various different types of HDR content can be used in image and frame processing. For example, 10-bit HDR content is widely used, as well as wide color gamut and other types of HDR content. Further, certain types of digital dimming can be used with HDR content. Digital dimming can be a process of dimming content (e.g., HDR content) when displayed on a digital device. For example, during HDR video playback, a user interface (UI) digital dimming can be used for 10-bit HDR content. During digital dimming, an original equipment manufacturer (OEM) can utilize one dimming layer to slowly change a gray level to control a dimming effect. By doing so, this can force some types of layers (e.g., all UI layers) to utilize client-side composition (e.g., GPU composition), while other types of layers (e.g., HDR video layers) can utilize device-side composition (e.g., DPU composition). For example, for some types of frame buffer targets (FBTs) that utilize GPU composition (e.g., 8-bit frame buffer targets (FBTs) or RGBA8888 format), the dimming effect or gray transition can not be smooth. Further, for other types of FBTs (e.g., 10-bit FBTs or RGBA1010102 format), the dimming effect or gray transition can be smooth, but there can be several UI visual effect issues. This can be caused by an alpha (A) blending issue in the last step of device-side composition (e.g., DPU composition), which can be due to insufficient precision of alpha values for certain formats (e.g., RGBA1010102 format). For example, the RGBA1010102 format can utilize only 2 bits for alpha values, which can not be precise enough for these types of formats. That is, there are 10 bits for RGB values, which can be sufficient for transitions, but 2 bits for alpha (A) values can not be enough to avoid blending issues. In fact, this lower bit allocation for alpha (A) values can cause visual effect issues in the final step of display composition.

[0063] Figure 6Illustrations 600 and 650 illustrate example visual problems in display devices. More specifically, illustrations 600 and 650 depict visual problems that can be caused by the incorrect allocation of certain bits (e.g., the α(A) bit). Figure 6 As shown, Figure 600 includes a display device 610, which includes a screen 620 and a pop-up window 630. Figure 600 depicts a pop-up window 630 that may appear on the screen 620 as a visual effect problem caused by the incorrect allocation of certain bits (e.g., α-bit) during color mixing (e.g., α-mixing). For example, the pop-up window 630 may be a type of visual effect problem caused when displaying HDR video playback. Furthermore, as... Figure 6 As illustrated, Figure 650 includes a display device 660, which includes a screen 670 that addresses display flicker issues. Figure 650 depicts a visual effect problem on screen 670 caused by the incorrect allocation of certain bits (e.g., α-bits) during color mixing (e.g., α-mixing). For example, the flicker problem on screen 670 could be a type of visual effect problem caused when displaying HDR video playback.

[0064] Certain types of color formats or (e.g., floating point (FP) formats or FP16 formats) can address the aforementioned visual issues (e.g., display flicker issues). However, these types of color formats or FP formats (e.g., FP16 formats) can have significant power consumption and memory consumption that can be detrimental to a device. Other types of color formats (e.g., RGBA10101010 formats) can be potentially helpful, but can present challenges for compatibility with operating systems (OSs) and / or rendering engines. Further, some types of color formats (e.g., RGBA10101010 formats) can have too many bits (e.g., too many bits allocated for alpha (A) values) that can consume too much power. That is, for some frame buffer targets (e.g., frame buffer targets for RGBA1010102 formats), 2-bit alpha values can not be sufficient, while other frame buffer targets (e.g., frame buffer targets for RGBA10101010 formats or FP16 formats) can need additional bits and have power issues. As indicated herein, increasing the amount of bits utilized (e.g., bits allocated for alpha (A) values) can improve the overall visual quality of a display device, but also increase the overall power consumption at the display device. Further, reducing the amount of bits utilized for color formats (e.g., bits allocated for alpha (A) values) can reduce the overall power consumption at the display device, but reduce the overall visual quality of the display device. Based on the above, it can be beneficial to provide a balanced approach to efficiently utilize each bit in certain types of color formats (e.g., RGBA formats that include RGBA pixels). Further, it can be beneficial to balance performance and power consumption at a device when utilizing certain types of display formats (e.g., HDR video playback) with certain types of display features (e.g., dimming features).

[0065] Aspects of the disclosure can provide a balanced and efficient approach to utilizing each bit in different color formats for a display device. For example, aspects presented herein can efficiently utilize each bit in certain types of color formats (e.g., RGBA formats that include RGBA pixels). Additionally, aspects of the disclosure can effectively balance performance and power consumption at a device when displaying certain types of color formats. For example, aspects of the disclosure can balance performance and power consumption at a device when utilizing certain types of display formats (e.g., HDR video playback) with certain types of display features (e.g., dimming features). That is, aspects presented herein can utilize a type of color format (e.g., a 10-bit RGBA format or a RGBA1010102 format) that includes a down-sampled channel or a spatially sub-sampled channel (e.g., an alpha channel). By doing so, aspects presented herein can provide visual / power optimizations for color / pixel blending (e.g., alpha blending).

[0066] In some cases, aspects of the present disclosure can more efficiently balance certain bit values of color channels during display processes. For example, aspects presented herein can balance the precision and memory size of channels of certain color formats (e.g., R / G / B / A channels of RGBA color formats). Aspects presented herein can utilize an enhanced color format (e.g., enhanced RGBA1010102 format) with a particular alpha (A) channel for pixels during display processes. In some aspects, the enhanced color format (e.g., enhanced RGBA1010102 format) can consume a similar amount of bits or memory size as other color formats (e.g., RGBA8888 format), but provide higher precision for R / G / B values and alpha (A) values. Moreover, since the alpha (A) value difference between adjacent pixels can be smaller, the alpha value difference can have less significant impact on the color blending result compared to R / G / A value differences. Thus, aspects presented herein can utilize down-sampling or sub-sampling (sub-sampling) of alpha (A) values in order to obtain some additional benefits power saving benefits. Additionally, aspects of the present disclosure can relate to optimization of power / visual balance of RGBA value precision and memory size. For example, aspects presented herein can efficiently utilize each bit of a RGBA pixel, i.e., consider power consumption and visual quality of each bit. For example, aspects presented herein propose an enhanced RGBA1010102 format, where each 2x2 pixel can be one composite block, each pixel in the block can have independent 10-bit RGB values, but share an 8-bit alpha (A) value, where each pixel contributes 2 bits for the alpha (A) value. The spatial sub-sampling rate can be variable to match different RGB bit alignment conditions. The enhanced RGBA1010102 format can consume the same bit / memory size as the RGBA8888 format, but provide higher precision for both RGB values and alpha (A) values.

[0067] Additionally, in some aspects, each block of pixels (e.g., a 2x2 block of pixels) can be a composite block, where each pixel in the block has independent R / G / B values (e.g., 10-bit R / G / B values) and shares an alpha (A) (e.g., an 8-bit alpha (A) value). In this case, each pixel in the block can contribute an amount of bits to the overall alpha (A) value in the block (e.g., for an 8-bit alpha (A) value, each pixel can contribute 2 bits to the A value). For example, in an enhanced RGBA1010102 format, each 2x2 block of pixels can correspond to a composite block, where each pixel in the block can have independent 10-bit R / G / B values. Further, each pixel in the block can share an 8-bit alpha (A) value, such that each pixel in the block can contribute 2 bits to the alpha (A) value. That is, the 10 bits of R / G / B values in a block of pixels can be independent for each pixel, but the 8 bits of alpha value in a block of pixels can be shared among the pixels, such that each pixel contributes 2 bits to the alpha value. Thus, each pixel in the block can contribute a 10-bit R value, a 10-bit G value, a 10-bit B value, and a 2-bit alpha (A) value, which corresponds to the enhanced RGBA1010102 format

[0068] In some aspects, certain channels of certain color formats (e.g., R / G / B channels of an RGBA color format) can be associated with full sampling, and other channels of the color format (e.g., an alpha (A) value of an RGBA color format) can be associated with sub-sampling or down-sampling. For example, the RGB values of an RGBA color format can be associated with full sampling, and the alpha (A) value can be associated with sub-sampling (e.g., sub-sampling at a rate of 0.5 in the horizontal direction and the vertical direction) or down-sampling. In some aspects, the spatial sub-sampling rate of the alpha (A) value can be variable to match different alignment conditions (e.g., RGB bit alignment conditions). For example, the sub-sampling rate of the alpha (A) value can be a rate of 0.5 in the horizontal direction and a rate of 0.5 in the vertical direction. Further, the sub-sampling rate of the alpha (A) value can be a rate of 0.5 in the horizontal direction and a full rate (e.g., a rate of 100%) in the vertical direction. Further, the sub-sampling rate of the alpha (A) value can be a rate of 0.25 in the horizontal direction and a rate of 0.25 in the vertical direction. Further, the reduced sampling rates in the horizontal direction and the vertical direction can be adjusted in order to match the bit alignment of the remaining pixels.

[0069] In some aspects, as indicated above, the alpha (A) values of each pixel in a pixel block in an image can be down-sampled or sub-sampled (sub-sampling). Down-sampling can correspond to replacing pixels in a sample region with an average pixel color. That is, down-sampling can average the pixels in a sample region and then replace the entire region with the average pixel color at a specified resolution. For example, to down-sample the alpha (A) values of a pixel block, an average of the alpha values of each pixel in the pixel block can be calculated and then the average of the alpha values of each pixel in the pixel block can be down-sampled. Sub-sampling can correspond to selecting a pixel, replacing the surrounding region with the same pixel. That is, sub-sampling can select a pixel in the center of a sample region and then replace the entire region with the selected pixel at a specified resolution. For example, to sub-sample the alpha (A) values of a pixel block, the reduced sampling rate in the horizontal direction and the vertical direction can be adjusted so as to match the bit alignment of the set of pixels.

[0070] Figure 7 is a diagram 700 illustrating an example pixel group. More specifically, the diagram 700 depicts an example RGBA pixel group that includes R / G / B values for each pixel and shares an alpha (A). As shown, the diagram 700 includes a group of 4 pixels (e.g., RGBA pixel 710, RGBA pixel 711, RGBA pixel 712, and RGBA pixel 713) that each include an alpha (A) value 720. Figure 7 As shown, the diagram 700 includes a group of 4 pixels (e.g., RGBA pixel 710, RGBA pixel 711, RGBA pixel 712, and RGBA pixel 713) that each include an alpha (A) value 720. Figure 7 As shown, the diagram 700 includes a group of 4 pixels (e.g., RGBA pixel 710, RGBA pixel 711, RGBA pixel 712, and RGBA pixel 713) that each include an alpha (A) value 720.

[0071] In some cases, an enhanced color format (e.g., an enhanced RGBA1010102 format) can be used in a variety of pipelines and stages. For example, an enhanced color format (e.g., an enhanced RGBA1010102 format) can be used as a frame buffer target format for compositing output. In some aspects, an enhanced color format can be used as a render output layer for HDR graphics content. In some use cases, an application can use Open Graphics Library (OpenGL) in order to process HDR content. Accordingly, aspects presented herein can use such an enhanced color format for output of HDR content processing. Aspects presented herein can also use an enhanced color format for digital brightness dimming control (e.g., OEM side digital brightness dimming control). For other types of applications (e.g., CPU, GPU, native signal processing (NSP) hardware, and / or digital signal processing (DSP) hardware), aspects presented herein can utilize an enhanced color format on 32-bit aligned buffers. Additionally, other types of digital systems can have specific bit alignment requests for utilizing an enhanced color format.

[0072] Aspects presented herein can also read / write pre-pixel RGB values from / to this enhanced RGBA1010102 format. For example, since the RGB values are pixel independent, aspects presented herein can read / write the RGB values of each pixel directly without having to fetch data of other pixels. That is, aspects presented herein can obtain an alpha value directly from a pixel without touching other neighboring pixels. Aspects presented herein can also read alpha (A) values from an enhanced color format (e.g., an enhanced RGBA1010102 format). For example, an alpha (A) value can be shared among pixels in a group (e.g., a 2x2 pixel block), so aspects presented herein can read the alpha value from all pixels in a group (e.g., 4 pixels) and combine the values to obtain a final alpha value. For example, 2-bit alpha (A) values from each pixel can be combined to produce a final 8-bit alpha (A) value. As Figure 7As shown, the total alpha value for RGBA pixels 710-713 = alpha (A) value 720 for RGBA pixel 710 + alpha (A) value 720 for RGBA pixel 711 + alpha (A) value 720 for RGBA pixel 712 + alpha (A) value 720 for RGBA pixel 713. Further, in some aspects, the total 8-bit alpha value = [alpha of pixel 713] « 6 + [alpha of pixel 712] « 4 + [alpha of pixel 711] « 2 + [alpha of pixel 710] « 0. Additionally, aspects presented herein can write alpha values to an enhanced color format (e.g., an enhanced RGBA1010102 format). For example, aspects presented herein can update the latest alpha (A) values to a group of pixels (e.g., a 2x2 block of pixels) and modify the alpha value (e.g., a 2-bit alpha value) for each pixel accordingly. In some aspects, if any alpha values for pixels in a block need to be updated, aspects presented herein can update the alpha values for the entire block of pixels because the alpha values in a block of pixels are shared. For example, a new alpha value can be updated for each pixel such that an 8-bit alpha value can be divided into four pixels. As Figure 7 As shown, the alpha value for pixel 710 = (8-bit alpha » 0) & 0x3; the alpha value for pixel 711 = (8-bit alpha » 2) & 0x3; the alpha value for pixel 712 = (8-bit alpha » 4) & 0x3; and the alpha value for pixel 713 = (8-bit alpha » 6) & 0x3.

[0073] Figure 8 is a diagram 800 illustrating an example down-sampling or sub-sampling process of pixels. More specifically, diagram 800 depicts an example down-sampling or sub-sampling of alpha values for pixels in an RGBA image. As Figure 8 As shown, diagram 800 includes a GPU / DPU 802, an RGBA image 810, a down-sampling / sub-sampling 820, and an RGBA image 830. Figure 8 GPU / DPU 802 is depicted receiving an indication of an RGBA image 810 including a set of pixels. GPU / DPU 802 then down-samples / sub-samples an alpha value for each pixel in a subset of pixels in the set of pixels of RGBA image 810. This down-sampling / sub-sampling 820 of alpha values can result in an RGBA image 830 including a down-sampled / sub-sampled alpha value for each pixel in the subset of pixels. Next, GPU / DPU 802 transmits an indication of RGBA image 830 including the down-sampled / sub-sampled alpha value for each pixel in the subset of pixels.

[0074] As Figure 8As shown, GPU / DPU 802 can obtain a first indication of an image (e.g., RGBA image 810) comprising a set of pixels associated with a color format (e.g., RGBA color format) comprising a set of color channels (e.g., RGBA channels), where the set of color channels comprises at least a first channel (e.g., R / G / B channel) and a second channel (e.g., alpha channel), where each pixel of the set of pixels comprises a first value (e.g., R / G / B value) of the first channel and a second value (e.g., alpha value) of the second channel. In some aspects, each pixel of a subset of pixels (e.g., RGBA pixels 710-713) of the set of pixels comprises a first value (e.g., R / G / B value) that is different from other pixels of the subset of pixels, and where each pixel of the subset of pixels (e.g., RGBA pixels 710-713) comprises a second value (e.g., alpha value 720) that is equal to other pixels of the subset of pixels. GPU / DPU 802 can also configure (e.g., downsample / subsample 820) the second value (e.g., alpha value 720) of each pixel of the subset of pixels (e.g., RGBA pixels 710-713) based on the set of pixels (e.g., GPU / DPU 802 downsample / subsample the alpha value of each pixel of the subset of pixels in the set of pixels of RGBA image 810). GPU / DPU 802 can also output a second indication of an image comprising the configured second value (e.g., downsampled / subsampled alpha value) of each pixel of the subset of pixels (e.g., RGBA pixels 710-713) (e.g., an indication of RGBA image 830).

[0075] In some aspects, when GPU / DPU 802 configures the second value (e.g., alpha value 720) of each pixel of the subset of pixels (e.g., RGBA pixels 710-713), GPU / DPU 802 can downsample the second value (e.g., alpha value 720) of the second channel of each pixel of the subset of pixels. Further, downsample the second value (e.g., alpha value 720) of each pixel of the subset of pixels (e.g., RGBA pixels 710-713) can comprise: compute an average of the second value (e.g., alpha value 720) of each pixel of the subset of pixels; and downsample the average of the second value (e.g., alpha value 720) of each pixel of the subset of pixels.

[0076] Additionally, in some cases, the first value (e.g., R / G / B value) of each pixel in the subset of pixels (e.g., RGBA pixels 710-713) can be associated with a full sampling process, and the second value (e.g., alpha value 720) of each pixel in the subset of pixels can be associated with a subsampling process (e.g., downsample / subsample 820). Moreover, in some aspects, when the GPU / DPU 802 configures the second value (e.g., alpha value 720) of each pixel in the subset of pixels (e.g., RGBA pixels 710-713), the GPU / DPU 802 can perform a subsampling process (e.g., downsample / subsample 820) on the second value (e.g., alpha value 720) of each pixel in the subset of pixels (e.g., RGBA pixels 710-713), where the subsampling process can be associated with a reduced sampling rate in the horizontal direction and the vertical direction. Furthermore, performing the subsampling process (e.g., downsample / subsample 820) on the second value (e.g., alpha value 720) of each pixel in the subset of pixels (e.g., RGBA pixels 710-713) can include adjusting the reduced sampling rate in the horizontal direction and the vertical direction in order to match the bit alignment of the set of pixels. Moreover, the reduced sampling rate can be at least one of: a 0.5 rate in the horizontal direction and a 0.5 rate in the vertical direction, a 0.5 rate in the horizontal direction and a full rate in the vertical direction, or a 0.25 rate in the horizontal direction and a 0.25 rate in the vertical direction.

[0077] Aspects of the disclosure can include a number of benefits or advantages. For example, aspects presented herein can also efficiently utilize each bit in certain types of color formats (e.g., RGBA format including RGBA pixels). That is, aspects presented herein can optimize the use of each bit of each RGBA pixel. Aspects presented herein can also provide an efficient balance between power usage and visual quality. For example, when utilizing certain types of display formats (e.g., HDR video playback) with certain types of display features (e.g., dimming features), aspects of the disclosure can balance performance and power consumption at a device. Moreover, aspects presented herein can satisfy certain types of buffer alignment conditions (e.g., GPU / CPU / DSP buffer alignment conditions). Additionally, aspects presented herein can utilize a novel spatial subsampling method for the alpha channel in certain color formats (e.g., RGBA format). This can be helpful in processing alpha values of certain color formats (e.g., RGBA format).

[0078] Figure 9 is a communication flow diagram 900 of image processing according to one or more techniques of the disclosure. As Figure 9As shown, according to one or more techniques of this disclosure, diagram 900 includes example communications between a GPU 902 (e.g., a graphics processor, CPU, or other central processor), a DPU 904 (e.g., a display processor, application, or CPU), and a memory 906 (e.g., a memory or cache at the GPU or DPU).

[0079] At 910, GPU 902 can obtain a first indication of an image including a set of pixels (e.g., GPU 902 can obtain indication 912 from DPU 904), where the set of pixels is associated with a color format including a set of color channels, where the set of color channels includes at least one first channel and a second channel, where each pixel in the set of pixels includes at least one first value of the at least one first channel and a second value of the second channel, where each pixel in a subset of pixels of the set of pixels includes a different at least one first value from other pixels in the subset of pixels, and where each pixel in the subset of pixels includes an equal second value from other pixels in the subset of pixels.

[0080] In some aspects, the color format can be a red (R) green (G) blue (B) alpha (A) (RGBA) color format, where the at least one first channel can include an R channel, a G channel, and a B channel, where the second channel can include an alpha (A) channel, where the at least one first value can include an R value, a G value, and a B value, and where the second value can include an alpha (A) value. Further, the RGBA color format can be a RGBA1010102 format. Additionally, in some aspects, a total number of bits of the second values of the subset of pixels can be equally divided among each pixel in the subset of pixels. For example, the subset of pixels can include 4 pixels, where a total number of bits of the second values of the subset of pixels can equal 8 bits, and where each pixel in the subset of pixels can include 2 bits. Further, in some aspects, a number of bits of the at least one first value of each pixel in the subset of pixels can equal a number of bits of the at least one first value of other pixels in the subset of pixels. For example, a number of bits of the at least one first value of each pixel in the subset of pixels can equal 10 bits.

[0081] At 920, GPU 902 can configure the second value of each pixel in the subset of pixels based on the set of pixels.

[0082] At 930, GPU 902 can downsample the second value of the second channel of each pixel in the subset of pixels. For example, configuring the second value of each pixel in the subset of pixels can include (e.g., comprise): downsample the second value of the second channel of each pixel in the subset of pixels. Further, downsample the second value of each pixel in the subset of pixels can include: calculate an average of the second value of each pixel in the subset of pixels; and downsample the average of the second value of each pixel in the subset of pixels.

[0083] At 940, GPU 902 can perform a sub-sampling process on the second value of each pixel in the subset of pixels (i.e., sub-sample the second value), where the sub-sampling process is associated with a reduced sampling rate in the horizontal direction and the vertical direction. In some aspects, at least one first value of each pixel in the subset of pixels can be associated with a full-sampling process, and the second value of each pixel in the subset of pixels can be associated with a sub-sampling process. For example, configuring the second value of each pixel in the subset of pixels can include performing a sub-sampling process on the second value of each pixel in the subset of pixels, where the sub-sampling process can be associated with a reduced sampling rate in the horizontal direction and the vertical direction.

[0084] At 950, GPU 902 can adjust the reduced sampling rate in the horizontal direction and the vertical direction in order to match a bit alignment of the set of pixels. For example, performing a sub-sampling process on the second value of each pixel in the subset of pixels can include adjusting the reduced sampling rate in the horizontal direction and the vertical direction in order to match a bit alignment of the set of pixels. In some aspects, the reduced sampling rate can be at least one of: a 0.5 rate in the horizontal direction and a 0.5 rate in the vertical direction, a 0.5 rate in the horizontal direction and a full rate in the vertical direction, or a 0.25 rate in the horizontal direction and a 0.25 rate in the vertical direction.

[0085] At 960, GPU 902 can output a second indication of an image including the configured second value of each pixel in the subset of pixels. In some aspects, outputting the second indication of the image including the configured second value of each pixel in the subset of pixels can include transmitting the second indication of the image including the configured second value of each pixel in the subset of pixels. Further, transmitting the second indication of the image including the configured second value of each pixel in the subset of pixels can include transmitting the second indication of the image including the configured second value of each pixel in the subset of pixels to at least one of: a frame composer, a graphics processing unit (GPU) component, a display processing unit (DPU), or a display (e.g., GPU 902 can transmit indication 962 to DPU 904). Additionally, in some aspects, outputting the second indication of the image including the configured second value of each pixel in the subset of pixels can include storing the second indication of the image including the configured second value of each pixel in the subset of pixels. Further, storing the second indication of the image including the configured second value of each pixel in the subset of pixels can include storing the second indication of the image including the configured second value of each pixel in the subset of pixels in at least one of: a frame buffer, a graphics buffer, a graphics memory, or a system memory (e.g., GPU 902 can store indication 964 in memory 906).

[0086] Figure 10is a flowchart 1000 of an example method of image processing in accordance with one or more techniques of this disclosure. The method can be performed by a GPU (or other graphics processor), a DPU (or other display processor), a CPU (or other central processor), a DPU driver, a DDIC, an apparatus for image processing, a wireless communication device, and / or any apparatus that performs data processing for use with examples as described in connection with Figures 1 to 9 .

[0087] At 1002, the GPU can obtain a first indication of an image comprising a set of pixels, where the set of pixels is associated with a color format comprising a set of color channels, where the set of color channels comprises at least one first channel and a second channel, where each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, where each pixel in a subset of the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and where each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels, as described in connection with Figures 1 to 9 . For example, as described in 910 of Figure 9 , the GPU 902 can obtain a first indication of an image comprising a set of pixels, where the set of pixels is associated with a color format comprising a set of color channels, where the set of color channels comprises at least one first channel and a second channel, where each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, where each pixel in a subset of the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and where each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels. Further, step 1002 can be performed by the processing unit 120 in Figure 1 . For example, the GPU 902 can obtain the indication 912 from the DPU 904.

[0088] In some aspects, the color format can be a red (R) green (G) blue (B) alpha (A) (RGBA) color format, where the at least one first channel can comprise an R channel, a G channel, and a B channel, where the second channel can comprise an alpha (A) channel, where the at least one first value can comprise an R value, a G value, and a B value, and where the second value can comprise an alpha (A) value. Further, the RGBA color format can be a RGBA1010102format. Additionally, in some aspects, a total number of bits of the second value of the subset of pixels can be equally divided among each pixel in the subset of pixels. For example, the subset of pixels can comprise 4 pixels, where a total number of bits of the second value of the subset of pixels can equal 8 bits, and where each pixel in the subset of pixels can comprise 2 bits. Further, in some aspects, a number of bits of the at least one first value of each pixel in the subset of pixels can equal a number of bits of the at least one first value of other pixels in the subset of pixels. For example, a number of bits of the at least one first value of each pixel in the subset of pixels can equal 10 bits.

[0089] At 1004, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the examples in Figures 1 to 9 At 1004, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the examples in Figure 9 At 1004, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the examples in Figure 1 At 1004, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the examples in

[0090] At 1012, the GPU can output a second indication of an image comprising the configured second value of each pixel in the subset of pixels, as described in connection with the examples in Figures 1 to 9 At 1012, the GPU can output a second indication of an image comprising the configured second value of each pixel in the subset of pixels, as described in connection with the examples in Figure 9 At 1012, the GPU can output a second indication of an image comprising the configured second value of each pixel in the subset of pixels, as described in connection with the examples in Figure 1In some aspects, outputting the second indication of the image including the configured second value for each pixel of the subset of pixels can include sending the second indication of the image including the configured second value for each pixel of the subset of pixels. Further, sending the second indication of the image including the configured second value for each pixel of the subset of pixels can include sending the second indication of the image including the configured second value for each pixel of the subset of pixels to at least one of a frame composer, a graphics processing unit (GPU) component, a display processing unit (DPU), or a display (e.g., GPU 902 can send indication 962 to DPU 904). Additionally, in some aspects, outputting the second indication of the image including the configured second value for each pixel of the subset of pixels can include storing the second indication of the image including the configured second value for each pixel of the subset of pixels. Further, storing the second indication of the image including the configured second value for each pixel of the subset of pixels can include storing the second indication of the image including the configured second value for each pixel of the subset of pixels in at least one of a frame buffer, a graphics buffer, a graphics memory, or a system memory (e.g., GPU 902 can store indication 964 in memory 906).

[0091] Figure 11 is a flow diagram 1100 of an example method of image processing in accordance with one or more techniques of this disclosure. The method can be performed by a GPU (or other graphics processor), a DPU (or other display processor), a CPU (or other central processor), a DPU driver, a DDIC, an apparatus for image processing, a wireless communication device, and / or any apparatus that performs data processing for example uses as described in connection with Figures 1 to 9 .

[0092] At 1102, the GPU can obtain a first indication of an image including a set of pixels, where the set of pixels is associated with a color format including a set of color channels, where the set of color channels includes at least one first channel and a second channel, where each pixel of the set of pixels includes at least one first value for the at least one first channel and a second value for the second channel, where each pixel of a subset of pixels of the set of pixels includes a different at least one first value from other pixels of the subset of pixels, and where each pixel of the subset of pixels includes an equal second value from other pixels of the subset of pixels, as described in connection with the examples of Figures 1 to 9 . For example, as described in connection with the examples of Figure 9As described in 910, GPU 902 can obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels of the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels. Further, step 1102 can be performed by processing unit 120 in Figure 1 As described in 910, GPU 902 can obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels of the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels. Further, step 1102 can be performed by processing unit 120 in

[0093] In some aspects, the color format can be a red (R) green (G) blue (B) alpha (A) (RGBA) color format, wherein the at least one first channel can comprise the R channel, the G channel, and the B channel, wherein the second channel can comprise the alpha (A) channel, wherein the at least one first value can comprise the R value, the G value, and the B value, and wherein the second value can comprise the alpha (A) value. Further, the RGBA color format can be a RGBA1010102 format. Additionally, in some aspects, a total number of bits of the second values of the subset of pixels can be equally divided among each pixel in the subset of pixels. For example, the subset of pixels can comprise 4 pixels, wherein a total number of bits of the second values of the subset of pixels can equal 8 bits, and wherein each pixel in the subset of pixels can comprise 2 bits. Further, in some aspects, a number of bits of the at least one first value of each pixel in the subset of pixels can equal a number of bits of the at least one first value of other pixels in the subset of pixels. For example, a number of bits of the at least one first value of each pixel in the subset of pixels can equal 10 bits.

[0094] At 1104, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the example of Figures 1 to 9 At 1104, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the example of Figure 9 At 1104, the GPU can configure the second value of each pixel in the subset of pixels based on the set of pixels, as described in connection with the example of Figure 1 Further, step 1104 can be performed by processing unit 120 in

[0095] At 1106, the GPU can downsample the second value of the second channel of each pixel in the subset of pixels, as described in connection with the example of Figures 1 to 9 At 1106, the GPU can downsample the second value of the second channel of each pixel in the subset of pixels, as described in connection with the example of Figure 9 At 1106, the GPU can downsample the second value of the second channel of each pixel in the subset of pixels, as described in connection with the example of Figure 1The second value of each pixel in the subset of pixels can be configured by the GPU 902, as described in connection with 950 of FIG. 9. For example, configuring the second value of each pixel in the subset of pixels can include (e.g., comprise) downsampling the second value of the second channel of each pixel in the subset of pixels. Further, downsampling the second value of each pixel in the subset of pixels can include calculating a mean of the second value of each pixel in the subset of pixels; and downsampling the mean of the second value of each pixel in the subset of pixels.

[0096] At 1108, the GPU can perform a sub-sampling process on the second value of each pixel in the subset of pixels (i.e., sub-sample the second value), where the sub-sampling process is associated with a reduced sampling rate in the horizontal direction and the vertical direction, as described in connection with the examples in Figures 1 to 9 At 1108, the GPU can perform a sub-sampling process on the second value of each pixel in the subset of pixels (i.e., sub-sample the second value), where the sub-sampling process is associated with a reduced sampling rate in the horizontal direction and the vertical direction, as described in connection with the examples in Figure 9 At 1108, the GPU can perform a sub-sampling process on the second value of each pixel in the subset of pixels (i.e., sub-sample the second value), where the sub-sampling process is associated with a reduced sampling rate in the horizontal direction and the vertical direction, as described in connection with the examples in Figure 1 The second value of each pixel in the subset of pixels can be configured by the GPU 902, as described in connection with 950 of FIG. 9. For example, configuring the second value of each pixel in the subset of pixels can include (e.g., comprise) downsampling the second value of the second channel of each pixel in the subset of pixels. Further, downsampling the second value of each pixel in the subset of pixels can include calculating a mean of the second value of each pixel in the subset of pixels; and downsampling the mean of the second value of each pixel in the subset of pixels.

[0097] At 1110, the GPU can adjust the reduced sampling rate in the horizontal direction and the vertical direction so as to match a bit alignment of the set of pixels, as described in connection with the examples in Figures 1 to 9 At 1110, the GPU can adjust the reduced sampling rate in the horizontal direction and the vertical direction so as to match a bit alignment of the set of pixels, as described in connection with the examples in Figure 9 At 1110, the GPU can adjust the reduced sampling rate in the horizontal direction and the vertical direction so as to match a bit alignment of the set of pixels, as described in connection with the examples in Figure 1 The second value of each pixel in the subset of pixels can be configured by the GPU 902, as described in connection with 950 of FIG. 9. For example, configuring the second value of each pixel in the subset of pixels can include (e.g., comprise) downsampling the second value of the second channel of each pixel in the subset of pixels. Further, downsampling the second value of each pixel in the subset of pixels can include calculating a mean of the second value of each pixel in the subset of pixels; and downsampling the mean of the second value of each pixel in the subset of pixels.

[0098] At 1112, the GPU can output a second indication of an image that includes the configured second value of each pixel in the subset of pixels, as described in connection with the examples in Figures 1 to 9The examples described in the document. For example, as... Figure 9 As described in 960, GPU 902 can output a second indication of an image comprising a configured second value for each pixel in a subset of pixels. Furthermore, step 1112 can be performed by... Figure 1 Figures 1 to 9 Figure 9 Figure 1 Figures 1 to 9 Figure 9 Figure 1 Figures 1 to 9 The processing unit 120 executes this. In some aspects, outputting a second indication of an image comprising the configured second value of each pixel in the pixel subset may include sending a second indication of an image comprising the configured second value of each pixel in the pixel subset. Furthermore, sending a second indication of an image comprising the configured second value of each pixel in the pixel subset may include sending the second indication of an image comprising the configured second value of each pixel in the pixel subset to at least one of: a frame synthesizer, a graphics processing unit (GPU) component, a display processing unit (DPU), or a display (e.g., GPU 902 may send indication 962 to DPU 904). Additionally, in some aspects, outputting a second indication of an image comprising the configured second value of each pixel in the pixel subset may include storing a second indication of an image comprising the configured second value of each pixel in the pixel subset. Furthermore, storing a second indication of an image for each pixel in a subset of pixels may include storing the second indication of an image for each pixel in a subset of pixels in at least one of the following: a frame buffer, a graphics buffer, graphics memory, or system memory (e.g., GPU 902 may store indication 964 in memory 906).

[0099] In various configurations, a method or apparatus for display processing is provided. The apparatus can be a GPU (or other graphics processor), a DPU (or other display processor), a CPU (or other central processor), a DPU driver, a DDIC, an apparatus for display processing, and / or some other processor that can perform display processing. In aspects, the apparatus can be a processing unit 120 within a device 104, or can be some other hardware within the device 104 or another device. The apparatus (e.g., the processing unit 120) can include means for obtaining a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value for the at least one first channel and a second value for the second channel, wherein each pixel in a subset of pixels in the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels. The apparatus (e.g., the processing unit 120) can also include means for configuring the second value of each pixel in the subset of pixels based on the set of pixels. The apparatus (e.g., the processing unit 120) can also include means for down-sampling the second value of the second channel of each pixel in the subset of pixels. The apparatus (e.g., the processing unit 120) can also include means for performing a sub-sampling process on the second value of each pixel in the subset of pixels, wherein the sub-sampling process is associated with a reduced sampling rate in a horizontal direction and a vertical direction. The apparatus (e.g., the processing unit 120) can also include means for adjusting the reduced sampling rate in the horizontal direction and the vertical direction so as to match a bit alignment of the set of pixels. The apparatus (e.g., the processing unit 120) can also include means for outputting a second indication of an image comprising the configured second value of each pixel in the subset of pixels.

[0100] The subject matter described herein can be implemented to realize one or more benefits or advantages. For example, the described data processing techniques can be used by a GPU, a graphics processor, a DPU, a display processor, a CPU, a central processor, a DPU driver, or some other processor that can perform image processing to implement the alpha blending techniques described herein. This can also be implemented at a low cost compared to other image processing techniques. Moreover, the data processing techniques herein can improve or speed up data processing or execution. Furthermore, the data processing techniques herein can improve resource or data utilization and / or resource efficiency. Additionally, aspects of the disclosure can utilize alpha blending techniques in order to improve memory bandwidth efficiency and / or increase processing speed at a GPU, a DPU, and / or a CPU.

[0101] It should be understood that the specific order or hierarchy of the boxes in the disclosed process / flowcharts is merely an example of the exemplary method. It should be understood that the specific order or hierarchy of the boxes in the process / flowcharts may be rearranged based on design preferences. Furthermore, some boxes may be combined or omitted. The appended method claims present the elements of various boxes in a sample order, but this does not imply limitation to the given specific order or hierarchy.

[0102] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein references to elements in the singular form, unless specifically stated otherwise, are not intended to mean “one and only one,” but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0103] Unless otherwise specified, the term "some" refers to one or more, and unless otherwise specified in the context, the term "or" may be interpreted as "and / or". Combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. The various aspects described throughout this disclosure are all structural and functional equivalents known now or hereafter to those skilled in the art, and are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly recited in the claims. Terms such as “module,” “mechanism,” “element,” and “device” cannot replace the word “component.” Therefore, no claim element will be interpreted as a functional component unless the element is explicitly stated using the phrase “component for…”.

[0104] In one or more examples, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. Though use of the term "processing unit" is used throughout this disclosure, such processing units can be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media can include computer data storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally can correspond to (1) tangible computer- readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media can be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other storage medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Computer program products can include computer-readable media.

[0105] According to the present disclosure, the term "or" can be understood to be "and / or" when used in this document in the absence of further qualification. Additionally, although the use of the phrases "one or more" or "at least one" can have been used herein in relation to some features but not others, features for which such language has not been used can be understood to have such implied meaning in the absence of further qualification.

[0106] In one or more examples, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. Though use of the term "processing unit" is used throughout this disclosure, such processing units can be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media can include computer data storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally can correspond to (1) tangible computer- readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media can be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other storage medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Computer program products can include computer-readable media.

[0107] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term "processor," as used herein can refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, the techniques could be fully implemented in one or more circuits or logic elements.

[0108] The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described herein to emphasize potential functional aspects of the disclosed technology, and do not necessarily imply that those components, modules, or units must be realized by separate hardware or software components. Rather, various

[0109] The following aspects are merely exemplary and can be combined with other aspects or teachings described herein without limitation.

[0110] Aspect 1 is an apparatus for image processing, the apparatus comprising at least one memory; and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels of the set of pixels comprises a different at least one first value from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises an equal second value from other pixels in the subset of pixels; configure the second value of each pixel in the subset of pixels based on the set of pixels; and output a second indication of the image comprising the configured second value of each pixel in the subset of pixels.

[0111] Aspect 2 is the apparatus of Aspect 1, wherein to configure the second value for each pixel in the subset of pixels, the at least one processor is, individually or in any combination, configured to downsample the second value for the second channel of each pixel in the subset of pixels.

[0112] Aspect 3 is the apparatus of Aspect 2, wherein to downsample the second value for each pixel in the subset of pixels, the at least one processor is, individually or in any combination, configured to compute a mean of the second value for each pixel in the subset of pixels; and downsample the mean of the second value for each pixel in the subset of pixels.

[0113] Aspect 4 is the apparatus of any of Aspects 1-3, wherein the at least one first value for each pixel in the subset of pixels is associated with a full-sampling process, and wherein the second value for each pixel in the subset of pixels is associated with a sub-sampling process.

[0114] Aspect 5 is the apparatus of Aspect 4, wherein to configure the second value for each pixel in the subset of pixels, the at least one processor is, individually or in any combination, configured to perform the sub-sampling process on the second value for each pixel in the subset of pixels, wherein the sub-sampling process is associated with a reduced sampling rate in a horizontal direction and a vertical direction.

[0115] Aspect 6 is the apparatus of Aspect 5, wherein to perform the sub-sampling process on the second value for each pixel in the subset of pixels, the at least one processor is, individually or in any combination, configured to adjust the reduced sampling rate in the horizontal direction and the vertical direction so as to match a bit alignment of the set of pixels.

[0116] Aspect 7 is the apparatus of any of Aspects 5-6, wherein the reduced sampling rate is at least one of: a 0.5 rate in the horizontal direction and the 0.5 rate in the vertical direction, the 0.5 rate in the horizontal direction and a full rate in the vertical direction, or a 0.25 rate in the horizontal direction and the 0.25 rate in the vertical direction.

[0117] Aspect 8 is the apparatus of any of Aspects 1-7, wherein the color format is a red (R) green (G) blue (B) alpha (A) (RGBA) color format, wherein the at least one first channel comprises an R channel, a G channel, and a B channel, wherein the second channel comprises an alpha (A) channel, wherein the at least one first value comprises an R value, a G value, and a B value, and wherein the second value comprises an alpha (A) value.

[0118] Aspect 9 is the apparatus of Aspect 8, wherein the RGBA color format is an RGBA1010102 format.

[0119] Aspect 10 is the apparatus of any of Aspects 1-9, wherein a total number of bits of the second values of the subset of pixels is equally divided among each pixel in the subset of pixels.

[0120] Aspect 11 is the apparatus of Aspect 10, wherein the subset of pixels comprises 4 pixels, wherein the total number of bits of the second values of the subset of pixels is equal to 8 bits, and wherein each pixel in the subset of pixels comprises 2 bits.

[0121] Aspect 12 is the apparatus of any of Aspects 1-11, wherein a number of bits of the at least one first value of each pixel in the subset of pixels is equal to a number of bits of the at least one first value of other pixels in the subset of pixels.

[0122] Aspect 13 is the apparatus of Aspect 12, wherein the number of bits of the at least one first value of each pixel in the subset of pixels is equal to 10 bits.

[0123] Aspect 14 is the apparatus of any of Aspects 1-13, wherein to output the second indication of the image comprising the configured second values of each pixel in the subset of pixels, the at least one processor, individually or in any combination, is configured to: transmit the second indication of the image comprising the configured second values of each pixel in the subset of pixels.

[0124] Aspect 15 is the apparatus of Aspect 14, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein to transmit the second indication of the image comprising the configured second values of each pixel in the subset of pixels, the at least one processor, individually or in any combination, is configured to: transmit, via at least one of the antenna or the transceiver, the second indication of the image comprising the configured second values of each pixel in the subset of pixels to at least one of: a frame composer, a graphics processing unit (GPU) component, a display processing unit (DPU), or a display.

[0125] Aspect 16 is the apparatus of any of Aspects 1-15, wherein to output the second indication of the image comprising the configured second values of each pixel in the subset of pixels, the at least one processor, individually or in any combination, is configured to: store the second indication of the image comprising the configured second values of each pixel in the subset of pixels.

[0126] Aspect 17 is the apparatus of Aspect 16, wherein to store the second indication of the image including the configured second value for each pixel in the subset of pixels, the at least one processor, individually or in any combination, is configured to store the second indication of the image including the configured second value for each pixel in the subset of pixels in at least one of: a frame buffer, a graphics buffer, a graphics memory, or a system memory.

[0127] Aspect 18 is a method of image processing to implement any of Aspects 1-17.

[0128] Aspect 19 is an apparatus for image processing, the apparatus comprising means for implementing any of Aspects 1-17.

[0129] Aspect 20 is a computer-readable medium (e.g., a non-transitory computer- readable medium) storing computer executable code, when executed by at least one processor, cause the at least one processor to implement any of Aspects 1-17.

Claims

1. An apparatus for image processing, the apparatus comprising: At least one memory; and At least one processor, coupled to the at least one memory, and configured individually or in any combination, based at least in part on information stored in the at least one memory, to: Obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels comprises the at least one first value that is different from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises the second value that is equal to other pixels in the subset of pixels; Configure the second value for each pixel in the pixel subset based on the pixel set; and Output a second indication of the image, which includes the configured second value for each pixel in the subset of pixels.

2. The apparatus of claim 1, wherein, in order to configure the second value for each pixel in the subset of pixels, the at least one processor is configured individually or in any combination as follows: The second value of the second channel of each pixel in the pixel subset is downsampled.

3. The apparatus of claim 2, wherein, in order to downsample the second value of each pixel in the subset of pixels, the at least one processor is configured individually or in any combination to: Calculate the average of the second value for each pixel in the pixel subset; and The average value of the second value for each pixel in the pixel subset is downsampled.

4. The apparatus of claim 1, wherein the at least one first value of each pixel in the pixel subset is associated with a full sampling process, and wherein the second value of each pixel in the pixel subset is associated with a subsampling process.

5. The apparatus of claim 4, wherein, in order to configure the second value of each pixel in the subset of pixels, the at least one processor is configured individually or in any combination as follows: The subsampling process is performed on the second value of each pixel in the subset of pixels, wherein the subsampling process is associated with a reduced sampling rate in the horizontal and vertical directions.

6. The apparatus of claim 5, wherein, in order to perform the subsampling process on the second value of each pixel in the subset of pixels, the at least one processor is configured individually or in any combination to: The reduced sampling rate in the horizontal and vertical directions is adjusted to match the bit alignment of the pixel set.

7. The apparatus of claim 5, wherein the reduced sampling rate is at least one of: a 0.5 rate in the horizontal direction and the 0.5 rate in the vertical direction, the 0.5 rate in the horizontal direction and the full rate in the vertical direction, or a 0.25 rate in the horizontal direction and the 0.25 rate in the vertical direction.

8. The apparatus of claim 1, wherein the color format is a red (R) green (G) blue (B) α (A) (RGBA) color format, wherein the at least one first channel includes an R channel, a G channel and a B channel, wherein the second channel includes an α (A) channel, wherein the at least one first value includes an R value, a G value and a B value, and wherein the second value includes an α (A) value.

9. The apparatus of claim 8, wherein the RGBA color format is RGBA1010102 format.

10. The apparatus of claim 1, wherein the total number of bits of the second value of the pixel subset is equally divided among each pixel in the pixel subset.

11. The apparatus of claim 10, wherein the subset of pixels comprises 4 pixels, wherein the total number of bits of the second value of the subset of pixels is equal to 8 bits, and wherein each pixel in the subset of pixels comprises 2 bits.

12. The apparatus of claim 1, wherein the number of bits of the at least one first value of each pixel in the pixel subset is equal to the number of bits of the at least one first value of the other pixels in the pixel subset.

13. The apparatus of claim 12, wherein the number of bits of the at least one first value of each pixel in the pixel subset is equal to 10 bits.

14. The apparatus of claim 1, wherein, in order to output the second indication of the image comprising the configured second value for each pixel in the subset of pixels, the at least one processor is configured individually or in any combination to: Send the second instruction to the image, which includes the configured second value for each pixel in the subset of pixels.

15. The apparatus of claim 14, further comprising at least one of an antenna or transceiver coupled to the at least one processor, wherein, in order to transmit the second indication of the image comprising the configured second value of each pixel in the subset of pixels, the at least one processor is configured individually or in any combination to: The second indication of the image, which includes the configured second value of each pixel in the subset of pixels, is transmitted via at least one of the antenna or the transceiver to at least one of the following: a frame synthesizer, a graphics processing unit (GPU) component, a display processing unit (DPU), or a display.

16. The apparatus of claim 1, wherein, in order to output the second indication of the image comprising the configured second value for each pixel in the subset of pixels, the at least one processor is configured individually or in any combination to: The second indication of the image, which stores the configured second value for each pixel in the subset of pixels.

17. The apparatus of claim 16, wherein, in order to store the second indication of the image comprising the configured second value of each pixel in the subset of pixels, the at least one processor is configured individually or in any combination to: The second indication of the image, which includes the configured second value for each pixel in the subset of pixels, is stored in at least one of the following: a frame buffer, a graphics buffer, graphics memory, or system memory.

18. A method for image processing, the method comprising: Obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels comprises the at least one first value that is different from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises the second value that is equal to other pixels in the subset of pixels; Configure the second value for each pixel in the pixel subset based on the pixel set; and Output a second indication of the image, which includes the configured second value for each pixel in the subset of pixels.

19. The method of claim 18, wherein configuring the second value for each pixel in the subset of pixels comprises: The second value of the second channel of each pixel in the pixel subset is downsampled.

20. The method of claim 19, wherein downsampling the second value for each pixel in the subset of pixels comprises: Calculate the average of the second value for each pixel in the pixel subset; as well as The average value of the second value for each pixel in the pixel subset is downsampled.

21. The method of claim 18, wherein the at least one first value of each pixel in the pixel subset is associated with a full sampling process, and wherein the second value of each pixel in the pixel subset is associated with a subsampling process.

22. The method of claim 21, wherein configuring the second value for each pixel in the subset of pixels comprises: The subsampling process is performed on the second value of each pixel in the subset of pixels, wherein the subsampling process is associated with a reduced sampling rate in the horizontal and vertical directions.

23. The method of claim 22, wherein performing the subsampling process on the second value of each pixel in the subset of pixels comprises: The reduced sampling rate in the horizontal and vertical directions is adjusted to match the bit alignment of the pixel set.

24. The method of claim 22, wherein the reduced sampling rate is at least one of: a 0.5 rate in the horizontal direction and the 0.5 rate in the vertical direction, the 0.5 rate in the horizontal direction and the full rate in the vertical direction, or a 0.25 rate in the horizontal direction and the 0.25 rate in the vertical direction.

25. The method of claim 18, wherein the color format is a red (R) green (G) blue (B) alpha (A) (RGBA) color format, wherein the at least one first channel includes an R channel, a G channel and a B channel, wherein the second channel includes an alpha (A) channel, wherein the at least one first value includes an R value, a G value and a B value, wherein the second value includes an alpha (A) value, and wherein the RGBA color format is an RGBA1010102 format.

26. The method of claim 18, wherein the total number of bits of the second value of the pixel subset is equally divided among each pixel in the pixel subset, wherein the pixel subset comprises 4 pixels, wherein the total number of bits of the second value of the pixel subset is equal to 8 bits, and wherein each pixel in the pixel subset comprises 2 bits; and The number of bits of the at least one first value of each pixel in the pixel subset is equal to the number of bits of the at least one first value of the other pixels in the pixel subset, and the number of bits of the at least one first value of each pixel in the pixel subset is equal to 10 bits.

27. The method of claim 18, wherein outputting the second indication of the image comprising the configured second value for each pixel in the subset of pixels comprises: The second instruction of the image, which includes the configured second value of each pixel in the pixel subset, is sent to at least one of the following: a frame synthesizer, a graphics processing unit (GPU) component, a display processing unit (DPU), or a display.

28. The method of claim 18, wherein outputting the second indication of the image comprising the configured second value for each pixel in the subset of pixels comprises: The second indication of the image, which includes the configured second value for each pixel in the subset of pixels, is stored in at least one of the following: a frame buffer, a graphics buffer, graphics memory, or system memory.

29. An apparatus for image processing, the apparatus comprising: A component for obtaining a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels comprises the at least one first value that is different from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises the second value that is equal to other pixels in the subset of pixels; A component for configuring the second value of each pixel in the subset of pixels based on the set of pixels; and A component for outputting a second indication of the image for each pixel in the subset of pixels, configured with a second value.

30. A computer-readable medium storing computer-executable code for image processing, said code, when executed by at least one processor, causing said at least one processor to: Obtain a first indication of an image comprising a set of pixels, wherein the set of pixels is associated with a color format comprising a set of color channels, wherein the set of color channels comprises at least one first channel and a second channel, wherein each pixel in the set of pixels comprises at least one first value of the at least one first channel and a second value of the second channel, wherein each pixel in a subset of pixels comprises the at least one first value that is different from other pixels in the subset of pixels, and wherein each pixel in the subset of pixels comprises the second value that is equal to other pixels in the subset of pixels; Configure the second value for each pixel in the pixel subset based on the pixel set; and Output a second indication of the image, which includes the configured second value for each pixel in the subset of pixels.

Images