Display panel, pixel circuit and driving method thereof

Abstract

The invention discloses a display panel, a pixel circuit (PC) and a driving method thereof. The pixel circuit (PC) comprises a driving transistor (T3), a first reset circuit (10), a write-in circuit (40), a compensation circuit (20), an isolation circuit (60), an energy storage circuit (30), a first light-emitting control circuit (70) and a second light-emitting control circuit (50). A first pole of the driving transistor (T3) receives a first power supply signal (ELVSS), a second pole of the driving transistor (T3) is connected with the light-emitting device (LD) through the first light-emitting control circuit (70), and the light-emitting device (LD) receives a second power supply signal (ELVDD); the voltage of the first power supply signal (ELVSS) is smaller than the voltage of the second power supply signal (ELVDD); the first reset circuit (10) is connected with the grid electrode of the driving transistor (T3); the write-in circuit (40) and the first end of the energy storage circuit (30) are connected to a write-in node (N2), the second end of the energy storage circuit (30) and the grid electrode of the driving transistor (T3) are connected to a control node (N1), and the write-in circuit (40) transmits a data signal (Data) to the write-in node (N2); the compensation circuit (20) is connected with the second pole of the driving transistor (T3) and the control node (N1); the isolation circuit (60) is connected with the third end of the energy storage circuit (30) and transmits an isolation signal; the second light-emitting control circuit (50) and the first end of the tank circuit (30) are connected to a write node (N2) and transmit a first power supply signal (ELVSS).

Description

Display panel, pixel circuit and driving method thereof TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel, a pixel circuit and a driving method of the pixel circuit. BACKGROUND

[0002] OLED (Organic Light Emitting Diode) display panel has the advantages of self-luminescence, wide color gamut, high contrast, high response, etc., and has wide application prospects. However, the uniformity of the luminous intensity of the current display panel still needs to be improved.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The present disclosure provides a display panel, a pixel circuit and a driving method of the pixel circuit.

[0006] According to one aspect of the present disclosure, a pixel circuit is provided, comprising a driving transistor, a first reset circuit, a write circuit, a compensation circuit, an isolation circuit, an energy storage circuit, a first light-emitting control circuit and a second light-emitting control circuit.

[0007] The first electrode of the driving transistor is configured to receive a first power supply signal, the second electrode is connected to a first electrode of a light-emitting device through the first light-emitting control circuit, and a second electrode of the light-emitting device is configured to receive a second power supply signal; the voltage of the first power supply signal is less than the voltage of the second power supply signal; the driving transistor is a metal oxide transistor;

[0008] The first reset circuit is connected to the gate of the driving transistor and configured to transmit a first reset signal capable of turning on the driving transistor to the gate of the driving transistor;

[0009] The write circuit is connected to a write node at a first end of the energy storage circuit and connected to a control node at a second end of the energy storage circuit and the gate of the driving transistor, and the write circuit is configured to transmit a data signal to the write node;

[0010] The compensation circuit is connected to the second electrode of the driving transistor and the control node;

[0011] The isolation circuit is connected to a third end of the energy storage circuit and configured to transmit an isolation signal to the energy storage circuit;

[0012] The second light emitting control circuit is connected to the first terminal and the write node, and is configured to transmit the first power signal to the write node.

[0013] The energy storage circuit is configured to store voltages of the write node and the control node when the isolation signal is received at the third terminal, and to couple the voltage of the write node to the control node when the isolation signal is not received at the third terminal.

[0014] In an exemplary embodiment of the present disclosure, the energy storage circuit includes a first capacitor and a second capacitor connected in series between the write node and the control node, and the first capacitor is connected to the control node and the second capacitor is connected to the write node, and the first capacitor and the second capacitor are connected to the third terminal.

[0015] In an exemplary embodiment of the present disclosure, the first light emitting control circuit includes a first light emitting control transistor, a first electrode of the first light emitting control transistor is connected to the second electrode of the drive transistor, and a second electrode of the first light emitting control transistor is connected to the first electrode of the light emitting device.

[0016] The second light emitting control circuit includes a second light emitting control transistor, a first electrode of the second light emitting control transistor is connected to the first electrode of the drive transistor, and a second electrode of the second light emitting control transistor is connected to the write node.

[0017] In an exemplary embodiment of the present disclosure, the isolation circuit includes an isolation transistor, a first electrode of the isolation transistor is configured to receive the isolation signal, and a second electrode of the isolation transistor is connected to the third terminal.

[0018] In an exemplary embodiment of the present disclosure, the first electrode of the isolation transistor is connected to the first electrode of the drive transistor, and the isolation signal is the first power signal.

[0019] In an exemplary embodiment of the present disclosure, the write circuit includes a write transistor, a first electrode of the write transistor is configured to receive the data signal, and a second electrode of the write transistor is connected to the write node.

[0020] The compensation circuit includes a compensation transistor, a first electrode of the compensation transistor is connected to the second electrode of the drive transistor, and a second electrode of the compensation transistor is connected to the control node.

[0021] In an exemplary embodiment of the present disclosure, the first reset circuit includes a first reset transistor, a first electrode of the first reset transistor is configured to receive the first reset signal, and a second electrode of the first reset transistor is connected to the first electrode of the light emitting device and the first light emitting control circuit.

[0022] In an example embodiment of the present disclosure, the first reset circuit includes a first reset sub-circuit and a second reset sub-circuit; the first reset sub-circuit is connected with the control node and is configured to transmit the first reset signal to the control node; the second reset sub-circuit is connected with the first electrode of the light emitting device and the first light emitting control circuit and is configured to transmit a second reset signal to the first electrode.

[0023] In an example embodiment of the present disclosure, the first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor; a first electrode of the first reset transistor is configured to receive the first reset signal, and a second electrode of the first reset transistor is connected with the control node; a first electrode of the second reset transistor is configured to receive the second reset signal, and a second electrode of the second reset transistor is connected with the first electrode of the light emitting device and the first light emitting control circuit.

[0024] In an example embodiment of the present disclosure, the pixel circuit further includes a second reset circuit, the second reset circuit is connected with the first electrode of the driving transistor and is configured to transmit a third reset signal to the first electrode of the driving transistor.

[0025] In an example embodiment of the present disclosure, the second reset circuit includes a third reset transistor, a first electrode of the third reset transistor is configured to receive the third reset signal, and a second electrode of the third reset transistor is connected with the first electrode of the driving transistor.

[0026] In an example embodiment of the present disclosure, the pixel circuit further includes a third light emitting control circuit, the second electrode of the driving transistor is connected with the first light emitting control circuit through the third light emitting control circuit; or the third light emitting control circuit is connected with the first electrode of the driving transistor and is configured to transmit the first power signal to the driving transistor.

[0027] In an example embodiment of the present disclosure, the third light emitting control circuit includes a third light emitting control transistor, a first electrode of the third light emitting control transistor is connected with the second electrode of the driving transistor, and a second electrode of the third light emitting control transistor is connected with the first light emitting control circuit; or a first electrode of the third light emitting control transistor is configured to receive the first power signal, and a second electrode of the third light emitting control transistor is connected with the first electrode of the driving transistor.

[0028] In an example embodiment of the present disclosure, the first light emitting control circuit and the second light emitting control circuit are turned on and turned off in response to the same control signal.

[0029] In an exemplary embodiment of the present disclosure, the isolation circuit comprises a first isolation sub-circuit and a second isolation sub-circuit, both of which are connected to the third terminal, and the first isolation sub-circuit is configured to transmit a first isolation signal to the third terminal, and the second isolation sub-circuit is configured to transmit a second isolation signal to the third terminal.

[0030] The first reset sub-circuit and the first isolation sub-circuit are turned on and turned off in response to the same control signal; and the compensation circuit and the second isolation sub-circuit are turned on and turned off in response to the same control signal.

[0031] In an exemplary embodiment of the present disclosure, one of the first reset sub-circuit and the second reset sub-circuit is turned on and turned off in response to the same control signal as the write circuit.

[0032] According to an aspect of the present disclosure, a driving method of a pixel circuit is provided, the pixel circuit comprising a driving transistor, a first reset sub-circuit, a second reset sub-circuit, a write circuit, a compensation circuit, an isolation circuit, an energy storage circuit, a first light-emitting control circuit and a second light-emitting control circuit; a first electrode of the driving transistor is configured to receive a first power signal, a second electrode of the driving transistor is connected to a first electrode of a light-emitting device through the first light-emitting control circuit, a second electrode of the light-emitting device is configured to receive a second power signal; the first reset sub-circuit is connected to a control node; the second reset sub-circuit is connected to the first electrode of the light-emitting device and the first light-emitting control circuit; the write circuit is connected to a write node at a first terminal of the energy storage circuit, and a second terminal of the energy storage circuit is connected to a gate of the driving transistor at the control node; the compensation circuit is connected to the second electrode of the driving transistor and the control node; the isolation circuit is connected to a third terminal of the energy storage circuit; the second light-emitting control circuit is connected to the write node at the first terminal; the driving transistor is an oxide transistor; a voltage of the first power signal is less than a voltage of the second power signal.

[0033] The driving method comprises:

[0034] In the reset phase, the first reset sub-circuit is turned on to transmit a first reset signal to the control node, so as to turn on the driving transistor; the second reset sub-circuit is turned on to transmit a second reset signal to the first electrode of the light-emitting device; and the isolation circuit is turned on to transmit an isolation signal to the third terminal.

[0035] In the compensation phase, the compensation circuit is turned on to write a threshold voltage of the driving transistor to the control node of the driving transistor and store the threshold voltage to the energy storage circuit; the second reset sub-circuit is turned on to transmit a second reset signal to the first electrode of the light-emitting device; and the isolation circuit is turned on to transmit an isolation signal to the third terminal.

[0036] In the writing stage, the writing circuit is turned on, a data signal is transmitted to the writing node, and is stored in the energy storage circuit; the second reset sub-circuit is turned on, a second reset signal is transmitted to the first electrode of the light emitting device; the isolation circuit is turned on, an isolation signal is transmitted to the third terminal;

[0037] In the light emitting stage, the isolation circuit is turned off; the first light emitting control circuit and the second light emitting control circuit are turned on, the first power signal is transmitted to the writing node, and the data signal, the first power signal and the isolation signal are coupled to the control node through the energy storage circuit to control the light emitting device to emit light.

[0038] According to one aspect of the present disclosure, a driving method of a pixel circuit is provided, the pixel circuit comprising a driving transistor, a first reset circuit, a writing circuit, a compensation circuit, an isolation circuit, an energy storage circuit, a first light emitting control circuit and a second light emitting control circuit; a first electrode of the driving transistor is used for receiving a first power signal, a second electrode of the driving transistor is connected with a first electrode of a light emitting device through the first light emitting control circuit, a second electrode of the light emitting device is used for receiving a second power signal; the first reset circuit is connected with a gate electrode of the driving transistor; the writing circuit is connected with a first terminal of the energy storage circuit at a writing node, a second terminal of the energy storage circuit is connected with the gate electrode of the driving transistor at a control node; the compensation circuit connects the second electrode of the driving transistor and the control node; the isolation circuit is connected with a third terminal of the energy storage circuit; the second light emitting control circuit is connected with the first terminal at the writing node; the driving transistor is an oxide transistor; a voltage of the first power signal is less than a voltage of the second power signal;

[0039] The driving method comprises:

[0040] In the reset stage, the first reset circuit, the compensation circuit and the first light emitting control circuit are turned on, a first reset signal is transmitted to the control node to turn on the driving transistor; the isolation circuit is turned on, an isolation signal is transmitted to the third terminal;

[0041] In the compensation stage, the first light emitting control circuit is turned off, the first reset circuit is turned on, the first reset signal is transmitted to the first electrode of the light emitting device; the isolation circuit is turned on, the isolation signal is transmitted to the third terminal; the compensation circuit is turned on, the threshold voltage of the driving transistor is written to the control node of the driving transistor, and is stored in the energy storage circuit;

[0042] In the writing stage, the writing circuit is turned on, a data signal is transmitted to the writing node and stored in the energy storage circuit; the first reset circuit is turned on, a first reset signal is transmitted to the first electrode of the light emitting device; the isolation circuit is turned on, an isolation signal is transmitted to the third terminal;

[0043] In the light emitting stage, the isolation circuit is turned off; the first light emitting control circuit and the second light emitting control circuit are turned on, the first power signal is transmitted to the writing node, and the data signal, the first power signal and the isolation signal are coupled to the control node through the energy storage circuit, so as to control the light emitting device to emit light.

[0044] According to an aspect of the present disclosure, there is provided a display panel comprising the pixel circuit as described in any one of the above.

[0045] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0046] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0047] Fig. 1 is a top view of an embodiment of a display panel of the present disclosure.

[0048] Fig. 2 is a cross-sectional view of an embodiment of a display panel of the present disclosure.

[0049] Fig. 3 is a schematic diagram of a pixel circuit of a first type of embodiment.

[0050] Fig. 4 is a timing diagram of the first type of embodiment.

[0051] Figs. 5-8 are schematic diagrams of the stages in Fig. 4.

[0052] Fig. 9 is a schematic diagram of a pixel circuit of the first type of embodiment.

[0053] Fig. 10 is a schematic diagram of another pixel circuit of the first type of embodiment.

[0054] Fig. 11 is a timing diagram of the embodiment in Fig. 10.

[0055] Fig. 12 is a schematic diagram of yet another pixel circuit of the first type of embodiment.

[0056] Fig. 13 is a timing diagram of the embodiment in Fig. 12.

[0057] FIG. 14 is a schematic diagram of a first pixel circuit of a second type of embodiment.

[0058] FIG. 15 is a schematic diagram of a second pixel circuit of the second type of embodiment.

[0059] FIG. 16 is a timing chart of the embodiment of FIG. 13.

[0060] FIG. 17 is a schematic diagram of a third pixel circuit of the second type of embodiment. DETAILED DESCRIPTION

[0061] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and thus a detailed description of them will not be repeated. In addition, the drawings are to be considered in the illustrative mode, and are not necessarily to scale.

[0062] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" of something is present; the terms "comprising" and "having" are used to mean "including" and mean the inclusion of something not limited to the elements listed; the term "first", "second", and "third" are used only as labels, and do not mean a limitation as to the number.

[0063] The row direction and the column direction herein are two intersecting directions, which can be perpendicular to each other or not. In the drawings of the present disclosure, the row direction is the horizontal direction and the column direction is the vertical direction, but this is not limited thereto. It can be understood by those skilled in the art that if the display panel is rotated, the actual orientation of the row direction and the column direction can change.

[0064] nTmC herein means that a circuit (for example, a pixel circuit, a gate drive circuit, etc.) includes n transistors (denoted by the letter "T") and m capacitors (denoted by the letter "C").

[0065] The transistor herein includes a gate, a first pole, and a second pole, and the conduction and the non-conduction between the first pole and the second pole can be realized by controlling the voltage of the gate; the first pole can be a source, and the second pole can be a drain; of course, the first pole can also be a drain, and the second pole can also be a source. Specifically, if the signal is input from the first pole, the first pole is the source, and the second pole is the drain; if the signal is input from the second pole, the second pole is the source, and the first pole is the drain; that is, the source and the drain can be exchanged according to the change of the input signal.

[0066] For P-type transistor, when the gate receives high level, the first pole and the second pole are off; when the gate receives low level, the first pole and the second pole are on. For N-type transistor, when the gate receives high level, the first pole and the second pole are on; when the gate receives low level, the first pole and the second pole are off.

[0067] As shown in FIG. 1, the display panel provided by the embodiment of the present disclosure can include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA can be a continuous annular area surrounding the display area AA, or can be discontinuous areas surrounding the display area AA.

[0068] As shown in FIG. 2, the display panel can include a driving backplane BP and a plurality of light emitting devices LD located on one side of the driving backplane BP. The light emitting devices LD are distributed along the row direction and the column direction. The light emitting devices LD can be driven to emit light by the driving circuit in the driving backplane BP, so as to display an image.

[0069] The light emitting devices LD can be located in the display area AA. The light emitting devices LD can be OLEDs (organic light emitting diodes) using organic light emitting materials, LEDs (light emitting diodes) using inorganic light emitting materials, such as Micro LED (micron light emitting diode) and Mini LED (sub-millimeter light emitting diode), QLED (quantum dot diode), and the like. The specific structure of the display panel is not specially limited here, as long as it can display an image.

[0070] As shown in FIG. 2, taking OLED as an example, the light emitting device can include a first electrode ANO, a light emitting layer EL, and a second electrode CAT stacked in sequence away from the driving backplane. By applying an electrical signal to the first electrode ANO and the second electrode CAT, the light emitting layer EL can be excited to emit light. The specific principle is not described in detail here. Meanwhile, in order to define the range of the light emitting device LD, a pixel definition layer PDL can be provided on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL can have pixel openings exposing each first electrode ANO. Thus, the range of the light emitting device LD can be defined through each pixel opening.

[0071] As shown in FIG. 1, the driving circuit can include pixel circuits PC located in the display area AA and peripheral circuits WP located in the peripheral area WA, the pixel circuits PC can be distributed along the row direction and the column direction, one pixel circuit PC can be connected with the first electrode ANO of one light emitting device LD, and one row of pixel circuits PC can be connected with the first electrode ANO of each of the light emitting devices LD in one row. Of course, the same pixel circuit PC can be connected with the first electrodes ANO of multiple light emitting devices LD. The pixel circuit PC can include multiple transistors and can also include a capacitor, which can be a 2T1C, 3T1C, 7T1C, or the like structure.

[0072] The peripheral circuit WP can be connected with the light emitting device LD through the pixel circuit PC, apply a power signal to the first electrode ANO of the light emitting device LD, on the other hand, the peripheral circuit WP can also be connected with the second electrode CAT of the light emitting device LD and apply another power signal to the second electrode CAT, and the current through the light emitting device LD can be controlled through the pixel circuit PC, so as to control the brightness of the light emitting device LD.

[0073] The peripheral circuit WP can include a gate driving circuit and a light emitting control circuit, which are used for scanning part of the transistors in the pixel circuit PC, i.e., outputting a control signal to the gate of the transistor to control the on and off of the transistor. The signals output by the above-mentioned gate driving circuit and light emitting driving circuit can realize the on and off of the transistor in the pixel circuit PC, i.e., realize the scanning of the pixel circuit PC, so as to control the light emitting of the light emitting device LD.

[0074] The gate driving circuit and the light emitting control circuit can each include multiple cascaded shift registers, i.e., the output end of the nth shift register is connected with the gate of the transistor of at least one row of pixel circuits PC and is also connected with the input end of the (n+1)th shift register, so that the output signal of the upper shift register is used as the input signal of the lower shift register. Any shift register can include multiple transistors and a capacitor, which can be a 7T2C, 8T2C, or the like structure, which is not specially limited here. In addition, the structures of the shift registers of the gate driving circuit and the light emitting control circuit can be different.

[0075] As shown in FIG. 1, the output signal of the output end of the shift register is the above-mentioned control signal, and the gate of part of the transistors of one row of pixel circuits PC can be connected with the output end of one shift register; of course, one shift register can be connected with multiple rows of pixel circuits PC and simultaneously scan multiple rows of pixel circuits PC, but the roles of the output signal of the same shift register in different rows of pixel circuits PC can be different.

[0076] In addition, as shown in FIG. 1, the peripheral area WA of the display panel can be provided with a source driving circuit DP for transmitting a data signal to the pixel circuit PC, which can be a chip or a circuit integrated on the display panel.

[0077] The pixel circuit of the present disclosure is exemplarily described as follows:

[0078] As shown in FIG. 3 and FIG. 14, the pixel circuit comprises a driving transistor T3, a first reset circuit 10, a write-in circuit 40, a compensation circuit 20, an isolation circuit 60, an energy storage circuit 30, a first light-emitting control circuit 70 and a second light-emitting control circuit 50, wherein:

[0079] The first electrode of the driving transistor T3 is configured to receive a first power signal ELVSS, the second electrode is connected with the first electrode of the light-emitting device LD through the first light-emitting control circuit 70, and the second electrode of the light-emitting device LD is configured to receive a second power signal ELVDD; both the first power signal ELVSS and the second power signal ELVDD are constant voltage signals, the voltage of the first power signal ELVSS is a first power voltage VSS, the voltage of the second power signal ELVDD is a second power voltage VDD, and the first power voltage VSS is less than the second power voltage VDD. The first light-emitting control circuit 70 can be turned on and turned off in response to a light-emitting control signal.

[0080] The driving transistor T3 is an oxide transistor and an N-type transistor, for example, the material of the active part of the driving transistor T3 can be IGZO (Indium Gallium Zinc Oxide), or IZO (Indium Zinc Oxide) and other metal oxides.

[0081] The first reset circuit 10 is connected with the gate of the driving transistor T3 and can transmit a first reset signal Ref1 of the driving transistor T3 to the gate of the driving transistor T3, the first reset signal Ref1 can be a constant voltage signal, and when the first electrode of the driving transistor T3 is the voltage of the first power signal ELVSS, the driving transistor T3 can be turned on, specifically, the voltage of the first reset signal Ref1 is a first reset voltage Vref1, the voltage difference between the first reset voltage Vref1 and the first power voltage VSS is the gate-source voltage difference of the driving transistor T3, and when the gate-source voltage difference is greater than the threshold voltage of the driving transistor T3, the driving transistor T3 is turned on.

[0082] The energy storage circuit 30 has a first end, a second end and a third end, when a constant voltage isolation signal is received at the third end, the energy storage circuit 30 can independently store the voltage of the signals transmitted to the first end and the second end, that is, the voltage jump of one of the first end and the second end will not cause the voltage jump of the other; and when there is no constant voltage signal at the third end, the voltage jump of one of the first end and the second end will cause the voltage jump of the other.

[0083] The write-in circuit 40 is connected to the write-in node N2 at the first end of the energy storage circuit 30, and the second end of the energy storage circuit 30 is connected to the gate of the driving transistor T3 at the control node N1, that is, the write-in circuit 40 is connected to the gate of the driving transistor T3 through the energy storage circuit 30. The write-in circuit 40 can be turned on and turned off in response to a write-in control signal. When the write-in circuit 40 is turned on, a data signal Data can be transmitted to the write-in node N2 through the write-in circuit 40.

[0084] The compensation circuit 20 is connected to the compensation input node N4 at the second electrode of the driving transistor T3, and is connected to the control node N1, that is, the second electrode and the gate of the driving transistor T3 are connected. The compensation circuit 20 can be turned on and turned off in response to a compensation control signal.

[0085] The isolation circuit 60 is connected to the third end of the energy storage circuit 30, and can be turned on and turned off in response to an isolation control signal. When the isolation circuit 60 is turned on, an isolation signal can be transmitted to the write-in node N2 through the isolation circuit 60.

[0086] The second light-emitting control circuit 50 is connected to the write-in node N2, and can be turned on and turned off in response to a light-emitting control signal. When the second light-emitting control circuit 50 is turned on, a first power supply signal ELVSS can be transmitted to the write-in node N2 through the second light-emitting control circuit 50.

[0087] The energy storage circuit 30 can store the voltages of the write-in node N2 and the control node N1 respectively when the third end receives the isolation signal, and can couple the voltage of the write-in node N2 to the control node N1 when the third end does not receive the isolation signal.

[0088] As shown in FIGS. 4-8, the principles and effects of the pixel circuit of the present disclosure will be described below in combination with the driving method of the pixel circuit of the present disclosure:

[0089] As shown in FIG. 5, in the reset phase t1, the first reset signal Ref1 is transmitted to the control node N1 through the first reset circuit 10 to initialize the control node N1, and the voltage difference between the first reset signal Ref1 and the voltage of the first electrode of the driving transistor T3 is greater than the threshold voltage Vth of the driving transistor T3, so that the driving transistor T3 is turned on; the isolation signal is transmitted to the third end of the energy storage circuit 30 through the isolation circuit 60. The first power voltage VSS of the voltage of the first electrode of the driving transistor T3 in the reset phase t1 is taken as an example in the compensation phase t2 to the light-emitting phase t4. In some embodiments, the first reset signal Ref1 and the second power voltage VDD can adopt the same signal, that is, the voltages of the two are the same, of course, they can also be independent signals, as long as the above voltage difference requirement is met.

[0090] As shown in Fig. 6, in the compensation stage t2, the compensation circuit 20 is turned on, the threshold voltage Vth of the driving transistor T3 is written into the control node N1 of the driving transistor T3, and is stored into the second end of the energy storage circuit 30; at the same time, the isolation circuit 60 is maintained to be turned on, the isolation signal is transmitted to the third end, and the voltage jump of the first end of the energy storage circuit 30 is avoided.

[0091] Since the driving transistor T3 is turned on in the reset stage t1, after the compensation circuit 20 is turned on, the first power voltage VSS can be transmitted to the control node N1 through the driving transistor, so that the voltage of the control node N1 gradually increases.

[0092] As shown in Fig. 7, in the writing stage t3, the isolation circuit 60 is maintained to be turned on, the data signal Data is transmitted to the writing node N2 through the writing circuit 40, and is stored into the first end of the energy storage circuit 30; at the same time, when the voltage Vg of the control node N1 increases to the sum of the first power voltage VSS and the threshold voltage Vth of the driving transistor T3, that is, Vg = VSS + Vth, the gate-source voltage difference Vgs of the driving transistor T3 (the voltage difference between the gate and the first electrode of the driving transistor T3) is equal to the threshold voltage Vth, the driving transistor T3 is turned off, and thus the threshold voltage Vth is written into the control node N1; that is, the writing of the data signal Data and the compensation of the threshold voltage Vth are simultaneously performed, so that the writing stage t3 and the compensation stage t2 can be overlapped, for example, the writing stage t3 is located after the beginning of the compensation stage t2 and before the end of the compensation stage t2.

[0093] As shown in Fig. 8, in the light emitting stage t4, the isolation circuit 60 is turned off; the first light emitting control circuit 70 and the second light emitting control circuit 50 are turned on, the first power signal ELVSS is transmitted to the writing node N2, and the data signal Data, the first power signal ELVSS and the isolation signal are coupled to the control node N1 through the energy storage circuit 30, so as to control the light emitting device LD to emit light.

[0094] In the light emitting stage t4, the voltage of the writing node N2 changes from the voltage Vdata of the data signal Data to the voltage VSS of the first power signal ELVSS, since the isolation circuit 60 is turned off, under the coupling of the energy storage circuit 30, the voltage of the control node N1 jumps to VSS + Vth + VSS - Vdata, that is, Vg jumps to VSS + Vth + VSS - Vdata. At this time, the current I of the driving transistor T3 = (μWCox / 2L) × (Vgs - Vth) 2 = (μWCox / 2L) × (VSS - Vdata) 2, μ is the carrier mobility; Cox is the unit area gate capacitance, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3. It can be seen that the pixel circuit of the present disclosure can eliminate the influence of the threshold voltage Vth on the current, can adjust the brightness of the light emitting device LD through the data signal Data, and can avoid the problem of uneven brightness caused by the threshold voltage offset due to process, material, and the like.

[0095] In the pixel circuit of the present disclosure, when the first power supply voltage VSS is less than the second power supply voltage VDD and the driving transistor is an N-type oxide transistor, the light emitting device LD adopts an inverted connection mode, that is, the light emitting device LD is directly connected to the high voltage end (the second electrode, that is, the drain, receiving the high voltage second power supply voltage VDD) of the driving transistor T3, rather than being directly connected to the low voltage end (the first electrode, that is, the source, receiving the low voltage first power supply voltage VSS), which can improve the problem of uneven brightness caused by the voltage drop of the low voltage first power supply signal ELVSS, that is, improve the LRU (Long range uniformity) problem.

[0096] The following describes the parts of the pixel circuit in detail:

[0097] As shown in FIGS. 3 and 14, in some embodiments of the present disclosure, the energy storage circuit 30 can include a first capacitor C1 and a second capacitor C2, both of which have opposite first and second plates; the first plate of the first capacitor C1 is connected to the control node N1, that is, connected to the gate of the driving transistor T3, and the second plate is connected to the first plate of the second capacitor C2 at the isolation node N3, and the second plate of the second capacitor C2 is connected to the write node N2, so that the first capacitor C1 and the second capacitor C2 are connected in series between the write node and the control node N1. The first end of the energy storage circuit 30 is the second plate of the second capacitor C2, the second end of the energy storage circuit 30 is the first plate of the first capacitor C1, and the third end can be the isolation node N3, that is, the first capacitor C1 and the second capacitor C2 are connected to the third end.

[0098] As shown in FIGS. 3 and 12, in some embodiments of the present disclosure, the first light emitting control circuit 70 can include a first light emitting control transistor T7, the first electrode of which is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode of the light emitting device LD, and the gate of the first light emitting control transistor T7 can be turned on and off in response to the light emitting control signal.

[0099] The second light-emitting control circuit 50 includes a second light-emitting control transistor T5, a first electrode of which is connected to the power supply node N5 and the first electrode of the driving transistor T3, a second electrode of which is connected to the write node N2, and a gate of which is turned on and off in response to a light-emitting control signal. The first electrode of the second light-emitting control transistor T5 can also receive the first power supply signal ELVSS, and can transmit the first power supply signal ELVSS to the write node N2 when turned on.

[0100] As shown in FIG. 3 and FIG. 14, in some embodiments of the present disclosure, the isolation circuit 60 can include an isolation transistor T6, a first electrode of which is used to receive an isolation signal, a second electrode of which is connected to the third end (e.g., the isolation node N3) of the energy storage circuit 30, and a gate of which is turned on and off in response to an isolation control signal GI3. The first electrode of the isolation transistor T6 can receive a constant-voltage isolation signal, and can transmit the isolation signal to the isolation node N3 when turned on. When the isolation node N3 receives the isolation signal, the first capacitor C1 and the second capacitor C2 do not affect each other. When the isolation transistor T6 is turned off, the voltage change of one of the write node N2 and the control node N1 will cause the voltage of the other to jump.

[0101] In some embodiments, as shown in FIG. 3, the isolation signal can be the first power supply signal ELVSS. In this case, the first electrode of the isolation transistor T6 can be connected to the first electrode of the driving transistor T3 at the isolation input node N7, which is connected between the power supply node N5 and the first electrode of the driving transistor T3, so as to receive the first power supply signal ELVSS. Alternatively, as shown in FIG. 9, in some embodiments, the first electrode of the isolation transistor T6 can not be connected to the first electrode of the driving transistor T3, but can receive other constant-voltage signals, such as the second power supply signal ELVDD or the first reset signal Ref1, the second reset signal Ref2, etc., which are not particularly limited herein.

[0102] As shown in FIG. 10, in some embodiments of the present disclosure, the isolation circuit 60 can include a first isolation sub-circuit 61 and a second isolation sub-circuit 62, both of which are connected with the isolation node N3, and the first isolation sub-circuit 61 can be turned on and turned off in response to a first isolation control signal GI31, and transmit a first isolation signal to the isolation node N3 when turned on; the second isolation sub-circuit 62 can be turned on and turned off in response to a second isolation control signal GI32, and transmit a second isolation signal to the isolation node N3 when turned on; both the first isolation signal and the second isolation signal are constant voltage signals, for example, the first power signal ELVSS, the second power signal ELVDD, the first reset signal Ref1, the second reset signal Ref2, etc., but the voltages of the two can be different, of course, they can also be the same. For example: the first isolation sub-circuit 61 can include a first isolation transistor T61, and the second isolation sub-circuit 62 can include a second isolation transistor T62; the first electrode of the first isolation transistor T61 is used to receive the first isolation signal, and the second electrode is connected with the isolation node N3; the first electrode of the second isolation transistor T62 is connected with the isolation input node N7, and the second electrode is connected with the isolation node N3. The first isolation signal can be one of the first power signal ELVSS, the second power signal ELVDD, the first reset signal Ref1 and the second reset signal Ref2, and the second isolation signal is the first power signal ELVSS. Of course, in other embodiments, the first electrode of the second isolation transistor T62 can not be connected with the isolation input node N7, but the first power signal ELVSS, the second power signal ELVDD, the first reset signal Ref1, the second reset signal Ref2 and other constant voltage signals can be externally connected.

[0103] As shown in FIG. 3 and FIG. 14, in some embodiments of the present disclosure, the write circuit 40 includes a write transistor T4, the first electrode of the write transistor T4 can receive a data signal Data, the second electrode is connected with the write node N2, and the gate of the write transistor T4 can be turned on and turned off in response to a write control signal. When the write transistor T4 is turned on, the data signal Data can be transmitted to the write node N2, so that the energy storage circuit 30 can store the voltage of the data signal Data.

[0104] As shown in FIG. 3 and FIG. 14, in some embodiments of the present disclosure, the compensation circuit 20 includes a compensation transistor T2, the first electrode of the compensation transistor T2 is connected with the second electrode of the drive transistor T3, the second electrode of the compensation transistor T2 is connected with the control node N1, and the gate of the compensation transistor T2 can be turned on and turned off in response to a compensation control signal GIC. When the drive transistor T3 and the compensation transistor T2 are turned on, the threshold voltage of the drive transistor T3 can be written to the control node N1.

[0105] The first reset circuit 10 can adopt various structures, for example:

[0106] As shown in FIG. 3, in the first type of embodiment, the first reset circuit 10 can initialize the gate of the driving transistor T3 and the first electrode of the light emitting device LD respectively through different sub-circuits. Specifically, the first reset circuit 10 can include a first reset sub-circuit 101 and a second reset sub-circuit 102, wherein:

[0107] The first reset sub-circuit 101 is connected to the control node N1, i.e., connected to the gate of the driving transistor T3. The first reset sub-circuit 101 can be turned on and turned off in response to a first reset control signal, and when turned on, can transmit a first reset signal Ref1 to the control node N1 to initialize the gate of the driving transistor T3 and eliminate the influence of the previous frame of image. For example, the first reset sub-circuit 101 includes a first reset transistor T1. The first electrode of the first reset transistor T1 can receive the first reset signal Ref1, the second electrode is connected to the control node N1, and the gate of the first reset transistor T1 can be turned on and turned off in response to the first reset control signal.

[0108] The second reset sub-circuit 102 is connected to the first electrode of the light emitting device LD and the first light emitting control circuit 70, and can affect the turning on and turning off of the second reset control signal. When turned on, the second reset sub-circuit 102 can transmit a second reset signal to the first electrode to initialize the light emitting device LD and eliminate the influence of the previous frame of image. For example, the second reset sub-circuit 102 includes a second reset transistor T8. The first electrode of the second reset transistor T8 is used to receive the second reset signal, the second electrode is connected to the first electrode of the light emitting device LD and the first light emitting control circuit 70 at the reset node N6, and the gate of the second reset transistor T8 can be turned on and turned off in response to the second reset control signal.

[0109] As shown in FIG. 3, based on the above-mentioned first type of embodiment, in some embodiments of the present disclosure, the first light emitting control circuit 70 and the second light emitting control circuit 50 are turned on and turned off in response to the same light emitting control signal EM. For example, the gates of the first light emitting control transistor T7 and the second light emitting control transistor T5 are connected and can receive the same light emitting control signal EM, avoiding the input of light emitting control signals respectively, which is beneficial to reduce the number of shift registers for outputting the light emitting control signal and simplify the structure.

[0110] As shown in FIG. 10 and FIG. 11, based on the above-mentioned first type of implementation with the first isolation sub-circuit 61 and the second isolation sub-circuit 62 in the implementation, in some implementations of the present disclosure, the first reset sub-circuit 101 and the first isolation sub-circuit 61 can be turned on and off in response to the same control signal, the compensation circuit 20 and the second isolation sub-circuit 62 are turned on and off in response to the same control signal, for example, the gate of the first reset transistor T1 and the first isolation transistor T61 can be connected, so that the first reset transistor T1 and the first isolation transistor T61 are turned on and off synchronously, that is, the first reset control signal GI1 and the first isolation control signal GI31 can be the same signal; at the same time, the gate of the compensation transistor T2 and the second isolation transistor T62 can be connected, so that the compensation transistor T2 and the second isolation transistor T62 are turned on and off synchronously, that is, the compensation control signal GIC and the second isolation control signal GI32 can be the same signal.

[0111] As shown in FIG. 12, based on the above-mentioned first type of implementation, in some implementations, for the isolation circuit 60 including the above-mentioned isolation transistor T6, the isolation circuit 60 and the compensation circuit 20 can be turned on and off in response to the same signal, for example, the gate of the isolation transistor T6 and the gate of the compensation transistor T2 can be connected, so that the isolation transistor T6 and the compensation transistor T2 can be turned on and off synchronously, that is, the isolation control signal GI3 and the compensation control signal GIC can be the same signal, in an implementation, the compensation control signal GIC can control the isolation transistor T6 and the compensation transistor T2 to be turned on and off synchronously. At the same time, the pixel circuit can further include a compensation input circuit 100 and a fourth light-emitting control circuit 110, wherein:

[0112] The compensation input circuit 100 can be connected to the first electrode of the driving transistor T3, can be turned on and off under the control of a compensation input control signal GIV, and when turned on, can transmit a compensation signal CV to the first electrode of the driving transistor T3. For example, the compensation input circuit 100 can include a compensation input transistor T100, the first electrode of which is used to receive the compensation signal CV, the second electrode of which is connected to the first electrode of the driving transistor T3 at the compensation node N8, and the gate of the compensation input transistor T100 can receive the compensation input control signal GIV and be turned on and off under the control of the compensation input control signal GIV.

[0113] The fourth light-emitting control circuit 110 can be connected to the power supply node N5 and the compensation node N8, and can be turned on and off under the control of a light-emitting control signal EM, and when turned on, can transmit a first power supply signal ELVSS. For example, the fourth light-emitting control circuit 110 can include a fourth light-emitting control transistor T110, which can be connected to the power supply node N5 and the compensation node N8, and the gate of the compensation input transistor T100 can receive the light-emitting control signal EM and be turned on and off under the control of the light-emitting control signal EM.

[0114] As shown in FIG. 13, based on the pixel circuit of FIG. 12, in the reset stage t1, the compensation input circuit 100, the first light emitting control circuit 70, the second light emitting control circuit 50, and the fourth light emitting control circuit 110 are turned off, the compensation circuit 20 and the isolation circuit 60 are turned on, and the isolation signal is transmitted to the isolation node N3. The states of other circuits can refer to the description of the reset stage t1 in the driving method above.

[0115] In the compensation stage t2, the first light emitting control circuit 70, the second light emitting control circuit 50, and the fourth light emitting control circuit 110 are turned off; the compensation input circuit 100, the compensation circuit 20, and the isolation circuit 60 are turned on, and the voltage Vcv of the compensation signal CV is less than the voltage difference between the voltage Vref1 of the first reset signal Ref1 and the threshold voltage Vth of the driving transistor T3, i.e., Vcv is less than Vref1-Vth, so that the driving transistor T3 is turned on, the compensation signal CV is transmitted to the control node N1, and the driving transistor T3 is turned off when the voltage of the control node N1 is equal to Vcv+Vth, so that the threshold voltage Vth is written to the control node N1. The compensation function can be realized by replacing the first power signal ELVSS in the above description with the compensation signal CV, i.e., the threshold voltage Vth is written to the control node N1, and the compensation principle is similar to the driving method above.

[0116] In the write stage t3, the write circuit 40 is turned on to write the data signal to the write node N2. The write stage t3 is located after the start of the compensation stage t2 and before the end of the compensation stage t2.

[0117] In the light emitting stage t4, the first light emitting control circuit 70, the second light emitting control circuit 50, and the fourth light emitting control circuit 110 are turned on, and the compensation input circuit 100, the compensation circuit 20, and the isolation circuit 60 are turned off. The specific principle can refer to the driving method above, and will not be described in detail here.

[0118] Based on the first type of implementation above, in some embodiments of the present disclosure, the second reset sub-circuit 102 and the write circuit 40 can be turned on and turned off in response to the same signal, for example, the gate of the second reset transistor T8 and the write transistor T4 can be connected, so that the second reset transistor T8 and the write transistor T4 are turned on and turned off synchronously, i.e., the second reset control signal and the write control signal can be the same signal, so that the writing of the data signal Data and the writing of the second reset signal Ref2 are performed at the same time; thereby avoiding controlling the second reset transistor T8 and the write transistor T4 by different signals, and only one signal line can be used to transmit the control signal to the second reset transistor T8 and the write transistor T4 at the same time, which is beneficial to reducing the number of shift registers.

[0119] In some embodiments of the present disclosure, the first reset sub-circuit 101 and the write-in circuit 40 can be turned on and turned off in response to the same signal, for example, the gate of the first reset transistor T1 and the write-in transistor T4 can be connected, so that the first reset transistor T1 and the write-in transistor T4 are turned on and turned off synchronously, that is, the first reset control signal GI1 and the write-in control signal GIW can be the same signal, so that the writing of the data signal Data and the writing of the first reset signal Ref1 are performed at the same time; thereby avoiding controlling the second reset transistor T8 and the write-in transistor T4 by different signals respectively, and only one signal line can be used to transmit the control signals to the first reset transistor T1 and the write-in transistor T4 at the same time, which is beneficial to reducing the number of shift registers.

[0120] As shown in FIGS. 14-17, in the second type of embodiment, the first reset circuit 10 is connected with the first electrode of the light emitting device LD and the first light emitting control circuit 70, and can receive the first reset signal Ref1, in the reset stage t1, the first reset circuit 10, the first light emitting control circuit 70 and the compensation circuit 20 can be turned on, and the first reset signal Ref1 is transmitted to the control node N1; in the compensation stage t2, the first light emitting control circuit 70 is turned off, and the first reset circuit 10 is maintained to be turned on, and the first electrode of the light emitting device LD1 can be initialized by the first reset signal Ref1. For example, the first reset circuit 10 includes the first reset transistor T1, the first electrode of which is used to receive the first reset signal Ref1, the second electrode of which is connected with the first electrode of the light emitting device LD and the first light emitting control circuit 70, and the first reset transistor T1 is not directly connected with the control node N1, and the gate of the first reset transistor T1 can be turned on and turned off in response to the first reset control signal.

[0121] The above-mentioned second type of embodiment does not need to initialize by two sub-circuits, and does not need two control signals of the first reset control signal and the second reset control signal, but only needs the first reset signal, and accordingly, only needs a group of shift register output control signals, which is beneficial to simplify the structure.

[0122] For the second type of embodiment, in some embodiments, as shown in FIG. 17, the light emitting control signal for controlling the first light emitting control transistor T7 is the first light emitting control signal EM1, and the light emitting control signal for controlling the second light emitting control transistor T5 is the second light emitting control signal EM2; the first light emitting control circuit 70 and the second light emitting control circuit 50 are synchronously turned on and turned off, i.e. the gates of the first light emitting control transistor T7 and the second light emitting control transistor T5 are connected. Alternatively, the first light emitting control signal EM1 and the second light emitting control signal EM2 can also be different, for example, as shown in FIG. 16, in the reset stage t1, the first light emitting control circuit 70 is turned on, while the second light emitting control circuit 50 is turned off; in the compensation stage t2, the first light emitting control circuit 70 is turned off, and the second light emitting control circuit 50 is turned on; the write stage t3 is located after the compensation stage t2, and in the write stage t3, the first light emitting control circuit 70 and the second light emitting control circuit 50 are both turned off; in the light emitting stage t4, the first light emitting control circuit 70 and the second light emitting control circuit 50 are both turned on.

[0123] Further, as shown in FIGS. 14-16, based on the above-mentioned second type of embodiment, the first light emitting control circuit 70 can be turned on and turned off in response to the first light emitting control signal EM1, and the second light emitting control circuit 50 can be turned on and turned off in response to the second light emitting control signal EM2. A third light emitting control circuit 90 can be provided between the first light emitting control circuit 70 and the driving transistor T3 or between the driving transistor T3 and the end receiving the first power signal ELVSS, and the third light emitting control circuit 90 can be turned on and turned off in response to the second light emitting control signal EM2, i.e. by synchronously turning on the second light emitting control circuit 50 and the third light emitting control circuit 90, it is ensured that in the reset stage t1 (the first light emitting control circuit 70 is turned on), the third light emitting control circuit 90 is turned off, avoiding the first power signal ELVSS writing the first electrode of the light emitting device LD in the reset stage t1, preventing the light emitting device LD from emitting light in the reset stage t1. Alternatively, the first light emitting control circuit 70 and the second light emitting control circuit 50 can also be turned on and turned off in response to the first light emitting control signal EM1, and be turned on in the reset stage t1 and the light emitting stage t4, and be turned off in the compensation stage t2 and the write stage t3, and the third light emitting control circuit 90 can be turned on and turned off in response to the second light emitting control signal EM2, and be turned off in the reset stage t1, and be turned on in the compensation stage t2, the write stage t3 and the light emitting stage t4. At this time, the write stage t3 can be located after the compensation stage t2.

[0124] For example:

[0125] As shown in FIG. 14 and FIG. 16, in the first embodiment, the second electrode of the driving transistor T3 is connected to the first light emitting control circuit 70 through the third light emitting control circuit 90, in the reset phase tl, the first light emitting control circuit 70 is turned on, and the third light emitting control circuit 90 is turned off, which does not affect the writing of the first reset signal Refl to the control node Nl, and the first electrode of the light emitting device LD is blocked from receiving the first power signal ELVSS by turning off the third light emitting control circuit 90. For example, the third light emitting control circuit 90 includes a third light emitting control transistor T9, the first electrode of which is connected to the second electrode of the driving transistor T3, the second electrode of which is connected to the compensation input node N4, so as to be connected to the first electrode of the first light emitting control transistor T7, and the gate of the third light emitting control transistor T9 can receive the second light emitting control signal EM2 and turn on and off in response to the second light emitting control signal EM2.

[0126] As shown in FIG. 15 and FIG. 16, in some embodiments, the third light emitting control circuit 90 is connected to the first electrode of the driving transistor T3, can receive the first power signal ELVSS, and can turn on and off in response to the second light emitting control signal EM2, and when turned on, can transmit the first power signal ELVSS to the first electrode of the driving transistor T3. Further, the third light emitting control circuit 90 is connected between the first electrode of the driving transistor T3 and the isolation input node N7.

[0127] As shown in FIG. 16, the third light emitting control circuit 90 is turned off only in the reset phase tl and the writing phase t3, and is turned on in the compensation phase t2 and the light emitting phase t4, and when turned off, does not affect the transmission of the first power signal ELVSS as an isolation signal to the third terminal of the energy storage circuit 30. For example, the third light emitting control circuit 90 includes a third light emitting control transistor T9, the first electrode of which is connected to the isolation input node N7 so as to receive the first power signal ELVSS, the second electrode of which is connected to the first electrode of the driving transistor T3, and the gate of the third light emitting control transistor T9 can receive the second light emitting control signal EM2 and turn on and off in response to the second light emitting control signal EM2.

[0128] In some embodiments, based on the embodiment of FIG. 15, as shown in FIG. 16, the compensation circuit 20 and the isolation circuit 60 can be turned on and off in response to the same signal, and are turned on in the reset phase tl, the compensation phase t2 and the writing phase t3, and are turned off in the light emitting phase t4.

[0129] As shown in FIG. 17, in some embodiments of the present disclosure, the pixel circuit can further include a second reset circuit 120, which can be connected to the first electrode of the driving transistor T3, for example, the second reset circuit 120 can be connected to the isolated input node N7. The second reset circuit 120 can be turned on and turned off in response to a third reset control signal GI4, and when turned on, can transmit a third reset signal Init to the first electrode of the driving transistor T3 to initialize the first electrode of the driving transistor T3, and can be transmitted to the isolated node N3 through the isolation circuit 60 as an isolated signal. For example, the second reset circuit 120 includes a third reset transistor T10, the first electrode of the third reset transistor T10 can receive the third reset signal Init, the second electrode is connected to the isolated input node N7, i.e. connected to the first electrode of the driving transistor T3, and the gate of the third reset transistor T10 can receive the third reset control signal GI4 and can be turned on and turned off in response to the third reset control signal GI4. In the compensation stage t2, the first light emitting control circuit 70 and the second light emitting control circuit 50 can be turned off in response to the same light emitting control signal EM, and the difference between the first reset signal Ref1 and the third reset signal Init is greater than the threshold voltage Vth, so that the driving transistor T3 is turned on until the voltage of the control node N1 becomes Vinit+Vth, the driving transistor T3 is turned off; Vinit is the voltage of the third reset signal Init; at the same time, the third reset signal Init is an isolated signal. In addition, the pixel circuit further includes a fourth light emitting control circuit 110, which can be connected to the power supply node N5 and the isolated input node N7, or the fourth light emitting control circuit 110 can be connected to the power supply node N5 and can receive the first power supply signal ELVSS; the fourth light emitting control circuit 110 can be turned on and turned off under the control of the light emitting control signal EM, and when turned on, the first power supply signal ELVSS can be transmitted. For example, the fourth light emitting control circuit 110 can include a fourth light emitting control transistor T110, which can be connected to the power supply node N5 and the isolated node N3, and the fourth light emitting control circuit 110 is turned off when the second reset circuit 120 is turned on.

[0130] In some embodiments of the present disclosure, if the pixel circuit has the fourth light emitting control circuit 110, the third light emitting control circuit 90 in the above can not be provided, of course, neither can be provided.

[0131] In some embodiments, the third reset control signal GI4 and the isolation control signal GI3 can be the same signal, i.e. both can be turned on and off in response to the same signal, so that the gate of the isolation transistor T6 and the gate of the third reset transistor T10 are connected. Alternatively, in some embodiments, the third light-emitting control circuit 90 is connected between the first electrode of the driving transistor T3 and the isolation input node N7, and the third light-emitting control circuit 90 is turned off only in the reset phase t1, and is turned on in the compensation phase t2, the write phase t3 and the light-emitting phase t4; the third reset control signal GI4 and the isolation control signal GI3 can use different signals, and the third reset transistor T10 can be turned on only in the reset phase t1, and is turned off in other phases, only playing an initialization role, and does not transmit the isolation signal.

[0132] In some embodiments of the present disclosure, one of the second reset transistor T8 and the first light-emitting control transistor T7 is an N-type transistor, and the other is a P-type transistor, and the gates of the two can receive the same control signal to control the turn-on and turn-off; alternatively, one of the second reset transistor T8 and the second light-emitting control transistor T5 is an N-type transistor, and the other is a P-type transistor, and the gates of the two can receive the same control signal to control the turn-on and turn-off. The material of the active part of the N-type transistor can be metal oxide, and the material of the active part of the P-type transistor can be polysilicon. In this way, it is beneficial to reduce the output control signal shift register, and facilitate the simplification of the structure.

[0133] The following exemplary description of the present disclosure is based on the above description, taking the first type of embodiment and the second type of embodiment and the driving method thereof as examples:

[0134] First type of embodiment

[0135] As shown in FIG. 3, the pixel circuit includes the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the write transistor T4, the second light-emitting control transistor T5, the isolation transistor T6, the first light-emitting control transistor T7 and the second reset transistor T8 described above, each of which is an N-type oxide transistor, and the first light-emitting control transistor T7 and the second light-emitting control transistor T5 are turned on and off in response to the same light-emitting control signal EM. For specific relationships, reference can be made to the description above, which will not be described in detail here.

[0136] The driving method of the first type of embodiment includes:

[0137] As shown in FIG. 4 and FIG. 5, in the reset stage t1, the first reset control signal GI1, the second reset control signal GI2 and the isolation control signal GI3 are high, the first reset transistor T1, the second reset transistor T8 and the isolation transistor T6 are turned on, the first reset signal Ref1 is transmitted to the control node N1, the second reset signal Ref2 is transmitted to the first electrode of the light emitting device LD, and the first power signal ELVSS is transmitted to the isolation node N3. The light emitting control signal EM, the compensation control signal GIC and the write control signal GIW are all low, the first light emitting control transistor T7, the second light emitting control transistor T5, the compensation transistor T2, the write transistor T4 and the off; wherein, since the voltage difference between the first reset signal Ref1 and the first power voltage VSS is greater than the threshold voltage Vth of the drive transistor T3, the drive transistor T3 is turned on.

[0138] As shown in FIG. 4 and FIG. 6, in the compensation stage t2, the second reset control signal GI2, the isolation control signal GI3 and the compensation control signal GIC are high, the second reset transistor T8, the isolation transistor T6 and the compensation circuit 20 are turned on, and the first power signal ELVSS is transmitted to the control node N1 through the drive transistor T3; the isolation transistor T6 can continue to transmit the first power signal ELVSS to the isolation node N3, maintain the voltage of the isolation node N3, so that the voltages of the first end and the second end of the energy storage circuit 30 do not affect each other; the second reset transistor T8 is turned on to stabilize the voltage of the first electrode of the light emitting device LD at the voltage Vref2 of the second reset signal Ref2. At the same time, the first reset control signal GI1, the light emitting control signal EM and the write control signal GIW are all low, the first reset transistor T1, the first light emitting control transistor T7, the second light emitting control transistor T5 and the write transistor T4 are turned off.

[0139] As shown in FIG. 4 and FIG. 7, in the writing stage t3, the second reset control signal GI2, the isolation control signal GI3, the writing control signal GIW and the compensation control signal GIC are high, the second reset transistor T8, the isolation transistor T6, the writing transistor T4 and the compensation transistor T2 are turned on; the first power signal ELVSS can continue to be transmitted to the control node N1 until the voltage of the control node N1 is equal to VSS+Vth, the driving transistor T3 is turned off, so as to write the threshold voltage Vth into the control node N1. The isolation transistor T6 can continue to transmit the first power signal ELVSS to the isolation node N3, maintain the voltage of the isolation node N3, and prevent the voltages of the first end and the second end of the energy storage circuit 30 from affecting each other; the second reset transistor T8 is turned on, so as to stabilize the voltage of the first electrode of the light emitting device LD at the voltage Vref2 of the second reset signal Ref2; the data signal Data can be transmitted to the writing node N2 through the writing transistor T4 and stored in the second capacitor C2, and will not cause the voltage of the control node N1 to jump under the action of the isolation signal (the first power signal ELVSS). At the same time, the first reset control signal GI1 and the light emitting control signal EM are both low, the first reset transistor T1, the first light emitting control transistor T7 and the second light emitting control transistor T5 are turned off. The compensation stage t2 can continue after the writing stage t3, and the writing of the threshold voltage Vth and the writing of the data signal Data overlap in time.

[0140] As shown in FIG. 4 and FIG. 8, in the light emitting stage t4, the light emitting control signal EM is high, the first light emitting control transistor T7 and the second light emitting control transistor T5 are turned on, and the voltage of the writing node N2 changes from the voltage Vdata of the data signal Data to the voltage VSS of the power supply node N5 at this time. At the same time, the first reset control signal GI1, the second reset control signal GI2, the writing control signal GIW, the isolation control signal GI3 and the compensation control signal GIC are all low, and the first reset transistor T1, the second reset transistor T8, the isolation transistor T6, the writing transistor T4 and the compensation transistor T2 are all turned off; at this time, since the isolation node N3 no longer receives the first power signal ELVSS, the voltage change of the writing node N2 is coupled to the control node N1 through the second capacitor C2 and the first capacitor C1, and the voltage of the control node N1 is VSS+Vth+VSS-Vdata, at this time, the light emitting device LD starts to emit light, the current I of the driving transistor T3 is (μWCox / 2L)×(VSS-Vdata) 2 , which can eliminate the influence of the threshold voltage Vth, and in the case that the first power voltage VSS is a constant voltage, the brightness of the light emitting device LD can be controlled through the voltage Vdata of the data signal Data, and the specific principle is not described here in detail.

[0141] Second type of implementation

[0142] As shown in FIG. 14 and FIG. 15, the pixel circuit includes the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the write transistor T4, the second light-emitting control transistor T5, the isolation transistor T6, the first light-emitting control transistor T7 and the third light-emitting control transistor T9, each of which is an N-type oxide transistor, the first light-emitting control transistor T7 is turned on and turned off in response to the first light-emitting control signal EM1, the second light-emitting control transistor T5 and the third light-emitting control transistor T9 are turned on and turned off in response to the second light-emitting control signal EM2, and the specific relationship can refer to the description above, which will not be described in detail here.

[0143] The driving method of the second type of embodiment includes:

[0144] As shown in FIG. 14 to FIG. 16, in the reset phase t1, the first light-emitting control signal EM1, the first reset control signal GI1, the compensation control signal GIC and the isolation control signal GI3 are high, the first light-emitting control transistor T7, the first reset transistor T1, the compensation transistor T2 and the isolation transistor T6 are turned on, the first reset signal Ref1 is transmitted to the first electrode of the light-emitting device LD, the compensation input node N4 and the control node N1 in turn, and the isolation signal (the first power signal ELVSS) is transmitted to the isolation node N3. The second light-emitting control signal EM2, the compensation control signal GIC and the write control signal GIW are all low, the second light-emitting control transistor T5, the third light-emitting control transistor T9 and the write transistor T4 are turned off; wherein, since the voltage difference between the first reset signal Ref1 and the first power voltage VSS is greater than the threshold voltage Vth of the drive transistor T3, the drive transistor T3 is turned on.

[0145] As shown in FIG. 14 to FIG. 16, in the compensation phase t2, the first reset control signal GI1, the isolation control signal GI3 and the compensation control signal GIC are high, the first reset transistor T1, the isolation transistor T6 and the compensation circuit 20 are turned on, and the first power signal ELVSS is transmitted to the control node N1 through the drive transistor T3; the isolation transistor T6 can continue to transmit the first power signal ELVSS to the isolation node N3, maintain the voltage of the isolation node N3, so that the voltages of the first end and the second end of the energy storage circuit 30 do not affect each other; the first reset transistor T1 is turned on to stabilize the voltage of the first electrode of the light-emitting device LD at the voltage Vref2 of the second reset signal Ref2. At the same time, the first light-emitting control signal EM1, the second light-emitting control signal EM2 and the write control signal GIW are all low, the first light-emitting control transistor T7, the second light-emitting control transistor T5, the third light-emitting control transistor T9 and the write transistor T4 are turned off.

[0146] As shown in FIGS. 14-16, in the write stage t3, the first reset control signal GI1, the isolation control signal GI3, the compensation control signal GIC and the write control signal GIW are high, the first reset transistor T1, the isolation transistor T6, the write transistor T4 and the compensation transistor T2 are turned on; the first power signal ELVSS can continue to be transmitted to the control node N1 until the voltage of the control node N1 is equal to VSS+Vth, the driving transistor T3 is turned off. The isolation transistor T6 can continue to transmit the first power signal ELVSS to the isolation node N3 to maintain the voltage of the isolation node N3; the first reset transistor T1 is turned on to stabilize the voltage of the first electrode of the light emitting device LD at the voltage Vref2 of the second reset signal Ref2; the data signal Data can be transmitted to the write node N2 through the write transistor T4 and stored in the second capacitor C2, and under the action of the isolation signal (the first power signal ELVSS), the voltage jump of the control node N1 will not be caused. At the same time, the first light emitting control signal EM1 and the second light emitting control signal EM2 are both low, the first light emitting control transistor T7, the second light emitting control transistor T5 and the third light emitting control transistor T9 are turned off. The compensation stage t2 can continue after the write stage t3, and the write of the threshold voltage Vth and the write of the data signal Data overlap in time.

[0147] As shown in FIGS. 14-16, in the light emitting stage t4, the first light emitting control signal EM1 and the second light emitting control signal EM2 are high, the first light emitting control transistor T7, the second light emitting control transistor T5 and the third light emitting control transistor T9 are turned on, and the voltage of the write node N2 changes from Vdata to the voltage VSS of the power node N5 at this time. At the same time, the first reset control signal GI1, the write control signal GIW, the isolation control signal GI3 and the compensation control signal GIC are all low, the first reset transistor T1, the isolation transistor T6, the write transistor T4 and the compensation transistor T2 are all turned off; at this time, since the isolation node N3 no longer receives the first power signal ELVSS, the voltage change of the write node N2 is coupled to the control node N1 through the second capacitor C2 and the first capacitor C1, so that the light emitting device LD starts to emit light, and through the coupling of the energy storage circuit 30, the influence of the threshold voltage Vth can be eliminated, and the specific principle is not described in detail here.

[0148] It should be noted that although the steps of the driving method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0149] As shown in FIG. 2, for the display panel of the pixel circuit with all N-type transistors as above, the driving backplane BP can include a substrate SU and, in sequence along a direction away from the substrate SU, a semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, a first source-drain layer SD1, and a second source-drain layer SD2, wherein the semiconductor layer SE can be made of metal oxide material, and can include the active part of each N-type transistor of the pixel circuit.

[0150] In addition, the driving backplane BP can further include a first gate insulating layer GL1, a second gate insulating layer GL2, a first insulating layer IL1, a first planar layer PLN1, and a second planar layer PLN2 made of insulating material, wherein:

[0151] The first gate insulating layer GL1 covers the semiconductor layer SE, and the first gate layer GA1 is arranged on the surface of the first gate insulating layer GL1 away from the substrate SU. The second gate insulating layer GL2 covers the first gate layer GA1, and the second gate layer GA2 is arranged on the surface of the second gate insulating layer GL2 away from the substrate SU. The first insulating layer IL1 can cover the second gate layer GA2, and the first source-drain layer SD1 is arranged on the surface of the first insulating layer IL1 away from the substrate SU. The first planar layer PLN1 can cover the first source-drain layer SD1. The second source-drain layer SD2 can be arranged on the surface of the first planar layer PLN1 away from the substrate SU. The second planar layer PLN2 can cover the second source-drain layer SD2. The first electrode ANO of the light emitting device LD and the pixel definition layer PDL can be arranged on the surface of the second planar layer PLN2 away from the substrate SU.

[0152] In addition, in some embodiments, the pixel circuit simultaneously has a P-type transistor made of polysilicon and an N-type transistor made of metal oxide, and the driving backplane BP can include a first semiconductor layer made of polysilicon and a second semiconductor layer made of metal oxide, which will not be described in detail here.

[0153] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the application are indicated by the appended claims.

Claims

1. A pixel circuit, comprising a driving transistor, a first reset circuit, a write circuit, a compensation circuit, an isolation circuit, an energy storage circuit, a first light emitting control circuit and a second light emitting control circuit; a first electrode of the driving transistor is configured to receive a first power signal, a second electrode of the driving transistor is connected to a first electrode of a light emitting device through the first light emitting control circuit, a second electrode of the light emitting device is configured to receive a second power signal, a voltage of the first power signal is less than a voltage of the second power signal, the driving transistor is a metal oxide transistor; the first reset circuit is connected to a gate electrode of the driving transistor and configured to transmit a first reset signal capable of turning on the driving transistor to the gate electrode of the driving transistor; the write circuit is connected to a write node at a first end of the energy storage circuit and a gate electrode of the driving transistor at a second end of the energy storage circuit, and configured to transmit a data signal to the write node; the compensation circuit is connected to the second electrode of the driving transistor and the gate electrode of the driving transistor; the isolation circuit is connected to a third end of the energy storage circuit and configured to transmit an isolation signal to the energy storage circuit; the second light emitting control circuit is connected to the write node at the first end and configured to transmit the first power signal to the write node; the energy storage circuit is configured to store voltages of the write node and the gate electrode of the driving transistor respectively when the isolation signal is received at the third end, and to couple the voltage of the write node to the gate electrode of the driving transistor when the isolation signal is not received at the third end.

2. The pixel circuit of claim 1, wherein, the energy storage circuit comprises a first capacitor and a second capacitor connected in series between the write node and the gate electrode of the driving transistor, the first capacitor is connected to the gate electrode of the driving transistor, the second capacitor is connected to the write node, and the first capacitor and the second capacitor are connected to the third end.

3. The pixel circuit of claim 1, wherein, the first light emitting control circuit comprises a first light emitting control transistor, a first electrode of the first light emitting control transistor is connected to the second electrode of the driving transistor, and a second electrode of the first light emitting control transistor is connected to the first electrode of the light emitting device; the second light emitting control circuit comprises a second light emitting control transistor, a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor, and a second electrode of the second light emitting control transistor is connected to the write node.

4. The pixel circuit of claim 1, wherein, the isolation circuit comprises an isolation transistor, a first electrode of the isolation transistor is configured to receive the isolation signal, and a second electrode of the isolation transistor is connected to the third end.

5. The pixel circuit of claim 4, wherein, the first electrode of the isolation transistor is connected to the first electrode of the driving transistor, and the isolation signal is the first power signal.

6. The pixel circuit of claim 1, wherein, the write circuit comprises a write transistor, a first electrode of the write transistor is configured to receive the data signal, and a second electrode of the write transistor is connected to the write node; the compensation circuit comprises a compensation transistor, a first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and a second electrode of the compensation transistor is connected to the gate electrode of the driving transistor.

7. The pixel circuit of claim 1, wherein, the first reset circuit comprises a first reset transistor, a first electrode of the first reset transistor is configured to receive the first reset signal, and a second electrode of the first reset transistor is connected to the first electrode of the light emitting device and the first light emitting control circuit.

8. The pixel circuit of claim 1, wherein, The first reset circuit comprises a first reset sub-circuit and a second reset sub-circuit; the first reset sub-circuit is connected with the control node and is configured to transmit the first reset signal to the control node; the second reset sub-circuit is connected with the first electrode of the light-emitting device and the first light-emitting control circuit and is configured to transmit a second reset signal to the first electrode.

9. The pixel circuit of claim 8, wherein, The first reset sub-circuit comprises a first reset transistor, and the second reset sub-circuit comprises a second reset transistor; a first electrode of the first reset transistor is configured to receive the first reset signal, and a second electrode of the first reset transistor is connected with the control node; a first electrode of the second reset transistor is configured to receive the second reset signal, and a second electrode of the second reset transistor is connected with the first electrode of the light-emitting device and the first light-emitting control circuit.

10. The pixel circuit of any of claims 1-9, wherein, The pixel circuit further comprises a second reset circuit, the second reset circuit being connected with the first electrode of the driving transistor and configured to transmit a third reset signal to the first electrode of the driving transistor.

11. The pixel circuit of claim 10, wherein, The second reset circuit comprises a third reset transistor, a first electrode of the third reset transistor being configured to receive the third reset signal, and a second electrode of the third reset transistor being connected with the first electrode of the driving transistor.

12. The pixel circuit of any of claims 1-9, wherein, The pixel circuit further comprises a third light-emitting control circuit, the second electrode of the driving transistor being connected with the first light-emitting control circuit through the third light-emitting control circuit; or the third light-emitting control circuit is connected with the first electrode of the driving transistor and configured to transmit the first power signal to the driving transistor.

13. The pixel circuit of claim 12, wherein, The third light-emitting control circuit comprises a third light-emitting control transistor, a first electrode of the third light-emitting control transistor being connected with the second electrode of the driving transistor, and a second electrode of the third light-emitting control transistor being connected with the first light-emitting control circuit; or a first electrode of the third light-emitting control transistor is configured to receive the first power signal, and a second electrode of the third light-emitting control transistor is connected with the first electrode of the driving transistor.

14. The pixel circuit of claim 1, wherein, The first light-emitting control circuit and the second light-emitting control circuit are turned on and turned off in response to the same control signal.

15. The pixel circuit of claim 8, wherein, The isolation circuit comprises a first isolation sub-circuit and a second isolation sub-circuit, the first isolation sub-circuit and the second isolation sub-circuit are both connected with the third terminal, the first isolation sub-circuit is configured to transmit a first isolation signal to the third terminal, and the second isolation sub-circuit is configured to transmit a second isolation signal to the third terminal. The first reset sub-circuit and the first isolation sub-circuit are turned on and turned off in response to the same control signal; the compensation circuit and the second isolation sub-circuit are turned on and turned off in response to the same control signal.

16. The pixel circuit of claim 8, wherein, One of the first reset sub-circuit and the second reset sub-circuit and the write circuit are turned on and turned off in response to the same control signal.

17. A driving method of a pixel circuit, the pixel circuit comprising a driving transistor, a first reset sub-circuit, a second reset sub-circuit, a writing circuit, a compensation circuit, an isolation circuit, an energy storage circuit, a first light emitting control circuit and a second light emitting control circuit; a first electrode of the driving transistor is configured to receive a first power signal, a second electrode of the driving transistor is connected with a first electrode of a light emitting device through the first light emitting control circuit, a second electrode of the light emitting device is configured to receive a second power signal; the first reset sub-circuit is connected with a control node; the second reset sub-circuit is connected with the first electrode of the light emitting device and the first light emitting control circuit; the writing circuit is connected with a first terminal of the energy storage circuit at a writing node, a second terminal of the energy storage circuit is connected with a gate of the driving transistor at the control node; the compensation circuit is connected with the second electrode of the driving transistor and the control node; the isolation circuit is connected with a third terminal of the energy storage circuit; the second light emitting control circuit is connected with the first terminal at the writing node. The driving transistor is an oxide transistor. The voltage of the first power signal is less than the voltage of the second power signal. The driving method comprises: In the reset stage, the first reset sub-circuit is turned on to transmit a first reset signal to the control node to turn on the drive transistor; the second reset sub-circuit is turned on to transmit a second reset signal to the first electrode of the light emitting device; and the isolation circuit is turned on to transmit an isolation signal to the third terminal. In the compensation stage, the compensation circuit is turned on to write the threshold voltage of the drive transistor into the control node and store it in the energy storage circuit; the second reset sub-circuit is turned on to transmit a second reset signal to the first electrode of the light emitting device; and the isolation circuit is turned on to transmit an isolation signal to the third terminal. In the write stage, the write circuit is turned on to transmit a data signal to the write node and store it in the energy storage circuit; the second reset sub-circuit is turned on to transmit a second reset signal to the first electrode of the light emitting device; and the isolation circuit is turned on to transmit an isolation signal to the third terminal. In the light emitting stage, the isolation circuit is turned off; the first light emitting control circuit and the second light emitting control circuit are turned on to transmit the first power signal to the write node, and the data signal, the first power signal and the isolation signal are coupled to the control node through the energy storage circuit to control the light emitting device to emit light.

18. A driving method of a pixel circuit, the pixel circuit comprising a driving transistor, a first reset circuit, a write circuit, a compensation circuit, an isolation circuit, an energy storage circuit, a first light emitting control circuit and a second light emitting control circuit; a first electrode of the driving transistor is configured to receive a first power signal, a second electrode of the driving transistor is connected to a first electrode of a light emitting device through the first light emitting control circuit, a second electrode of the light emitting device is configured to receive a second power signal; the first reset circuit is connected to a gate of the driving transistor; the write circuit and a first terminal of the energy storage circuit are connected to a write node, a second terminal of the energy storage circuit is connected to the gate of the driving transistor and a control node; the compensation circuit is connected to the second electrode of the driving transistor and the control node; the isolation circuit is connected to a third terminal of the energy storage circuit; the second light emitting control circuit is connected to the write node and the first terminal. The drive transistor is an oxide transistor. The voltage of the first power signal is less than the voltage of the second power signal. The drive method comprises: In the reset stage, the first reset circuit, the compensation circuit and the first light emitting control circuit are turned on to transmit a first reset signal to the control node to turn on the drive transistor; and the isolation circuit is turned on to transmit an isolation signal to the third terminal. In the compensation stage, the first light emitting control circuit is turned off, the first reset circuit is turned on to transmit the first reset signal to the first electrode of the light emitting device; the isolation circuit is turned on to transmit an isolation signal to the third terminal; and the compensation circuit is turned on to write the threshold voltage of the drive transistor into the control node and store it in the energy storage circuit. In the write stage, the write circuit is turned on to transmit a data signal to the write node and store it in the energy storage circuit; the first reset circuit is turned on to transmit a first reset signal to the first electrode of the light emitting device; and the isolation circuit is turned on to transmit an isolation signal to the third terminal. In the light emitting stage, the isolation circuit is turned off; the first light emitting control circuit and the second light emitting control circuit are turned on to transmit the first power signal to the write node, and the data signal, the first power signal and the isolation signal are coupled to the control node through the energy storage circuit to control the light emitting device to emit light.

19. A display panel comprising the pixel circuit of any one of claims 1-18.

Images