Memory device, memory system, memory controller and operating method

Abstract

The embodiment of the invention provides a memory device, a memory system, a memory controller and an operation method, and the memory device comprises a memory unit array which comprises a plurality of memory units, and a preset number of memory units form a code word; the peripheral circuit is coupled with the storage unit array and is configured to generate a first boundary voltage and a second boundary voltage according to a first result corresponding to the at least one code word under the target reading voltage; adjusting the target reading voltage for at least one time, and obtaining a corresponding first result under the adjusted target reading voltage after each adjustment; in the adjustment process, the current voltage adjustment direction is changed according to the fact that the target reading voltage after one-time adjustment exceeds the range limited by the first boundary voltage and the second boundary voltage; according to the condition that a first result corresponding to the adjusted target reading voltage meets a preset condition, target valley voltage is determined, and the target valley voltage is used as the reading voltage when the reading operation is executed on the at least one code word.

Description

Memory device, memory system, memory controller and operation method Technical Field

[0001] The present application relates to, but is not limited to, a memory device, a memory system, a memory controller, and an operating method. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells changes with age, repeated read operations, and temperature fluctuations, affecting the accuracy of data read from the cells.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory device, comprising: a memory cell array comprising a plurality of memory cells, a preset number of memory cells forming a codeword; a peripheral circuit coupled to the memory cell array and configured to: generate a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword at a target read voltage; the first result comprises a representation of the number of bits flipped in two read results of at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the target read voltage is adjusted at least once, and the first result corresponding to the adjusted target read voltage is obtained after each adjustment; during the adjustment process, the direction of the current voltage adjustment is changed based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; the target valley voltage is determined based on the first result corresponding to the adjusted target read voltage satisfying a preset condition, and the target valley voltage is used as the read voltage when performing a read operation on at least one codeword.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: one or more memory devices as provided in the first aspect; and a memory controller coupled to and controlling the memory devices.

[0006] In a third aspect, an embodiment of the present application provides a memory controller, which includes a control unit and is configured to: generate a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of storage cells in at least one memory device coupled to the memory controller under a target read voltage; the first result represents the number of bits flipped in the two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the target read voltage is adjusted at least once, and the first result corresponding to the adjusted target read voltage is obtained after each adjustment; during the adjustment process, the direction of the current voltage adjustment is changed based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; the target valley voltage is determined based on the first result corresponding to the adjusted target read voltage meeting a preset condition, and the target valley voltage is used as the read voltage when performing a read operation on at least one codeword.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, the operating method comprising: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of memory cells in the memory device under a target read voltage; the first result comprises a representation of the number of bits flipped in two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; determining a target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying a preset condition, the target valley voltage being used as the read voltage when performing a read operation on at least one codeword.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, the operating method comprising: a memory controller in the memory system sends a first instruction, the first instruction instructing to obtain information representing a target valley voltage; a memory device in the memory system receives the first instruction, obtains information representing the target valley voltage according to the operating method of the memory device provided in the fourth aspect, and sends the obtained information representing the target valley voltage to the memory controller; the memory controller uses the predicted target valley voltage in the information representing the target valley voltage to control the memory device to perform a read operation, and performs an error correction decoding operation on the read result of the read operation.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method for a memory controller, the memory controller including a control unit, the operating method including: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of storage cells in at least one memory device coupled to the memory controller under a target read voltage; the first result includes a representation of the number of bits flipped in two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; determining a target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying a preset condition, the target valley voltage being used as the read voltage when performing a read operation on at least one codeword.

[0010] In the seventh aspect, an embodiment of the present application provides a storage medium having executable instructions stored thereon, which, when executed by a processor, implement the steps of any one of the operating methods provided in the fourth aspect, the fifth aspect, and the sixth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0012] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0013] FIG2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0014] FIG2B is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0015] FIG3 is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0016] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0017] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0018] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0019] FIG7 is a schematic diagram illustrating a flowchart of an implementation of an operation method performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0020] FIG8A is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including two memory bits provided in one embodiment of the present application;

[0021] FIG8B is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0022] FIG8C is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0023] FIG9A is a schematic diagram of a method for confirming predicted valley voltage / target valley voltage of the first and second stages corresponding to the lower page shown in FIG8B , provided by an embodiment of the present application;

[0024] 9B is a schematic diagram of a method for confirming predicted valley voltages / target valley voltages of the first and second stages corresponding to the middle page shown in FIG8B , provided by an embodiment of the present application;

[0025] FIG9C is a schematic diagram of a method for confirming the predicted valley voltage / target valley voltage of the first and second stages corresponding to the upper page shown in FIG8B , provided by an embodiment of the present application;

[0026] FIG9D is an enlarged schematic diagram of the rectangular dotted line area in FIG9A ;

[0027] FIG9E is an enlarged schematic diagram of the rectangular dotted line area in FIG9B ;

[0028] FIG9F is an enlarged schematic diagram of the rectangular dotted line area in FIG9C ;

[0029] 10A and 10B are schematic diagrams showing a method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG. 9C according to an embodiment of the present application;

[0030] 10C and 10D are schematic diagrams of a second method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG. 9C , provided in one embodiment of the present application;

[0031] 10E and 10F are schematic diagrams of a third method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG. 9C , provided in one embodiment of the present application;

[0032] 10G , 10H , and 10I are fourth schematic diagrams of a method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG. 9C , provided in one embodiment of the present application;

[0033] 10J and 10K are schematic diagrams of a fifth method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG. 9C , provided in one embodiment of the present application;

[0034] 10L and 10M are schematic diagrams of a sixth method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG. 9C , provided in one embodiment of the present application;

[0035] FIG10N is a seventh schematic diagram of a method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG9C according to an embodiment of the present application;

[0036] FIG11 is a schematic diagram of an exemplary structure of a memory system provided in one embodiment of the present application;

[0037] FIG12 is a block diagram of a memory system provided by an embodiment of the present application;

[0038] FIG13 is a flowchart of a method for operating a memory device according to an embodiment of the present application;

[0039] FIG14 is a second flowchart of a method for operating a memory device according to an embodiment of the present application;

[0040] FIG15 is a timing diagram of an exemplary start-up single-stage read mode operation provided by the present application;

[0041] FIG16 is a timing diagram of predicting valley voltage / target valley voltage and executing a read operation according to an embodiment of the present application;

[0042] FIG17 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0044] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0045] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0046] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0049] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0050] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0051] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0052] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0053] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0054] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0055] 2A , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1 ).

[0056] 2B , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0057] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each word line constitute a physical page.

[0058] FIG3 illustrates a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0059] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0060] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0061] As shown in FIG3 , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and an upper select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0062] As shown in FIG3 , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0063] 3 , each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318 , and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding select transistor (eg, top select transistor (TSG) 312 ).

[0064] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0065] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0066] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0067] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0068] Referring back to FIG3 , the peripheral circuit 302 can be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0069] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0070] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0071] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0072] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient error correction algorithm is typically employed during data reading.

[0073] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error rate exceeds the error correction capability, data read failures can occur.

[0074] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0075] In some embodiments, a reread operation can typically be performed by querying a retry table provided by the manufacturer. The reread operation is essentially an error correction mechanism. The reread table provides a reference voltage for reading data. By querying the reread table, each storage cell is read again at a read voltage that deviates from the normal threshold voltage and corrects the error in conjunction with an error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the reread table query stops. If the read error data cannot be corrected, the reread table query continues until the entire reread table is traversed.

[0076] The aforementioned reread operation method requires querying the reread table line by line, which inevitably increases the number of trial and error cycles and is time-consuming. Furthermore, the reread table provided by the manufacturer is only a reference value for specific environments. Real-world usage scenarios vary greatly, so the manufacturer's reread table does not cover many scenarios. Consequently, even after traversing the reread table, data may not be corrected, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the reread table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0077] Based on one or more of the above problems, in a first aspect, embodiments of the present application provide a memory device. As shown in FIG7 , the memory device includes: a memory cell array including a plurality of memory cells, wherein a predetermined number of memory cells form a codeword; and a peripheral circuit coupled to the memory cell array and configured to include the following steps:

[0078] Step S10: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword at a target read voltage; the first result includes a number of bits flipped in the at least one codeword read at the first read voltage and at the second read voltage; and the difference between the first read voltage and the second read voltage is less than a preset voltage.

[0079] Step S20: adjusting the target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment;

[0080] Step S30: During the adjustment process, according to the target read voltage after the adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage, changing the direction of the current voltage adjustment;

[0081] Step S40 : determining a target valley voltage based on whether the first result corresponding to the adjusted target read voltage satisfies a preset condition. The target valley voltage is used as a read voltage when performing a read operation on at least one codeword.

[0082] Here, the structure of the memory device is referred to above FIG3 and will not be described in detail here.

[0083] In some embodiments, a memory device includes a memory cell array, the memory cell array includes a plurality of memory cells, and a preset number of memory cells form a code word (CW).

[0084] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a physical page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a physical page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, the codeword may include 2 4 , 2 8 or 2 12 storage units.

[0085] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements.

[0086] Memory cells in different types of memory devices (eg, MLC, TLC, or QLC) can store different numbers of bits.

[0087] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0088] It is understandable that a codeword may include multiple storage units, and the number of storage units included in a codeword may be adjusted according to actual conditions.

[0089] In some embodiments, during the reading of the memory device, a read operation reads out the data of a physical page. When the number of storage cells contained in a codeword may be less than the number of storage cells coupled to a physical page, the codeword is a unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the current read voltage can be obtained here. For example, a physical page may include 4 codewords, and the page buffer hardware operation can count the fail bit count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a physical page, and the subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of a physical page, and a physical page can include multiple codewords.

[0090] In some embodiments, the memory cell array includes memory cells with a storage bit number of P bits, the P storage bits correspond to P pages respectively, and the P-bit memory cells read their P-bit storage data through a Q-level read voltage; P and Q are both integers greater than 1, and Q=2 P -1.

[0091] For example, when the number of storage bits of a memory cell includes two bits, the corresponding storage states include states 0 to 4. Referring to FIG8A , the four states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, and state 3 (also called the third storage state) P3. The binary data corresponding to these four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, a lower page (LP) and an upper page (UP).

[0092] Taking the memory cell shown in FIG8A as an example, the two-bit memory cell reads its two-bit four-state storage data through three levels of read voltage (the first level read voltage L1, the second level read voltage L2 and the third level read voltage L3 shown in FIG8A).

[0093] For example, one page corresponds to multiple read voltages, and the other page corresponds to a single read voltage. As shown in FIG8A , the binary data corresponding to the lower page is 1001, and reading the lower page requires the corresponding first read voltage L1 and third read voltage L3. The binary data corresponding to the upper page is 1100, and reading the upper page requires the corresponding second read voltage L2.

[0094] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG8B , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7. The binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages: a lower page, a middle page (MP), and an upper page.

[0095] Taking the memory cell shown in FIG8B as an example, the three-bit memory cell reads its three-bit eight-state storage data through seven levels of read voltages (the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7 shown in FIG8B ).

[0096] For example, each page corresponds to multiple read voltage levels. As shown in FIG8B , the binary data corresponding to the lower page are 10000111, and reading the lower page requires corresponding to the first read voltage L1 and the fifth read voltage L5. The binary data corresponding to the middle page are 11001100, and reading the middle page requires corresponding to the second read voltage L2, the fourth read voltage L4, and the sixth read voltage L6. The binary data corresponding to the upper page are 11100001, and reading the upper page requires corresponding to the third read voltage L3 and the seventh read voltage L7.

[0097] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG8C , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four pages, namely, a lower page, a middle page, an upper page, and an extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0098] Taking the memory cell shown in Figure 8C as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in Figure 8C).

[0099] Exemplarily, each page corresponds to multiple read voltage levels. As shown in FIG8C , the binary data corresponding to the lower page are 1100000011111100. Reading the lower page requires corresponding read voltages L2, L8, and L14. The binary data corresponding to the middle page are 1110000110000111. Reading the middle page requires corresponding read voltages L3, L7, L9, and L13. The binary data corresponding to the upper page are 1111100000110001. Reading the upper page requires corresponding read voltages L5, L10, L12, and L15. The binary data corresponding to the extra pages are 1000110000011111. Reading the extra pages requires corresponding first-level read voltage L1, fourth-level read voltage L4, sixth-level read voltage L6 and eleventh-level read voltage L11.

[0100] The lower page is usually closest to the source / drain, so each level of the read voltage corresponding to the lower page is determined first, with the fastest access speed and shortest response time, which can ensure balanced performance and durability during data access.

[0101] It should be noted that the method of preferentially determining each level of read voltage corresponding to the next page is only an example and is not used to limit the order of determining each level of read voltage in the multi-level read voltage corresponding to at least part of the pages in the embodiment of the present application.

[0102] It should be noted that the difference between the first read voltage and the second read voltage can be less than a preset voltage. In some specific embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5mV to 20mV, and can be 5mV, 10mV, 15mV, or 20mV, for example. In other specific embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5mV to -20mV, and can be -5mV, -10mV, -15mV, or -20mV, for example.

[0103] It should be noted that the first read voltage and the second read voltage are contextually related. That is, the second read voltage is obtained after performing the third adjustment based on the first read voltage. Based on this, the voltage difference between the first read voltage and the second read voltage is the step size of the third adjustment. A difference between the first read voltage and the second read voltage that is less than the preset voltage can be understood as a smaller voltage difference between the first read voltage and the second read voltage. The preset voltage is related to the step size of the third adjustment and can be a voltage slightly larger than the step size of the third adjustment. In some embodiments, the preset voltage range is set to 6mV to 21mV. Exemplarily, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. In other embodiments, the preset voltage range is set to -6mV to -21mV. Exemplarily, the preset voltage can be -6mV, -11mV, -16mV, or -21mV. In other embodiments, the preset voltage range is set to -4mV to -21mV. Exemplarily, the preset voltage can be -4mV, -11mV, -16mV, or -21mV.

[0104] It should be noted that the first read voltage and the second read voltage are both general terms. The target read voltage and the read voltage after the first and second adjustments to the target read voltage may all be referred to as the first read voltage, and the read voltage obtained after the third adjustment to the first read voltage may all be referred to as the second read voltage. In other words, the first read voltage is a general term and can be understood as the target read voltage or the target adjusted read voltage (the voltage obtained after the first or second adjustment to the target read voltage with a target step size, wherein the target step size can be set to a range of 20mV to 40mV. Exemplarily, the first adjustment step size can be 20mV, 30mV, or 40mV. The target step size can also be set to a range of 50mV to 150mV. Exemplarily, the second adjustment step size can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV).

[0105] In each embodiment of the present application, the first result corresponding to a specific voltage can be understood as: the specific voltage is subjected to a third adjustment, that is, the specific voltage and the specific voltage after the third adjustment have a first voltage difference △V1, and the number of bits flipped in the two reading results of a preset number of storage cells at the specific voltage and the specific voltage after the third adjustment can be used as the first result corresponding to the specific voltage, wherein the preset number of storage cells can form at least one codeword.

[0106] For example, the first result corresponding to the first read voltage can be understood as follows: the first read voltage is adjusted by the third adjustment, i.e., the first read voltage and the second read voltage have a first voltage difference ΔV1, and the number of bits flipped in the two read results of the preset number of memory cells at the first read voltage and the second read voltage can be used as the first result corresponding to the first read voltage. The first read voltage can be the target read voltage of the first stage (V0 shown in FIG9D ), and the second read voltage can be the read voltage after the first read voltage is adjusted by the third adjustment (V1 shown in FIG9D ). Alternatively, the first read voltage can be the target adjusted read voltage of the first stage (V2 shown in FIG9D ), and the second read voltage can be the read voltage after the target adjusted read voltage is adjusted by the third adjustment (V3 shown in FIG9D ).

[0107] In various embodiments of the present application, the target valley voltage can be obtained as follows: based on whether a first result corresponding to a specific voltage satisfies a preset condition, a specific voltage is determined to be the target valley voltage. For example, based on whether the first result corresponding to the read voltage of the first stage is less than or equal to a second preset value, the read voltage of the first stage is determined to be the target valley voltage of the first stage; wherein the second preset value is set in the range of 5 to 30, and more specifically, the second preset value can be 5, 10, 15, 20, 25, or 30.

[0108] In each embodiment of the present application, the acquisition of the predicted valley voltage can be understood as follows: based on a specific voltage and a first mapping function, a predicted valley voltage is generated. For example, based on the predicted valley voltage of the first order / the target valley voltage of the first order and the first mapping function, the predicted valley voltage of the second order is obtained, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order. The acquisition of the predicted valley voltage can also be understood as follows: based on the first result corresponding to a specific voltage, the order of a specific voltage, and the second mapping function, a predicted valley voltage is generated. For example, based on the first result corresponding to the target read voltage of the first order, the order of the first order, and the second mapping function, a predicted valley voltage of the first order is generated; wherein the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order of each order, and the predicted valley voltage.

[0109] In various embodiments of the present application, obtaining an adjusted voltage (e.g., an adjusted read voltage / an adjusted target read voltage) can be understood as follows: obtaining a voltage obtained by adjusting a specific voltage according to a target step size. For example, a first adjustment is performed on the target read voltage multiple times with a first step size, and the target read voltages after the multiple first adjustments are obtained. Alternatively, a second adjustment is performed on the target read voltage multiple times with a second step size, and the target read voltages after the multiple second adjustments are obtained.

[0110] In some embodiments, before obtaining a first result corresponding to at least one codeword at a target read voltage, the read mode of the memory device is set to a single-level read mode (SLR). The single-level read mode includes reading at least one bit of data stored in a memory cell using a single read voltage. In some specific embodiments, the memory device is configured to enter the single-level read mode in response to a mode setting command, and to obtain a first result corresponding to at least one codeword at the target read voltage in the single-level read mode.

[0111] It should be noted that the predicted valley voltage can be used directly as a target valley voltage to perform a read operation on the data to be read, or can be further processed to obtain the target valley voltage. The specific method of generating the predicted valley voltage will be further described below.

[0112] Here and below, a memory cell array including a memory cell with a storage bit number of 3 bits is used as an example for detailed description, but this is not intended to limit the various embodiments of the present application. Specifically, as shown in Figures 9A, 9B, 9C, 9D, 9E, and 9F, the storage bit number of the memory cell of at least one codeword is 3 bits, corresponding to the lower page, the middle page, and the upper page, respectively; wherein each page corresponds to multiple levels, the multiple levels of the lower page include the first level and the fifth level, the first level read voltage L1 is less than the fifth level read voltage L5, the multiple levels of the middle page include the second level, the fourth level, and the sixth level, the second level read voltage L2 and the fourth level read voltage L4 are both less than the sixth level read voltage L6, and the multiple levels of the upper page include the third level and the seventh level, the third level read voltage L3 is less than the seventh level read voltage L7. Here, the fifth-level read voltage L5, the sixth-level read voltage L6 and the seventh-level read voltage L7 correspond to the first-level read voltages of the lower page, the middle page and the upper page respectively, the first-level read voltage L1 corresponds to the second-level read voltage of the lower page, the second-level read voltage L2 and the fourth-level read voltage L4 correspond to the second-level read voltage of the middle page, and the third-level read voltage L3 corresponds to the second-level read voltage of the upper page.

[0113] In some specific embodiments, the target read voltage may be an empirical value (e.g., a read voltage corresponding to successful data reading); or it may be a default value configured for the memory device when it leaves the factory, which is obtained through a large number of simulation experiments before the memory device leaves the factory; the default valley voltage may be a default value configured for the memory device when it leaves the factory, which is obtained through a large number of simulation experiments before the memory device leaves the factory.

[0114] In some specific embodiments, the range of the absolute value of the difference between the initial first boundary voltage and the initial second boundary voltage (hereinafter referred to as the initial absolute value) can be a first range, which is smaller than the absolute value of the difference between two adjacent default valley top voltages (hereinafter referred to as the second absolute value), and greater than the absolute value of the difference between an adjacent valley bottom voltage and a valley top voltage (hereinafter referred to as the first absolute value), wherein the target read voltage is between the initial first boundary voltage and the initial second boundary voltage.

[0115] Exemplarily, as shown in FIG10A , the absolute value of the difference between the initial first boundary voltage VLB0 and the initial second boundary voltage VRB0 of the target read voltage of the seventh level (the initial absolute value VR0 of the target read voltage of the seventh level) can be less than or equal to the absolute value of the difference between the sixth-level default valley voltage VT6 and the seventh-level default valley voltage VT7, or can be greater than or equal to the absolute value of the difference between the sixth-level default valley voltage VT6 and the seventh-level default valley voltage VT7, that is, the initial absolute value VR0 is greater than or equal to the first absolute value VRa and less than or equal to the second absolute value VRb.

[0116] Exemplarily, as shown in FIG10C , the initial absolute value VR0 of the target read voltage of the seventh level may also be less than or equal to the absolute value of the difference between the sixth level default valley top voltage VT6 and the seventh level default valley top voltage VT7, and may also be greater than or equal to the absolute value of the difference between the seventh level default valley bottom voltage VB7 and the seventh level default valley top voltage VT7, that is, the initial absolute value VR0 is greater than or equal to the first absolute value VRa and less than or equal to the second absolute value VRb.

[0117] In this application, the term "first result corresponding to the target reading voltage" can be referred to as the "first first result", the term "first result corresponding to the predicted valley voltage" can be referred to as the "predicted first result", and the term "first result corresponding to the default valley voltage" can be referred to as the "default first result".

[0118] In some specific embodiments, the absolute value of the difference between the first boundary voltage and the second boundary voltage (hereinafter referred to as the target absolute value) is positively correlated with the offset degree, and the offset degree is the absolute value of the difference between the initial first result and the default first result.

[0119] For example, the larger the absolute value of the difference between the initial first result and the default first result, the larger the target absolute value. For example, if the difference between the initial first result Y1 and the default first result in FIG10D is smaller than the difference between the initial first result Y2 and the default first result in FIG10F , it can be seen that the target absolute value VR1 in FIG10D is smaller than the target absolute value VR2 in FIG10F .

[0120] In some specific embodiments, the relationship between the first boundary voltage and the second boundary voltage and the first result corresponding to the target read voltage includes the relationship between the initial first boundary voltage and the initial second boundary voltage and the first result corresponding to the target read voltage, the relationship between the adjustment value of the initial first boundary voltage and the initial second boundary voltage of the target read voltage and the first result corresponding to the target read voltage, and the first boundary voltage and the second boundary voltage of the target read voltage are generated based on the initial first boundary voltage and the initial second boundary voltage and the adjustment value.

[0121] In some specific embodiments, the first mapping function is also used to characterize the relationship between the level number of the target read voltage and / or the usage scenario of the memory device (such as a data retention scenario or a read disturb scenario) and the first result corresponding to the target read voltage.

[0122] Exemplarily, in a data retention scenario, as shown in Figures 10C and 10D, when the first result Y1 (for example, 500) corresponding to the target read voltage of the seventh level exceeds a threshold value (for example, 400), according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a strong left-shifted state, and according to the first result Y1 corresponding to the target read voltage of the seventh level, the first boundary voltage and the second boundary voltage of the target read voltage of the seventh level and the increased adjustment value are generated, wherein the adjustment value includes a first adjustment value and a second adjustment value, which are used to adjust the initial first boundary voltage and the initial second boundary voltage, respectively, and the first adjustment value and the second adjustment value are negative values ​​to indicate that the adjustment direction is a left-shifted direction, and the absolute value of the first adjustment value is less than the absolute value of the second adjustment value.

[0123] Exemplarily, in a read operation interference scenario, as shown in Figures 10A and 10B, when the first result Y1 (for example, 400) corresponding to the target read voltage of the seventh level exceeds the threshold value (for example, 300), according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a strong right-shifted state, and according to the first result Y1 corresponding to the target read voltage of the seventh level, the first boundary voltage and the second boundary voltage of the target read voltage of the seventh level and the increased adjustment value are generated, wherein the adjustment value includes a first adjustment value and a second adjustment value, which are used to adjust the initial first boundary voltage and the initial second boundary voltage, respectively, and the positive values ​​of the first adjustment value and the second adjustment value indicate that the adjustment direction is a left-shifted direction, and the absolute value of the first adjustment value is greater than the absolute value of the second adjustment value.

[0124] For example, based on the threshold voltage VT shift pattern of NAND under various conditions, a smaller range of left and right boundaries is preset for the current level (e.g., the seventh level) (for example, initial first boundary voltage {DMY, -5, -5, -8, -8, -12, -18, -20}, initial second boundary voltage {DMY, 10, 10, 5, 8, 8, 8, 8}, unit: 10mV). Based on the first result corresponding to the target read voltage of the current level (e.g., the seventh level), the initial first boundary voltage and the initial second boundary voltage of the level (e.g., the seventh level) are adjusted (e.g., the offset value and the shift direction are adjusted).

[0125] In some specific embodiments, data retention scenario: when, for example, the first result of the seventh level (for example, 500) exceeds the threshold value (for example, 400), according to the NAND characteristics, it can be considered that the threshold voltage VT of the storage cell is in a strong left-shifted state, and the initial first boundary voltage and the initial second boundary voltage of the first to seventh levels are readjusted to the first boundary voltage and the second boundary voltage of the first to seventh levels (for example: first boundary voltage {DMY, -5, -2, -2, -14, -34, -42, -50}, second boundary voltage {DMY, 5, 16, 5, 0, 0, 0, 0}, unit: 10mv).

[0126] In some specific embodiments, a read operation interference scenario: when, for example, the first result of the first level (e.g., 400) exceeds a threshold value (e.g., 300), it can be considered that the threshold voltage VT of the storage cell is in a strong right-shifted state according to the NAND characteristics, and the initial first boundary voltage and the initial second boundary voltage of the first level are readjusted to the first boundary voltage and the second boundary voltage of the first level (for example: the first boundary voltage L1{0} of the first level, the second boundary voltage L1{24} of the first level).

[0127] In some specific embodiments, according to the threshold voltage VT shift rule of NAND under various conditions, a larger left and right boundary is preset for the current level (e.g., the seventh level) (for example, smaller than the initial first boundary voltage {DMY, -5, -5, -8, -8, -12, -18, -20} and larger than the initial second boundary voltage {DMY, 10, 10, 5, 8, 8, 8, 8}, unit: 10 mv). According to the first result corresponding to the target read voltage of the current level (e.g., the seventh level), the initial first boundary voltage and the initial second boundary voltage of the level (e.g., the seventh level) are adjusted (for example, adjusting the offset value and the moving direction) to smaller left and right boundaries (for example, larger than the initial first boundary voltage {DMY, -5, -5, -8, -8, -12, -18, -20} and smaller than the initial second boundary voltage {DMY, 10, 10, 5, 8, 8, 8, 8}, unit: 10 mv).

[0128] In some specific embodiments, the offset of the next point is predicted based on the initial offset direction and step size. If the predicted offset exceeds the left and right boundaries and the iteration has not converged at this time, a reverse search is performed from the boundary until the target valley voltage position is found.

[0129] In some embodiments, the number of storage bits of a memory cell is multiple bits, and the multiple storage bits correspond to multiple levels of read voltages; the peripheral circuit is configured to: obtain an initial first boundary voltage and an initial second boundary voltage corresponding to a target level in the multiple levels; adjust the initial first boundary voltage and the initial second boundary voltage corresponding to the target level according to a first result corresponding to at least one codeword under a target read voltage of the target level, and obtain a first boundary voltage and a second boundary voltage corresponding to the target level; determine a target valley voltage corresponding to the target level based on whether the first result corresponding to the adjusted target read voltage of the target level satisfies a preset condition.

[0130] It should be noted that, here and below, the term "multi-level" includes a first level and a second level. The first level and the second level are used to distinguish between a high-level read voltage and a low-level read voltage in the multi-level read voltage corresponding to at least a portion of the page, where the low-level read voltage is lower than the high-level read voltage. For a memory cell containing multiple storage bits, a page corresponding to one storage bit may include one or more levels, and a single level may include one or more levels.

[0131] For example, referring to FIG8A , a memory device includes a lower page and an upper page, wherein the lower page corresponds to multiple levels, the multiple levels of the lower page include a first level and a third level, and the first level read voltage L1 is less than the third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first level of the lower page (the upper level read voltage of the lower page), and the first level read voltage L1 corresponds to the read voltage of the second level of the lower page (the lower level read voltage of the lower page).

[0132] For example, referring to FIG8B , a memory device includes a lower page, a middle page, and an upper page, wherein each page corresponds to multiple levels. The multiple levels of the lower page include a first level and a fifth level, where a first level read voltage L1 is less than a fifth level read voltage L5. The multiple levels of the middle page include a second level, a fourth level, and a sixth level, where a second level read voltage L2 and a fourth level read voltage L4 are both less than a sixth level read voltage L6. The multiple levels of the upper page include a third level and a seventh level, where a third level read voltage L3 is less than a seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 correspond to the first level read voltages of the lower, middle, and upper pages, respectively, and the first level read voltage L1, the second level read voltage L2, the fourth level read voltage L4, and the third level read voltage L3 correspond to the second level read voltages of the lower, middle, and upper pages, respectively.

[0133] Exemplarily, referring to Figure 8C, the memory device includes a lower page, a middle page, an upper page and an additional page, wherein each page corresponds to multiple levels, the multiple levels of the lower page include the second level, the eighth level and the fourteenth level, the second level read voltage L2 and the eighth level read voltage L8 are both less than the fourteenth level read voltage L14, the multiple levels of the middle page include the third level, the seventh level, the ninth level and the thirteenth level, the third level read voltage L3, the seventh level read voltage L7 and the ninth level read voltage L9 are all less than the thirteenth level read voltage L13, the multiple levels of the upper page include the fifth level, the tenth level, the twelfth level and the fifteenth level, the fifth level read voltage L5, the tenth level read voltage L10 and the twelfth level read voltage L12 are less than the fifteenth level read voltage L15, the multiple levels of the additional page include the first level, the fourth level, the sixth level and the eleventh level, the first level read voltage L1, the fourth level read voltage L4 and the sixth level read voltage L6 are less than the eleventh level read voltage L11. Here, the fourteenth-level read voltage L14, the thirteenth-level read voltage L13, the fifteenth-level read voltage L15 and the eleventh-level read voltage L11 correspond to the first-level read voltages of the lower page, middle page, upper page and extra page respectively, the second-level read voltage L2 and the eighth-level read voltage L8 correspond to the second-level read voltage of the lower page, the third-level read voltage L3, the seventh-level read voltage L7 and the ninth-level read voltage L9 correspond to the second-level read voltage of the middle page, the fifth-level read voltage L5, the tenth-level read voltage L10 and the twelfth-level read voltage L12 correspond to the second-level read voltage of the upper page, the first-level read voltage L1, the fourth-level read voltage L4 and the sixth-level read voltage L6 correspond to the second-level read voltage of the extra page. As shown in Figures 10G, 10H and 10I, in some specific embodiments, the peripheral circuit is configured to: obtain an initial first boundary voltage VLB0 and an initial second boundary voltage VRB0 of the target read voltage of the seventh level; adjust the initial first boundary voltage VLB0 and the initial second boundary voltage VRB0 of the target read voltage of the seventh level according to a first result Y4 corresponding to at least one codeword at the target read voltage of the seventh level to obtain a first boundary voltage VLB3 and a second boundary voltage VRB3 of the target read voltage of the seventh level; adjust the target read voltage of the seventh level multiple times and obtain the first result (multiple first results Y5 to Y12) corresponding to the adjusted target read voltage after each adjustment; determine the target valley voltage of the seventh level (seventh-level read voltage L7) based on the first result corresponding to the adjusted target read voltage of the seventh level being less than the first threshold; wherein, during the adjustment process, the direction of the current voltage adjustment is changed based on the target read voltage after one adjustment exceeding the range limited by the first boundary voltage VLB3 and the second boundary voltage VRB3.

[0134] For example, when the target read voltage after the first adjustment exceeds the range defined by the second boundary voltage VRB3 , the direction of the current voltage adjustment is changed.

[0135] In the first adjustment and the second adjustment, in the case of the second boundary voltage VRB3, although the first result Y5 corresponding to the target read voltage after the first adjustment is smaller than the first result Y6 corresponding to the target read voltage after the second adjustment, the target read voltage after the first adjustment exceeds the range defined by the second boundary voltage VRB3, the direction of the current voltage adjustment is changed, and the direction of the second adjustment is determined to be the correct direction. Based on the target read voltage after the second adjustment, the adjustment is continued in the left offset direction. After the left offset direction is adjusted, it is closer to the bottom position of the seventh-level read voltage L7, and the seventh-level read voltage L7 can be determined subsequently.

[0136] It should be noted that in the first adjustment and the second adjustment, when the second boundary voltage VRB3 does not exist or is not considered, since the first result Y5 corresponding to the target read voltage after the first adjustment is smaller than the first result Y6 corresponding to the target read voltage after the second adjustment, in the adjustment after the first adjustment and the second adjustment, the direction of the first adjustment is determined to be the correct direction, and the target read voltage after the first adjustment is used as a reference, and the adjustment is continued in the right offset direction. After the adjustment to the right offset direction, it is further away from the bottom position of the seventh-level read voltage L7, and the seventh-level read voltage L7 cannot be determined subsequently or an incorrect seventh-level read voltage L7 is determined.

[0137] In some embodiments, the range defined by the initial first boundary voltage and the initial second boundary voltage is smaller than the first preset range; the peripheral circuit is configured to: based on the first result corresponding to at least one codeword at the target read voltage of the target level being greater than the first preset value, expand the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

[0138] As shown in Figures 10G and 10H, in some specific embodiments, the peripheral circuit is configured as follows: based on the absolute value of the difference between the initial first boundary voltage VLB0 and the initial second boundary voltage VRB0 of the seventh level (hereinafter referred to as the initial absolute value VR0 of the seventh level) being less than the second absolute value VRb, and the first result Y4 corresponding to at least one codeword at the target read voltage of the seventh level being greater than a first preset value (for example, 400), the range defined by the initial first boundary voltage VLB0 and the initial second boundary voltage VRB0 of the seventh level is expanded to obtain the first boundary voltage VLB3 and the second boundary voltage VRB3 of the seventh level, and the absolute value of the difference between the first boundary voltage VLB3 and the second boundary voltage VRB3 of the seventh level (hereinafter referred to as the target absolute value VR3 of the seventh level) is greater than the initial absolute value VR0 of the seventh level.

[0139] In some embodiments, the usage scenario of the memory device includes a first scenario and a second scenario; the peripheral circuit is configured as: based on the usage scenario of the memory device being the first scenario, the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level are expanded by shifting both toward a decreasing direction; based on the usage scenario of the memory device being the second scenario, the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level are expanded by shifting both toward an increasing direction.

[0140] Exemplarily, in a data retention scenario, as shown in Figures 10G and 10H, when the first result Y4 (for example, 500) corresponding to the target read voltage of the seventh level exceeds a threshold value (for example, 400), according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a strong left-offset state, and according to the first result Y4 corresponding to the target read voltage of the seventh level, the first boundary voltage and the second boundary voltage of the target read voltage of the seventh level and the increased adjustment value are generated, wherein the adjustment value includes a first adjustment value and a second adjustment value, which are used to adjust the initial first boundary voltage and the initial second boundary voltage, respectively, and the first adjustment value and the second adjustment value are negative values ​​to indicate that the adjustment direction is a left-offset direction, the first adjustment value and the second adjustment value are both negative values, and the target absolute value VR3 of the seventh level is greater than the initial absolute value VR0 of the seventh level.

[0141] Exemplarily, in a read operation interference scenario, as shown in Figures 10J and 10K, when the first result Y4 (for example, 400) corresponding to the target read voltage of the seventh level exceeds the threshold value (for example, 300), according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a strong right-offset state, and according to the first result Y4 corresponding to the target read voltage of the seventh level, the first boundary voltage and the second boundary voltage of the target read voltage of the seventh level and the increased adjustment value are generated, wherein the adjustment value includes a first adjustment value and a second adjustment value, which are used to adjust the initial first boundary voltage and the initial second boundary voltage, respectively, and the positive values ​​of the first adjustment value and the second adjustment value indicate that the adjustment direction is a left-offset direction, the first adjustment value and the second adjustment value are both positive values, and the target absolute value VR3 of the seventh level is greater than the initial absolute value VR0 of the seventh level.

[0142] In some embodiments, the range defined by the initial first boundary voltage and the initial second boundary voltage is greater than the second preset range; the peripheral circuit is configured to: based on the first result corresponding to at least one codeword at the target read voltage of the target level being less than the second preset value, narrow the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

[0143] As shown in Figures 10L and 10M, in some specific embodiments, the peripheral circuit is configured as follows: based on the absolute value of the difference between the initial first boundary voltage VLB0 and the initial second boundary voltage VRB0 of the seventh level (hereinafter referred to as the initial absolute value VR0 of the seventh level) being greater than the second absolute value VRb, and the first result Y4 corresponding to at least one codeword at the target read voltage of the seventh level being greater than a first preset value (for example, 400), the range defined by the initial first boundary voltage VLB0 and the initial second boundary voltage VRB0 of the seventh level is narrowed to obtain the first boundary voltage VLB3 and the second boundary voltage VRB3 of the seventh level, and the absolute value of the difference between the first boundary voltage VLB3 and the second boundary voltage VRB3 of the seventh level (hereinafter referred to as the target absolute value VR3 of the seventh level) is less than the initial absolute value VR0 of the seventh level.

[0144] In some embodiments, the peripheral circuit is configured to: perform M first adjustments on the target read voltage to be adjusted with the first step length, and obtain M first results corresponding to the target read voltage after the M first adjustments; take the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; perform N second adjustments on the inflection point voltage with a second step length, and obtain N first results corresponding to the target read voltage after the N second adjustments; the second step length is smaller than the first step length; M and N are both positive integers greater than 1; and determine the target valley voltage based on whether the first results corresponding to the target read voltage after the N second adjustments satisfy the preset conditions.

[0145] In some specific embodiments, as shown in FIG10N , taking the target read voltage of the seventh stage as an example, the peripheral circuit is configured to obtain the knee voltage V4 through the following steps:

[0146] After obtaining the first result Y1 corresponding to the target read voltage, the target read voltage is adjusted for the first time using the first step length value (positive value) based on the target read voltage to obtain the first result Y1-2, and the first step length value (negative value) is used to adjust the target read voltage for the second time to obtain the first result Y1-3;

[0147] According to the first result Y1-2 being greater than the first result Y1-1 and the first result Y1-3 being less than the first result Y1-1, determining to use the first step length value (negative value) to adjust the target read voltage multiple times to obtain first results after the multiple adjustments (for example, first results Y1-4, Y1-5, Y1-6, Y1-7, or first results Y1-4 to Y1-9, or first results Y1-4 to Y1-10);

[0148] Based on at least one upward trend, it is determined that the first adjustment of the target read voltage is stopped. Here, an upward trend can be understood as a first result Y1-(N+1) obtained by performing the Nth first adjustment on the target read voltage using the first step length value (negative value) is less than the first result Y1-(N+2) obtained by performing the (N+1)th first adjustment on the target read voltage using the first step length value (negative value), and it is determined as an upward trend. For example, the first result Y7 is greater than the first result Y1-6, the first result Y1-8 is greater than the first result Y1-7, the first result Y1-9 is greater than the first result Y1-8, or the first result Y1-10 is greater than the first result Y1-9, and all of these can be determined as an upward trend.

[0149] The minimum value among the first results corresponding to the read voltages obtained after multiple first adjustments is determined as the inflection point value, and the target read voltage corresponding to the inflection point value is the inflection point voltage; for example, the minimum value among the multiple first results is the first result Y1-6, the first result Y1-6 is the inflection point value Yt, and the target read voltage corresponding to the inflection point value Yt is the inflection point voltage V4.

[0150] As shown in Figure 10N, in some embodiments, the first result corresponding to the target read voltage after multiple first adjustments includes a first adjacent value and a second adjacent value adjacent to the inflection point value, and the peripheral circuit is configured to: based on the difference between the first adjacent value and the inflection point value being less than the difference between the second adjacent value and the inflection point value, narrow the range of the multiple second adjustments to between the target read voltage corresponding to the first adjacent value and the inflection point voltage; and take the average value of the read voltage corresponding to the first adjacent value and the inflection point voltage, and based on the first result corresponding to the average value being less than the first threshold, use the average value as the target valley voltage; based on the first result corresponding to the average value being greater than or equal to the first threshold, continue to perform a second adjustment between the read voltage corresponding to the first adjacent value and the inflection point voltage until the first result corresponding to the adjusted target read voltage is less than the first threshold.

[0151] In some specific embodiments, as shown in FIG10N , taking the target read voltage of the seventh stage as an example, the peripheral circuit is configured to: after obtaining the knee point value Yt and the knee point voltage V4, perform at least one second adjustment using the second step value based on the knee point voltage V4 to obtain an adjusted target read voltage. The detailed process of performing at least one second adjustment using the second step value can be understood by referring to the detailed process of performing at least one first adjustment using the first step value in the above embodiment, wherein the first step value is greater than the second step value, and will not be further described here.

[0152] Here, the absolute value of the first step length is greater than the absolute value of the second step length; illustratively, the first step length value range is set to 50mV to 150mV, which can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV or 150mV, or the first step length value range is set to -50mV to -150mV, which can be -50mV, -60mV, -70mV, -80mV, -100mV, -120mV or -150mV. The second step length value range is set to 20mV to 50mV, which can be 20mV, 30mV, 40mV, 50mV, or the second step length value range is set to -20mV to -50mV, which can be -20mV, -30mV, -40mV, -50mV.

[0153] In some specific embodiments, as shown in FIG10N , taking the target read voltage of the seventh level as an example, the peripheral circuit is configured as follows: based on the difference between the first adjacent value (first result Y1-7) and the inflection point value Yt (first result Y1-6) being less than the difference between the second adjacent value (first result Y1-5) and the inflection point value Yt, the range of multiple second adjustments is narrowed to between the target read voltage V3 corresponding to the first adjacent value (first result Y1-7) and the inflection point voltage V4; and taking the average value of the read voltage V3 and the inflection point voltage V4 corresponding to the first adjacent value, and based on the first result Yv corresponding to the average value being less than the first threshold, taking the average value as the target valley voltage V2, and determining the target valley voltage V2 as the seventh level read voltage L7.

[0154] In some embodiments, the peripheral circuit is configured to: before performing M first adjustments on the target read voltage to be adjusted, generate a first threshold value based on a first result corresponding to at least one codeword at the target read voltage, the first threshold value being used to characterize the maximum value of the first result corresponding to the target valley voltage; based on the first result corresponding to the adjusted target read voltage being greater than or equal to the first threshold value, generate the next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage, until the first result corresponding to the adjusted target read voltage is less than the first threshold value; and after the first result corresponding to the adjusted target read voltage is less than the first threshold value, perform M first adjustments on the target read voltage to be adjusted with the first step length.

[0155] In some specific embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage as the initial target read voltage, adjust the initial target read voltage at least once, and obtain a first result corresponding to the adjusted target read voltage after each adjustment; determine the target valley voltage based on whether the first result corresponding to the adjusted target read voltage meets a preset condition; generate a predicted valley voltage of the second stage based on the determined target valley voltage of the first stage; and perform a second read operation on at least one codeword based on the determined target valley voltage of the first stage and the predicted valley voltage of the second stage.

[0156] For example, as shown in Figures 9A and 9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in Figure 9D ) as the initial target read voltage of the fifth stage, adjust the predicted valley voltage of the fifth stage at least once, and obtain a first result Y3 corresponding to the adjusted target read voltage (V22 shown in Figure 9D ) after each adjustment; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result corresponding to the adjusted target read voltage being less than or equal to a second preset value. As shown in Figures 9B and 9E , and Figures 9C and 9F , the sixth-stage read voltage L6 and the seventh-stage read voltage L7 are determined in a manner similar to that used to determine the fifth-stage read voltage L5.

[0157] A second read operation is performed on the lower page of at least one codeword based on the determination of the fifth-level read voltage L5 and the predicted valley voltage of the first level (V4 shown in Figure 9A), a second read operation is performed on the middle page of at least one codeword based on the determination of the sixth-level read voltage L6, the predicted valley voltage of the fourth level (V4 shown in Figure 9B) and the predicted valley voltage of the second level (V5 shown in Figure 9B), and a second read operation is performed on the upper page of at least one codeword based on the determination of the seventh-level read voltage L7 and the predicted valley voltage of the third level (V4 shown in Figure 9C).

[0158] In some specific embodiments, the peripheral circuit is configured to: generate a predicted valley voltage of the second stage with the largest read voltage among the multiple second stages of each page based on the predicted valley voltage of the first stage / the target valley voltage of the first stage; and sequentially generate predicted valley voltages of the second stages with smaller read voltages adjacent to the second stage with the larger read voltage among the multiple second stages of each page, until a predicted valley voltage of each second stage of each page is generated.

[0159] For example, as shown in Figures 9B and 9E , the middle page includes a first stage (i.e., the sixth stage) and multiple second stages (i.e., the fourth and second stages); the peripheral circuit is configured to: generate a predicted valley voltage for the fourth stage of the middle page based on the predicted valley voltage of the sixth stage of the middle page / determine the target valley voltage of the sixth stage; and generate a predicted valley voltage for the second stage of the middle page based on the predicted valley voltage of the fourth stage of the middle page. As shown in Figures 9A and 9D , a predicted valley voltage for the first stage of the lower page is generated based on the predicted valley voltage of the fifth stage of the lower page / determine the target valley voltage of the fifth stage. As shown in Figures 9C and 9F , a predicted valley voltage for the third stage of the upper page is generated based on the predicted valley voltage of the seventh stage of the upper page / determine the target valley voltage of the seventh stage.

[0160] In some embodiments, in the scenario of a QLC type memory cell, the number of storage bits of the memory cell includes four bits, and the corresponding storage states include the 0th state to the 15th state. The four storage bits corresponding to the 16 states are respectively stored in the lower page, the middle page, the upper page, and the extra page. The lower page includes a first level (i.e., the fourteenth level) and multiple second levels (i.e., the eighth level and the second level); the middle page includes a first level (i.e., the thirteenth level) and multiple second levels (i.e., the ninth level, the seventh level, and the third level); the upper page includes a first level (i.e., the fifteenth level) and multiple second levels (i.e., the twelfth level, the tenth level, and the fifth level); and the extra page includes a first level (i.e., the eleventh level) and multiple second levels (i.e., the sixth level, the fourth level, and the first level).

[0161] In some embodiments, the peripheral circuit is configured to: generate a predicted valley voltage of the eighth level of the lower page according to the predicted valley voltage of the fourteenth level / determine the target valley voltage of the fourteenth level, generate a predicted valley voltage of the second level of the lower page according to the predicted valley voltage of the eighth level of the lower page; generate a predicted valley voltage of the ninth level of the middle page according to the predicted valley voltage of the thirteenth level / determine the target valley voltage of the thirteenth level, generate a predicted valley voltage of the seventh level of the middle page according to the predicted valley voltage of the ninth level of the middle page, generate a predicted valley voltage of the third level of the middle page according to the predicted valley voltage of the seventh level of the middle page; generate a predicted valley voltage of the eighth level of the upper page according to the predicted valley voltage of the fifteenth level of the upper page The predicted valley voltage of the 12th level of the upper page is predicted / determined, and the target valley voltage of the 15th level is generated. The predicted valley voltage of the 12th level of the upper page is generated based on the predicted valley voltage of the 12th level of the upper page. The predicted valley voltage of the 5th level of the upper page is generated based on the predicted valley voltage of the 10th level of the upper page. The predicted valley voltage of the 6th level of the additional page is generated based on the predicted valley voltage of the 11th level of the additional page. The predicted valley voltage of the 4th level of the additional page is generated based on the predicted valley voltage of the 6th level of the additional page. The predicted valley voltage of the 1st level of the additional page is generated based on the predicted valley voltage of the 4th level of the additional page. In this way, 15 voltages required for reading QLC type memory cells are generated, for example, the 15 voltages are the 15 predicted valley voltages, or a portion of the 15 voltages are the target valley voltages and the other portion are the predicted valley voltages generated based on the target valley voltages.

[0162] In some embodiments, the first boundary voltage is less than the second boundary voltage, and the peripheral circuit is configured to: adjust the target read voltage in an increasing direction starting from the first boundary voltage based on the target read voltage generated after the next adjustment being less than or equal to the first boundary voltage; or adjust the read voltage in a decreasing direction starting from the second boundary voltage based on the target read voltage generated after the next adjustment being greater than or equal to the second boundary voltage.

[0163] As shown in FIG. 10I , after the first adjustment, the target read voltage exceeds the range defined by the first boundary voltage VLB3 or the second boundary voltage VRB3 , and the direction of the current voltage adjustment is changed.

[0164] In the first adjustment and the second adjustment, in the case of the second boundary voltage VRB3, although the first result Y5 corresponding to the target read voltage after the first adjustment is smaller than the first result Y6 corresponding to the target read voltage after the second adjustment, the target read voltage after the first adjustment exceeds the range defined by the second boundary voltage VRB3, the direction of the current voltage adjustment is changed, and the direction of the second adjustment is determined to be the correct direction. Based on the target read voltage after the second adjustment, the adjustment is continued in the left offset direction. After the left offset direction is adjusted, it is closer to the bottom position of the seventh-level read voltage L7, and the seventh-level read voltage L7 can be determined subsequently.

[0165] In the seventh and eighth adjustments, in the case of the first boundary voltage VLB3, the target read voltage after the eighth adjustment exceeds the range limited by the first boundary voltage VLB3, the direction of the current voltage adjustment is changed, and the opposite direction of the eighth adjustment direction is determined to be the correct direction. With the first boundary voltage VLB3 as the reference, the adjustment is made in the right offset direction. After the right offset direction is adjusted, it is closer to the bottom position of the seventh-level read voltage L7, and the seventh-level read voltage L7 can be determined subsequently.

[0166] In some embodiments, the peripheral circuit is configured to: take the adjusted target read voltage that is less than the first threshold value for the first time among the multiple first results corresponding to the target read voltage after multiple adjustments as the near-valley point voltage; in the process of performing multiple first adjustments to the near-valley point voltage with the first step length, start from the near-valley point voltage and adjust in the first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the first direction is greater than the first threshold value; start from the near-valley point voltage and adjust in a second direction opposite to the first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the second direction is greater than the first threshold value.

[0167] In some embodiments, the peripheral circuit is configured to: generate a first threshold value based on the first result corresponding to the target read voltage and the first mapping function; wherein the first mapping function is used to characterize the relationship between the first threshold value and the first result corresponding to the target read voltage; generate a predicted value of the target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function, and the order number of the target order; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment, the order number of the target order, and the predicted value of the target valley voltage of the target order.

[0168] In some specific embodiments, the first mapping function is used to characterize the relationship between the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage relative to the target read voltage of the first stage and the predicted valley voltage of the second stage, and / or the relationship between the usage scenario of the memory device and the corresponding first result under the target read voltage.

[0169] Exemplarily, in a data retention scenario, when the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage of the first stage exceeds a threshold value, according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a relatively strong left-shifted state, and according to the predicted valley voltage of the first stage / the target valley voltage of the first stage and the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage, the predicted valley voltage of the second stage can be adjusted based on the first mapping function, wherein, relative to the target read voltage of the second stage, the predicted valley voltage of the second stage is in a relatively strong left-shifted state.

[0170] For example, in a read operation interference scenario, when the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage exceeds a threshold value, according to the characteristics of the memory device, it can be given priority to consider that the threshold voltage VT of the storage cell of the memory device is in a stronger right-shifted state, and the predicted valley voltage of the second stage can be adjusted based on the first mapping function according to the predicted valley voltage of the first stage / the target valley voltage of the first stage and the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage.

[0171] In some specific embodiments, the predicted valley voltage of the first stage may refer to a predicted read voltage predicted based on a first result corresponding to a target read voltage of the first stage and a usage scenario of the memory device. The predicted valley voltage of the first stage is obtained by querying a preset mapping table based on the first result (here, the first result corresponding to the target read voltage of the first stage). The preset mapping table stores empirical values ​​of the predicted valley voltage of the first stage corresponding to the first result, which are obtained through a large number of simulation experiments.

[0172] In some specific embodiments, the second mapping function is used to characterize the relationship between the difference between the first result corresponding to the target read voltage of the first stage and the first result threshold configured when the memory device leaves the factory and the predicted valley voltage of the first stage, the stage number of the predicted valley voltage of the first stage, and / or the relationship between the usage scenario of the memory device and the predicted valley voltage of the first stage.

[0173] Exemplarily, in a data retention scenario, when the first result corresponding to the target read voltage of the first stage exceeds a threshold value (e.g., 400), based on the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a relatively strong left-shifted state. According to the first result corresponding to the target read voltage of the first stage, the predicted valley voltage of the first stage can be adjusted based on the second mapping function, wherein, relative to the target read voltage of the first stage, the predicted valley voltage of the first stage is in a relatively strong left-shifted state.

[0174] For example, in a read operation interference scenario, when the first result corresponding to the target read voltage of the first stage exceeds a threshold value (for example, 300), according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a relatively strong left-shifted state. According to the first result corresponding to the target read voltage of the first stage, the predicted valley voltage of the first stage can be adjusted based on the second mapping function, wherein, relative to the target read voltage of the first stage, the predicted valley voltage of the first stage is in a relatively strong right-shifted state.

[0175] In some embodiments, the peripheral circuit is configured as follows: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in two opposite directions with a second step size, in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed, and the third boundary voltage and the fourth boundary voltage are determined based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in each direction, if the first result corresponding to the target read voltage after one adjustment is lower than the second threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference from the reference value is less than the third threshold is greater than a preset number, the adjustment is stopped and the read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

[0176] As shown in FIG10I , in the seventh and eighth adjustments, in the case of the first boundary voltage VLB3, if the target read voltage after the eighth adjustment exceeds the range defined by the first boundary voltage VLB3, the first boundary voltage VLB3 is determined to be the third boundary voltage VLB4. The direction of the current voltage adjustment is changed, and the opposite direction of the eighth adjustment is determined to be the correct direction. The voltage before the seventh adjustment is used as a reference, and the adjustment is performed in a rightward offset direction. An upward trend is determined through the ninth, tenth, and eleventh adjustments, and the voltage after the eleventh adjustment is determined to be the fourth boundary voltage VRB4. In multiple adjustments between the third boundary voltage VLB4 and the fourth boundary voltage VRB4, if the first result corresponding to the target read voltage after one adjustment is lower than the second threshold, or if the smallest first result among the multiple first results corresponding to the multiple target read voltages after multiple adjustments is used as the reference value, and if the number of the remaining multiple first results whose differences from the reference value are less than the third threshold is greater than a predetermined number, the adjustment is stopped and the read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

[0177] As shown in FIG10I , exemplarily, adjacent to the voltage before the seventh adjustment are the voltage after the seventh adjustment and the voltage before the sixth adjustment, and the seventh-level reading voltage L7 can be the average value of the average values ​​of the voltage after the seventh adjustment and the voltage before the sixth adjustment.

[0178] In some embodiments, the peripheral circuit is configured as follows: during the adjustment process in each direction, the adjusted target read voltage corresponding to the total statistical number equal to the preset number is used as the third boundary voltage and the fourth boundary voltage respectively; during the adjustment process in each direction, if the third boundary voltage and the fourth boundary voltage have been determined, the first result corresponding to the target read voltage after the last adjustment is obtained, and the target read voltage after the last adjustment is the average value of the third boundary voltage and the fourth boundary voltage; the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

[0179] In some embodiments, the memory cell array includes memory cells having multiple storage bits, and the multiple storage bits correspond to multiple pages respectively; at least some of the pages correspond to multiple stages, and the multiple stages include a first stage and a second stage, and the read voltage of the second stage is lower than the read voltage of the first stage; the peripheral circuit is configured to: according to the target valley voltage corresponding to the stage number belonging to the first stage under the determined target valley voltage, use the determined target valley voltage to generate a target valley voltage for the second stage in the multiple stages and / or target valley voltages of other first stages with lower corresponding read voltages.

[0180] In some specific embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; obtain a first result corresponding to the initial target read voltage; determine that the initial target read voltage is the target valley voltage based on the first result corresponding to the initial target read voltage satisfying a preset condition; and perform a second read operation on at least one codeword based on the valley target voltage.

[0181] In some specific embodiments, the preset condition can be that the first result corresponding to the initial target read voltage is less than or equal to a second preset value; the second preset value serves as a judgment threshold for determining the target valley voltage. That is, when the first result is less than or equal to the second preset value, it indicates that when the read voltage corresponding to the first result is used as the target valley voltage, the read result has a low error rate and high reliability. Here, the size of the second preset value is related to the type and storage density of the memory device. The second preset value can be an empirical value; it can also be a default value configured when the memory device is shipped, which is obtained through a large number of simulation experiments before the memory device is shipped. Exemplarily, the second preset value is set in the range of 5 to 30. More specifically, the second preset value can be 5, 10, 15, 20, 25, or 30.

[0182] For example, as shown in FIG9A and FIG9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in FIG9D ) as the initial target read voltage of the fifth stage, obtain a first result Y2 corresponding to the initial target read voltage of the fifth stage; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result Y2 corresponding to the initial target read voltage of the fifth stage being less than or equal to the second preset value. A similar method is used to determine the fifth-stage read voltage L5 to determine the first-stage read voltage L1.

[0183] For example, as shown in FIG9B and FIG9E , the peripheral circuit is configured to: use the predicted valley voltage of the sixth stage (V2 shown in FIG9E ) as the initial target read voltage of the sixth stage, obtain a first result Y2 corresponding to the initial target read voltage of the sixth stage; and determine the initial target read voltage of the sixth stage as the sixth-stage read voltage L6 based on the first result Y2 corresponding to the initial target read voltage of the sixth stage being less than or equal to the second preset value. A similar method is used to determine the sixth-stage read voltage L6 to determine the fourth-stage read voltage L4 and the second-stage read voltage L2.

[0184] For example, as shown in FIG9C and FIG9F , the peripheral circuit is configured to: use the predicted valley voltage of the seventh stage (V2 shown in FIG9F ) as the initial target read voltage of the seventh stage, obtain a first result Y2 corresponding to the initial target read voltage of the seventh stage; and determine the initial target read voltage of the seventh stage as the seventh-stage read voltage L7 based on the first result Y2 corresponding to the initial target read voltage of the seventh stage being less than or equal to the second preset value. A similar method is used to determine the seventh-stage read voltage L7 to determine the third-stage read voltage L3.

[0185] A second read operation is performed on the lower page of at least one codeword based on determining the fifth-level read voltage L5 and determining the first-level read voltage L1, a second read operation is performed on the middle page of at least one codeword based on determining the sixth-level read voltage L6, determining the fourth-level read voltage L4 and the second-level read voltage L2, and a second read operation is performed on the upper page of at least one codeword based on determining the seventh-level read voltage L7 and determining the third-level read voltage L3.

[0186] In some specific embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; adjust the initial target read voltage at least once, and obtain a first result corresponding to the adjusted target read voltage after each adjustment; determine that the adjusted target read voltage is the target valley voltage based on whether the first result corresponding to the adjusted target read voltage meets a preset condition; and perform a second read operation on at least one codeword based on the target valley voltage.

[0187] In some specific embodiments, at least one adjustment can be a first adjustment; the first adjustment can be understood as a larger adjustment, with the first adjustment amplitude being greater than the second adjustment amplitude. In some specific embodiments, the step size of the first adjustment is set to range from 50mV to 150mV. Exemplarily, the first adjustment step size can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV. Exemplarily, as shown in Figures 9A and 9D, a first adjustment is performed on the predicted valley voltage V2 of the fifth stage to obtain an adjusted target read voltage V22 of the fifth stage. A second voltage difference ΔV2 exists between the predicted valley voltage V2 of the fifth stage and the adjusted target read voltage V22 of the fifth stage. The magnitude of the second voltage difference ΔV2 is the step size of the first adjustment. The step size of the first adjustment is greater than the step size of the third adjustment, i.e., the second voltage difference ΔV2 is greater than the first voltage difference ΔV1.

[0188] For example, as shown in Figures 9A and 9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in Figure 9D ) as the initial target read voltage of the fifth stage, adjust the predicted valley voltage of the fifth stage at least once, and obtain a first result Y3 corresponding to the adjusted target read voltage (V22 shown in Figure 9D ) after each adjustment; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result corresponding to the adjusted target read voltage being less than or equal to a second preset value. A similar method is used to determine the fifth-stage read voltage L5 for determining the first-stage read voltage L1. As shown in Figures 9B and 9E , and Figures 9C and 9F , a similar method is used to determine the fifth-stage read voltage L5 for determining the sixth-stage read voltage L6, the fourth-stage read voltage L4, and the second-stage read voltage L2, and the seventh-stage read voltage L7 and the third-stage read voltage L3.

[0189] A second read operation is performed on the lower page of at least one codeword based on determining the fifth-level read voltage L5 and determining the first-level read voltage L1, a second read operation is performed on the middle page of at least one codeword based on determining the sixth-level read voltage L6, determining the fourth-level read voltage L4 and the second-level read voltage L2, and a second read operation is performed on the upper page of at least one codeword based on determining the seventh-level read voltage L7 and determining the third-level read voltage L3.

[0190] In some embodiments, the peripheral circuit is configured to: read the stored data of at least one codeword at a first read voltage to obtain a second result; read the stored data of at least one codeword at a second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0191] For example, as shown in Figures 9A and 9D, data stored in the lower page of the storage cells in at least one codeword are read at a first read voltage (V0 shown in Figure 9D), and the storage cells whose threshold voltage is less than the first read voltage are marked as bit 1, and the storage cells whose threshold voltage is greater than the first read voltage are marked as bit 0, to obtain a second result.

[0192] For example, as shown in Figures 9A and 9D, data stored in the lower page of the storage cells in at least one codeword are read at a second read voltage (V1 shown in Figure 9D), and the storage cells whose threshold voltage is less than the second read voltage are marked as bit 1, and the storage cells whose threshold voltage is greater than the second read voltage are marked as bit 0, to obtain a third result.

[0193] Exemplarily, the second result and the third result are subjected to an XOR operation to obtain a fourth result. It should be noted that the XOR operation is one of the basic logical operations. In binary, if two binary numbers at the same position are the same, the result is "0", and if two binary numbers at the same position are different, the result is "1" (i.e., the same is 0, and different is 1).

[0194] Exemplarily, a bit that is 1 in the fourth result indicates that the data read from a storage cell in at least one codeword at the first read voltage and at the second read voltage are different, and a bit that is 0 in the fourth result indicates that the data read from a storage cell in at least one codeword at the first read voltage and at the second read voltage are the same. In other words, the number of bits that are 1 in the fourth result indicates the number of bits of the at least one codeword that are flipped between the first read voltage and the second read voltage, and the number of bits that are 0 in the fourth result indicates the number of bits of the at least one codeword that are identical between the first read voltage and the second read voltage. Because a single-stage read mode is employed, i.e., both read operations read a single bit of data stored in the lower page of the storage cell in the at least one codeword, the number of bits that are 1 in the fourth result indicates the number of storage cells of the at least one codeword that are flipped between the first read voltage and the second read voltage, and this number is recorded as the first result corresponding to the first read voltage. For example, at least one codeword corresponds to a first result Y1 at the target read voltage of the first stage (V0 shown in Figure 9D), at least one codeword corresponds to a first result Y2 at the target adjusted read voltage of the first stage (V2 shown in Figure 9D), and at least one codeword corresponds to a first result Y3 at the adjusted target read voltage of the first stage (V22 shown in Figure 9D).

[0195] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0196] Exemplarily, the stored data of at least one codeword read at a first read voltage (i.e., the second result) is stored in the first latch, the stored data of at least one codeword read at a second read voltage (i.e., the third result) is stored in the second latch, and the data after performing an XOR operation on the second result and the third result (i.e., the fourth result) is stored in the third latch.

[0197] On the first aspect, in each memory device provided by the embodiments of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted is reduced; the first boundary voltage and the second boundary voltage are generated based on the first result corresponding to the target read voltage, and have a dynamic first threshold, and the iterative convergence speed of determining the target valley voltage is faster; the process of obtaining the first result converges inside the memory device, does not occupy the space of, for example, a memory controller, and has a low degree of dependence on, for example, a memory controller; the process of obtaining the predicted valley voltage / target valley voltage based on the first result is completed in the memory device; the transmission time of the output port is reduced; and it is suitable for MLC, TLC or QLC type memory devices.

[0198] In a second aspect, an embodiment of the present application provides a memory system, as shown in Figures 11 and 12, the memory system 102 includes: one or more memory devices 104 as provided in the first aspect; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0199] As shown in FIG11 , in some embodiments, a memory system 102 is coupled to a host, responding to host instructions and performing various feedback operations. Memory system 102 may include a memory controller 106 and a memory device 104. Memory controller 106 is configured to control memory device 104 to perform operations such as read, write, and erase. Memory controller 106 and memory device 104 may also be coupled in any suitable manner.

[0200] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106. The host interface 1061 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole. The specific steps executed by the memory controller described above are mainly executed and completed by the control unit 1063 here. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The ROM 1069 generally contains the firmware or firmware program code of the memory controller 106, which is used to initialize and operate the various components of the memory controller. The RAM 1070 is generally used to cache data. The error correction module 1064 can further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0201] The garbage collection module 1065 is used to read valid data from some storage blocks, rewrite it, and then mark these storage blocks as new backup storage blocks after the storage space of the memory device reaches a certain threshold. Garbage collection is generally implemented in three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to the target storage block. At this point, all data in the source storage block becomes invalid data, and the source storage block is marked and can be used as a new backup storage block. The wear leveling module 1066 is used to maintain a balanced wear (number of erases) on each storage block in the memory system through data statistics and algorithms. Wear leveling is generally implemented in two steps: selecting a source storage block containing cold data; reading valid data from the source storage block and writing it to a storage block with a relatively high erase count. At this point, the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0202] In some embodiments, the memory controller is configured to: before performing a read operation on data stored in the memory device, send a first instruction instructing to obtain information representing the valley voltage; the memory device is configured to: receive the first instruction, obtain information representing the valley voltage, and send the obtained information representing the valley voltage to the memory controller; the memory controller is further configured to: use the valley voltage in the information representing the valley voltage to control the memory device to perform a read operation, and perform an error correction decoding operation on the read result of the read operation.

[0203] In some embodiments, a memory device 104 includes a memory cell array comprising a plurality of memory cells, wherein a predetermined number of memory cells form a codeword; a peripheral circuit of the memory device 104 is coupled to the memory cell array and configured to perform the following steps: obtaining a first result corresponding to at least one codeword at a target read voltage; the first result including a number of bits flipped in two read results of the at least one codeword at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage being less than a predetermined voltage; generating a first threshold value based on the first result corresponding to the target read voltage; the first threshold value being used to represent the first result corresponding to a maximum value within a valid range of predicted valley voltages; adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; and determining a valley voltage based on whether a relationship between the first result corresponding to the adjusted target read voltage and the first threshold value satisfies a first predetermined condition or whether the first results corresponding to multiple adjusted target read voltages satisfy a second predetermined condition; and using the valley voltage as a read voltage when performing a read operation on the at least one codeword. In some embodiments, the memory controller 106 is configured to control the memory device 104 to perform a first read operation on the at least one codeword.

[0204] On the second aspect, in the memory system provided by the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted between the memory device and the memory controller is reduced; the first boundary voltage and the second boundary voltage are generated according to the first result corresponding to the target read voltage, and have a dynamic first threshold, and the iterative convergence speed of determining the valley voltage is faster; the process of obtaining the first result converges inside the memory device, does not occupy the space of the memory controller, and has a low degree of dependence on the memory controller; the process of obtaining the predicted valley voltage / determining the valley voltage based on the first result is completed in the memory device; the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller are reduced, the iteration time of the error correction decoding algorithm of the memory controller is saved, and the error correction decoding speed is faster; it is suitable for MLC, TLC or QLC type memory systems.

[0205] In a third aspect, an embodiment of the present application provides a memory controller, which includes a control unit and is configured to: generate a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of storage cells in at least one memory device coupled to the memory controller under a target read voltage; the first result represents the number of bits flipped in the two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the target read voltage is adjusted at least once, and the first result corresponding to the adjusted target read voltage is obtained after each adjustment; during the adjustment process, the direction of the current voltage adjustment is changed based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; based on the first result corresponding to the adjusted target read voltage meeting a preset condition, a valley voltage is determined, and the valley voltage is used as the read voltage when performing a read operation on at least one codeword.

[0206] In some embodiments, the number of storage bits of a storage unit is multiple bits, and the multiple storage bits correspond to multiple levels of read voltages; the control unit is configured to: obtain an initial first boundary voltage and an initial second boundary voltage corresponding to a target level in the multiple levels; adjust the initial first boundary voltage and the initial second boundary voltage corresponding to the target level according to a first result corresponding to at least one codeword under the target read voltage of the target level, and obtain the first boundary voltage and the second boundary voltage corresponding to the target level; determine the valley voltage corresponding to the target level based on whether the first result corresponding to the adjusted target read voltage of the target level meets a preset condition.

[0207] In some embodiments, the range defined by the initial first boundary voltage and the initial second boundary voltage is smaller than the first preset range; the control unit is configured to: based on the first result corresponding to at least one codeword at the target read voltage of the target level being greater than the first preset value, expand the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

[0208] In some embodiments, the usage scenario of the memory device includes a first scenario and a second scenario; the control unit is configured to: based on the usage scenario of the memory device being the first scenario, expand the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level by shifting both in a decreasing direction; based on the usage scenario of the memory device being the second scenario, expand the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level by shifting both in an increasing direction.

[0209] In some embodiments, the range defined by the initial first boundary voltage and the initial second boundary voltage is greater than the second preset range; the memory controller is configured to: based on the first result corresponding to the target read voltage of the target level of at least one codeword being less than the second preset value, narrow the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

[0210] In some embodiments, the control unit is configured to: perform M first adjustments on the target read voltage to be adjusted with the first step length, and respectively obtain M first results corresponding to the target read voltage after the M first adjustments; take the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; perform N second adjustments on the inflection point voltage with a second step length, and respectively obtain N first results corresponding to the target read voltage after the N second adjustments; the second step length is smaller than the first step length; M and N are both positive integers greater than 1; and determine the valley voltage based on whether the first results corresponding to the target read voltage after the N second adjustments obtained meet the preset conditions.

[0211] In some embodiments, the control unit is configured to: before performing M first adjustments on the target read voltage to be adjusted, generate a first threshold value based on the first result corresponding to at least one codeword at the target read voltage, the first threshold value being used to characterize the maximum value of the first result corresponding to the near-bottom voltage; based on the first result corresponding to the adjusted target read voltage being greater than or equal to the first threshold value, generate the next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage, until the first result corresponding to the adjusted target read voltage is less than the first threshold value; and after the first result corresponding to the adjusted target read voltage is less than the first threshold value, perform M first adjustments on the target read voltage to be adjusted with the first step length.

[0212] In some embodiments, the first boundary voltage is less than the second boundary voltage, and the control unit is configured to: adjust the read voltage in an increasing direction starting from the first boundary voltage based on the generated target read voltage after the next adjustment being less than or equal to the first boundary voltage; or adjust the read voltage in a decreasing direction starting from the second boundary voltage based on the generated target read voltage after the next adjustment being greater than or equal to the second boundary voltage.

[0213] In some embodiments, the control unit is configured to: take the adjusted target read voltage that is less than the first threshold value for the first time among the multiple first results corresponding to the target read voltage after multiple adjustments as the near-valley point voltage; in the process of performing multiple first adjustments to the near-valley point voltage with the first step length, start from the near-valley point voltage and adjust in the first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the first direction is greater than the first threshold value; start from the near-valley point voltage and adjust in a second direction opposite to the first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the second direction is greater than the first threshold value.

[0214] In some embodiments, the control unit is configured to: generate a first threshold value based on the first result corresponding to the target read voltage and the first mapping function; wherein the first mapping function is used to characterize the relationship between the first threshold value and the first result corresponding to the target read voltage; generate a predicted value of the target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function, and the order number of the target order; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment, the order number of the target order and the predicted value of the valley voltage of the target order.

[0215] In some embodiments, the control unit is configured to: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjust in two opposite directions with a second step size, and in the process of adjusting in each direction, when the first result corresponding to the target reading voltage after the next adjustment is greater than the first result corresponding to the reading voltage after the previous adjustment, perform a statistical analysis showing an upward trend, and determine the third boundary voltage and the fourth boundary voltage based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in each direction, if the first result corresponding to the target reading voltage after one adjustment is lower than the second threshold, or the smallest first result among the multiple first results corresponding to the target reading voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference from the reference value is less than the third threshold is greater than the preset number, stop the adjustment and use the reading voltage corresponding to the smallest first result among the multiple first results as the valley voltage.

[0216] In some embodiments, the control unit is configured as follows: during the adjustment process in each direction, the adjusted target read voltages corresponding to the total statistical number of times equal to the preset number are respectively used as the third boundary voltage and the fourth boundary voltage; during the adjustment process in each direction, if the third boundary voltage and the fourth boundary voltage have been determined, the first result corresponding to the target read voltage after the last adjustment is obtained, and the target read voltage after the last adjustment is the average value of the third boundary voltage and the fourth boundary voltage; the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the valley voltage.

[0217] In some embodiments, the memory cell array includes memory cells having multiple storage bits, and the multiple storage bits correspond to multiple pages respectively; at least some of the pages correspond to multiple stages, and the multiple stages include a first stage and a second stage, and the read voltage of the second stage is lower than the read voltage of the first stage; the control unit is configured to: according to the determined valley voltage, the corresponding stage number belongs to the valley voltage of the first stage, and use the determined valley voltage to generate the valley voltage of the second stage in the multiple stages and / or other valley voltages of the first stage with lower corresponding read voltages.

[0218] On the third aspect, in the memory controller provided by the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted between the memory device and the memory controller is reduced; the first boundary voltage and the second boundary voltage are generated according to the first result corresponding to the target read voltage, and have a dynamic first threshold, and the iterative convergence speed of determining the valley voltage is faster; the process of obtaining the first result converges inside the memory device, does not occupy the space of the memory controller, and has a low degree of dependence on the memory controller; compared with in the memory device, the process of obtaining the predicted valley voltage / determining the valley voltage according to the first result in the memory controller is more efficient; the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller are reduced, the iteration time of the error correction decoding algorithm of the memory controller is saved, and the error correction decoding speed is faster; it is suitable for MLC, TLC or QLC type memory systems.

[0219] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, the operating method comprising: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of memory cells in the memory device under a target read voltage; the first result comprises a representation of the number of bits flipped in two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; determining a valley voltage based on the first result corresponding to the adjusted target read voltage satisfying a preset condition, the valley voltage being used as the read voltage when performing a read operation on at least one codeword.

[0220] In some embodiments, the operating method includes: obtaining an initial first boundary voltage and an initial second boundary voltage corresponding to a target level in multiple levels; adjusting the initial first boundary voltage and the initial second boundary voltage corresponding to the target level according to a first result corresponding to at least one codeword under a target read voltage of the target level to obtain a first boundary voltage and a second boundary voltage corresponding to the target level; determining a valley voltage corresponding to the target level based on whether the first result corresponding to the adjusted target read voltage of the target level meets a preset condition; wherein the number of storage bits of the storage unit is multiple bits, and multiple storage bits correspond to multiple levels of read voltages.

[0221] In some embodiments, the operating method includes: based on the first result corresponding to at least one codeword at the target read voltage of the target level being greater than a first preset value, expanding the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level; wherein the range defined by the initial first boundary voltage and the initial second boundary voltage is smaller than the first preset range.

[0222] In some embodiments, the operating method includes: based on the usage scenario of the memory device being a first scenario, expanding the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level by shifting both toward a decreasing direction; based on the usage scenario of the memory device being a second scenario, expanding the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level by shifting both toward an increasing direction; wherein the usage scenarios of the memory device include the first scenario and the second scenario.

[0223] In some embodiments, the operating method includes: based on the first result corresponding to at least one codeword at the target read voltage of the target level being less than a second preset value, narrowing the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level; wherein the range defined by the initial first boundary voltage and the initial second boundary voltage is greater than the second preset range.

[0224] In some embodiments, the operating method includes: performing M first adjustments on the target read voltage to be adjusted with a first step length, and respectively obtaining M first results corresponding to the target read voltage after the M first adjustments; taking the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the target read voltage after the N second adjustments; the second step length is smaller than the first step length; M and N are both positive integers greater than 1; and determining the valley voltage based on whether the first results corresponding to the target read voltage after the N second adjustments obtained meet the preset conditions.

[0225] In some embodiments, the operating method includes: before performing M first adjustments on the target read voltage to be adjusted, generating a first threshold value based on a first result corresponding to at least one codeword at the target read voltage, the first threshold value being used to characterize the maximum value of the first result corresponding to the near-valley voltage; based on the first result corresponding to the adjusted target read voltage being greater than or equal to the first threshold value, generating the next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage, until the first result corresponding to the adjusted target read voltage is less than the first threshold value; and after the first result corresponding to the adjusted target read voltage is less than the first threshold value, performing M first adjustments on the target read voltage to be adjusted with the first step length.

[0226] In some embodiments, the operating method includes: adjusting the target read voltage in an increasing direction starting from the first boundary voltage based on the target read voltage generated after the next adjustment being less than or equal to the first boundary voltage; or adjusting the read voltage in a decreasing direction starting from the second boundary voltage based on the target read voltage generated after the next adjustment being greater than or equal to the second boundary voltage; wherein the first boundary voltage is less than the second boundary voltage.

[0227] In some embodiments, the operating method includes: taking the adjusted target read voltage that is first less than the first threshold value among the multiple first results corresponding to the target read voltage after multiple adjustments as the near-valley point voltage; in the process of performing multiple first adjustments to the near-valley point voltage with the first step length, starting from the near-valley point voltage, adjusting in a first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the first direction is greater than the first threshold value; starting from the near-valley point voltage, adjusting in a second direction opposite to the first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the second direction is greater than the first threshold value.

[0228] In some embodiments, the operating method includes: generating a first threshold value based on the first result corresponding to the target read voltage and the first mapping function; wherein the first mapping function is used to characterize the relationship between the first threshold value and the first result corresponding to the target read voltage; generating a predicted value of the target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function, and the order number of the target order; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment, the order number of the target order and the predicted value of the valley voltage of the target order.

[0229] In some embodiments, the operating method includes: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in two opposite directions with a second step size, and in the process of adjusting in each direction, when the first result corresponding to the target reading voltage after the next adjustment is greater than the first result corresponding to the target reading voltage after the previous adjustment, performing an upward trend statistics, and determining the third boundary voltage and the fourth boundary voltage based on the total number of statistics being greater than or equal to a preset number; in the process of adjusting in each direction, if the first result corresponding to the target reading voltage after one adjustment is lower than the second threshold, or the smallest first result among the multiple first results corresponding to the target reading voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference from the reference value is less than the third threshold is greater than the preset number, stop adjusting and use the read voltage corresponding to the smallest first result among the multiple first results as the valley voltage.

[0230] In some embodiments, the operating method includes: in the process of adjusting in each direction, the adjusted target read voltage corresponding to the total statistical number equal to the preset number is used as the third boundary voltage and the fourth boundary voltage respectively; in the process of adjusting in each direction, if the third boundary voltage and the fourth boundary voltage have been determined, the first result corresponding to the target read voltage after the last adjustment is obtained, and the target read voltage after the last adjustment is the average value of the third boundary voltage and the fourth boundary voltage; the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the valley voltage.

[0231] In some embodiments, the operating method includes: based on the determined valley voltage, the corresponding order belongs to the first order valley voltage, and using the determined valley voltage to generate the second order valley voltage in the multiple orders and / or other first order valley voltages with lower corresponding read voltages; wherein, the memory cell array includes memory cells with multiple storage bits, and the multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple orders, the multiple orders include the first order and the second order, and the read voltage of the second order is lower than the read voltage of the first order.

[0232] In some embodiments, the operating method includes: reading the stored data of at least one codeword at a first read voltage to obtain a second result; reading the stored data of at least one codeword at a second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and counting the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0233] In a fifth aspect, an embodiment of the present application provides an operating method of a memory system, which includes a memory device and a memory controller coupled to and controlling the memory device. The operating method includes: executing any one of the operating methods of the memory device provided in the fourth aspect.

[0234] In some specific embodiments, a method for operating a memory device includes: a memory controller in a memory system sends a first instruction, the first instruction instructing to obtain information representing a valley voltage; a memory device in the memory system receives the first instruction, obtains information representing the valley voltage according to the method for operating a memory device provided in the fourth aspect, and sends the obtained information representing the valley voltage to the memory controller; the memory controller uses the predicted valley voltage in the information representing the valley voltage to control the memory device to perform a read operation, and performs an error correction decoding operation on the read result of the read operation.

[0235] In a sixth aspect, an embodiment of the present application provides an operating method for a memory controller, the memory controller including a control unit, the operating method including: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of storage cells in at least one memory device coupled to the memory controller under a target read voltage; the first result includes a representation of the number of bits flipped in two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment based on the target read voltage after one adjustment exceeding the range defined by the first boundary voltage and the second boundary voltage; determining a valley voltage based on the first result corresponding to the adjusted target read voltage satisfying a preset condition, the valley voltage being used as the read voltage when performing a read operation on at least one codeword.

[0236] In some embodiments, the operating method includes: obtaining an initial first boundary voltage and an initial second boundary voltage corresponding to a target level in multiple levels; adjusting the initial first boundary voltage and the initial second boundary voltage corresponding to the target level according to a first result corresponding to at least one codeword under a target read voltage of the target level to obtain a first boundary voltage and a second boundary voltage corresponding to the target level; determining a valley voltage corresponding to the target level based on whether the first result corresponding to the adjusted target read voltage of the target level meets a preset condition; wherein the number of storage bits of the storage unit is multiple bits, and multiple storage bits correspond to multiple levels of read voltages.

[0237] In some embodiments, the operating method includes: based on the first result corresponding to at least one codeword at the target read voltage of the target level being greater than a first preset value, expanding the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level; wherein the range defined by the initial first boundary voltage and the initial second boundary voltage is smaller than the first preset range.

[0238] In some embodiments, the operating method includes: based on the usage scenario of the memory device being a first scenario, expanding the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level by shifting both toward a decreasing direction; based on the usage scenario of the memory device being a second scenario, expanding the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level by shifting both toward an increasing direction; wherein the usage scenarios of the memory device include the first scenario and the second scenario.

[0239] In some embodiments, the operating method includes: based on the first result corresponding to at least one codeword at the target read voltage of the target level being less than a second preset value, narrowing the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level; wherein the range defined by the initial first boundary voltage and the initial second boundary voltage is greater than the second preset range.

[0240] In some embodiments, the operating method includes: performing M first adjustments on the target read voltage to be adjusted with a first step length, and respectively obtaining M first results corresponding to the target read voltage after the M first adjustments; taking the smallest first result among the M first results as the inflection point value, and the reading voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the target read voltage after the N second adjustments; the second step length is smaller than the first step length; M and N are both positive integers greater than 1; and determining the valley voltage based on whether the first results corresponding to the target read voltage after the N second adjustments satisfy a preset condition.

[0241] In some embodiments, the operating method includes: before performing M first adjustments on the target read voltage to be adjusted, generating a first threshold value based on a first result corresponding to at least one codeword at the target read voltage, the first threshold value being used to characterize the maximum value of the first result corresponding to the near-valley voltage; based on the first result corresponding to the adjusted target read voltage being greater than or equal to the first threshold value, generating the next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage, until the first result corresponding to the adjusted target read voltage is less than the first threshold value; and after the first result corresponding to the adjusted target read voltage is less than the first threshold value, performing M first adjustments on the target read voltage to be adjusted with the first step length.

[0242] In some embodiments, the operating method includes: adjusting the read voltage in an increasing direction starting from the first boundary voltage based on the target read voltage generated after the next adjustment being less than or equal to the first boundary voltage; or adjusting the read voltage in a decreasing direction starting from the second boundary voltage based on the target read voltage generated after the next adjustment being greater than or equal to the second boundary voltage; wherein the first boundary voltage is less than the second boundary voltage.

[0243] In some embodiments, the operating method includes: taking the adjusted target read voltage that is first less than the first threshold value among the multiple first results corresponding to the target read voltage after multiple adjustments as the near-valley point voltage; in the process of performing multiple first adjustments to the near-valley point voltage with the first step length, starting from the near-valley point voltage, adjusting in a first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the first direction is greater than the first threshold value; starting from the near-valley point voltage, adjusting in a second direction opposite to the first direction with the first step length until the first result corresponding to the target read voltage after adjusting in the second direction is greater than the first threshold value.

[0244] In some embodiments, the operating method includes: generating a first threshold value based on a first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to characterize the relationship between the first threshold value and the first result corresponding to the target read voltage; generating a predicted value of the target read voltage after the next adjustment based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function, the order number of the target order; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment, the order number of the target order and the predicted value of the valley voltage of the target order.

[0245] In some embodiments, the operating method includes: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in two opposite directions with a second step size, and in the process of adjusting in each direction, when the first result corresponding to the target reading voltage after the next adjustment is greater than the first result corresponding to the reading voltage after the previous adjustment, performing an upward trend statistics, and determining the third boundary voltage and the fourth boundary voltage based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in each direction, if the first result corresponding to the target reading voltage after one adjustment is lower than the second threshold, or the smallest first result among the multiple first results corresponding to the target reading voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference from the reference value is less than the third threshold is greater than the preset number, stop adjusting and use the reading voltage corresponding to the smallest first result among the multiple first results as the valley voltage.

[0246] In some embodiments, the operating method includes: in the process of adjusting in each direction, the adjusted target read voltage corresponding to the total statistical number equal to the preset number is used as the third boundary voltage and the fourth boundary voltage respectively; in the process of adjusting in each direction, if the third boundary voltage and the fourth boundary voltage have been determined, the first result corresponding to the target read voltage after the last adjustment is obtained, and the target read voltage after the last adjustment is the average value of the third boundary voltage and the fourth boundary voltage; the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the valley voltage.

[0247] In some embodiments, the operating method includes: based on the determined valley voltage, the corresponding order belongs to the first order valley voltage, and using the determined valley voltage to generate the second order valley voltage in the multiple orders and / or other first order valley voltages with lower corresponding read voltages; wherein, the memory cell array includes memory cells with multiple storage bits, and the multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple orders, the multiple orders include the first order and the second order, and the read voltage of the second order is lower than the read voltage of the first order.

[0248] FIG13 is a flowchart of a method for operating a memory device according to an embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG13. It should be noted that, herein and hereinafter, the target valley voltage refers to the voltage used to perform a read operation on the data to be read.

[0249] In step S101, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S102 is executed.

[0250] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage for each level of the at least one level of read voltage corresponding to each of the multiple pages is determined sequentially. In step S103, one level is selected from the multiple levels corresponding to a page as the target level, and the target valley voltage corresponding to the target level read voltage is first determined. For example, using TLC as an example, the target valley voltages for the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S103 is executed.

[0251] In step S103, the main task is to determine the type of the target level. Here, the target level can be divided into two categories, the first level (also called high level) and the second level (also called low level), wherein the read voltage of the first level is greater than the read voltage of the second level. For example, still taking the lower page of TLC as an example, L5 is the first level and L1 is the second level. If L1 is selected as the target level in step S103, the target level is the second level, that is, the low level; if L5 is selected as the target level in step S104, the target level is the first level, that is, the high level. According to the target level being the low level, execute step S104; according to the target level being the high level, execute step S106.

[0252] In step S104, a predicted valley voltage is obtained. Here, the predicted valley voltage is generated based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S105 is executed.

[0253] In step S105, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to generate a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is generated based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the fourth mapping function. The second prediction is to generate a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is generated based on the high-order predicted valley voltage, the order of the low-order, and the third mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S121 is executed. If the hard decoding fails, the two-step prediction is failed. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S107 is continued.

[0254] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jump from step S105 to S107.

[0255] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S106, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S107 is executed after step S106.

[0256] It should be noted that here and below, the conversion relationship between DAC and the aforementioned mv is 1DAC=10mv.

[0257] In step S107, the target valley voltage is determined by searching or looping. Step S108 is executed after step S107.

[0258] For the first execution loop, in step S108, a first result at the target read voltage is obtained. It is understood that for subsequent execution loops, in step S108, a first result at an adjusted target read voltage is obtained. After step S108, step S109 is executed.

[0259] In step S109, a first threshold value TH1 is determined or adjusted based on the first result at the target read voltage. It is understood that, during a read operation, the further the threshold voltage of a memory cell deviates from the threshold voltage during a write operation, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result at the default read voltage can be used to determine the first threshold value TH1. The first threshold value TH1 is used to characterize the change (increase) in the target valley voltage caused by the memory cell threshold voltage deviation. Step S110 is executed after step S109.

[0260] It should be noted that step S109 is mainly for the first execution of the loop process, and can be skipped for subsequent execution of the loop process.

[0261] In step S110, a predicted valley voltage is generated and a determination is made as to whether the predicted valley voltage is less than the aforementioned first threshold TH1. Based on the first result corresponding to the previously adjusted target read voltage and a related mapping function (such as the aforementioned second mapping function), a predicted valley voltage after the next adjustment is generated, and the generated predicted valley voltage is compared with the first threshold TH1. If the determination result in step S110 is negative, indicating that the predicted valley voltage generated at that time is greater than or equal to the first threshold TH1, the process continues with step S108, adjusting the target read voltage and regenerating the predicted valley voltage. After each regeneration of the predicted valley voltage, the predicted valley voltage is compared with the first threshold TH1 until the generated predicted read voltage is less than the first threshold TH1. In other words, the prediction is iterated using the aforementioned prediction formula or related mapping function until the generated predicted read voltage is less than the first threshold TH1. If the determination result in step S110 is positive, indicating that the predicted valley voltage generated at that time is less than the first threshold TH1, the process proceeds to the next step S111.

[0262] In step S111, an inflection point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. The inflection point can be understood as a point relatively close to the bottom of the valley. In some embodiments, it is possible to start from the near-valley point with a coarser step size (first step size), and search to the left and right boundaries respectively until the left and right boundaries are reached, and the point corresponding to the minimum first result in the search process is used as the inflection point. Here, the inflection point is a point that is closer to the bottom of the valley than the near-valley point. The point that is less than the first threshold in the aforementioned step can be used as the near-valley point. For example, the near-valley point can be the point that is less than the first threshold that appears for the first time in the aforementioned step. The first step size can be a larger step size. In some embodiments, the first step size can be 5DAC-15DAC. Exemplarily, the first step size can be 5DAC, 10DAC or 15DAC. Step S112 is performed after step S111.

[0263] In step S112, it is determined whether an inflection point has been found. If no inflection point has been found, the search continues, and step S111 is continued until an inflection point is found. After the inflection point is found, step S113 is executed.

[0264] In step S113 and step S114, the search can be performed starting from the near-valley point with a finer step size (second step size) to the left boundary and the right boundary respectively until the left boundary and the right boundary are reached or the statistics of the upward trend exceed the preset number of times. Here, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistics of the upward trend is performed. In some embodiments, the preset number of times is 3-7 times. Exemplarily, the preset number of times can be 3, 5 or 7 times. It should be noted that the positions of step S113 and step S114 can be interchanged. The second step size can be a smaller step size. In some embodiments, the second step size can be 2DAC-4DAC. Exemplarily, the second step size can be 2DAC, 3DAC or 4DAC.

[0265] When the searches in step S113 and step S114 satisfy the aforementioned conditions (reaching the boundary or the statistics showing an upward trend exceed the preset number of times), step S115 is executed.

[0266] In step S115, the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S115, step S116 is executed.

[0267] In step S116, it is determined whether the target valley voltage is valid. The method for determining whether the target valley voltage is valid may be to read data using the target valley voltage and decode the read data via the memory controller. Successful decoding indicates whether the target valley voltage is valid. If the result of step S116 is yes, step S121 is executed; if the result of step S116 is no, step S117 is executed.

[0268] In step S117, it is determined whether the loop has ended. If the determination result of step S117 is yes, step S119 is executed; if the determination result of step S117 is no, step S118 is executed.

[0269] In step S118, the process enters the next loop and continues searching. Step S118 jumps to step S107.

[0270] In step S119, it is determined whether the target order is a high order. If the determination result of step S119 is yes, step S120 is executed; if the determination result of step S119 is no, step S121 is executed.

[0271] In step S120, a predicted valley voltage of the low-order is generated based on the target valley voltage of the high-order. Here, the predicted valley voltage of the low-order can be generated using the target valley voltage of the high-order, the order of the low-order, and a related mapping function (such as the third mapping function described above). Step S121 is executed after step S120.

[0272] In step S121, it is determined whether the corresponding target valley voltages for all the read voltage levels included in the page have been determined. If the determination result in step S121 is yes, it means that the target valley voltages for all the read voltage levels included in the page have been determined, and step S123 can be executed. If the determination result in step S121 is no, it means that the target valley voltages for all the read voltage levels included in the page have not yet been determined, and step S122 can be executed.

[0273] In step S122, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S122 jumps to step S102.

[0274] In step S123 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S123 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0275] FIG14 is a second flowchart of the operating method of the memory device provided in one embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG14.

[0276] In step S201, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S202 is executed.

[0277] In step S202, in some embodiments, the read mode of the memory device is set to a single-level read mode, where the single-level read mode includes reading at least one bit of data stored in the memory cell using a single-level read voltage.

[0278] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage of each level of the at least one level of read voltage corresponding to each page in the multiple pages is determined in sequence. In step S203, one level is selected from the multiple levels corresponding to a page as the target level, and the target valley voltage corresponding to the target level read voltage is first determined. For example, taking TLC as an example, the target valley voltages of the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S204 is executed.

[0279] In step S204, the main task is to determine the type of the target order. Here, the target order can be divided into two categories, the first order (also called high order) and the second order (also called low order), wherein the read voltage of the first order is greater than the read voltage of the second order. For example, still taking the lower page of TLC as an example, L5 is the first order and L1 is the second order. If L1 is selected as the target order in step S203, the target order is the second order, that is, the low order; if L5 is selected as the target order in step S204, the target order is the first order, that is, the high order. According to the target order being the low order, execute step S205; according to the target order being the high order, execute step S207.

[0280] In step S205, a predicted valley voltage is obtained. Here, the predicted valley voltage is generated based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S206 is executed.

[0281] In step S206, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to generate a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is generated based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the fourth mapping function. The second prediction is to generate a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is generated based on the high-order predicted valley voltage, the order of the low-order, and the third mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S245 is executed. If the hard decoding fails, the two-step prediction is failed. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S220 is continued. Step S220 will be described in detail in the subsequent description.

[0282] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jumping from step S206 to S208; or the point corresponding to the predicted valley voltage can be directly used as the near-valley point of the subsequent iteration, that is, jumping from step S206 (S219) to S220.

[0283] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S207, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S208 is executed after step S207.

[0284] In step S208, the target valley voltage is determined by searching or looping. After step S208, step S209 is executed.

[0285] During the first execution of the loop, step S209 is to obtain the first result at the target read voltage. It is understood that during subsequent execution of the loop, step S209 is to obtain the first result at the adjusted target read voltage. Step S210 is executed after step S209.

[0286] In step S210, various parameters are determined or adjusted based on the first result under the target read voltage. Here, the various parameters may include at least a first threshold, a first boundary voltage (the position corresponding to the first boundary voltage is also called the left boundary) and a second boundary voltage (the position corresponding to the second boundary voltage is also called the right boundary). It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts from the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result under the default read voltage can be used to confirm the first threshold value. The first threshold value is used to characterize the change (elevation) in the target valley voltage caused by the shift of the threshold voltage of the memory cell. Here, the initial first boundary voltage and the initial second boundary voltage can be set based on empirical values, such as initially setting an initial first boundary voltage and an initial second boundary voltage with a relatively large range. Then, based on the first result under the target read voltage, the initial first boundary voltage and the initial second boundary voltage are adjusted, such as narrowing the range of the first boundary voltage and the second boundary voltage to obtain the first boundary voltage and the second boundary voltage. Step S211 is performed after step S10.

[0287] It should be noted that step S210 is mainly for the first execution cycle process, and can be skipped for subsequent execution cycles.

[0288] During the first execution of the loop, step S211 determines whether the first result at the target read voltage is less than the first threshold. It is understood that during subsequent executions of the loop, step S211 determines whether the first result at the adjusted target read voltage is less than the first threshold. If the determination result in step S211 is yes, it can be assumed that the first result corresponding to the adjusted target read voltage basically meets the requirements for read data decoding. The process then jumps to step S242, terminating the loop and outputting the corresponding target valley voltage. If the determination result in step S211 is no, the loop continues to step S212.

[0289] In step S212, it is determined whether the target memory block is a partially written memory block. Here, the target memory block is the memory block where at least one codeword to be read is located. A partially written memory block includes a memory block that has both a programmed state and an erased state. If the result of step S212 is yes, step S213 is executed; if the result of step S212 is no, step S214 is executed.

[0290] It should be noted that step S212 is mainly for the first execution of the loop process, and for subsequent execution of the loop process, this step can be skipped. After skipping this step, step S214 is continued.

[0291] In step S213, considering that the offset of the threshold voltage of the storage cell in the underfilled storage block is more complex than the offset of the threshold voltage of the storage cell in the filled storage block (the filled storage block can be understood as a storage block with the same application scenario as the underfilled storage block and a write time difference less than a preset time length), the offset of the threshold voltage of the storage cell in the underfilled storage block is also related to the position of the first blank physical page in the underfilled storage block (the first blank physical page can be understood as the physical page in which the first data state appearing in the underfilled storage block is all erased according to the programming order) and the position of the physical page to be read (the physical page where the at least one codeword to be read is located). Based on this, a predicted valley voltage can be generated based on the first offset corresponding to the filled storage block, the second offset corresponding to the position of the first blank physical page in the underfilled storage block, and the third offset corresponding to the position of the physical page to be read, and then the process proceeds to step S214. It is understandable that the generated predicted valley voltage is more targeted than the blind adjustment of the target read voltage, and can shorten the search time to a certain extent and determine the target valley voltage more quickly.

[0292] In step S214, determine whether a near-valley point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. In the process of adjusting the target read voltage multiple times, the point corresponding to the multiple first results corresponding to the multiple adjusted target read voltages that is first less than the near-valley threshold can be used as the near-valley point. The near-valley threshold is used to characterize the maximum value of the first result corresponding to the target valley bottom voltage. It should be noted that there is a difference between the near-valley threshold and the aforementioned first threshold. When the first result is less than the near-valley threshold, it means that a more refined search can be carried out next; when the first result is less than the first threshold, it means that the search can be stopped next. When the judgment result of step S214 is yes, execute step S219; when the judgment result of step S214 is no, execute step S215.

[0293] If no near-valley point is found in step S215, the process proceeds to step S215, where a predicted read voltage after the next adjustment is generated based on the first result corresponding to the previously adjusted target read voltage and a related mapping function (such as the aforementioned second mapping function). This means that the prediction is iterated using the aforementioned prediction formula or mapping function. After step S215, step S216 is executed.

[0294] In step S216, a determination is made as to whether the next adjusted predicted read voltage hits a boundary. The boundary here can be either the left boundary or the right boundary, and hitting the boundary can be understood as being exactly on the boundary or crossing the boundary. If the determination result in step S216 is yes, step S217 is executed; if the determination result in step S216 is no, step S218 is executed.

[0295] In step S217, the adjustment direction is changed. There are two adjustment directions for adjusting the target read voltage: positive (rightward) and negative (leftward). Adjusting the offset direction can be understood as: previously adjusting to the right, then adjusting to the left after hitting the right boundary; or previously adjusting to the left, then adjusting to the right after hitting the left boundary. After step S217, step S218 is executed.

[0296] In step S218, the first result of the adjusted target read voltage is obtained. After step S218, step S214 is executed. That is, after each target voltage adjustment and the corresponding first result is obtained, a determination is made as to whether the latest adjustment point is a near-valley point. One or more adjustments are performed until a near-valley point is found.

[0297] It should be noted that if the next cycle is entered after the step of finding the near valley point because the subsequent conditions are not met, steps S215 to S218 can be skipped.

[0298] In step S219, you can refer to the description in step S206. When the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the point corresponding to the predicted valley bottom voltage can be directly used as the near-valley point of the subsequent iteration, that is, jump from step S219 to S220.

[0299] In step S220, it is determined whether the predicted valley voltage at the current point (the latest adjusted target read voltage) is valid. In some embodiments, the predicted valley voltage can be determined to be valid by the first result corresponding to the latest adjusted target read voltage being less than the first threshold. It should be noted that although in step S211, when the first result under the (adjusted) target read voltage is not less than the first threshold, S212 and subsequent steps are entered, but before the judgment result of step S214 is yes, the target read voltage is adjusted at least once, so the new adjusted target read voltage may be less than the first threshold at this time. When the judgment result of step S220 is yes, step S224 is executed; when the judgment result of step S220 is no, step S221 is executed.

[0300] In step S221, a determination is made as to whether the first result fbc of the current point is greater than the fbc of the previous point. After finding the near-valley point, a rough search for an inflection point begins to the left. Generally, the magnitude of fbc decreases and then increases. When the first result fbc of the current point is greater than the fbc of the previous point, this indicates that fbc will increase further during the subsequent leftward adjustment, and the previous point was a relatively small point. In this case, the previous point is set as the inflection point. In some embodiments, the step size used for the rough search can be a larger step size, for example, 5DAC-15DAC, or more specifically, 5DAC, 10DAC, or 15DAC. Based on this, if the determination result of step S221 is yes, step S223 is executed; if the determination result of step S221 is no, step S222 is executed.

[0301] In step S222, a rough search is performed to the left starting from the point near the valley, and each search is compared with the fbc of the previous search until a point is found where the value stops decreasing and starts increasing. Once this point is found, step S222 is completed and the process goes to step S223.

[0302] In step S223, the previous point (i.e., the point where the decrease stops and the increase begins) is set as the inflection point, and a fine search is performed to the right starting from the inflection point. In some embodiments, the step size used in the fine search can be a smaller step size, for example, 1DAC-4DAC, more specifically, 2DAC or 3DAC. After step S223, step S225 is executed.

[0303] In step S224, the current point is set as the inflection point, and a fine search is started from the inflection point to the right. In some embodiments, the step size used in the fine search can refer to step S223. After step S224, step S225 is executed.

[0304] In step S225 , it is determined whether the target read voltage is adjusted to the left. If the determination result of step S225 is yes, step S229 is executed; if the determination result of step S225 is no, step S226 is executed.

[0305] In step S226, the target read voltage is adjusted rightward. During the adjustment, a determination is made as to whether the right boundary is hit or whether the rise count (also known as an upward trend count, where an upward trend count is performed when the first result corresponding to the next adjusted target read voltage is greater than the first result corresponding to the previous adjusted target read voltage) exceeds a preset number TH2. In some embodiments, the preset number is 3-7 times, and illustratively, the preset number can be 3, 5, or 7 times. If the determination in step S226 is yes, step S228 is executed; if the determination in step S226 is no, step S227 is executed.

[0306] In step S227, if the right boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the right boundary, and a judgment is made after each search until the right boundary is hit or the lift count exceeds the preset number TH2. In other words, when step S227 is completed, jump to step S228.

[0307] In step S228 , the target read voltage starts to be adjusted leftward.

[0308] In step S229, while adjusting the target read voltage to the left, it is determined whether the left boundary or lift count is hit. The lift count here can be understood with reference to the aforementioned step S226. The thresholds for the left and right lift counts are generally set to the same value. If the judgment result of step S229 is yes, step S231 is executed; if the judgment result of step S229 is no, step S230 is executed.

[0309] In step S230, if the left boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the left boundary, and a judgment is made after each search until the left boundary is hit or the lift count exceeds the preset number TH2. That is, when step S230 is completed, jump to step S231.

[0310] In step S231, a determination is made as to whether the most recent first result is the minimum. Here, the most recent first result refers to whether the first result at the adjusted target read voltage after the last target read voltage adjustment is the minimum. At this point, it is necessary to traverse all search points in at least this loop to find the adjusted target read voltage corresponding to the point with the minimum first result. If the determination result in step S231 is yes, step S233 is executed; if the determination result in step S231 is no, step S232 is executed.

[0311] In step S232, the latest first result is updated using the found minimum first result. Step S233 is executed after step S232.

[0312] In step S233, a determination is made as to whether the near-valley count exceeds a preset number TH3. Here, the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value. If the number of remaining first results whose difference from the reference value is less than a second threshold (equivalent to the preset difference) is greater than a preset number, the search is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage. In some embodiments, the second threshold (equivalent to the preset difference) and the preset number can be set together based on actual conditions. Generally, a slightly larger second threshold (equivalent to the preset difference) results in a relatively larger preset number; and a slightly smaller second threshold (equivalent to the preset difference) results in a relatively smaller preset number. If the determination result in step S233 is yes, the search is stopped and step S237 is executed. If the determination result in step S233 is no, the process proceeds to the next determination step, step S234.

[0313] In step S234, a determination is made as to whether the repeated valley count exceeds a preset count TH4. Here, during multiple adjustments to the target read voltage, different adjustment methods may be employed. If the target read voltages corresponding to the different adjustment methods exceeding the preset count are the same, and the first result corresponding to the same target read voltage is the minimum value among all first results, the same target read voltage is used as the target valley voltage. In some embodiments, the preset count is 2-4, and illustratively, the preset number of times may be 2, 3, or 4. If the determination result in step S234 is yes, the search is terminated and step S237 is executed. If the determination result in step S234 is no, the search proceeds to the next determination and step S235 is executed.

[0314] It should be noted that step S233 and step S234 belong to different judgment methods and their positions can be interchanged. In other words, the repeated valley count can be judged first, and then the approximate estimate can be judged when the repeated valley count does not meet the conditions. It is understandable that other judgments can also be performed here to determine whether the loop has ended.

[0315] In step S235, it is determined whether the loop has ended. If the determination result of step S235 is yes, step S237 is executed; if the determination result of step S235 is no, step S236 is executed.

[0316] In step S236, the process enters the next loop and continues searching. Step S236 jumps to step S209.

[0317] In step S237, the target step search is completed, and the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S237, step S238 is executed.

[0318] In step S238, it is determined whether the target order is a high order. If the determination result of step S238 is yes, step S239 is executed; if the determination result of step S238 is no, step S240 is executed.

[0319] In step S239, a predicted valley voltage of the low order is generated based on the target valley voltage of the high order. Here, the predicted valley voltage of the low order can be generated by the target valley voltage of the high order, the order of the low order, and a related mapping function (such as the fourth mapping function described above). Step S240 is executed after step S239.

[0320] In step S240, it is determined whether the corresponding target valley voltages have been determined for all the read voltage levels included in the page. If the determination result in step S240 is yes, it means that the target valley voltages corresponding to all the read voltage levels included in the page have been determined, and step S242 can be executed. If the determination result in step S240 is no, it means that the target valley voltages corresponding to all the read voltage levels included in the page have not yet been determined, and step S241 can be executed.

[0321] In step S241, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S236 jumps to step S202.

[0322] In step S242 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S242 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0323] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0324] 15 is a timing diagram of an exemplary start-up single-stage read mode operation provided by the present application. DQx can be represented as a data bus signal, and Cycle Type can further represent the type of the data bus signal.

[0325] As shown in FIG15 , the set function command may include, for example, a sub-command (e.g., EFh). Exemplarily, the memory device starts the single-level read mode upon receiving a sub-command EFh. In the single-level read mode, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. During the read time, the data DATA (e.g., Dn) corresponding to the page of the received address may be cached in the page buffer first, and then the data DATA may be read on demand. It should be noted that, in the above embodiment, when performing a reread operation, the data corresponding to a physical page (e.g., Dn) needs to be frequently transmitted (Din / Dout) between the memory device and the memory controller, and the transmission of the data takes a long time.

[0326] FIG16 is a timing diagram for determining a target valley voltage and performing a read operation according to an embodiment of the present application. As shown in FIG16 , a read command may include, for example, two sub-commands (e.g., 00h and 30h). Exemplarily, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the memory device receives sub-command 30h, within the read time, the corresponding data DATA (e.g., Dn) in the page of the received address may be cached in the page buffer before the data DATA is read on demand. It should be noted that in the above embodiment, when performing a reread operation, the memory device and the memory controller frequently transmit data corresponding to a physical page, and transmitting this data takes a long time. In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After receiving subcommand 30h, memory device 104 receives subcommands EFh and xxh of the first / second instructions. Under the direction of the first / second instructions, memory device 104 obtains a first result corresponding to the codeword at the corresponding read voltage and sends the obtained first result to the memory controller. The memory controller determines a target valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device and performs a read operation on the data stored in the memory device based on the target valley voltage.

[0327] As shown in FIG16 , in some other embodiments, the first instruction / second instruction includes subcommands 05 / 06h and E0h. During the process of determining the target valley voltage, subcommands 05 / 06h and E0h are executed at most twice. In an exemplary embodiment, each subcommand 05 / 06h and E0h command performs a read operation on at least one codeword of the control memory device and performs an error correction decoding operation on the result of the read operation. During the process of determining the target valley voltage, a read operation is performed at most twice, and thus, only two error correction decoding operations are performed at most. This minimizes the number of iterations (at most two) required to decode at least one codeword, significantly improving decoding efficiency.

[0328] In some specific embodiments, the memory controller 106 is configured to: send a first instruction, the first instruction including sub-commands 05 / 06h and E0h, instructing the memory device to perform a first read operation; the memory device 104 is configured to: receive the first instruction, perform the first read operation using the predicted valley voltage in the information representing the multi-level predicted valley voltage; and send the obtained information representing the first read result of the first read operation to the memory controller; the memory controller 106 is further configured to: perform a second error correction decoding operation on the first read result of the first read operation.

[0329] In some specific embodiments, the memory controller 106 is configured to: output a first read result based on the success of the first error correction decoding; or, based on the failure of the first error correction decoding, send a second instruction, the second instruction including subcommands 05 / 06h and E0h, instructing the memory device to perform a second read operation. The memory device 104 is configured to: receive the second instruction, perform a second read operation using the predicted valley voltage in the re-acquired information representing the predicted valley voltages of the multiple levels, and send the acquired information representing the second read result of the second read operation to the memory controller. The memory controller 106 is further configured to: perform a second error correction decoding operation on the second read result of the second read operation. It should be noted that the second instruction provided in the embodiments of the present application is merely an example and should not unduly limit the scope of protection of the present application. In some embodiments, the data size of the first result is less than a predetermined data size threshold, for example, the data size of the first result ranges from 1 byte to 4 bytes. Therefore, during the process of determining the target valley voltage, the data size transmitted between the memory device and the memory controller is small and fast, which is beneficial for improving the overall speed of the read operation.

[0330] It should be noted that the embodiments mentioned in the first and second parts of this application do not include the timing of the two sub-commands 05 / 06h and E0h as shown in Figure 16.

[0331] Referring to Figure 17, which is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application. In a seventh aspect, an embodiment of the present application provides a storage medium, as shown in Figure 17, on which executable instructions are stored. When the executable instructions are executed by a processor, the steps of any of the operating methods provided in the fourth, fifth, and sixth aspects are implemented.

[0332] In some specific embodiments, the storage medium can be a memory such as a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disc, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above memory devices.

[0333] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0334] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code portions).

[0335] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0336] In some specific embodiments, referring to Figure 17, Figure 17 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein, the storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102; when the executable instruction is executed by the memory device, the first storage medium can be used to implement the steps of the operating method of the memory device in the above embodiment of the present application; when the executable instruction is executed by the memory controller, the second storage medium can be used to implement the steps of the operating method of the memory controller in the above embodiment of the present application; when the executable instruction is executed by the memory system, the third storage medium can be used to implement the steps of the operating method of the memory system in the above embodiment of the present application.

[0337] In the memory device and its operating method, memory system and its operating method provided by the embodiments of the present application, a first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted by the memory device is reduced; the first boundary voltage and the second boundary voltage are generated based on the first result corresponding to the target read voltage, and have a dynamic first threshold, so that the iterative convergence speed of determining the target valley voltage is faster; the process of obtaining the first result converges inside the memory device, does not occupy the space of, for example, a memory controller, and has a low degree of dependence on, for example, a memory controller; the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller are reduced, saving the iteration time of the error correction decoding algorithm of the memory controller, and the error correction decoding speed is faster; it is suitable for MLC, TLC or QLC type memory devices / memory systems.

[0338] The memory device and operating method thereof, as well as the memory system and operating method thereof, provided in the embodiments of the present application, effectively avoid the time-consuming and incomplete scenario coverage issues associated with using a reread table. This reduces the space occupied by the reread table, allows for faster and more accurate identification of the target valley voltage, and effectively reduces the latency associated with determining the target valley voltage. Furthermore, performing a read operation at the obtained target valley voltage significantly increases the probability of correctly reading stored data, improving product reliability and user experience.

[0339] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0340] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application. Industrial Applicability

[0341] The memory device and operating method thereof, as well as the memory system and operating method thereof, provided in the embodiments of the present application, effectively avoid the time-consuming and incomplete scenario coverage issues associated with using a reread table. This reduces the space occupied by the reread table, allows for faster and more accurate identification of the target valley voltage, and effectively reduces the latency associated with determining the target valley voltage. Furthermore, performing a read operation at the obtained target valley voltage significantly increases the probability of correctly reading stored data, improving product reliability and user experience.

Claims

1. A memory device comprising: A memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; A peripheral circuit is coupled to the memory cell array and is configured to: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one of the codewords at a target read voltage; wherein the first result includes a number of bits flipped in the read results of at least one of the codewords at the first read voltage and the second read voltage; and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; Adjusting the target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment according to the adjusted target read voltage exceeding the range defined by the first boundary voltage and the second boundary voltage; According to the first result corresponding to the adjusted target read voltage meeting a preset condition, a target valley voltage is determined, and the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

2. The memory device according to claim 1, wherein The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; The peripheral circuit is configured as follows: Obtaining an initial first boundary voltage and an initial second boundary voltage corresponding to a target step in the multiple steps; Adjusting the initial first boundary voltage and the initial second boundary voltage corresponding to the target level according to a first result corresponding to at least one codeword at the target read voltage of the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level; According to the first result corresponding to the adjusted target read voltage of the target step meeting a preset condition, a target valley voltage corresponding to the target step is determined.

3. The memory device according to claim 2, wherein The range defined by the initial first boundary voltage and the initial second boundary voltage is smaller than the first preset range; The peripheral circuit is configured as follows: According to the fact that the first result corresponding to at least one of the codewords at the target read voltage of the target level is greater than a first preset value, the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level is expanded to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

4. The memory device according to claim 3, wherein The usage scenarios of the memory device include a first scenario and a second scenario; The peripheral circuit is configured as follows: Based on the usage scenario of the memory device being the first scenario, the ranges defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level are expanded by shifting both toward a decreasing direction; Based on the usage scenario of the memory device being the second scenario, the ranges defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level are expanded by shifting both toward an increasing direction.

5. The memory device according to claim 2, wherein The range defined by the initial first boundary voltage and the initial second boundary voltage is greater than the second preset range; The peripheral circuit is configured as follows: According to the fact that the first result corresponding to at least one of the codewords at the target read voltage of the target level is less than a second preset value, the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level is narrowed to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

6. The memory device according to claim 2, wherein: The peripheral circuit is configured as follows: Performing M first adjustments on the target read voltage to be adjusted with the first step length, and respectively obtaining M first results corresponding to the target read voltage after the M first adjustments; The smallest first result among the M first results is used as the inflection point value, and the read voltage corresponding to the inflection point value is the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step length, and respectively obtaining N first results corresponding to the target read voltage after the N second adjustments, wherein the second step length is smaller than the first step length; Both M and N are positive integers greater than 1; and The target valley voltage is determined according to whether the first result corresponding to the target read voltage obtained after the N second adjustments satisfies a preset condition.

7. The memory device according to claim 6, wherein: The peripheral circuit is configured as follows: Before performing M first adjustments on the target read voltage to be adjusted, generating a first threshold value according to a first result corresponding to at least one of the codewords at the target read voltage, the first threshold value being used to represent a maximum value of the first result corresponding to a target valley voltage; According to the first result corresponding to the adjusted target read voltage being greater than or equal to the first threshold, generating a next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage, until the first result corresponding to the adjusted target read voltage is less than the first threshold; and After the first result corresponding to the adjusted target read voltage is less than the first threshold, the target read voltage to be adjusted is adjusted M times with the first step length.

8. The memory device according to claim 7, wherein The first boundary voltage is less than the second boundary voltage, and the peripheral circuit is configured as follows: Based on the generated target read voltage after the next adjustment being less than or equal to the first boundary voltage, the target read voltage is adjusted in an increasing direction starting from the first boundary voltage; or, based on the generated target read voltage after the next adjustment being greater than or equal to the second boundary voltage, the read voltage is adjusted in a decreasing direction starting from the second boundary voltage.

9. The memory device according to claim 7, wherein: The peripheral circuit is configured as follows: The adjusted target reading voltage corresponding to the first result of the target reading voltages adjusted multiple times is smaller than the first threshold for the first time as the near-valley point voltage; In the process of performing multiple first adjustments on the near-valley point voltage with a first step length, starting from the near-valley point voltage, adjusting in a first direction with the first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than the first threshold; starting from the near-valley point voltage, Adjustment is performed with the first step length in a second direction opposite to the first direction until a first result corresponding to the target read voltage after adjustment in the second direction is greater than the first threshold.

10. The memory device according to claim 7, wherein The peripheral circuit is configured as follows: generating the first threshold value according to the first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to represent the relationship between the first threshold value and the first result corresponding to the target read voltage; Based on the first result corresponding to the target read voltage after the last adjustment and the second mapping function, and the order number of the target order, a predicted value of the target read voltage after the next adjustment is generated; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment, the order number of the target order and the predicted value of the target valley voltage of the target order.

11. The memory device according to claim 6, wherein The peripheral circuit is configured as follows: During the process of performing N second adjustments on the knee point voltage with a second step size, starting from the knee point voltage, the adjustment is performed in two opposite directions with the second step size. During the adjustment in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed, and a third boundary voltage and a fourth boundary voltage are determined based on the total number of statistical analyses being greater than or equal to a preset number. During the adjustment process in each direction, if the first result corresponding to the target read voltage after one adjustment is lower than the second threshold, or if the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and the number of the remaining multiple first results whose differences from the reference value are less than the third threshold is greater than a preset number, the adjustment is stopped and the read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

12. The memory device according to claim 11, wherein The peripheral circuit is configured as follows: During the adjustment process in each direction, the adjusted target read voltages corresponding to the total statistical number of times being equal to the preset number are respectively used as the third boundary voltage and the fourth boundary voltage; During the adjustment process in each direction, if the third boundary voltage and the fourth boundary voltage have been determined, obtaining a first result corresponding to the target read voltage after the last adjustment, where the target read voltage after the last adjustment is the average of the third boundary voltage and the fourth boundary voltage; The read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

13. The memory device according to claim 2, wherein: The memory cell array includes memory cells having a plurality of storage bits, wherein the plurality of storage bits correspond to a plurality of pages respectively; at least some of the pages correspond to a plurality of levels, wherein the plurality of levels include a first level and a second level, wherein a read voltage of the second level is less than a read voltage of the first level; The peripheral circuit is configured as follows: According to the target valley voltage corresponding to the first stage under the determined target valley voltage, the target valley voltage of the second stage in the multiple stages and / or the target valley voltage of other first stages with lower corresponding read voltage are generated using the determined target valley voltage.

14. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Reading stored data of at least one of the codewords at the first read voltage to obtain a second result; reading stored data of at least one of the codewords at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; The first result is obtained by counting the number of bits in the fourth result that represent that the third result is flipped compared with the second result.

15. The memory device according to claim 14, wherein The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to: store the second result; The second latch is configured to: store the third result; The third latch is configured to store the fourth result.

16. A memory system comprising: One or more memory devices according to any one of claims 1 to 15; as well as A memory controller is coupled to the memory device and controls the memory device.

17. The memory system according to claim 16, wherein: The memory controller is configured to: before performing a read operation on data stored in the memory device, send a first instruction instructing to obtain information representing a target valley voltage; The memory device is configured to: receive the first instruction, obtain information representing the target valley voltage, and send the obtained information representing the target valley voltage to the memory controller; The memory controller is further configured to: control the memory device to perform a read operation using the target valley voltage in the information representing the target valley voltage, and perform an error correction decoding operation on a read result of the read operation.

18. A memory controller comprising a control unit configured to: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of memory cells in at least one memory device coupled to the memory controller at a target read voltage; the first result representing the number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; and a difference between the first read voltage and the second read voltage being less than a preset voltage; Adjusting the target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment according to the adjusted target read voltage exceeding the range defined by the first boundary voltage and the second boundary voltage; According to the first result corresponding to the adjusted target read voltage meeting a preset condition, a target valley voltage is determined, and the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

19. The memory controller according to claim 18, wherein: The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; The control unit is configured to: Obtaining an initial first boundary voltage and an initial second boundary voltage corresponding to a target step in the multiple steps; Adjusting the initial first boundary voltage and the initial second boundary voltage corresponding to the target level according to a first result corresponding to at least one codeword at the target read voltage of the target level to obtain the first boundary voltage and the second boundary voltage corresponding to the target level; According to the first result corresponding to the adjusted target read voltage of the target step meeting a preset condition, a target valley voltage corresponding to the target step is determined.

20. The memory controller according to claim 19, wherein: The range defined by the initial first boundary voltage and the initial second boundary voltage is smaller than the first preset range; The control unit is configured to: According to the fact that the first result corresponding to at least one of the codewords at the target read voltage of the target level is greater than a first preset value, the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level is expanded to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

21. The memory controller according to claim 20, wherein: The usage scenarios of the memory device include a first scenario and a second scenario; The control unit is configured to: Based on the usage scenario of the memory device being the first scenario, the ranges defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level are expanded by shifting both toward a decreasing direction; Based on the usage scenario of the memory device being the second scenario, the ranges defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level are expanded by shifting both toward an increasing direction.

22. The memory controller according to claim 19, wherein: The range defined by the initial first boundary voltage and the initial second boundary voltage is greater than the second preset range; The memory controller is configured to: According to the fact that the first result corresponding to at least one of the codewords at the target read voltage of the target level is less than a second preset value, the range defined by the initial first boundary voltage and the initial second boundary voltage corresponding to the target level is narrowed to obtain the first boundary voltage and the second boundary voltage corresponding to the target level.

23. The memory controller according to claim 19, wherein: The control unit is configured to: Performing M first adjustments on the target read voltage to be adjusted with the first step length, and respectively obtaining M first results corresponding to the target read voltage after the M first adjustments; The smallest first result among the M first results is used as the inflection point value, and the reading corresponding to the inflection point value is Take the voltage as the knee point voltage; Performing N second adjustments on the knee point voltage with a second step length, and respectively obtaining N first results corresponding to the target read voltage after the N second adjustments, wherein the second step length is smaller than the first step length; Both M and N are positive integers greater than 1; and The target valley voltage is determined according to whether the first result corresponding to the target read voltage obtained after the N second adjustments satisfies a preset condition.

24. The memory controller according to claim 23, wherein: The control unit is configured to: Before performing M first adjustments on the target read voltage to be adjusted, generating a first threshold value according to a first result corresponding to at least one of the codewords at the target read voltage, the first threshold value being used to represent a maximum value of the first result corresponding to a target valley voltage; According to the first result corresponding to the adjusted target read voltage being greater than or equal to the first threshold, generating a next adjusted target read voltage based on the first result corresponding to the last adjusted target read voltage, until the first result corresponding to the adjusted target read voltage is less than the first threshold; and After the first result corresponding to the adjusted target read voltage is less than the first threshold, the target read voltage to be adjusted is adjusted M times with the first step length.

25. The memory controller according to claim 24, wherein: The first boundary voltage is lower than the second boundary voltage, and the control unit is configured to: Based on the generated target read voltage after the next adjustment being less than or equal to the first boundary voltage, the read voltage is adjusted in an increasing direction starting from the first boundary voltage; or based on the generated target read voltage after the next adjustment being greater than or equal to the second boundary voltage, the read voltage is adjusted in a decreasing direction starting from the second boundary voltage.

26. The memory controller according to claim 24, wherein: The control unit is configured to: The adjusted target reading voltage corresponding to the first result of the target reading voltages adjusted multiple times is smaller than the first threshold for the first time as the near-valley point voltage; In the process of performing multiple first adjustments on the near-valley point voltage with the first step length, starting from the near-valley point voltage, adjusting in the first direction with the first step length until the adjustment in the first direction is completed. The first result corresponding to the target read voltage is greater than the first threshold; starting from the near-valley point voltage, adjustment is performed in a second direction opposite to the first direction with the first step length until the first result corresponding to the target read voltage after adjustment in the second direction is greater than the first threshold.

27. The memory controller according to claim 24, wherein: The control unit is configured to: generating the first threshold value according to the first result corresponding to the target read voltage and a first mapping function; wherein the first mapping function is used to represent the relationship between the first threshold value and the first result corresponding to the target read voltage; According to the first result and the second mapping function corresponding to the target read voltage after the last adjustment, the order number of the target order is used to generate a predicted value of the target read voltage after the next adjustment; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage after the last adjustment, the order number of the target order and the predicted value of the target valley voltage of the target order.

28. The memory controller according to claim 23, wherein: The control unit is configured to: During the process of performing N second adjustments on the knee point voltage with a second step size, starting from the knee point voltage, the adjustment is performed in two opposite directions with the second step size. During the adjustment in each direction, when a first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed, and a third boundary voltage and a fourth boundary voltage are determined based on a total statistical number being greater than or equal to a preset number. During the adjustment process in each direction, if the first result corresponding to the target read voltage after one adjustment is lower than the second threshold, or if the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and the number of the remaining multiple first results whose differences from the reference value are less than the third threshold is greater than a preset number, the adjustment is stopped and the read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

29. The memory controller according to claim 28, wherein: The control unit is configured to: During the adjustment process in each direction, the adjusted target read voltages corresponding to the total statistical number of times being equal to the preset number are respectively used as the third boundary voltage and the fourth boundary voltage; During the adjustment process in each direction, if the third boundary voltage and the fourth boundary voltage have been determined, the first result corresponding to the target read voltage after the last adjustment is obtained. The adjusted target read voltage is an average value of the third boundary voltage and the fourth boundary voltage; The read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

30. The memory controller according to claim 19, wherein The memory cell array includes memory cells having a plurality of storage bits, wherein the plurality of storage bits correspond to a plurality of pages respectively; at least some of the pages correspond to a plurality of levels, wherein the plurality of levels include a first level and a second level, wherein a read voltage of the second level is less than a read voltage of the first level; The control unit is configured to: According to the target valley voltage corresponding to the first stage under the determined target valley voltage, the target valley voltage of the second stage in the multiple stages and / or the target valley voltage of other first stages with lower corresponding read voltage are generated using the determined target valley voltage.

31. A method for operating a memory device, comprising: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of memory cells in the memory device at a target read voltage; the first result including a number of bits flipped in the at least one codeword read at the first read voltage and at the second read voltage; and the difference between the first read voltage and the second read voltage being less than a preset voltage; Adjusting the target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment according to the adjusted target read voltage exceeding the range defined by the first boundary voltage and the second boundary voltage; According to the first result corresponding to the adjusted target read voltage meeting a preset condition, a target valley voltage is determined, and the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

32. A method for operating a memory system, comprising: The memory controller in the memory system sends a first instruction, wherein the first instruction instructs obtaining information representing a target valley voltage; A memory device in the memory system receives the first instruction, The operating method of the memory device according to claim 31, acquiring information representing a target valley voltage, and sending the acquired information representing the target valley voltage to the memory controller; The memory controller controls the memory device to perform a read operation using the target valley voltage in the predicted information representing the target valley voltage, and performs an error correction decoding operation on a read result of the read operation.

33. A method for operating a memory controller, comprising a control unit, the method comprising: generating a first boundary voltage and a second boundary voltage based on a first result corresponding to at least one codeword formed by a preset number of memory cells in at least one memory device coupled to the memory controller at a target read voltage; the first result includes a number of bits flipped in a read result representing at least one of the codewords at the first read voltage and at the second read voltage; and a difference between the first read voltage and the second read voltage is less than a preset voltage; Adjusting the target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; during the adjustment process, changing the direction of the current voltage adjustment according to the adjusted target read voltage exceeding the range defined by the first boundary voltage and the second boundary voltage; According to the first result corresponding to the adjusted target read voltage meeting a preset condition, a target valley voltage is determined, and the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

34. A storage medium having executable instructions stored thereon, wherein the executable instructions, when executed, implement the steps of the operating method according to any one of claims 31 to 33.

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