Semiconductor device and method of manufacturing the same

Abstract

It is difficult to stably manufacture a conventional GaN-based HEMT in which an AlN isolation layer is provided below a source electrode and a drain electrode to reduce an access resistance and in which the AlN isolation layer is not present directly below a gate electrode to reduce a gate leakage current. A method for manufacturing a semiconductor device in which a GaN HEMT is formed according to the present disclosure is provided with: a step for laminating a metal film (21) on an epitaxial wafer (10); a step for opening an opening (31) in a portion of the metal film (21) corresponding to the position at which the gate electrode (18) is to be formed; and a step for annealing the isolation layer (13) and the channel layer (12) by irradiating the opening (31) with laser light (90).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a GaN-based HEMT having an AlN layer. BACKGROUND

[0002] A GaN (Gallium Nitride)-based HEMT (High Electron Mobility Transistor) having an AlN (Aluminum Nitride) isolation layer is well known. In Patent Literature 1, a GaN-based HEMT is disclosed which reduces access resistance by providing an AlN isolation layer in a portion other than directly below a gate electrode between a source electrode and a drain electrode, and makes the AlN isolation layer not exist directly below the gate electrode to reduce gate leakage current.

[0003] In Patent Literature 1, after the AlN isolation layer of the region which becomes directly below the gate electrode is removed by etching, a barrier layer is grown again on the upper portion of the channel layer and the AlN isolation layer.

[0004] Patent Literature 1: Japanese Patent No. 5744346

[0005] Generally, the thickness of the isolation layer in the GaN-based HEMT is very thin, for example, 1 nm in Patent Literature 1. In Patent Literature 1, only the thin isolation layer is removed by etching directly below the gate.

[0006] In the manufacturing process of a semiconductor, the etching amount is controlled by the etching time, but regardless of dry etching or wet etching, the etching rate inevitably deviates in practical use. Therefore, in a case where a thin layer is desired to be removed by etching, an etching stop layer having a lower etching rate than the layer desired to be removed is generally provided behind it to stop etching, thereby ensuring a manufacturing margin to stabilize production.

[0007] However, in Patent Literature 1, the AlN isolation layer is below the GaN channel layer. The etching rate of GaN is significantly higher than that of AlN. Therefore, if etching is continued after the etching of the AlN isolation layer is completed, the GaN channel layer is easily over-etched. Therefore, it is very difficult to stably remove only the AlN channel layer by etching when considering uniformity in wafer plane and the like. In addition, it is difficult to provide an etching stop layer between the AlN isolation layer and the GaN channel layer because it affects the generation of two-dimensional electron gas, that is, the operation itself of the GaN-based HEMT.

[0008] Therefore, it is very difficult to stably manufacture the GaN-based HEMT disclosed in Patent Literature 1. SUMMARY

[0009] The present disclosure has been made in view of the above-described problems, and an object of the present disclosure is to provide a manufacturing method of a GaN-based HEMT which reduces an access resistance and reduces a gate leakage current while avoiding the difficulty of removing an AlN isolation layer by etching. In addition, another object of the present disclosure is to provide a GaN-based HEMT which reduces an access resistance and reduces a gate leakage current.

[0010] The manufacturing method of a semiconductor device according to the present disclosure is a manufacturing method of a semiconductor device formed with a GaN-based HEMT, including: a step of forming an epitaxial wafer having a channel layer and an isolation layer; a step of forming a metal film above the epitaxial wafer; a step of forming an opening portion at a position of the metal film where a gate electrode is to be formed; a step of annealing the isolation layer and the channel layer by irradiating laser light to the opening portion; and a step of forming the gate electrode in the opening portion.

[0011] The semiconductor device according to the present disclosure is a semiconductor device including a GaN-based HEMT having an epitaxial wafer formed with a channel layer above a substrate and an isolation layer above the channel layer, and a gate electrode formed above the epitaxial wafer, a portion of the channel layer located at a lower portion of the gate electrode containing Al diffused from the isolation layer, and a portion of the channel layer located at a position other than the lower portion of the gate electrode not containing Al diffused from the isolation layer.

[0012] According to the present disclosure, it is possible to provide a manufacturing method of a GaN-based HEMT which reduces an access resistance and reduces a gate leakage current while avoiding the difficulty of removing an AlN isolation layer by etching. In addition, according to the present disclosure, it is possible to provide a GaN-based HEMT which reduces an access resistance and reduces a gate leakage current. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a cross-sectional view showing a semiconductor device 100 according to Embodiment 1 of the present disclosure.

[0014] Figure 2 is a view showing a manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present disclosure.

[0015] Figure 3 is a view showing a manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present disclosure.

[0016] Figure 4 is a view showing a manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present disclosure.

[0017] Figure 5 is a view showing a manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present disclosure.

[0018] Figure 6 is a cross-sectional TEM image of the epitaxial wafer 10.

[0019] Figure 7 is a graph showing the results of elemental analysis of the epitaxial wafer before annealing.

[0020] Figure 8 is a graph showing the results of elemental analysis of the epitaxial wafer after annealing. DETAILED DESCRIPTION

[0021] Embodiment 1

[0022] An electric power amplifier according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. The same or corresponding components are denoted by the same reference numerals, and repetitive explanations can be omitted in some cases.

[0023] Figure 1 is a cross-sectional view showing a semiconductor device 100 according to Embodiment 1 of the present application.

[0024] The semiconductor device 100 is a GaN-based HEMT formed on an epitaxial wafer 10. The epitaxial wafer 10 includes a substrate 11, a channel layer 12, an isolation layer 13, a barrier layer 14, and a cap layer 15. The substrate 11 is formed of semi-insulating SiC (silicon carbide). The thickness of the substrate 11 is, for example, 100 μm, and the upper surface is, for example, the (0001) plane. The material of the substrate 11 can also be a single-crystal sapphire or the like.

[0025] The channel layer 12 formed of GaN is formed above the surface side of the substrate 11.

[0026] The isolation layer 13 is formed above the channel layer 12 so as to be in contact with the channel layer 12. The material of the isolation layer 13 is AlN, and the thickness thereof is very thin. Specifically, it can be 10 nm or less, and more preferably 0.5 nm or more and 1.5 nm or less.

[0027] The barrier layer 14 formed of AlGaN (aluminum gallium nitride) is formed above the isolation layer 13.

[0028] The cap layer 15 formed of GaN is formed above the barrier layer 14.

[0029] The source electrode 16, the drain electrode 17, and the gate electrode 18 are provided so as to be in contact with the cap layer 15. The other portions of the cap layer 15 are covered with a protective film 19 formed mainly of SiN (silicon nitride).

[0030] Further, the channel layer 12 can be laminated after a nucleation layer or a buffer layer is laminated above the substrate 11. The nucleation layer can be a thin layer formed of AlN, and the buffer layer can be a layer formed of GaN or AlGaN.

[0031] Further, it is known that a two-dimensional electron gas 20 called 2DEG is generated at the interface of the channel layer 12 composed of GaN and the isolation layer 13 composed of AlGaN in the GaN-based HEMT. In the conventional configuration, the 2DEG is uniformly distributed within the transistor.

[0032] On the other hand, in the semiconductor device 100, as described later, Al in the portion of the isolation layer 13 located at the lower portion of the gate electrode 18 is diffused to the channel layer 12 and the barrier layer 14 by laser annealing. Therefore, the concentration of the two-dimensional electron gas 20 located at the lower portion of the gate electrode 18 is reduced from other portions, and the high resistance is implemented at the lower portion of the gate electrode 18.

[0033] Next, Figures 2 to 5 is a view showing a manufacturing method of the semiconductor device 100 according to Embodiment 1. Referring to Figures 2 to 5 , the manufacturing method of the semiconductor device 100 will be described.

[0034] First, the channel layer 12 is formed on the surface side of the substrate 11, the isolation layer 13 is formed on the channel layer 12, the barrier layer 14 is formed on the isolation layer 13, and the cap layer 15 is formed on the barrier layer 14, respectively, by epitaxial growth, thereby forming an epitaxial wafer 10.

[0035] Next, as shown in (a) of Figure 2 , the source electrode 16 and the drain electrode 17 are formed on the surface of the epitaxial wafer 10 by evaporation, sputtering, plating, or the like. Thereafter, the protective film 19 is formed so as to cover the epitaxial wafer 10. The material of the protective film 19 is, for example, a silicon nitride film, a silicon oxide film, an aluminum nitride film, an aluminum oxide film, and is formed, for example, by MOCVD, ALD (Atomic Layer Deposition).

[0036] Next, as shown in (b) of Figure 2 , the metal film 21 is formed so as to cover the protective film 19. The metal film 21 is a metal thin film for reflecting the laser 90 described later. Although the material of the metal film 21 is Ni in Embodiment 1, it is not limited thereto, and can be a metal such as Au.

[0037] Next, as shown in (c) of Figure 2 , the resist 30 is applied so as to cover the metal film 21.

[0038] Next, as shown in (d) of Figure 3 , in semiconductor manufacturing, the portion of the resist 30 where the gate electrode 18 is to be formed is removed using a general so-called photolithography process, and the opening 42 is formed in the resist 30.

[0039] Next, asFigure 3 As shown in (e) of FIG. 8, the metal film 21 exposed from the opening 42 is opened using an etching process, and the opening portion 31 is formed in the metal film 21. Further, the protective film 19 is removed, and the epitaxial wafer 10 is exposed. The portion of the epitaxial wafer 10 exposed from the opening portion 31 is set as the exposed portion 32. The opening portion 31 and the exposed portion 32 are formed with the same degree of fineness as the gate electrode 18 using a so-called photolithography process.

[0040] Next, as shown in (f) of FIG. 9, the resist 30 is removed using a wet etching process or a dry etching process. Figure 3

[0041] Next, as shown in (g) of FIG. 10, the opening portion 31 is irradiated with laser light 90 to heat the exposed portion 32. As a result, the isolation layer 13 and the channel layer 12 located in the lower portion of the exposed portion 32 are annealed. The wavelength of the laser light 90 can be any wavelength at which the materials of GaN, AlGaN, AlN, and the like absorb light, and is generally a wavelength shorter than 400 nm. Figure 4

[0042] Next, as shown in (h) of FIG. 11, the metal film 21 is removed using a wet etching process or a dry etching process. Figure 4

[0043] Next, as shown in (i) of FIG. 12, after the resist 33 is applied, an opening 44 is formed in the resist 33 using a photolithography process. The opening 44 is an opening for fabricating the gate electrode 18, and is formed while exposing the opening portion 31 and the exposed portion 32 around the opening portion 31 and the exposed portion 32. Figure 4

[0044] Next, as shown in (j) of FIG. 13, the gate electrode 18 is formed in the opening portion 31. The gate electrode 18 is formed in contact with the exposed portion 32. Figure 5

[0045] Next, as shown in (k) of FIG. 14, the resist 33 is removed. Figure 5

[0046] Next, the effect of annealing will be described. Figure 6 is a cross-sectional TEM image of the vicinity of the interface between the channel layer 12 and the isolation layer 13 of the epitaxial wafer 10 observed before and after annealing, and shows the diffusion of Al in AlN by annealing. Figure 6 GaN, AlN, and AlGaN in (a) of FIG. 15 correspond to the channel layer 12, the isolation layer 13, and the barrier layer 14, respectively.

[0047] Figure 6 (a) in the upper left and (c) in the lower left of FIG. 15 are cross-sectional TEM images of the epitaxial wafer 10 before annealing, Figure 6 ​​​​​​(b) and (d) of the right upper and right lower of FIG. 10 are cross-sectional TEM images after annealing the epitaxial wafer 10 at 1140°C for 5 minutes. Figure 6 (c) of FIG. 10 is an enlarged view of the vicinity of the GaN / AlN interface of (a) of FIG. 10. Figure 6 (d) of FIG. 10 is an enlarged view of the vicinity of the GaN / AlN interface of (b) of FIG. 10. Figure 6 (a) of FIG. 11 is a cross-sectional TEM image of the epitaxial wafer 10 before annealing. Figure 6 (b) of FIG. 11 is a cross-sectional TEM image of the epitaxial wafer 10 after annealing at 1140°C for 5 minutes.

[0048] From a comparison of (a) of FIG. 11 with (b) of FIG. 11 or a comparison of (c) of FIG. 10 with (d) of FIG. 10, it is confirmed that the definition of the vicinity of the interface of the isolation layer 13 and the barrier layer 14 and the channel layer 12 and the isolation layer 13 is lost due to annealing. In particular, from a comparison of (c) of FIG. 10 with (d) of FIG. 10, the change at the AlN / GaN interface is remarkable. Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 7

[0049] Figure 8 is a result of element analysis of the epitaxial wafer 10 before annealing, Figure 7 is a result of element analysis of the epitaxial wafer 10 after annealing. Figure 8 , Figure 7 Both of (a) and (b) of FIG. 12 are graphs in which the horizontal axis indicates the distance in the depth direction from the wafer surface, the left being the barrier layer 14 side and the right being the channel layer 12 side. In addition, (a) of FIG. 12 is a graph in which the intensity of Al is shown in 5 times. Figure 8 and Figure 7 The horizontal axis of (a) and (b) of FIG. 12 does not indicate the absolute distance from the wafer surface, and thus the positions cannot be directly compared. The vertical axis indicates the intensity of the detected element (Ga, N, Al). In addition, only the intensity of Al is shown in 5 times.

[0050] When the intensity distribution of Al is compared between (a) of FIG. 12 and (b) of FIG. 12, in (a) of FIG. 12, the intensity of Al sharply drops with an amplitude of 1.6 nm from a point at a distance of 9.2 nm in the figure toward a point at a distance of 10.8 nm. That is, it is known that the concentration distribution of Al sharply switches. On the other hand, in (b) of FIG. 12, the intensity of Al drops with an amplitude of 3 nm from a point at a distance of 7.2 nm in the figure toward a point at a distance of 10.2 nm. That is, compared with before annealing, the steepness is lost, and it is known that Al of the isolation layer 13 diffuses to the channel layer 12 side after annealing. Figure 8 Figure 7 Figure 8 Figure 3

[0051] In addition, although a part of Al of the isolation layer 13 also diffuses to the barrier layer 14, the Al concentration of the channel layer 12 is overwhelmingly lower than the Al concentration of the barrier layer 14, and thus it is considered that Al diffusing from the isolation layer 13 to the channel layer 12 is much more than Al diffusing from the isolation layer 13 to the barrier layer 14.​​​​​​​​​​

[0052] Next, the operation and effects of the present disclosure are described.

[0053] In the semiconductor device 100, in a state where the metal film 21 remains except for the opening portion 31, laser light 90 is irradiated to the opening portion 31 where the gate electrode 18 is to be formed. By selecting a material of the metal film 21 that easily reflects the laser light 90, only the exposed portion 32 can be effectively heated in the surface of the epitaxial wafer 10.

[0054] Thus, in the semiconductor device 100, in the lower portion of the opening portion 31, the isolation layer 13 and the channel layer 12 are annealed, Al of the isolation layer 13 diffuses to the channel layer 12, and the concentration of the two-dimensional electron gas 20 is reduced.

[0055] On the other hand, the isolation layer 13 and the channel layer 12 including the lower portion of the source electrode and the drain electrode except for the lower portion of the opening portion 31 are not annealed. Therefore, Al of the isolation layer 13 does not diffuse to the channel layer 12, and the concentration of the two-dimensional electron gas 20 is not reduced.

[0056] Further, it is additionally described that the lower portion of the opening portion 31 herein includes not only the directly below portion of the opening portion 31 but also the vicinity of the directly below portion of the opening portion 31 that is annealed by irradiating the laser light 90 to the opening portion 31.

[0057] In other words, by irradiating the laser light 90 to the opening portion 31 where the gate electrode 18 is to be formed, Al of the isolation layer 13 diffuses to the channel layer 12 in the lower portion of the opening portion 31, as a result, the concentration of the two-dimensional electron gas 20 in the lower portion of the opening portion 31 becomes lower than the concentration of the two-dimensional electron gas 20 in the portion except for the lower portion of the opening portion 31.

[0058] As a result, the semiconductor device 100 functions to reduce the access resistance by providing the AlN isolation layer in the portion except for the lower portion of the gate electrode 18 and to realize high withstand voltage by high-resistance in the lower portion of the gate electrode 18.

[0059] In addition, the manufacturing process of the semiconductor device 100 can avoid the difficulty of removing the thin isolation layer 13 made of AlN by etching.

[0060] Further, although in the above description of the (e) of the (d), the protective film 19 is removed to expose the epitaxial wafer 10, the protective film 19 can be thinly remained, for example, to the extent that it does not affect the annealing of the isolation layer 13 and the channel layer 12 by the laser light irradiation, and removed at the time of forming the gate electrode 18 described in the (j) below. Figure 5 ​ In this way, by not exposing the surface of the epitaxial wafer 10 to the outside atmosphere, it is possible to reduce the damage to the exposed portion 32 in the middle process.​

[0061] The present disclosure is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments are embodiments that are described in detail for the purpose of easily understanding the present disclosure, and are not necessarily limited to having all the structures described. In addition, addition, deletion, or substitution of other structures can be made to a part of the structure of the embodiments.

[0062] Explanation of Reference Signs

[0063] 10...epitaxial wafer; 11...substrate; 12...channel layer; 13...isolation layer; 14...barrier layer; 15...cap layer; 16...source electrode; 17...drain electrode; 18...gate electrode; 19...protective film; 20...two-dimensional electron gas; 21...metal film; 31...opening portion; 32...exposed portion; 90...laser; 100...semiconductor device.

Claims

1. A method for manufacturing a semiconductor device, comprising a GaN-based HEMT semiconductor device, characterized in that, have: A process for forming an epitaxial wafer having a channel layer and an isolation layer disposed in contact with the channel layer; The process of forming a metal film on the epitaxial wafer; The process of creating an opening in the metal film; The process of annealing the insulating layer and the channel layer by irradiating the opening with a laser; and The process of forming the gate electrode at the opening.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The isolation layer is composed of AlN, and the Al in the isolation layer diffuses into the channel layer through the annealing process.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The metal film is Ni or Au.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The wavelength of the laser is shorter than 400 nm.

5. A semiconductor device comprising a GaN-based HEMT, the semiconductor device having an epitaxial wafer having a channel layer formed above a substrate and an isolation layer formed above the channel layer, and a gate electrode formed above the epitaxial wafer. Its features are, The portion of the channel layer located below the gate electrode contains Al diffused from the isolation layer, while the portion of the channel layer located elsewhere does not contain Al diffused from the isolation layer.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The isolation layer is composed of AlN.

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