Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. A semiconductor device is provided that includes a vertical transistor (242) and a memory cell (244) coupled to the vertical transistor, respectively. The vertical transistor includes a semiconductor layer (252) and a gate structure (256, 248). The semiconductor layer includes a vertical portion (256) extending in a vertical direction and a first lateral portion (258) extending in a lateral direction from a first end of the vertical portion. The gate structure is coupled to the vertical portion of the semiconductor layer and extends in the vertical direction. The first lateral portions of the semiconductor layers of two adjacent vertical transistors in the lateral direction are connected to each other.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] Planar memory cells have been scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become more difficult and more costly. As a result, the memory density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate operation of the memory array. SUMMARY

[0004] In one aspect of the present disclosure, a semiconductor device is provided, which includes vertical transistors and memory cells coupled to the vertical transistors. The vertical transistors include semiconductor layers and gate structures. The semiconductor layers include vertical portions extending in a vertical direction and first lateral portions extending in a lateral direction from first ends of the vertical portions. The gate structures are coupled to the vertical portions of the semiconductor layers and extend in the vertical direction. The first lateral portions of the semiconductor layers of two adjacent vertical transistors in the lateral direction are connected to each other.

[0005] In some embodiments, the semiconductor layers have a U-shaped cross-section in a plane formed by the vertical direction and the lateral direction.

[0006] In some embodiments, the semiconductor layers of the vertical transistors include second lateral portions extending in the lateral direction from second ends of the vertical portions, and the second lateral portions are coupled to respective memory cells.

[0007] In some embodiments, the memory cells include capacitors having first electrodes, second electrodes, and dielectric layers between the first electrodes and the second electrodes. The first electrodes are directly coupled to the second lateral portions of the semiconductor layers of respective vertical transistors.

[0008] In some embodiments, the second electrodes include a multi-layer structure, each layer of the multi-layer structure including one of carbon, polysilicon, metal, a metal compound, and a silicide.

[0009] In some embodiments, two adjacent vertical transistors along the lateral direction are separated by an isolation structure, and the gate structure of the vertical transistors is located on a side of the vertical portion of the semiconductor layer opposite the isolation structure.

[0010] In some embodiments, the isolation structure includes a conductor layer and a dielectric layer surrounding the conductor layer.

[0011] In some embodiments, the dielectric layer includes a first dielectric layer located below the conductor layer, a second dielectric layer located on the conductor layer, a left sidewall located on a left side of the conductor layer to separate the conductor layer from a first vertical transistor on the left side, and a right sidewall located on a right side of the conductor layer to separate the conductor layer from a second vertical transistor on the right side.

[0012] In some embodiments, the first dielectric layer, the second dielectric layer, the left sidewall, and the right sidewall include different materials.

[0013] In some embodiments, the semiconductor device further includes a bit line extending along the lateral direction and directly coupled to the vertical transistors through the first lateral portion of the semiconductor layer of the vertical transistors.

[0014] In some embodiments, the bit line is coupled to the first lateral portion at a bottom of the semiconductor layer.

[0015] In some embodiments, the semiconductor layer has a leakage value lower than one picoampere.

[0016] In some embodiments, the semiconductor layer includes In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga xZn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O and In x Ga y one of O, Yb, Ga, Zn, Sn, O and In, or a combination thereof.

[0017] In some embodiments, the semiconductor device further comprises a peripheral circuit stacked on the vertical transistor.

[0018] In some embodiments, the semiconductor device further comprises a pad-out interconnect layer stacked on the memory cell.

[0019] In another aspect of the disclosure, a method for forming a semiconductor device is provided. The method includes forming a cell hole on a substrate, and then forming a dielectric layer of a capacitor in the cell hole, the cell hole being partially filled by the dielectric layer. The method further includes forming a first electrode of the capacitor covering the dielectric layer, the cell hole being completely filled by the first electrode. The method further includes forming a vertical transistor coupled with the first electrode and forming a second electrode of the capacitor surrounding the dielectric layer.

[0020] In some embodiments, the substrate includes at least one mesh layer alternately stacked with at least one sacrificial layer. Forming the second electrode of the capacitor includes removing at least one sacrificial layer to form a cavity and filling the cavity with the second electrode of the capacitor.

[0021] In some embodiments, filling the cavity with the second electrode of the capacitor includes forming a multi-layer structure in the cavity. Each layer of the multi-layer structure includes one of carbon, polysilicon, metal, metal compound, and silicide.

[0022] In some embodiments, forming a vertical transistor coupled with the first electrode includes forming an isolation structure between two adjacent vertical transistors.

[0023] In some embodiments, forming the isolation structure between two adjacent vertical transistors includes forming a first dielectric layer on the substrate, forming a conductor layer on the first dielectric layer, and forming a second dielectric layer on the conductor layer.

[0024] In some embodiments, forming the isolation structure between two adjacent vertical transistors further comprises forming a left side wall on a left side of the conductor layer to separate the conductor layer from the first vertical transistor on the left side; and forming a right side wall on a right side of the conductor layer to separate the conductor layer from the second vertical transistor on the right side.

[0025] In some embodiments, the first dielectric layer, the second dielectric layer, the left side wall, and the right side wall comprise different materials.

[0026] In some embodiments, forming the vertical transistor coupled to the first electrode comprises forming a semiconductor layer covering the isolation structure. The semiconductor layer has a U-shaped cross-section in a plane formed by a vertical direction and a lateral direction.

[0027] In some embodiments, the semiconductor layer comprises: a vertical portion of the first vertical transistor covering the left side wall; a first lateral portion of the first vertical transistor covering the second dielectric layer; a vertical portion of the second vertical transistor covering the right side wall; and a first lateral portion of the second vertical transistor covering the second dielectric layer.

[0028] In some embodiments, forming the vertical transistor coupled to the first electrode further comprises etching the first electrode to form a recess to accommodate the vertical transistor.

[0029] In some embodiments, the method further comprises forming a bit line extending along a lateral direction and directly coupled to the vertical transistor through the first lateral portion of the semiconductor layer of the vertical transistor.

[0030] In some embodiments, the bit line is coupled to the first lateral portion at a bottom of the semiconductor layer.

[0031] In some embodiments, the method further comprises forming a peripheral circuit stacked on the vertical transistor.

[0032] In some embodiments, the method further comprises forming a pad-out interconnect layer stacked on the capacitor.

[0033] In some embodiments, the semiconductor layer has a leakage value lower than one pico-amp.

[0034] In some embodiments, the semiconductor layer comprises In x Ga y Zn z O, In x Ga y Si z O, Inx Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O and In x Ga y O, or combinations thereof.

[0035] In yet another aspect of the disclosure, a semiconductor device is provided that includes a single-gate vertical transistor and a storage cell coupled in correspondence with the single-gate vertical transistor. Two adjacent single-gate vertical transistors in a lateral direction are separated by an isolation structure and share a U-shaped semiconductor layer that covers both sides of the isolation structure in the lateral direction. The gate structure of the single-gate vertical transistor is coupled with a side of the semiconductor layer opposite the isolation structure. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0037] Figure 1 A schematic circuit diagram of a semiconductor device including an array of memory cells, each having a vertical transistor, is shown in accordance with some embodiments of the present disclosure.

[0038] Figure 2 A schematic side view of a cross-section of a vertical transistor and a storage cell of a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0039] Figure 3 A flowchart of a manufacturing method for forming a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0040] Figures 4A-4O each illustrating a semiconductor device at a certain manufacturing stage of a method according to various embodiments of the present disclosure Figure 3 schematic diagram of a semiconductor device at a certain manufacturing stage of a method.

[0041] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0042] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the present disclosure. Moreover, the present disclosure can also be employed in various other applications, including, for example, those not specifically described herein. Accordingly, the function and / or the arrangement of the elements described in the present disclosure can be combined, adjusted, and / or modified in various ways without departing from the scope of the present disclosure.

[0043] In general, terminology can be understood at least in part from usage in context. For example, terms, such as "one or more" as used herein, can be taken to mean that "at least one," or "one," and that an inclusion of the integer zero in each instance is contemplated, unless the content clearly dictates otherwise. As used herein, terms, such as "component," "member," "element," "entity," "device," "unit," "step," "operation," "process," and / or "function" can be understood as including one or more instances, singular or plural, unless the content clearly dictates otherwise. As used herein, terms, such as "axial," "radial," "circumferential," "annular," "central," "radially," "axially," "circumferentially," "annularly," "centrally," and the like can be understood to mean that the orientation of the device is as shown in the drawings, unless the content clearly dictates otherwise. As used herein, terms, such as "coupled," "connected," and "in communication with" can be understood to mean directly connected to or in communication with, or indirectly connected to or in communication with through one or more intervening, supporting, and / or interstitial elements, layers, features, and / or spaces, unless the content clearly dictates otherwise.

[0044] It should be readily understood that the terms "on," "over," and "above" in the present disclosure are to be interpreted in the broadest context possible so that "on" means not only directly on something, but also includes the meaning of being on something with intervening features or layers therebetween, and "over" or "above" includes not only over or above something, but also includes the meaning of being over or above something without intervening features or layers therebetween (i.e., directly on something).

[0045] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] As used herein, the term "substrate" refers to a material on which a subsequent material layer is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer, etc.

[0047] As used herein, the term "layer" refers to a portion of material comprising a region having a thickness. A layer can extend over the entire underlying or overlying structure, or can have a scope less than the underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along a tapering surface. A substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers thereon, above and / or below. A layer can comprise multiple layers. For example, an interconnect layer can comprise one or more conductor and contact layers (within which interconnect lines and / or vertical interconnect via contacts are formed) and one or more dielectric layers.

[0048] In some semiconductor devices, such as dynamic random access memory (DRAM), memory cells use transistors as switching or selection devices. In a one transistor one capacitor (1T1C) DRAM structure, data is stored in a capacitor. There is a high demand for low leakage on the selection transistor. Thus, there is a need to identify alternative channel materials with lower leakage compared to using single crystalline silicon as the channel material. Further, as DRAM continues to scale, the cell size of each capacitor cell continues to decrease, the etch aspect ratio of the capacitor increases, causing significant difficulties in the manufacturing process and increasing product cost.

[0049] To solve one or more of the aforementioned problems, the present disclosure introduces a solution in which a low leakage material such as a metal oxide semiconductor material is selected to be used as the channel of the select transistor to solve the leakage problem in the DRAM scaling process. The disclosed semiconductor device includes single gate vertical transistors and the shape and structure of the active region of each vertical transistor is redesigned to accommodate the low leakage material. A corresponding manufacturing process of the semiconductor device is described in which the semiconductor layer connecting two adjacent vertical transistors and the capacitor can be formed before the transistor of the 1T1C DRAM structure, and the manufacturing of the vertical transistors occurs in the middle of the manufacturing of the capacitor. By using the new channel material of the select transistor in the DRAM and the corresponding new manufacturing method, the disclosed semiconductor device can have a high memory density with further reduced cell size. The manufacturing difficulty of the disclosed semiconductor device is reduced by applying the disclosed capacitor manufacturing process. The disclosed manufacturing process can have a simplified process compared to the existing method, thus reducing the manufacturing cost.

[0050] According to some embodiments of the present disclosure, each vertical transistor includes a semiconductor layer extending in a vertical direction and a gate structure located beside the semiconductor layer, according to the scope of the present disclosure. In some embodiments, the word line and the bit line connected to the vertical transistor are arranged along a first lateral direction and a second lateral direction, respectively. Each semiconductor layer of the corresponding vertical transistor extends in the vertical direction. By using such an arrangement, the memory area efficiency can be improved. In addition, the memory cell array and the peripheral circuit can be formed separately on different wafers, so that the manufacturing processes of the memory cell array and the peripheral circuit do not affect each other, thus further improving the memory area efficiency.

[0051] According to some embodiments of the present disclosure, the semiconductor layers of two adjacent vertical transistors along the lateral direction are connected to each other, thus extending the channel length of each vertical transistor, according to the scope of the present disclosure. Thus, the short channel effect caused by the reduced feature size can be alleviated by using the extended channel. In addition, the dielectric layer and the first electrode of the capacitor are formed before the vertical transistors are manufactured, and the second electrode of the capacitor is formed after the vertical transistors are manufactured. This new manufacturing method is compatible with high temperature processes, thus being able to completely consume the heat budget of the manufacturing process.

[0052] Figure 1A schematic diagram of a semiconductor device 100 including a peripheral circuit and an array of memory cells, each having a vertical transistor, is shown in accordance with some aspects of the present disclosure. The semiconductor device 100 can include a memory cell array 110 and a peripheral circuit 120 coupled to the memory cell array 110. The memory cell array 110 can be any suitable array of memory cells, where each memory cell 130 includes a vertical transistor 132 and a storage cell 134 coupled to the vertical transistor 132. In some implementations, the memory cell array 110 is an array of DRAM cells, and the storage cell 134 is a capacitor for storing charge as binary information stored by the respective DRAM cell. As shown in Figure 1 The memory cells 130 can be arranged in a two-dimensional (2D) array having rows and columns, as shown in

[0053] In accordance with the scope of the present disclosure, the vertical transistors 132 (e.g., vertical metal-oxide-semiconductor field-effect transistors (MOSFETs)) can replace conventional planar transistors as pass transistors of the memory cells 130 to reduce the area occupied by the pass transistors, coupling capacitance, and interconnect wiring complexity, as described in detail below. As shown in Figure 1As shown in FIG. 1, in some embodiments, unlike planar transistors formed into a substrate, vertical transistors 132 include a semiconductor body that extends vertically (in the z-direction) above a substrate (not shown). That is, the semiconductor body can extend above a top surface of the substrate, such that not only a top surface of the semiconductor body is exposed, but also one or more of the side surfaces of the semiconductor body are exposed. As shown in FIG. 1, for example, the semiconductor body can have a cuboid shape, such that four side surfaces are exposed. It should be understood that the semiconductor body can take any appropriate shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other appropriate shape. It should be understood that a semiconductor layer having a circular or elliptical shape in plan view can still be considered to have multiple side surfaces, such that a gate structure is coupled with more than one side surface of the semiconductor layer, in accordance with the scope of the present disclosure. As described below in connection with a fabrication process, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate). Figure 1 As shown in FIG. 1, for example, the semiconductor body can have a cuboid shape, such that four side surfaces are exposed. It should be understood that the semiconductor body can take any appropriate shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other appropriate shape. It should be understood that a semiconductor layer having a circular or elliptical shape in plan view can still be considered to have multiple side surfaces, such that a gate structure is coupled with more than one side surface of the semiconductor layer, in accordance with the scope of the present disclosure. As described below in connection with a fabrication process, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0054] As shown in FIG. 1, for example, the semiconductor body can have a cuboid shape, such that four side surfaces are exposed. It should be understood that the semiconductor body can take any appropriate shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other appropriate shape. It should be understood that a semiconductor layer having a circular or elliptical shape in plan view can still be considered to have multiple side surfaces, such that a gate structure is coupled with more than one side surface of the semiconductor layer, in accordance with the scope of the present disclosure. As described below in connection with a fabrication process, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate). Figure 1 As shown in FIG. 1, for example, the semiconductor body can have a cuboid shape, such that four side surfaces are exposed. It should be understood that the semiconductor body can take any appropriate shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other appropriate shape. It should be understood that a semiconductor layer having a circular or elliptical shape in plan view can still be considered to have multiple side surfaces, such that a gate structure is coupled with more than one side surface of the semiconductor layer, in accordance with the scope of the present disclosure. As described below in connection with a fabrication process, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate). Figure 1 As shown in FIG. 1, for example, the semiconductor body can have a cuboid shape, such that four side surfaces are exposed. It should be understood that the semiconductor body can take any appropriate shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other appropriate shape. It should be understood that a semiconductor layer having a circular or elliptical shape in plan view can still be considered to have multiple side surfaces, such that a gate structure is coupled with more than one side surface of the semiconductor layer, in accordance with the scope of the present disclosure. As described below in connection with a fabrication process, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0055] As shown in FIG. 1, for example, the semiconductor body can have a cuboid shape, such that four side surfaces are exposed. It should be understood that the semiconductor body can take any appropriate shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other appropriate shape. It should be understood that a semiconductor layer having a circular or elliptical shape in plan view can still be considered to have multiple side surfaces, such that a gate structure is coupled with more than one side surface of the semiconductor layer, in accordance with the scope of the present disclosure. As described below in connection with a fabrication process, the semiconductor body can be formed from the substrate (e.g., by etching or epitaxy), and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate). Figure 1As shown, the vertical transistor 132 may further include a pair of source and drain electrodes (S / D, doped regions, also known as source and drain electrodes) formed at opposite ends of the semiconductor body in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain electrodes may be separated by a gate structure in the vertical direction (z-direction). As a result, when the gate voltage applied to the gate electrode of the gate structure exceeds the threshold voltage of the vertical transistor 132, one or more channels (not shown) of the vertical transistor 132 may be formed in the semiconductor body vertically located between the source and drain electrodes.

[0056] In some implementations, such as Figure 1 As shown, the vertical transistor 132 is a multi-gate transistor. This means that the gate structure can be connected to more than one side of the semiconductor body (e.g., Figure 1 The four sides of the transistor are coupled together to form more than one gate, allowing multiple channels to be formed between the source and drain during operation. This differs from planar transistors, which include only a single planar gate (and thus a single planar channel). Figure 1 The vertical transistor 132 shown may include a plurality of vertical gates located on multiple sides of a semiconductor body, which is attributed to the semiconductor structure of the semiconductor body and the gate structure surrounding the multiple sides of the semiconductor body. Compared to planar transistors, Figure 1 The vertical transistor 132 shown can have a larger gate control area, thereby achieving better channel control with a smaller subthreshold swing. During the off-state, leakage current of the vertical transistor 132 is also significantly reduced because the channel is fully depleted. As described in detail below, multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side-gate vertical transistors), tri-gate vertical transistors (e.g., tri-side-gate vertical transistors), and GAA vertical transistors.

[0057] Although the vertical transistor 132 is shown as Figure 1 The present invention pertains to multi-gate transistors, but it should be understood that the vertical transistors disclosed herein may also include single-gate transistors, as detailed below. That is, the gate structure may be coupled to one side of the semiconductor body, for example, to increase transistor and memory cell density. It should also be understood that although the gate dielectric is shown as separate from other gate dielectrics of adjacent vertical transistors (not shown) (i.e., a separate structure), the gate dielectric may be part of a continuous dielectric layer of gate dielectrics having multiple vertical transistors.

[0058] like Figure 1As shown in FIG. 1, the storage unit 134 can be coupled to the source or drain of the vertical transistor 132. The storage unit 134 can include any device capable of storing binary data (e.g., 0s and Is), including but not limited to capacitors for DRAM cells and FRAM cells and PCM elements for PCM cells. The peripheral circuitry 120 can be coupled to the memory cell array 110 by bit lines 150, word lines 140, and any other appropriate metal wiring. As described above, the peripheral circuitry 120 can include any appropriate circuitry to facilitate operation of the memory cell array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from each memory cell 130 via the word lines 140 and bit lines 150. The peripheral circuitry 120 can include various types of peripheral circuitry formed using CMOS technology.

[0059] Figure 2 A side view of a cross-section of a semiconductor device 200 including a vertical transistor is shown in accordance with some aspects of the present disclosure. It should be appreciated that Figure 2 For illustrative purposes only, and not necessarily reflecting actual device structures (e.g., interconnects) in practice. In some embodiments, the semiconductor device 200 represents an example of a bonded chip. The components of the semiconductor device 200 (e.g., the memory cell array and the peripheral circuitry) can be formed separately onto different substrates, which are then bonded together to form the bonded chip. The semiconductor device 200 can include a first semiconductor structure 210 having peripheral circuitry for a memory cell array. The semiconductor device 200 can also include a second semiconductor structure 220 having a memory cell array disposed in a stack above the first semiconductor structure 210. According to some embodiments, the first semiconductor structure 210 and the second semiconductor structure 220 are bonded at a bonding interface 230 located therebetween. As Figure 2 As shown in FIG. 2, the first semiconductor structure 210 can include a substrate 202, which can include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material.

[0060] The first semiconductor structure 210 can include peripheral circuitry 204 located on the substrate 202. In some embodiments, the peripheral circuitry 204 includes a plurality of transistors 203 (e.g., planar transistors and / or semiconductor junctions). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 203) can also be formed on or within the substrate 202.

[0061] In some embodiments, the first semiconductor structure 210 further includes an interconnect layer 206 located above the peripheral circuitry 204 to transmit electrical signals to and from the peripheral circuitry 204. The interconnect layer 206 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect channel (VIA) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-process (BEOL) interconnects. The interconnect layer 206 may further include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”), within which the interconnects and VIA contacts may be formed. That is, the interconnect layer 206 may include interconnects and VIA contacts located within multiple ILD layers. In some embodiments, the peripheral circuitry 204 is coupled to each other via interconnects in the interconnect layer 206. The interconnects in the interconnect layer 206 may be encapsulated in a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer can be formed using dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0062] like Figure 2 As shown, the first semiconductor structure 210 may further include a bonding layer 207 located at the bonding interface 230 above the interconnect layer 206 and the peripheral circuitry 204. The bonding layer 207 may include a plurality of bonding contacts 205 and a dielectric material electrically isolating the bonding contacts 205. The bonding contacts 205 may include a conductive material, such as Cu. The remaining regions of the bonding layer 207 may be formed using a dielectric material, such as silicon oxide. The bonding contacts 205 in the bonding layer 207 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 2 As shown, the second semiconductor structure 220 may also include a bonding layer 215 located above the bonding layer 207 of the first semiconductor structure 210 at the bonding interface 230. The bonding layer 215 may include a plurality of bonding contacts 213 and a dielectric material electrically isolating the bonding contacts 213. The bonding contacts 213 may include a conductive material, such as Cu. The remaining regions of the bonding layer 215 may be formed using a dielectric material, such as silicon oxide. The bonding contacts 213 in the bonding layer 215 and the surrounding dielectric material may be used for hybrid bonding. According to some embodiments, the bonding contacts 213 are coupled to the bonding contacts 205 at the bonding interface 230.

[0063] The second semiconductor structure 220 can be bonded to the top of the first semiconductor structure 210 in a face-to-face manner at a bonding interface 230. In some embodiments, the bonding interface 230 is disposed between the bonding layer 215 and the bonding layer 207 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intervening layer such as solder or adhesive) and can achieve both metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 230 is where the bonding layer 215 and the bonding layer 207 meet and bond. In practice, the bonding interface 230 can be a layer of a certain thickness that includes the top surface of the bonding layer 207 of the first semiconductor structure 210 and the bottom surface of the bonding layer 215 of the second semiconductor structure 220.

[0064] In some embodiments, the second semiconductor structure 220 further includes an interconnect layer 212 including bit lines 217 over the bonding layer 215 to carry electrical signals. The interconnect layer 212 can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 212 also include local interconnects such as bit line contacts, word line contacts, and capacitor contacts. The interconnect layer 212 can further include one or more ILD layers within which interconnect lines and VIA contacts can be formed. The interconnects in the interconnect layer 212 can be of a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0065] In some embodiments, the second semiconductor structure 220 includes a DRAM device in which memory cells are provided in the form of an array of DRAM cells 240 over the interconnect layer 212 and the bonding layer 215. That is, the interconnect layer 212 including the bit lines 217 can be disposed between the bonding layer 215 and the array of DRAM cells 240. It should be appreciated that the array of DRAM cells 240 can be disposed over the bonding layer 215 and the interconnect layer 212. Figure 2 A cross-section of the semiconductor device 200 in FIG. 1A can be taken along the bit line direction (y-direction) and a bit line 217 in the interconnect layer 212 that extends in the y-direction laterally can be coupled to a column of DRAM cells 240.

[0066] Each DRAM cell 240 can include a vertical transistor 242 and a capacitor 244 coupled to the vertical transistor 242. The DRAM cell 240 can be a 1T1C cell composed of one transistor and one capacitor. It should be appreciated that the DRAM cell 240 can have any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc.

[0067] The vertical transistors 242 can be MOSFETs used to switch the respective DRAM cells 240. In some embodiments, the vertical transistors 242 include a semiconductor layer 252 (i.e., an active region capable of forming multiple channels therein) extending vertically (along the z-direction) and a gate structure coupled with multiple sides of the semiconductor layer 252. In some embodiments, the semiconductor layer 252 has a leakage value below a pico-amp. For example, the semiconductor layer 252 can include a metal-oxide semiconductor material. In the present embodiment, the semiconductor layer can be one or more of zinc indium gallium oxide (In x Ga y Zn z O), silicon indium gallium oxide (In x Ga y Si z O), zinc indium tin oxide (In x Sn y Zn z O), zinc indium oxide (In x Zn y O), zinc oxide (Zn x O), tin zinc oxide (Zn x Sn y O), zinc oxynitride (Zn x O y N), tin zinc zirconium oxide (Zr x Zn y Sn z O), tin oxide (Sn x O), zinc indium hafnium oxide (Hf x In y Zn z O), tin zinc gallium oxide (Ga x Zn y Sn z O), tin zinc aluminum oxide (Al x Zn y Sn z O), zinc gallium ytterbium oxide (Yb x Ga y Zn z O), gallium indium oxide (In x Ga y O), and the like.

[0068] As Figure 2As shown in FIG. 2, in some embodiments, the semiconductor layer 252 includes a vertical portion 256 extending along a vertical direction (z direction), a first lateral portion 254 extending from a first end of the vertical portion 256 along a lateral direction (y direction), and a second lateral portion 258 extending from a second end of the vertical portion 256 along the lateral direction (y direction). The first lateral portion 254 is coupled to the bit line 217, and the second lateral portion 258 is coupled to the corresponding memory cell 244. Referring to Figure 2 Two first lateral portions 258 of the semiconductor layer of two adjacent vertical transistors 242 along the lateral direction are interconnected, resulting in a U-shaped cross section of the semiconductor layer 252 of the two adjacent vertical transistors 242 in the y-z plane.

[0069] The vertical transistor 242 can further include a source and a drain disposed at two ends (upper end and lower end) of the semiconductor layer 252 along the vertical direction (z direction), respectively. In some embodiments, one of the source and the drain is coupled to the capacitor 244 and the other of the source and the drain is coupled to the bit line 217. The source and the drain can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. As shown in FIG. 2, the source and the drain of the vertical transistor 242 are doped with an N-type dopant (e.g., P or As) at a desired doping level. Figure 2 As shown in FIG. 2, the contact area between the capacitor 244 and the vertical transistor 242 is equal to the area of the second lateral portion 258 in the x-y plane, which is ten times larger than the area of the second end of the vertical portion 256 in the x-y plane. Due to the increase of the contact area, the contact resistance can be significantly reduced. In this case, the source node contact between the capacitor 244 and the vertical transistor 242 can be omitted. As shown in FIG. 2, the source or the drain coupled to the bit line 217 extends along the lateral direction (y direction). The bit line 217 can be directly formed on the laterally extended source or drain of the vertical transistor 242, thereby simplifying the manufacturing process compared to coupling the bit line 217 to the first end of the vertical portion 256. Figure 2

[0070] ​In some embodiments, the gate structure includes a gate dielectric 256 and a gate electrode 248. In some embodiments, the gate dielectric 256 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric including, but not limited to, aluminum oxide (AI2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), or any combination thereof. In some embodiments, the gate electrode 248 includes a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 248 includes multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure can be a "gate oxide / gate polysilicon" gate, in which the gate dielectric 256 includes silicon oxide and the gate electrode includes doped polysilicon. In another example, the gate structure can be a high-k metal gate (HKMG), in which the gate dielectric 256 includes a high-k dielectric and the gate electrode includes a metal.

[0071] As described above, since the gate electrode 248 can be part of a word line or extend as a word line in the word line direction (x direction), although Figure 2 Although not directly shown in FIG. 2, the second semiconductor structure 220 of the semiconductor device 200 can also include a plurality of word lines each extending in the word line direction (x direction). Each word line can be coupled to a row of DRAM cells 240. That is, the bit lines 217 and the word lines can extend in two mutually perpendicular lateral directions, and the semiconductor layers 252 of the vertical transistors 242 can extend in a vertical direction perpendicular to the two lateral directions in which the bit lines 217 and the word lines extend.

[0072] In some embodiments, the rows of vertical transistors 242 separated by the trench isolation 250 are mirror-symmetric with respect to the isolation structure 250, with the gate structures of the vertical transistors 242 located on a side of the vertical portions 256 of the semiconductor layers 252 opposite the isolation structure 250. The isolation structure 250 can be formed using a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be appreciated that the isolation structure 250 can include air gaps each disposed laterally between adjacent semiconductor layers 252. As described below in connection with the fabrication process, the air gaps can be formed due to the relatively small pitch of the vertical transistors 242 in the bit line direction (e.g., the y direction). On the other hand, the relatively large dielectric constant of air (e.g., approximately 4 times the dielectric constant of silicon oxide) in the air gaps can improve the insulating effect between the vertical transistors 242 compared to some dielectrics (e.g., silicon oxide).

[0073] In some embodiments, the isolation structure 250 includes a conductor layer 245 surrounded by a dielectric layer. The plurality of conductor layers 245 in the semiconductor device 200 are connected to a common ground such that no charge accumulates between two adjacent vertical transistors 240, which greatly reduces the electrical coupling between the semiconductor layers 252 of two adjacent vertical transistors 240 in this way. In some embodiments, the conductor layer 245 includes a conductive material, which includes but is not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the conductor layer 245 includes a plurality of conductive layers, for example, a W layer on top of a TiN layer.

[0074] As shown in FIG. 2B, the semiconductor device 200 includes a plurality of vertical transistors 240, each of which includes a semiconductor layer 252, a source / drain electrode 254, and a gate electrode 258. In some embodiments, the semiconductor layer 252 includes a semiconductor material, which includes but is not limited to silicon, germanium, silicon- germanium, gallium arsenide, or any combination thereof. In some embodiments, the semiconductor layer 252 includes a plurality of semiconductor layers, for example, a silicon layer on top of a germanium layer. Figure 2 As shown in FIG. 2B, the semiconductor device 200 includes a plurality of vertical transistors 240, each of which includes a semiconductor layer 252, a source / drain electrode 254, and a gate electrode 258. In some embodiments, the semiconductor layer 252 includes a semiconductor material, which includes but is not limited to silicon, germanium, silicon- germanium, gallium arsenide, or any combination thereof. In some embodiments, the semiconductor layer 252 includes a plurality of semiconductor layers, for example, a silicon layer on top of a germanium layer.

[0075] As shown in FIG. 2B, the semiconductor device 200 includes a plurality of vertical transistors 240, each of which includes a semiconductor layer 252, a source / drain electrode 254, and a gate electrode 258. In some embodiments, the semiconductor layer 252 includes a semiconductor material, which includes but is not limited to silicon, germanium, silicon- germanium, gallium arsenide, or any combination thereof. In some embodiments, the semiconductor layer 252 includes a plurality of semiconductor layers, for example, a silicon layer on top of a germanium layer. Figure 2 As shown in FIG. 2B, the semiconductor device 200 includes a plurality of vertical transistors 240, each of which includes a semiconductor layer 252, a source / drain electrode 254, and a gate electrode 258. In some embodiments, the semiconductor layer 252 includes a semiconductor material, which includes but is not limited to silicon, germanium, silicon- germanium, gallium arsenide, or any combination thereof. In some embodiments, the semiconductor layer 252 includes a plurality of semiconductor layers, for example, a silicon layer on top of a germanium layer.

[0076] In some embodiments, the first electrode 253 and / or the second electrode 257 can comprise an electrically conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the first electrode 253 and / or the second electrode 257 comprises a multi-layer structure, each layer of which comprises one of TiN, TaN, carbon, polysilicon, metal, metal compound, and silicide. For example, as shown in Figure 2 the second electrode 257 comprises a first layer 261 directly coupled with the capacitor dielectric 255, a second layer 262 surrounded by the first layer 261, and a third layer 263 surrounded by the second layer 262. In some embodiments, the material of each layer of the multi-layer structure is different from the material of the other layers. For example, the first layer 261 is TiN, the second layer 262 is carbon, and the third layer 263 is W. In some embodiments, the capacitor dielectric 255 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric including, but not limited to, AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof.

[0077] In some embodiments, the capacitor 244 has a relatively large height and needs to be mechanically stabilized by means of at least one grid layer 260, as shown in Figure 2 Therefore, the spacing between the capacitors 244 remains consistent, thereby preventing the capacitors from breaking. Without the grid layer 260, the capacitors can tilt over the adjacent capacitors and come into contact with them. The grid layer 260 comprises a dielectric material having a Mohs hardness greater than that of silicon oxide, which has a Mohs hardness of about 6. In some embodiments, the grid layer 260 can be silicon nitride, silicon carbide, corundum, boron carbide, boron nitride, or any combination thereof. In some embodiments, as the aspect ratio of the capacitor 409 increases, two or more levels of grids are needed to ensure mechanical stability.

[0078] As shown in Figure 3 In some embodiments, the vertical transistor 242 is vertically disposed between the capacitor 244 and the bonding interface 230. That is, the vertical transistor 242 can be arranged closer to the peripheral circuit 204 of the first semiconductor structure 210 and the bonding interface 230 than the capacitor 244. According to some embodiments, since the bit line 217 and the capacitor 244 are coupled to opposite ends of the vertical transistor 242 as described above, the bit line 217 (as part of the interconnect layer 212) is vertically disposed between the vertical transistor 242 and the bonding interface 230. As a result, the interconnect layer 212 including the bit line 217 can be arranged close to the bonding interface 230 to reduce the routing distance and complexity of the interconnect.

[0079] As shown in Figures 4A-4OAs shown, the second semiconductor structure 220 may further include a pad-out interconnect layer 270 located above the DRAM cell 240. The pad-out interconnect layer 270 may include interconnects located within one or more ILD layers, such as contact pads 272. The pad-out interconnect layer 270 and the interconnect layer 212 may be formed on opposite sides of the DRAM cell 240. According to some embodiments, a capacitor 244 is configured to be located vertically between the vertical transistor 242 and the pad-out interconnect layer 270. In some embodiments, the interconnects in the pad-out interconnect layer 270 are capable of transmitting electrical signals between the semiconductor device 200 and external circuitry, for example, to achieve pad-out purposes. In some embodiments, the second semiconductor structure 220 further includes one or more contacts 274 that extend through a portion of the pad-out interconnect layer 270, thereby establishing a connection between the pad-out interconnect layer 270 and the interconnect layer 212. Peripheral circuitry 204 can be coupled to DRAM cell 240 via interconnect layers 206 and 212 and bonding layers 215 and 207. Peripheral circuitry 204 and DRAM cell 240 can be coupled to external circuitry via contact pads and pads leading out from interconnect layer 270. Contact pads 272 and contact portions 274 can include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, contact pads 272 can include Al, and contact portions 274 can include W.

[0080] It should be understood that the vertical transistors 242 in the DRAM cell 240 are not limited to, for example, Figure 3 The single-gate transistor shown can be a dual-gate transistor or a gate-all-around transistor, and their structures will be described in detail below.

[0081] Figure 3 A flowchart is shown of a manufacturing method 300 for forming a semiconductor device including vertical transistors according to some embodiments of the present disclosure. Figure 3 The illustration shows various embodiments of the present disclosure. Figures 4A-4C This is a schematic diagram of the semiconductor device 400 during certain manufacturing stages of method 300. It should be understood that the operations shown in method 300 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the operations shown. Figure 4A The execution is performed in the order shown.

[0082] like Figure 4A As shown, method 300 may begin with operation 302, thereby forming a second semiconductor structure 420 including an array of memory cells. In operation 302, an array of capacitors 409 may be formed on substrate 402.Figure 4B A schematic side view cross-section of the 3D semiconductor device in the y-z plane in some manufacturing stage of operation 302 of method 300 is shown.

[0083] In some embodiments, as shown in Figure 4B A substrate comprising a first substrate 402 and a second substrate 404 is formed. In some embodiments, the first substrate 402 can be a semiconductor substrate, which can comprise silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. In some other embodiments, the first substrate 402 can be a carrier substrate, which can comprise any suitable semiconductor material or non-conductive material, such as glass, plastic, or sapphire wafer. In some embodiments, the first substrate 402 can be omitted. The second substrate 404 is formed on the first substrate 402 to define an area in which the capacitors 409 will be formed in subsequent processes. The second substrate 404 can be any suitable material different from the dielectric layer of the capacitors 409.

[0084] In some embodiments, the capacitors 409 have a relatively large height and need to be mechanically stabilized by means of at least one grid layer 403, as shown in Figure 3 and Figure 4C The spacing between the capacitors 409 is thus kept uniform, thereby avoiding breakage of the capacitors. Without the grid layer 403, the capacitors can tilt over the adjacent capacitors and come into contact with them. The grid layer 403 comprises a dielectric material having a Mohs hardness greater than that of silicon oxide, which has a Mohs hardness of about 6. In some embodiments, the grid layer 403 has a material different from that of the second substrate 404 and can be silicon nitride, silicon carbide, corundum, boron carbide, boron nitride, or any combination thereof. In some embodiments, the at least one grid layer 403 is interleaved with at least one dielectric layer. In some embodiments, as the aspect ratio of the capacitors 409 increases, two or more grid layers 403 are needed to ensure mechanical stability, as shown in Figure 3 In some embodiments, a plurality of cell holes 406 are then formed in the second substrate 404 and each cell hole 406 passes through the second substrate 404 to expose the first substrate 402.

[0085] As shown in Figure 4EAs shown in FIG. 3B, method 300 can proceed to operation 304, in which a dielectric layer 405 of capacitor 409 is formed in cell hole 406, and cell hole 406 is partially filled by dielectric layer 405. Thereafter, method 300 can proceed to operation 306, in which a first electrode 407 of capacitor 409 is formed over dielectric layer 405 of capacitor 409, and cell hole 406 is completely filled by first electrode 407. Figure 4D A schematic side view cross-section of second semiconductor structure 420 in the y-z plane is shown after operation 306 of method 300.

[0086] In some embodiments, dielectric layer 405 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It is noted that dielectric layer 405 is of a different material than second substrate 404. Dielectric layer 405 of capacitor 409 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, first electrode 407 can comprise a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, dielectric layer 405 and first electrode 407 can be formed by a series of fabrication processes, including thin film deposition processes (e.g., CVD, PVD, ALD, etc.), patterning processes (e.g., optical lithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.). It is noted that the fabrication processes and / or order of forming dielectric layer 405 and first electrode 407 can vary depending on front-side or back-side processing.

[0087] As shown in FIG. 3B, method 300 can proceed to operation 304, in which a dielectric layer 405 of capacitor 409 is formed in cell hole 406, and cell hole 406 is partially filled by dielectric layer 405. Thereafter, method 300 can proceed to operation 306, in which a first electrode 407 of capacitor 409 is formed over dielectric layer 405 of capacitor 409, and cell hole 406 is completely filled by first electrode 407. Figure 4D As shown in FIG. 3B, method 300 can proceed to operation 304, in which a dielectric layer 405 of capacitor 409 is formed in cell hole 406, and cell hole 406 is partially filled by dielectric layer 405. Thereafter, method 300 can proceed to operation 306, in which a first electrode 407 of capacitor 409 is formed over dielectric layer 405 of capacitor 409, and cell hole 406 is completely filled by first electrode 407. Figure 4D A schematic side view cross-section of second semiconductor structure 420 in the y-z plane is shown after operation 306 of method 300.

[0088] In some embodiments, a multi-layer structure comprising a conductor layer is formed over the array of capacitors 409, thereby forming an isolation structure 421 between two adjacent transistors, as shown in FIG. 3B. Figure 4EAs shown in the diagram. In some embodiments, the multilayer structure includes a first dielectric layer 411, a conductor layer 413 covering the first dielectric layer 411, and a second dielectric layer 415 covering the conductor layer 413. In some embodiments, the first dielectric layer 411 and the second dielectric layer 415 may include a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the conductor layer 413 may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. The first dielectric layer 411, the conductor layer 413, and the second dielectric layer 415 may be formed by a series of manufacturing processes, including thin film deposition processes such as CVD, PVD, ALD, etc.

[0089] In some embodiments, a plurality of isolation trenches 412 are then formed on the multilayer structure, thereby dividing the multilayer structure into a plurality of isolation structures 421, such as Figure 4E As shown in the diagram, an isolation trench 412 extends through the multilayer structure, exposing the top of the capacitor 409. (Reference) Figure 4E Two adjacent capacitors 409 are exposed through the same isolation trench 412. In some other embodiments, each isolation trench 412 is configured to expose one corresponding capacitor 409 (not shown). In some embodiments, two sidewalls 417 are formed to cover the left and right sides of each isolation structure 421. (See reference...) Figure 4E A left sidewall 417 is formed on the left side of the conductor layer 413 to separate the conductor layer 413 from the first vertical transistor on the left, and a right sidewall 417 is formed on the right side of the conductor layer 413 to separate the conductor layer 413 from the second vertical transistor on the right. In some embodiments, the first dielectric layer 411, the second dielectric layer 415, and the sidewall 417 may comprise different materials, such as silicon oxide, silicon nitride, or high-k dielectrics, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In such embodiments, the conductor layer 413 may be surrounded by dielectric layers on all sides, thereby isolating it from adjacent vertical transistors. Multiple conductor layers 413 are connected to a common ground, preventing charge accumulation between two adjacent vertical transistors. In this way, electrical coupling between the semiconductor layers 419 of two adjacent vertical transistors can be greatly reduced. In some embodiments, the conductor layer 413 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the conductor layer 413 comprises multiple conductive layers, such as a W layer situated above a TiN layer.

[0090] In some embodiments, a semiconductor layer 419 is formed over the isolation structure 421, as shown in Figure 4E In some embodiments, the semiconductor layer can be one or more of In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O and In x Ga y O, etc. In some embodiments, the semiconductor layer 419 can be formed by a deposition process. For example, a semiconductor layer covering both the isolation structure 421 and the isolation trench 412 can be formed by a deposition process, and then portions of the semiconductor layer covering the bottom of the isolation trench 412 are removed by a lithography process, thereby forming a plurality of semiconductor layers 419 covering the isolation trench. In some embodiments, the semiconductor layer covering the capacitor 409 is preserved during the lithography process to form an extended portion of the semiconductor layer 419. As shown in Figure 4E The semiconductor layer 419 is isolated from the conductor layer 413 by the first dielectric layer 411, the second dielectric layer 415, and the sidewall 417 between the conductor layer 413 and the semiconductor layer 419.

[0091] Referring to Figure 4FEach vertical transistor 429 has a semiconductor layer 419 including a vertical portion 416 extending in a vertical direction (z-direction), a first lateral portion 418 extending in a lateral direction (y-direction) from a first end of the vertical portion 416, and a second lateral portion 414 extending in the lateral direction (y-direction) from a second end of the vertical portion 416. The second lateral portion 414 is coupled to a corresponding capacitor 409. (Reference) Figure 4F During the manufacturing process, the first transverse portion 418, the vertical portion 416, and the second transverse portion 414 are formed as a single unit. For example... Figure 4G As shown, each semiconductor layer 419 formed in the corresponding isolation trench 412 has a U-shaped cross-section in the yz plane. The U-shaped semiconductor layer 419 includes a vertical portion 416 covering the left sidewall 417 of the first vertical transistor, a first lateral portion 418 covering the second dielectric layer 415 of the first vertical transistor, a vertical portion 416 covering the right sidewall 417 of the second vertical transistor, and a first lateral portion 418 covering the second dielectric layer 415 of the second vertical transistor. In some embodiments, the U-shaped semiconductor layer 419 further includes second lateral portions 414 of the first and second vertical transistors. In some embodiments, the first electrode 407 is etched back to form a recess before forming the semiconductor layer 419, and the second lateral portion 414 can then be formed in this recess. In this way, an edge is established between the semiconductor layer in the recess and another portion of the bottom of the isolation trench covering the semiconductor layer. Because this edge is detectable and can be used as a marker during mask and semiconductor layer alignment, subsequent photolithography is facilitated.

[0092] In this embodiment, a gate dielectric layer 422 may be formed over the semiconductor layer 419. The gate dielectric layer 422 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 422 may include silicon oxide, i.e., a gate oxide, which may be formed during the fabrication of the gate electrode 424. In some embodiments, the gate dielectric layer 422 may be a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. A gate electrode 424 may be formed over the gate dielectric layer 422. The gate electrode 424 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the gate electrode 424 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 424 includes multiple conductive layers, such as a W layer located above the TiN layer. An isolation layer 425 is then formed to fill the space between the vertical transistors 429, such as Figure 4HAn air gap (not shown in the figures) can be formed in the isolation layer 425 between adjacent vertical transistors, as described below in connection with the fabrication process. The relatively large dielectric constant of air in the air gap can improve the isolation effect between the vertical transistors 429 compared to some electrolytes (e.g., silicon oxide).

[0093] In some embodiments, a plurality of bit lines 426 and word lines 424 (also referred to as gate electrodes 424) can be formed over the array of vertical transistors 429. Figure 4H A schematic side view cross-sectional view of the semiconductor device in the y-z plane after formation of the bit lines 426 is shown. Figures 4I to 4K A schematic cross-sectional view of the semiconductor device taken along the AA' direction in the x-y plane is shown. Figure 4I A schematic cross-sectional view of the semiconductor device taken along the BB' direction in the x-y plane is shown. The vertical transistors 429 extend vertically and are coupled with respective word lines 424. The first lateral portions 418 of the semiconductor layers 419 of the vertical transistors 429 are coupled with the bit lines 426. As Figure 4J As shown in FIG. 4B, the bit lines 426 can be formed directly on the isolation layer 425 and the first lateral portions 418 of the semiconductor layers 419 of the vertical transistors 429. Unlike the formation of the bit lines coupled with the vertical portions 416, the bit lines 426 in the present disclosure can be formed by a deposition process without etching the isolation layer 425. This approach can significantly reduce the manufacturing complexity and cost associated with the formation of the first lateral portions 418.

[0094] In some embodiments, reference is made to Figure 3 The second semiconductor structure 420 is bonded with the first semiconductor structure 410 containing the peripheral circuitry to form the semiconductor device 400 by hybrid bonding. As Figures 4L to 4NAs shown in FIG. 4A, the second semiconductor structure 420 can further include an interconnect layer 432 that includes a bonding layer 433 that is to be coupled to the bonding layer of the first semiconductor structure 410 at the bonding interface 430. The bonding layer 433 can include a plurality of bonding contacts 431 and a dielectric that electrically isolates the bonding contacts 431. The bonding contacts 431 can include a conductive material, such as Cu. The remaining areas of the bonding layer 433 surrounding the bonding contacts 431 can include a dielectric material, such as silicon oxide. The bonding contacts 431 and the surrounding dielectric in the bonding layer 433 can be used for hybrid bonding. According to some embodiments, the bonding contacts 431 are coupled to the bonding contacts of the first semiconductor structure 410 at the bonding interface 430. The first semiconductor structure 410 can include a peripheral circuit 438 that is located on a substrate 436. In some embodiments, the peripheral circuit 438 includes a plurality of transistors 437 (e.g., planar transistors and / or semiconductor crystals). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions can be formed on or within the substrate 436. In some embodiments, the first semiconductor structure 410 further includes an interconnect layer 442 that is located beneath the peripheral circuit 438 to deliver electrical signals to and from the peripheral circuit 438. The interconnect layer 442 can include a plurality of interconnects (also referred to herein as "contacts"), which include lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnect, such as a middle-of-line (MEOL) interconnect and a back-end-of-line (BEOL) interconnect. The interconnect layer 442 can further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") within which the interconnect lines and VIA contacts can be located. That is, the interconnect layer 442 can include interconnect lines and VIA contacts that are located within a plurality of ILD layers. In some embodiments, the peripheral circuit 438 is coupled to one another through interconnects in the interconnect layer 442. The interconnects in the interconnect layer 442 can be of a conductive material, which includes, but is not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can be formed of a dielectric material, which includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0095] As Figure 4L and 4KAs shown in FIG. 4A, the first semiconductor structure 410 can further include a bonding layer 441 on the interconnect layer 442 and the peripheral circuitry 438 at the bonding interface 430. The bonding layer 441 can include a plurality of bonding contacts 443 along with a dielectric that electrically isolates the bonding contacts 443. The bonding contacts 443 can include a conductive material, such as Cu. The rest of the bonding layer 441 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 443 and the surrounding dielectric in the bonding layer 441 can be used for hybrid bonding.

[0096] As shown in FIG. 4A, the first semiconductor structure 410 can further include a bonding layer 441 on the interconnect layer 442 and the peripheral circuitry 438 at the bonding interface 430. The bonding layer 441 can include a plurality of bonding contacts 443 along with a dielectric that electrically isolates the bonding contacts 443. The bonding contacts 443 can include a conductive material, such as Cu. The rest of the bonding layer 441 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 443 and the surrounding dielectric in the bonding layer 441 can be used for hybrid bonding. Figure 4L As shown in FIG. 4A, the first semiconductor structure 410 can further include a bonding layer 441 on the interconnect layer 442 and the peripheral circuitry 438 at the bonding interface 430. The bonding layer 441 can include a plurality of bonding contacts 443 along with a dielectric that electrically isolates the bonding contacts 443. The bonding contacts 443 can include a conductive material, such as Cu. The rest of the bonding layer 441 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 443 and the surrounding dielectric in the bonding layer 441 can be used for hybrid bonding. Figure 4M As shown in FIG. 4A, the first semiconductor structure 410 can further include a bonding layer 441 on the interconnect layer 442 and the peripheral circuitry 438 at the bonding interface 430. The bonding layer 441 can include a plurality of bonding contacts 443 along with a dielectric that electrically isolates the bonding contacts 443. The bonding contacts 443 can include a conductive material, such as Cu. The rest of the bonding layer 441 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 443 and the surrounding dielectric in the bonding layer 441 can be used for hybrid bonding.

[0097] Figure 4M A schematic side view cross-section of the semiconductor device 400 in the y-z plane is shown after removing the substrate 402 to expose the bottom of the second substrate 404. In some embodiments, the mesh layer 403 at the bottom of the second substrate 404 is exposed, as shown in FIG. 4B. Thereafter, a plurality of openings 452 are formed on the mesh layer 403 to expose the dielectric layer of the second substrate 404, as shown in FIG. 4C. Figure 4M Thereafter, a plurality of openings 452 are formed on the mesh layer 403 to expose the dielectric layer of the second substrate 404, as shown in FIG. 4C. Figure 4N In some embodiments, there are two or more mesh layers formed in the second substrate 404. For example, as shown in FIG. 4D, three mesh layers 403 are formed in the second substrate 404 with two dielectric layers sandwiched between the mesh layers 403. In such embodiments, the openings 452 can be formed on the second mesh layer after removing the first dielectric layer, and thereafter the second dielectric layer is removed through the openings in the second mesh layer in a similar manner. As shown in FIG. 4E, the dielectric layer 405 is exposed from the cavities 451. Figure 4N Figure 4O As shown in FIG. 4A, the first semiconductor structure 410 can further include a bonding layer 441 on the interconnect layer 442 and the peripheral circuitry 438 at the bonding interface 430. The bonding layer 441 can include a plurality of bonding contacts 443 along with a dielectric that electrically isolates the bonding contacts 443. The bonding contacts 443 can include a conductive material, such as Cu. The rest of the bonding layer 441 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 443 and the surrounding dielectric in the bonding layer 441 can be used for hybrid bonding.

[0098] ​ A schematic side view cross-section of the semiconductor device 400 in the y-z plane is shown after forming the second electrode 456. In some embodiments, the second electrode 456 includes a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the second electrode 456 includes a multi-layer structure, where each layer in the multi-layer structure includes one of TiN, TaN, carbon, polysilicon, metal, metal compound, and silicide. For example, as shown in FIG. 4F, the second electrode 456 includes a multi-layer structure including a first layer 456a of TiN, a second layer 456b of TaN, a third layer 456c of carbon, a fourth layer 456d of polysilicon, a fifth layer 456e of W, and a sixth layer 456f of silicide. ​ ​As shown in the middle, the second electrode 456 includes a first layer 453 directly coupled with the capacitor dielectric 405, a second layer 454 surrounded by the first layer 453, and a third layer 455 surrounded by the second layer 454. In some embodiments, the material of each layer in the multi-layer structure is different from the material of the other layers. For example, the first layer 453 is TiN, the second layer 454 is carbon, and the third layer 455 is W. In some embodiments, a common plate 458 is formed on the array of capacitors 409, and the second electrode 456 is directly coupled with the common plate 458. In some embodiments, the formation of the second electrode 456 can involve a series of fabrication processes, including thin film deposition processes and patterning processes.

[0099] In some embodiments, a pad-out interconnect layer 460 is formed. ​ A schematic side cross-sectional view of the semiconductor device 400 in the y-z plane is shown after the pad-out interconnect layer 460 is formed on the common plate 458. The pad-out interconnect layer 460 can include interconnects, such as contact pads 462, disposed within one or more ILD layers. The pad-out interconnect layer 460 and the first semiconductor structure 410 can be formed on the same side of the second semiconductor structure 420. In some embodiments, the interconnects in the pad-out interconnect layer 460 can carry electrical signals between the semiconductor device and external circuitry, for example, for pad-out purposes. In some embodiments, the second semiconductor structure 420 further includes one or more contacts 464 to connect the pad-out interconnect layer 460 to the DRAM cells (e.g., vertical transistors 429 and capacitors 409). The contact pads 462 and the contacts 464 can include electrically conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 462 can include Al, and the contacts 464 can include W.

[0100] The foregoing description of specific implementations has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Many modifications and variations are possible in light of the teaching and

[0101] The breadth and scope of the present disclosure should not be limited by any of the above-described implementations, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising vertical transistors and storage cells coupled to the vertical transistors, wherein the vertical transistors comprise: a semiconductor layer comprising a vertical portion extending along a vertical direction and a first lateral portion extending along a lateral direction from a first end of the vertical portion, and a gate structure coupled to the vertical portion of the semiconductor layer and extending along the vertical direction; and the first lateral portions of the semiconductor layers of two adjacent vertical transistors along the lateral direction are connected to each other.

2. The semiconductor device of claim 1, wherein the semiconductor layer has a U-shaped cross-section in a plane formed by the vertical direction and the lateral direction.

3. The semiconductor device of claim 1, wherein the semiconductor layer of the vertical transistors comprises a second lateral portion extending along the lateral direction from a second end of the vertical portion, and the second lateral portion is coupled to a respective storage cell.

4. The semiconductor device of claim 3, wherein the storage cell comprises a capacitor having a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode; and the first electrode is directly coupled to the second lateral portion of the semiconductor layer of a respective vertical transistor.

5. The semiconductor device of claim 4, wherein the second electrode comprises a multi-layer structure, each layer of the multi-layer structure comprising one of carbon, polysilicon, metal, metal compound, and silicide.

6. The semiconductor device of claim 1, wherein two adjacent vertical transistors along the lateral direction are separated by an isolation structure, and the gate structure of the vertical transistors is located on a side of the vertical portion of the semiconductor layer opposite the isolation structure. the isolation structure comprises:

7. The semiconductor device of claim 6, wherein, a conductor layer; and a dielectric layer surrounding the conductor layer. the dielectric layer comprises:

8. The semiconductor device of claim 7, wherein, a first dielectric layer under the conductor layer; a second dielectric layer on the conductor layer; a left side wall on a left side of the conductor layer to separate the conductor layer from a first vertical transistor on the left side; and a right side wall on a right side of the conductor layer to separate the conductor layer from a second vertical transistor on the right side.

9. The semiconductor device of claim 8, wherein the first dielectric layer, the second dielectric layer, the left side wall, and the right side wall comprise different materials.

10. The semiconductor device of claim 1, further comprising: a bit line extending along the lateral direction and directly coupled to the vertical transistors through the first lateral portions of the semiconductor layers of the vertical transistors.

11. The semiconductor device of claim 10, wherein the bit line is coupled to the first lateral portions at a bottom of the semiconductor layers.

12. The semiconductor device of claim 1, wherein the semiconductor layer has a leakage value lower than one picoampere.

13. The semiconductor device of claim 12, wherein ​ the semiconductor layer comprises In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O and In x Ga y O 14. The semiconductor device of claim 1, further comprising a peripheral circuit stacked on the vertical transistors.

15. The semiconductor device of claim 1, further comprising a pad-out interconnect layer stacked on the memory cells.

16. A method for forming a semiconductor device, comprising: forming a cell hole on a substrate; forming a dielectric layer of a capacitor in the cell hole, the cell hole being partially filled by the dielectric layer; forming a first electrode of the capacitor covering the dielectric layer, the cell hole being completely filled by the first electrode; forming a vertical transistor coupled with the first electrode; and forming a second electrode of the capacitor surrounding the dielectric layer.

17. The method of claim 16, wherein: the substrate comprises at least one mesh layer alternately stacked with at least one sacrificial layer; and forming the second electrode of the capacitor comprises: removing the at least one sacrificial layer to form a cavity; and filling the cavity with the second electrode of the capacitor. filling the cavity with the second electrode of the capacitor comprises:

18. The method of claim 17, wherein, forming a multi-layer structure in the cavity; and each layer in the multi-layer structure comprises one of carbon, polysilicon, metal, metal compound, and silicide. forming the vertical transistor coupled with the first electrode comprises:

19. The method of claim 16, wherein, forming an isolation structure between two adjacent vertical transistors. forming the isolation structure between two adjacent vertical transistors comprises:

20. The method of claim 19, wherein, forming a first dielectric layer on the substrate; forming a conductor layer on the first dielectric layer; and forming a second dielectric layer on the conductor layer. forming the isolation structure between two adjacent vertical transistors further comprises:

21. The method of claim 20, wherein, forming a left-side sidewall on a left side of the conductor layer to separate the conductor layer from a first vertical transistor on the left side; and forming a right-side sidewall on a right side of the conductor layer to separate the conductor layer from a second vertical transistor on the right side.

22. The method of claim 21, wherein: the first dielectric layer, the second dielectric layer, the left-side sidewall, and the right-side sidewall comprise different materials. forming the vertical transistor coupled with the first electrode comprises:

23. The method of claim 21, wherein, forming a semiconductor layer covering the isolation structure; and the semiconductor layer has a U-shaped cross-section in a plane formed by a vertical direction and a lateral direction. the semiconductor layer comprises:

24. The method of claim 23, wherein, a vertical portion of the first vertical transistor covering the left-side sidewall; a first lateral portion of the first vertical transistor covering the second dielectric layer; a vertical portion of the second vertical transistor covering the right-side sidewall; and a first lateral portion of the second vertical transistor covering the second dielectric layer.

25. The method of claim 24, further comprising: prior to forming the vertical transistor coupled with the first electrode, etching the first electrode to form a recess to accommodate the vertical transistor.

26. The method of claim 24, further comprising: ​ a bit line formed along a lateral direction and directly coupled with the first lateral portion of the semiconductor layer through the vertical transistor.

27. The method of claim 26, wherein, the bit line is coupled with the first lateral portion at a bottom of the semiconductor layer.

28. The method of claim 16, further comprising: forming a peripheral circuit stacked on the vertical transistor.

29. The method of claim 16, further comprising: forming a pad-out interconnect layer stacked on the capacitor.

30. The method of claim 24, wherein the semiconductor layer has a leakage value lower than one pico-amp.

31. The method of claim 30, wherein the semiconductor layer comprises In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O and In x Ga y O 32. A semiconductor device comprising a single-gate vertical transistor and a memory cell coupled with the single-gate vertical transistor, wherein two adjacent single-gate vertical transistors along a lateral direction are separated by an isolation structure and share a U-shaped semiconductor layer covering both sides of the isolation structure along the lateral direction; and a gate structure of the single-gate vertical transistor is coupled with a side of the semiconductor layer opposite to the isolation structure.

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