Semiconductor device

Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a first transistor, a capacitor, and a second transistor. The first transistor includes a silicon layer having a channel formation region. The capacitor includes a first electrode and a second electrode. The second transistor includes an oxide semiconductor layer having a channel formation region. The first electrode is electrically connected to the first gate electrode of the first transistor. The second electrode is electrically connected to one of the source electrode and the drain electrode of the second transistor. The first electrode is provided along a side surface and a bottom portion of a first opening portion in a first insulating layer provided on the first gate electrode. The oxide semiconductor layer is provided along a side surface and a bottom portion of a second opening portion in a second insulating layer provided on the second electrode. The first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions when viewed in plane.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device or the like.

[0002] Note that one embodiment of the present application is not limited to the technical field described above. The technical field of the application disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present application relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the application disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. BACKGROUND

[0003] In recent years, the importance of measures against global warming has been increasing. The amount of carbon dioxide, which is one of the causes of global warming, has not been reduced yet, although the amount of energy consumption is increasing. Simply reducing the amount of energy consumption can sometimes lead to a decrease in convenience. In order to reduce the amount of energy consumption without causing a decrease in convenience, a technology for low power consumption in an electronic device is very important.

[0004] As a technology applicable to low power consumption in an electronic device, for example, a signal processing circuit using a transistor including an oxide semiconductor (also referred to as an OS transistor) to hold data is known (see Patent Document 1, for example). The signal processing circuit described in Patent Document 1 can perform non-destructive readout and low-voltage operation (writing and readout) by using the characteristics of an OS transistor in which a current flowing at the time of off-state is extremely small for data holding. Further, the signal processing circuit has extremely high rewrite endurance. Thus, low power consumption of an electronic device including the signal processing circuit can be achieved.

[0005] [Prior Art Documents]

[0006] [Patent Documents]

[0007] [Patent Document 1] Japanese Published Patent Application No. 2013-179642 SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] In the signal processing circuit described in Patent Document 1, data is held by making the OS transistor connected to the gate of the transistor including silicon (Si transistor) into an off state. The miniaturization of the Si transistor is being advanced. When the miniaturization of the OS transistor is also similarly advanced, it is necessary to reduce the driving voltage. Thus, a transistor having a structure in which the current flowing in the off state is extremely small and the driving voltage is small is demanded.

[0010] In addition, in Patent Document 1, the charge corresponding to data is held in the capacitor connected to the gate of the Si transistor. However, when a capacitor having a large storage capacity is connected to the gate of the Si transistor, a problem of an increase in circuit area occurs. In addition, when both the connection of the capacitor to the gate of the Si transistor and the connection of one of the source and the drain of the OS transistor to the gate of the Si transistor are performed, since the number of opening portions increases, a problem of an increase in circuit area occurs.

[0011] One of objects of one embodiment of the present application is to provide a semiconductor device having a novel structure. Furthermore, one of objects of one embodiment of the present application is to provide a semiconductor device which is excellent in reduction in power consumption, improvement in operation speed, miniaturization, or improvement in storage capacity.

[0012] Note that objects of one embodiment of the present application are not limited to the above-described objects. The above-described enumerated objects do not preclude the existence of other objects. In addition, the other objects are objects which are not mentioned above and will be described below. A person with an ordinary skill in the art can derive and appropriately extract the objects which are not mentioned above from the description, drawings, and the like. Note that one embodiment of the present application achieves at least one of the above-described objects and / or other objects.

[0013] Means for solving the technical problem

[0014] One embodiment of the present application is a semiconductor device including a first transistor, a capacitor, and a second transistor, in which the first transistor includes a silicon layer having a channel formation region, the capacitor includes a first electrode and a second electrode, the second transistor includes an oxide semiconductor layer having a channel formation region, the first electrode is electrically connected to a first gate electrode of the first transistor, the second electrode is electrically connected to one of a source electrode and a drain electrode of the second transistor, the first electrode is provided along a side surface and a bottom of a first opening portion in a first insulating layer provided over the first gate electrode, the oxide semiconductor layer is provided along a side surface and a bottom of a second opening portion in a second insulating layer provided over the second electrode, and the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have a region overlapping with each other.

[0015] In the semiconductor device of one embodiment of the present application, it is preferable that the other of the source and drain electrodes of the second transistor be provided over the first electrode with the second insulating layer interposed therebetween.

[0016] In the semiconductor device of one embodiment of the present application, it is preferable that the silicon layer be provided over a substrate including a single crystal silicon, and that the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have a region overlapping with each other in a direction perpendicular to a surface of the substrate.

[0017] In the semiconductor device of one embodiment of the present application, it is preferable that the second transistor include a second gate electrode, and that the second gate electrode have a region overlapping with the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer in a direction perpendicular to a surface of the substrate.

[0018] In the semiconductor device of one embodiment of the present application, it is preferable that the capacitor be provided over the first transistor, the second transistor be provided over the capacitor, and that the first transistor, the capacitor, and the second transistor have a region overlapping with each other.

[0019] In the semiconductor device of one embodiment of the present application, it is preferable that the first electrode be directly connected to the gate electrode of the first transistor.

[0020] In the semiconductor device of one embodiment of the present application, it is preferable that the oxide semiconductor layer contain at least In.

[0021] Note that other embodiments of the present application are described in the description and the drawings of the embodiments described below.

[0022] Effects of Invention

[0023] One embodiment of the present application can provide a novel semiconductor device and the like. Furthermore, one embodiment of the present application can provide a semiconductor device which is excellent in reduction in power consumption, improvement in operation speed, reduction in size, or improvement in memory capacity.

[0024] Note that the description of these effects does not preclude the presence of other effects. Note that one embodiment of the present application does not necessarily achieve all the effects described above. Furthermore, an effect other than those described above can be derived from the description, the drawings, the claims, and the like.

[0025] BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1A FIG. 1 is a circuit diagram illustrating a structure example of a semiconductor device. FIG. 1B FIG. 2 is a cross-sectional schematic view illustrating a structure example of a semiconductor device.

[0027] FIG. 2 FIG. 3 is a cross-sectional schematic view illustrating a structure example of a semiconductor device.

[0028] FIG. 3A and FIG. 3B is a plan view showing a structure example of a semiconductor device, FIG. 3C is a cross-sectional schematic view showing a structure example of a semiconductor device.

[0029] FIG. 4A and FIG. 4B is a cross-sectional schematic view showing a structure example of a semiconductor device.

[0030] FIG. 5A is a cross-sectional schematic view showing a structure example of a semiconductor device, FIG. 5B is a circuit diagram showing a structure example of a semiconductor device.

[0031] FIG. 6A and FIG. 6B is a cross-sectional schematic view showing a structure example of a semiconductor device.

[0032] FIG. 7A is a circuit diagram showing a structure example of a semiconductor device. FIG. 7B is a timing chart showing a structure example of a semiconductor device.

[0033] FIG. 8 is a circuit diagram showing a structure example of a semiconductor device.

[0034] FIG. 9A is a circuit diagram showing a structure example of a semiconductor device. FIG. 9B is a schematic view showing a structure example of a semiconductor device.

[0035] FIG. 10A to FIG. 10D is a cross-sectional view showing a deposition method of a metal oxide according to one embodiment of the present application.

[0036] FIG. 11A to FIG. 11D is a cross-sectional view showing a deposition method of a metal oxide according to one embodiment of the present application.

[0037] FIG. 12A and FIG. 12B is a diagram showing one example of an electronic component.

[0038] FIG. 13A to FIG. 13D is a diagram showing one example of an electronic device.

[0039] FIG. 14A and FIG. 14B is a diagram showing one example of an electronic device.

[0040] FIG. 15A to FIG. 15C is a diagram showing one example of an electronic device.

[0041] FIG. 16FIG. 1 is a diagram showing an example of a large-scale computer.

[0042] Means for carrying out the present application

[0043] Embodiments will be described below with reference to the accompanying drawings. However, it is readily apparent to one of ordinary skill in the art that the embodiments can be carried out in many different forms and that the means and details thereof can be changed in various ways without departing from the spirit and scope of the present application. Therefore, the present application should not be construed as being limited to the embodiments described below.

[0044] In the drawings, the size, the thickness of layers, or regions are sometimes exaggerated for clarity. Therefore, the present application should not be construed as being limited to the size in the drawings. In addition, in the drawings, well-known elements or the like are not shown in order not to obscure the concept of the present application. Therefore, the present application should not be construed as being limited to the shape, the numerical value, or the like of the drawings.

[0045] In addition, in this specification and the like, the off-state current refers to a drain current when a transistor is in an off state (also referred to as a non-conduction state, a blocking state). In the case where no particular description is given, in an n-channel transistor, the off state refers to a state where the voltage V gs between a gate and a source is lower than the threshold voltage V th (these are also referred to as V gs and V th , respectively).

[0046] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (Oxide Semiconductor, which can also be simply referred to as OS), and the like. For example, in the case where a metal oxide is used for an active layer of a transistor, the metal oxide is also referred to as an oxide semiconductor. In other words, an OS transistor can refer to a transistor including a metal oxide or an oxide semiconductor.

[0047] In addition, when a plurality of components use the same reference numerals and the components need to be distinguished from each other, a symbol such as _1, _2, _R, _W, and the like is added to the reference numerals.

[0048] (Embodiment 1)

[0049] A semiconductor device according to one embodiment of the present application will be described with reference to drawings. Note that a semiconductor device is a device using semiconductor characteristics, and is also a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit.

[0050] FIG. 1A is a circuit diagram of a semiconductor device 10 of one embodiment of the present application, the semiconductor device 10 including a transistor MT, a transistor VT, and a capacitor Cl. Note that FIG. 1B is a cross-sectional view illustrating the configuration of each component of the semiconductor device 10 shown in FIG. 1A FIG. 1B shows the element layer 20 and the element layer 30.

[0051] An arrow indicating an X direction, a Y direction, and a Z direction is sometimes attached to a drawing or the like to be described below. The X direction, the Y direction, and the Z direction are directions orthogonal to one another. In this specification and the like, one of the X direction, the Y direction, and the Z direction is sometimes referred to as a first direction. In addition, one of the other two directions is sometimes referred to as a second direction. Furthermore, the remaining one is sometimes referred to as a third direction. Note that a formed surface of a conductive layer or an insulating layer and the like corresponds to an XY plane. Furthermore, the Z direction corresponds to a direction perpendicular to the above-described formed surface.

[0052] The transistor MT includes a silicon layer including a channel formation region. A transistor including a silicon layer including a channel formation region is sometimes referred to as an Si transistor. FIG. 1B The element layer 20 shown in FIG. 1A is a layer including a transistor including a silicon layer.

[0053] As the silicon layer, single crystal silicon or polycrystal silicon or the like having high crystallinity is particularly used. When an Si transistor contains silicon having high crystallinity, high field-effect mobility can be achieved, and thus higher-speed operation can be performed. Thus, the semiconductor device 10 can perform high-speed operation of backup and restoration of data of a storage circuit such as a latch circuit or a flip-flop circuit provided in the same layer as the Si transistor.

[0054] FIG. 1A and FIG. 1B An electrode GE, an electrode SD1, an electrode SD2, an electrode BSD, an electrode TSD, an electrode TGE, an electrode CE1, and an electrode CE2 are shown. The electrode BSD is an electrode serving also as the electrode CE1. In FIG. 1A and FIG. 1B , the electrode BSD (the electrode CE1) is illustrated. The electrode GE is connected to the electrode CE2. In FIG. 1A , the electrode GE (the electrode CE2) is illustrated. As shown in FIG. 1B , the electrode GE and the electrode CE2 can be different electrodes. In FIG. 1B , the electrode GE and the electrode CE2 are connected through conductive layers 328 and 330.

[0055] ​The electrode GE functions as a gate electrode of the transistor MT. The electrode SD1 functions as one of a source electrode and a drain electrode of the transistor MT. The electrode SD2 functions as the other of the source electrode and the drain electrode of the transistor MT. The electrode CE1 functions as one electrode of the capacitor Cl. The electrode CE2 functions as the other electrode of the capacitor Cl. The electrode TGE functions as a gate electrode of the transistor VT. The electrode TSD functions as one of a source electrode and a drain electrode of the transistor VT. The electrode BSD functions as the other of the source electrode and the drain electrode of the transistor VT.

[0056] The capacitor Cl is formed so that the electrode BSD (the electrode CE1) faces the electrode CE2 with an insulating layer therebetween. The capacitor Cl is formed in an opening portion provided in the insulating layer. That is, the capacitor Cl can be a capacitor of a trench structure. Thus, the electrode area of the capacitor per unit area can be increased. In addition, the capacitor Cl can place the electrode CE2 and the electrode GE connected to the electrode CE2 in an electrically floating state. Thus, a change in potential of the electrode CE2 and the electrode GE corresponding to a change in potential of the electrode BSD can be generated. Note that although a structure in which the electrode BSD functions as the electrode CE1 is described, the electrode can function as another electrode. Alternatively, the electrodes such as the electrode CE1, the electrode CE2, and the like can be formed of a plurality of conductive layers.

[0057] The transistor VT includes an oxide semiconductor layer including a channel formation region. A transistor including an oxide semiconductor layer including a channel formation region is sometimes referred to as an OS transistor. FIG. 1B The element layer 30 illustrated in FIG. 1 includes the capacitor Cl in addition to the transistor VT including the oxide semiconductor layer. The element layer 30 can be provided over the element layer 20 in a stacked manner.

[0058] As a metal oxide which can be used for the oxide semiconductor layer of the OS transistor, for example, an indium oxide (In oxide), a gallium oxide (Ga oxide), and a zinc oxide (Zn oxide) can be given. Further, an In-Zn oxide can be used as the metal oxide for the OS transistor. Further, the metal oxide preferably contains two or more kinds selected from indium, an element M, and zinc. Further, the element M is one or more kinds selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, the element M is preferably one or more kinds selected from aluminum, gallium, yttrium, and tin.

[0059] The off-state current of the OS transistor is extremely small. In the semiconductor device 10, the transistor VT can be brought to an on state and the potential of the electrode BSD can be made a potential corresponding to the potential of the electrode TSD (data potential), so that the transistor VT can be brought to an off state and the charge corresponding to the data potential can be held in the semiconductor device 10 for a long time. In this specification, the case where the potential of the electrode BSD is set to a potential corresponding to the potential of the electrode TSD is also referred to as writing data to the semiconductor device 10. In this specification, bringing the transistor VT to an off state and holding the potential of the electrode BSD is also referred to as holding of data.

[0060] In addition, the OS transistor has superior electrical characteristics to the Si transistor in a high-temperature environment. Specifically, even at a high temperature of 125 °C or higher and 150 °C or lower, the ratio of the on-state current to the off-state current is large, so that good switching operation can be performed. In other words, the heat resistance of the OS transistor is very good.

[0061] In the semiconductor device 10, data is written by charging and discharging of the capacitor Cl, so that there is no limit to the number of rewriting in principle, and the energy is low. In addition, in the semiconductor device 10, no power is consumed when data is held. Therefore, the semiconductor device 10 can be used as a low-power-consumption memory capable of holding data for a long period.

[0062] The electrode GE and the electrode CE2 are in an electrically floating state. Therefore, according to writing of data to the semiconductor device 10, a potential variation accompanied by capacitive coupling occurs in the electrodes at both ends of the capacitor Cl in a manner corresponding to a potential variation of the electrode BSD. Specifically, according to a potential variation of the electrode BSD, a potential variation of the electrode GE and a potential variation of the electrode CE2 can also be caused. That is, the gate of the transistor MT can be a potential corresponding to the written data. Therefore, in the transistor MT, a current corresponding to the potential of the electrode BSD holding a charge corresponding to the data can flow. Since the transistor MT is a Si transistor, a high field-effect mobility can be achieved, so that a large current can flow between the electrode SD1 and the electrode SD2.

[0063] In this specification, the flow of a current corresponding to the potential of the gate of the transistor MT, the flow of a current between the electrode SD1 and the electrode SD2, is also referred to as data readout. When data is read out in the semiconductor device 10, by setting the electrode SD1 to a voltage VDD (also referred to as a high-level-side power supply voltage, an H-level potential, an H level), for example, and setting the electrode SD2 to a voltage VSS (a low-level-side power supply voltage), for example, a current corresponding to the potential of the gate of the transistor MT can flow.

[0064] A VT transistor is a vertical transistor where the electrodes TSD and BSD are located at different heights. In a vertical transistor, current flows along the height direction (Z direction) of the channel formation region in the oxide semiconductor layer. In other words, the channel length direction can be said to include a component in the height direction (vertical direction). Therefore, the aforementioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, or a vertical transistor, etc.

[0065] Compared to lateral transistors (also known as planar structures or planar transistors) where electrodes SD1 and SD2 are located at the same height, vertical transistors have a structure that allows at least a portion of the source region, channel formation region, and drain region to overlap when viewed in a plane, thus reducing the occupied area (also known as the footprint). Furthermore, because they have a structure that allows for a shorter channel length and a wider channel width, the on-state resistance can be reduced (increasing the on-state current).

[0066] exist FIG. 1A and FIG. 1B In the structure of the semiconductor device 10 shown, the transistor VT is a vertical transistor. Compared to lateral transistors, vertical transistors can reduce the channel length and increase the channel width. Therefore, even if the OS transistor is miniaturized in the same way as the Si transistor, the drive voltage can be reduced. Thus, although the current flowing through the transistor in the off state is extremely small, it can be a semiconductor device with a device structure that has a low drive voltage.

[0067] In addition, FIG. 1A and FIG. 1B In the structure of the semiconductor device 10 shown, capacitor C1 has a trench structure, and one of its electrodes is connected to the gate of transistor MT. Because the trench structure capacitor has... FIG. 1B The structure shown, with the capacitor electrodes arranged in the opening, allows for a capacitor that maintains a large capacitance per unit area. Furthermore, in... FIG. 1A and FIG. 1B In the structure of the semiconductor device 10 shown, since the gate of the transistor MT has a structure for data readout based on capacitive coupling using an electrically floating state, the circuit area can be reduced without increasing the number of openings such as the connection between the capacitor and the gate of the Si transistor, or the connection between one of the source and drain of the OS transistor and the gate of the Si transistor.

[0068] Reference FIG. 2 illustrate FIG. 1A and FIG. 1B The semiconductor device 10 shown is an example of the structure of the transistor MT. FIG. 2The transistor MT shown is disposed on a substrate 311 and includes a conductive layer 316 serving as a gate electrode, an insulating layer 315, a semiconductor region 313 formed by a portion of the substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions.

[0069] Note that the transistor MT can be either p-channel or n-channel. For example, the transistor MT can be used as a p-channel transistor, and the transistor VT can be used as an n-channel transistor. By adopting this structure, a complementary circuit structure (also known as CMOS: Complementary Metal Oxide Semiconductor) can be achieved.

[0070] In the low resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or elements such as boron that impart p-type conductivity are also included.

[0071] also, FIG. 2 The transistor MT shown is just an example; appropriate transistors can be used depending on the circuit structure or driving method, and the structure is not limited to it.

[0072] A wiring layer, including interlayer films, wiring, and connectors, may also be provided between component layer 20 and component layer 30. For example, on a transistor MT, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 and the like are embedded in insulating layers 320 and 322. Furthermore, conductive layers 330 and the like are embedded in insulating layers 324 and 326. Additionally, conductive layers 328 and 330 serve as contact connectors or wiring.

[0073] Reference FIG. 3A to FIG. 5B illustrate FIG. 2 The capacitor C1 and transistor VT are included in the component layer 30 on the component layer 20 shown.

[0074] FIG. 3A This is a plan view showing an example of the structure of the capacitor C1 and transistor VT included in the element layer 30 and their surroundings. FIG. 3B It is an omission FIG. 3A A plan view of a portion of the constituent elements shown. FIG. 3C It is along FIG. 3A The cross-sectional view shown is the dotted-dotted line A1-A2. Note that in... FIG. 3A In the diagram, for example, some components of the transistor VT, such as the insulating layer 250, are omitted. Furthermore, in subsequent transistor planar diagrams, some components such as the insulating layer are also omitted.

[0075] exist FIG. 3CIn the middle, it is equipped with FIG. 2 The diagram shows insulating layers 322, 324 and 326 including conductive layers 328 and 330. Insulating layer 180 is disposed on insulating layer 326, insulating layer 280 is disposed on insulating layer 180, and insulating layer 285 is disposed on insulating layer 280.

[0076] An opening 601 is provided in the region where the insulating layer 180 overlaps with the conductive layer 330. A conductive layer 115 is provided in contact with the bottom and sides of the opening 601. That is, the conductive layer 115 has a region in the opening 601 that contacts the top surface of the conductive layer 330 and a region that contacts the side surface of the insulating layer 180. Note that in FIG. 3C In the middle, the conductive layer 115 has a region that contacts the top surface of the insulating layer 180.

[0077] An insulating layer 116 is provided on the insulating layer 180 and the conductive layer 115. Additionally, a conductive layer 220 is provided on the insulating layer 116. The conductive layer 220 is provided in a manner that it is embedded in the opening 601.

[0078] The capacitor C1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 116.

[0079] In capacitor C1, conductive layer 115 serves as one of a pair of electrodes, conductive layer 220 serves as the other of a pair of electrodes, and insulating layer 116 serves as a dielectric material sandwiched between the pair of electrodes.

[0080] A transistor VT is disposed above the capacitor C1. The transistor VT includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0081] In transistor VT, conductive layer 260 serves as the gate electrode, and insulating layer 250 serves as the gate insulating film. Conductive layers 220 and 240 serve as the source electrode or drain electrode, respectively. Note that, as mentioned above, conductive layer 220 also serves as the other of the pair of electrodes in capacitor C1.

[0082] In semiconductor layer 270, the entire region between the source electrode and the drain electrode, separated by a gate insulating film and opposite to the gate electrode, serves as a channel formation region. Furthermore, in semiconductor layer 270, the region in contact with the source electrode serves as the source region, and the region in contact with the drain electrode serves as the drain region.

[0083] Insulating layer 280 can be used as an interlayer insulating layer. Here, the interlayer insulating layer can be an interlayer film used to separate the source electrode and the gate electrode in transistor VT.

[0084] An insulating layer 280 is provided with a conductive layer 240. An opening 602 is provided in the insulating layer 280 that reaches the conductive layer 220. An opening 603 is provided in the conductive layer 240 that reaches the opening 602. In other words, the opening 603 has a region that overlaps with the opening 602.

[0085] exist FIG. 3A In the diagram, conductive layer 220, conductive layer 240, conductive layer 260, opening 602, and opening 603 are shown as components of transistor VT. Here, FIG. 3B Showing omissions FIG. 3A The diagram shows a structural example of the conductive layer 260 among the constituent elements. That is, FIG. 3B The conductive layer 220, conductive layer 240, opening 602, and opening 603 are shown.

[0086] FIG. 3A and FIG. 3B An example is shown where both openings 602 and 603 are circular in shape when viewed from above. When the planar shapes of openings 602 and 603 are circular, the processing accuracy during their formation can be improved, allowing for the formation of openings 602 and 603 with minute dimensions. Therefore, miniaturization or high integration of OS transistors and capacitors can be achieved. Note that in this specification, the circle is not limited to a perfect circle. For example, the planar shapes of openings 602 and 603 can be elliptical or curved. Alternatively, they can be polygonal or have rounded corners.

[0087] The description of the shapes of openings 602 and 603 can also be applied to opening 601.

[0088] The conductive layer 240 is preferably not disposed inside the opening 602. That is, the conductive layer 240 preferably does not contact the side of the insulating layer 280 on the side of the opening 602. By adopting this structure, both the opening 603 and the opening 602 can be formed simultaneously, thereby simplifying the process.

[0089] FIG. 3C An example is shown where the bottom end of the conductive layer 240 in the opening 603 coincides with or substantially coincides with the top end of the insulating layer 280 in the opening 602. Note that in this specification, the bottom surface of the conductive layer 240 refers to the surface on one side of the insulating layer 280. The top surface of the insulating layer 280 refers to the surface on one side of the conductive layer 240.

[0090] Note that end alignment or approximate alignment can also be described as end-aligned or approximately aligned. In cases of end-aligned or approximate alignment, and in cases of consistent or approximate planar shapes, it can be said that, when viewed from the plane, at least a portion of its edges overlaps with each other between the stacked layers. For example, this includes situations where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, sometimes the edges do not overlap and the upper layer is inside or outside the lower layer; in such cases, it can also be said that the ends are approximately aligned or the planar shapes are approximately consistent.

[0091] Hereinafter, the opening including opening 602 and opening 603 will sometimes be referred to as opening 290. That is, the insulating layer 280 and the conductive layer 240 are provided with opening 290 that leads to the conductive layer 220. Opening 602 is a part of opening 290, and opening 603 is another part of opening 290.

[0092] At least a portion of the semiconductor layer 270 is disposed in the opening 290. The semiconductor layer 270 has a region in the opening 290 that contacts the side surface of the conductive layer 240, a region that contacts the side surface of the insulating layer 280, and a region that contacts the top surface of the conductive layer 220. The semiconductor layer 270 has a region that contacts the top surface of the conductive layer 240.

[0093] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is disposed on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region that contacts the top surface of the semiconductor layer 270, a region that contacts the side surface of the semiconductor layer 270, a region that contacts the side surface of the conductive layer 240, and a region that contacts the top surface of the insulating layer 280.

[0094] A conductive layer 260 is disposed on an insulating layer 250 and has a region that contacts the top surface of the insulating layer 250. The conductive layer 260 is disposed such that it is embedded in an opening 290. The conductive layer 260 is disposed such that it is embedded in a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270 across the insulating layer 250.

[0095] FIG. 3C An example is shown where the conductive layer 260 overlaps with the conductive layer 240 across the insulating layer 250 and the semiconductor layer 270, but the invention is not limited thereto. For example, the conductive layer 260 may also be disposed without overlapping the conductive layer 240. By employing this structure, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the semiconductor device can be improved.

[0096] The transistor VT has the following structure: the direction of the channel length is not approximately parallel to the substrate (not shown) but along the sidewall of the opening 602 provided in the insulating layer 280. That is, the transistor VT is a vertical transistor.

[0097] Vertical transistors have a structure in which at least a portion of the source region, channel formation region, and drain region overlap when viewed from a plane, thus reducing the occupied area (also known as the footprint). Furthermore, because they have a structure that allows for a smaller channel length and a larger channel width, the on-state resistance can be reduced (and the on-state current increased).

[0098] Furthermore, one aspect of the present invention provides a vertical transistor having a structure in which at least a portion of the gate electrode of the Si transistor can overlap with the electrodes at both ends of the capacitor C1. That is, the conductive layer 316 of the transistor MT, the conductive layers 115 and 220 constituting the capacitor C1, and the semiconductor layer 270 of the transistor VT can have overlapping areas when viewed from a planar perspective. Thus, in the vertical transistor, the Si transistor and the capacitor C1 can be interconnected with a structure occupying a small area.

[0099] FIG. 3A An example is shown where the conductive layer 240 extends in a direction perpendicular to the conductive layers 330 and 260.

[0100] Here, FIG. 4A Show FIG. 3C A magnified view of semiconductor layer 270 and its vicinity. Furthermore... FIG. 4B A cross-sectional view of the XY plane including the conductive layer 240 is shown.

[0101] like FIG. 4A As shown, the semiconductor layer 270 has region 270i, region 270na and region 270nb disposed in a manner that sandwiches region 270i.

[0102] Region 270na is the region in semiconductor layer 270 that contacts conductive layer 220. Region 270nb is the region in semiconductor layer 270 that contacts conductive layer 240. Regions 270na and 270nb are used as the source or drain regions of transistor VT, respectively. FIG. 4B As shown, the conductive layer 240 contacts the entire outer periphery of the semiconductor layer 270. Therefore, the source or drain region of the transistor VT may be formed on the entire outer periphery of the portion of the semiconductor layer 270 formed in the same layer as the conductive layer 240.

[0103] Region 270i is the region in semiconductor layer 270 sandwiched between regions 270na and 270nb. Region 270i serves as the channel formation region for transistor VT. That is, the channel formation region for transistor VT is formed in a portion of semiconductor layer 270 located between conductive layer 220 and conductive layer 240. Alternatively, it can be stated that the channel formation region for transistor VT is located in or near the region of semiconductor layer 270 that is in contact with insulating layer 280.

[0104] The channel length of transistor VT is the distance between the source and drain regions. In other words, the channel length of transistor VT can be said to be determined by the thickness of the insulating layer 280 on the conductive layer 220. FIG. 4A In the diagram, the channel length L of transistor VT is represented by a dashed double arrow. Viewed in cross-section, the channel length L is the distance from the end of the region where semiconductor layer 270 contacts conductive layer 220 to the end of the region where semiconductor layer 270 contacts conductive layer 240. In other words, the channel length L is equivalent to the length of the side surface of the opening 602 of insulating layer 280 when viewed in cross-section.

[0105] In planar transistors, the channel length is determined according to the exposure limit of photolithography. However, in this invention, the channel length can be determined based on the thickness of the insulating layer 280. Therefore, the channel length of the transistor VT can be set to a very fine structure below the exposure limit of photolithography (e.g., 60nm or less, 50nm or less, 40nm or less, 30nm or less, 20nm or less, or 10nm or less but more than 1nm or more, or more than 5nm). This increases the on-state current of the transistor VT, improving its frequency characteristics. Consequently, a semiconductor device with high operating speed can be provided.

[0106] Furthermore, as described above, a channel forming region, a source region, and a drain region can be formed in the opening 290. Therefore, compared to a planar transistor where the channel forming region, source region, and drain region are respectively provided on the XY plane, the occupied area of ​​the transistor VT can be reduced. As a result, the semiconductor device can be highly integrated.

[0107] In addition, with FIG. 4B Similarly, on the XY plane including the channel formation region of semiconductor layer 270, semiconductor layer 270, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of semiconductor layer 270 across insulating layer 250. In other words, when viewed from above, the entire outer periphery of semiconductor layer 270 forms the channel formation region. At this time, for example, the channel width of transistor VT is determined by the length of the outer periphery of semiconductor layer 270. In other words, it can be said that the channel width of transistor VT is determined by the maximum width of opening 602. FIG. 4A andFIG. 4B In the diagram, a double-headed arrow with a double-dotted line represents the maximum width D of the opening 602. FIG. 4B In the diagram, the double-headed arrow with a dotted line represents the channel width W of transistor VT. By increasing the maximum width D of the opening 602, the channel width per unit area can be increased, thereby increasing the on-state current.

[0108] When forming the opening 602 using photolithography, the maximum width D of the opening 602 is set according to the exposure limit of the photolithography method. Furthermore, the maximum width D of the opening 602 is set according to the thickness of each of the semiconductor layer 270, insulating layer 250, and conductive layer 260 provided in the opening 602. The maximum width D of the opening 602 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more and less than 100 nm, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the shape of the opening 602 in top view is circular, the maximum width D of the opening 602 is equivalent to the diameter of the opening 602, and the channel width W can be calculated as "D×π".

[0109] Furthermore, the maximum width D of the opening 602 can be appropriately calculated based on the shape of the opening 602 when viewed from a plane. For example, when the opening 602 is a quadrilateral when viewed from a plane, the maximum width of the opening 602 is preferably the length of the diagonal of the quadrilateral. Alternatively, for example, when the shape of the opening 602 when viewed from a plane is an ellipse, a polygon, or a polygon with rounded corners, the maximum width of the opening 602 is preferably the diameter of the smallest circle (also called the smallest containing circle) that includes the shape of the opening 602 when viewed from a plane.

[0110] In one embodiment of the semiconductor device of the present invention, the channel length L of the transistor VT is preferably at least smaller than the channel width W of the transistor VT. In one embodiment of the present invention, the channel length L of the transistor VT is at least 0.1 times and less than 0.99 times the channel width W of the transistor VT, preferably at least 0.5 times and less than 0.8 times. By employing this structure, a transistor with good electrical characteristics and high reliability can be realized.

[0111] Furthermore, by forming the opening 602 in a nearly circular manner when viewed from above, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged in a concentric circle. As a result, the distance between the conductive layer 260 and the semiconductor layer 270 is approximately uniform, so a gate electric field can be applied to the semiconductor layer 270 approximately uniformly.

[0112] Note that in FIG. 4AIn the example, the opening 602 is provided such that the side surface of the opening 602 is perpendicular to the top surface of the conductive layer 220, but the present invention is not limited to this. For example, the side surface of the opening 602 may also be tapered.

[0113] In this specification and the like, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface. For example, it is preferable to have an area with an inclined side surface and a substrate surface (also referred to as a cone angle) of less than 90°.

[0114] like FIG. 3C As shown, a portion of the insulating layer 250 is located outside the opening 603, i.e., on the insulating layer 280. In this case, the insulating layer 250 preferably covers the side end of the conductive layer 240. This prevents a short circuit between the conductive layer 260 and the conductive layer 240.

[0115] Note that the semiconductor layer 270 can be a single layer or a stack of oxide semiconductors.

[0116] Semiconductor layer 270 preferably has a layered crystal that is substantially parallel to the side surface of insulating layer 280 in opening 602. By adopting this structure, the layered crystal of semiconductor layer 270 is substantially parallel to the channel length direction of transistor VT, thus increasing the on-state current of transistor.

[0117] When the semiconductor layer 270 contacts the conductive layer 220, metal compounds or oxygen vacancies are formed, and region 270na of the semiconductor layer 270 is reduced in resistance. By reducing the resistance of the semiconductor layer 270 in contact with the conductive layer 220, the contact resistance between the semiconductor layer 270 and the conductive layer 220 can be reduced. Similarly, when the semiconductor layer 270 contacts the conductive layer 240, region 270nb of the semiconductor layer 270 is reduced in resistance. This reduces the contact resistance between the semiconductor layer 270 and the conductive layer 240.

[0118] The conductive layer 240 may have a stacked structure of a first conductive layer and a second conductive layer on the first conductive layer. In this case, a highly conductive material can be used to form the first conductive layer, and an oxygen-containing conductive material can be used to form the second conductive layer. When an oxide semiconductor is used as the semiconductor layer 270, by using an oxygen-containing conductive material as the second conductive layer of the conductive layer 240 that contacts the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced, thereby suppressing the decrease in the on-state current of the transistor VT caused by the contact resistance. For example, tungsten is preferably used as the first conductive layer of the conductive layer 240, and indium tin oxide with added silicon is preferably used as the second conductive layer of the conductive layer 240.

[0119] A recess is provided in the conductive layer 220 at a position overlapping with the opening 602. The semiconductor layer 270 contacts the bottom and side surfaces of the recess included in the conductive layer 220. Note that the recess included in the conductive layer 220 can also be considered as part of the opening 290.

[0120] By including a recess in the conductive layer 220 at the location overlapping with the opening 602, compared to the case without the recess, the height of the bottom surface of the insulating layer 250 and the bottom surface of the conductive layer 260 within the opening 290 can be lower than the height of the top surface of the conductive layer 220 that contacts the insulating layer 280, when the top surface of the insulating layer 326 is taken as a reference. Here, the height of each surface can be determined based on the surface on which the transistor is formed. Here, the top surface of the insulating layer 326 is taken as a reference. There is no particular limitation on the surface used as a reference; for example, the top surface of the substrate on which the memory cell or transistor is disposed can also be used as a reference.

[0121] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing their contact resistance. Consequently, the decrease in the on-state current of the transistor VT due to the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, a gate electric field can be easily applied to the channel formation region of the semiconductor layer 270, thereby improving the electrical characteristics of the transistor VT. Moreover, a gate electric field can also be easily applied to the region of the semiconductor layer 270 that contacts the conductive layer 220, thus increasing the on-state current of the transistor VT. Furthermore, using either the conductive layer 220 or the conductive layer 240 as the drain electrode improves the electrical characteristics of the transistor VT.

[0122] As the conductive layer 220, it is preferable to use a conductive material containing oxygen. When an oxide semiconductor is used as the semiconductor layer 270, the contact resistance between the semiconductor layer 270 and the conductive layer 220 can be reduced by using a conductive material containing oxygen as the conductive layer 220.

[0123] Alternatively, the conductive layer 220 can also be constructed by stacking tungsten under an oxygen-containing conductive material. By stacking tungsten in this way, the conductivity of the conductive layer 220 can be improved.

[0124] Insulating layers 280 and 285 serve as interlayer films, so their relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, the capacitance value of parasitic capacitance generated between the wirings can be reduced.

[0125] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This helps to suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 270.

[0126] Furthermore, an insulator containing excess oxygen is preferably used as the insulating layer 280. By heat-treating the insulating layer 280 containing excess oxygen, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, thereby reducing oxygen vacancies and V. O H. This allows the electrical characteristics of transistor VT to be stabilized, thereby improving its reliability.

[0127] The transistors that can be used in this invention are not limited to FIG. 3C The transistor VT is shown. For example, it can also be used. FIG. 5A The transistor VT_BG with the structure shown is shown. FIG. 5A The transistor VT_BG shown is FIG. 3C The difference in the transistor VT shown is that it has a conductive layer 215 and an insulating layer 225.

[0128] like FIG. 5A As shown, a conductive layer 215 is provided on the insulating layer 280. Furthermore, an insulating layer 281 is disposed on both the insulating layer 280 and the conductive layer 215. Additionally, a conductive layer 240 is provided on the insulating layer 281.

[0129] An opening 604 leading to the conductive layer 220 is provided in the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240. The opening 604 includes openings in the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240. The sidewalls of the opening 604 include the sidewalls of the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240.

[0130] Each of the insulating layer 225, semiconductor layer 270, insulating layer 250, and conductive layer 220 is disposed such that at least a portion of each is located in the opening 604. Specifically, the insulating layer 225 is disposed such that it covers a portion of the bottom and sidewalls of the opening 290; the semiconductor layer 270 is disposed such that it covers the remaining portion of the bottom of the opening 290 and the insulating layer 225; and the insulating layer 250 is disposed such that it covers the semiconductor layer 270. Furthermore, the conductive layer 260 is disposed such that it is embedded in a recess of the insulating layer 250 that reflects the shape of the opening 604.

[0131] The insulating layer 225 contacts a portion of the top surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 215, the side surface of the insulating layer 281, and the side surface of the conductive layer 240 in the opening 604.

[0132] exist FIG. 5AIn the transistor VT_BG shown, semiconductor layer 270 is used as a semiconductor layer, conductive layer 260 is used as a first gate electrode, insulating layer 250 is used as a first gate insulating film, conductive layer 215 is used as a second gate electrode, insulating layer 225 is used as a second gate insulating film, and conductive layer 220 and conductive layer 240 are used as source electrode or drain electrode, respectively.

[0133] The threshold voltage V of the transistor can be controlled by independently changing the potential applied to the conductive layer 215 without linking it to the potential applied to the conductive layer 260. th In particular, by applying a negative potential to the conductive layer 215, the Vt of the transistor can be further increased. th This reduces the off-state current. Therefore, compared to not applying a negative potential to the conductive layer 215, applying a negative potential to the conductive layer 215 can reduce the drain current when the potential applied to the conductive layer 260 is 0V. Furthermore, the conductive layer 260 can be used as the second gate electrode, and the conductive layer 215 can be used as the first gate electrode.

[0134] Alternatively, conductive layer 215 can also be connected to conductive layer 260. By connecting conductive layer 215 and conductive layer 260 and applying the same potential to them, the on-state current can be increased, the initial characteristic deviation can be reduced, the electrical characteristic degradation under negative GBT (Gate Bias-Temperature) stress testing can be suppressed, and the rise voltage variation of the on-state current under different drain voltages can be suppressed.

[0135] As mentioned above, due to FIG. 5A The transistor VT_BG shown includes a first gate electrode and a second gate electrode, thus enabling the transistor VT included in the semiconductor device 10 to have good electrical characteristics. FIG. 5B This illustrates when the structure of transistor VT_BG is applied... FIG. 1A The circuit diagram at that time. FIG. 5B The semiconductor device 10A shown can be a transistor VT_BG that includes an electrode BGL used as a second gate electrode.

[0136] FIG. 6A This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device different from semiconductor device 10. FIG. 6A The semiconductor device 10B shown is equivalent to a structure that omits conductive layers 328 and 330 and the insulating layer including conductive layers 328 and 330. By adopting this structure, the wiring distance between capacitor C1 and transistor MT can be shortened. As a result, the parasitic capacitance of the gate electrode of transistor MT is significantly reduced, thereby reducing power consumption and signal delay.

[0137] FIG. 6B This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device different from semiconductor device 10.FIG. 6B The semiconductor device 10C shown includes, in addition to conductive layers 328 and 330, a wiring layer 40 for connecting the electrode GE of transistor MT and the electrode CE1 of capacitor C1. Wiring layer 40 includes electrodes LE for connecting elements included in element layer 20 and elements included in element layer 30. By employing this structure, the wiring distance between capacitor C1 and transistor MT can be increased. Therefore, the distance between transistor VT and transistor MT can be increased, thereby preventing electrical interference between transistors. Furthermore, by using electrode LE as a wiring layer, the freedom of circuit design can be increased.

[0138] The following describes the constituent materials that can be used in semiconductor devices.

[0139] Substrates suitable for use in semiconductor devices can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0140] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0141] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative permittivity as the insulator used as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material based on the function of the insulator. Additionally, materials with a low relative permittivity are also materials with high dielectric strength.

[0142] Materials with relatively high permittivity (high-k) include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0143] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Additionally, porous silicon oxides can be cited. Moreover, these silicon oxides may also contain nitrogen.

[0144] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities and oxygen.

[0145] Furthermore, the insulating layer in contact with the semiconductor layer, or the insulating layer disposed near the semiconductor layer, such as a gate insulating film, preferably has regions containing excess oxygen. For example, when an insulating layer having regions containing excess oxygen is in contact with the semiconductor layer, or when an insulating layer having regions containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0146] In addition, examples of oxygen-barrier insulators include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0147] In addition, examples of insulators that have hydrogen-blocking properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.

[0148] An oxygen-blocking insulator and a hydrogen-blocking insulator can be described as an insulator that blocks one or both of oxygen and hydrogen.

[0149] Furthermore, as insulators capable of trapping or fixing hydrogen, examples include oxides containing magnesium or oxides containing one or both of aluminum and hafnium. Moreover, these oxides are more preferably amorphous. Oxides with amorphous structures sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. Furthermore, while these metal oxides are preferably amorphous, some may also have crystalline regions.

[0150] Note that in this specification, the term "barrier insulating film" refers to an insulating film with barrier properties. Furthermore, barrier properties refer to the property that makes it difficult for the corresponding substance to diffuse (also known as the property that makes it difficult for the corresponding substance to pass through, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Additionally, the function of trapping or fixing (also known as gettering) the corresponding substance can be referred to as barrier properties. Furthermore, hydrogen, denoted as the corresponding substance, refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc., does not readily diffuse.

[0151] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. As an alloy containing the above-mentioned metallic elements, a nitride of the alloy or an oxide of the alloy may also be used. For example, tantalum nitride, titanium nitride, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred.

[0152] Furthermore, conductive materials containing nitrogen, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, or titanium and aluminum nitrides; conductive materials containing oxygen, such as ruthenium oxide, strontium and ruthenium oxides, or lanthanum and nickel oxides; and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0153] In addition, conductive materials with tungsten, copper or aluminum as the main components have high conductivity and are therefore preferred.

[0154] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0155] Furthermore, when using oxide semiconductors in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0156] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can be used. Furthermore, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon can also be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the oxide semiconductor in which the channel is formed can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0157] Semiconductor materials that can be used as semiconductor layers are not limited to oxide semiconductors. Semiconductor materials with band gaps (semiconductor materials that are not zero-bandgap semiconductors) can also be used as semiconductor layers. For example, it is preferable to use single-element semiconductors, compound semiconductors, or layered materials (also known as atomic layer materials, two-dimensional materials, etc.) as semiconductor materials.

[0158] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using materials that are semiconductors and have high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0159] Examples of semiconductors that can be used as single-element semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include, for instance, low-temperature polycrystalline silicon (LTPS).

[0160] Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride suitable for use in semiconductor layers preferably has an amorphous structure. Boron arsenide suitable for use in semiconductor layers preferably comprises crystals with a cubic crystal structure.

[0161] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride, a layered material, carbon, nitrogen, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0162] As a semiconductor layer, transition metal chalcogenides, which are typically used as semiconductors, are preferred, for example. Examples of transition metal chalcogenides suitable for use in semiconductor layers include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By using the aforementioned transition metal chalcogenides as semiconductor layers, semiconductor devices with high on-state currents can be provided.

[0163] In one embodiment of the semiconductor device of the present invention, the OS transistor is a vertical transistor. Compared to a lateral transistor, a vertical transistor can reduce the channel length and increase the channel width. Therefore, even if the OS transistor is miniaturized in the same way as the Si transistor, the drive voltage can be reduced. Thus, although the current flowing through the transistor in the off state is extremely small, it can be a semiconductor device with a device structure having a low drive voltage.

[0164] Furthermore, in one embodiment of the semiconductor device of the present invention, the capacitor has a trench structure, and one of its electrodes is connected to the gate of the Si transistor. Since the capacitor electrodes are arranged in the openings of the trench structure capacitor, a capacitor with a large storage capacitance per unit area can be achieved. Additionally, in one embodiment of the semiconductor device of the present invention, since a structure is adopted for data readout using capacitive coupling with the gate of the Si transistor in an electrically floating state, the circuit area can be reduced without increasing the number of openings, such as the connection between the capacitor and the gate of the Si transistor, or the connection between one of the source and drain electrodes of the Si transistor and the gate of the Si transistor.

[0165] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0166] (Implementation Method 2)

[0167] In this embodiment, an example of the structure of a signal processing circuit including the semiconductor device described in Embodiment 1 above will be described.

[0168] FIG. 7A A block diagram of a signal processing circuit 100 including a semiconductor device 10 is shown. FIG. 7B It is a timing diagram used to illustrate the operation of the signal processing circuit 100.

[0169] FIG. 7A The signal processing circuit 100 includes a storage circuit 101, a semiconductor device 10, an inverter circuit 111, a switching circuit 112, and an inverter circuit 113. The inverter circuit 111 includes a p-channel transistor 111P and an n-channel transistor 111N. The storage circuit 101 retains data only during the period when the power supply voltage is supplied. The semiconductor device 10 includes the transistor MT, capacitor C1, and transistor VT described in Embodiment 1.

[0170] Additionally, the signal processing circuit 100 may include other circuit elements such as diodes, resistors, or inductors, as needed.

[0171] exist FIG. 7A In this circuit, the gate of transistor VT is input with control signal S1. Inverter circuit 111 is input with control signal S2, which is different from control signal S1. Switching circuit 112 is input with control signal S3, which is different from both control signals S1 and S2. Additionally, voltage V2 is applied to inverter circuit 111. The output signal of inverter circuit 111 is supplied to switching circuit 112 via inverter circuit 113. Transistor MT of semiconductor device 10 is supplied with voltage V1. Voltage V2 is, for example, voltage VDD. Voltage V1 is, for example, voltage VSS or ground potential GND.

[0172] exist FIG. 7A In this circuit, the voltage equivalent to the potential difference between voltages V1 and V2 is supplied to the storage circuit 101 as the power supply voltage of the signal processing circuit 100. During periods when no power supply voltage is supplied to the storage circuit 101, the potential difference between voltages V1 and V2 can be (substantially) eliminated. For example, both voltages V1 and V2 can be voltage VSS.

[0173] One of the source and drain terminals of transistor VT is connected to terminal D of storage circuit 101. IN Connection. Terminal D INThe data potential of dataX is held by the output storage circuit 101. By controlling the on or off state of transistor VT according to the control signal S1, the data potential of dataX can be maintained in node M1, i.e., one electrode of capacitor C1. Since the potentials of the other electrode of capacitor C1 and the gate electrode of transistor M1 are in an electrically floating state, they become the potentials corresponding to the changes in the data potential of dataX. The potentials of the other electrode of capacitor C1 and the gate electrode of transistor M1 are initially voltage V1 based on the leakage current through the gate insulating film. Therefore, the potentials of the other electrode of capacitor C1 and the gate electrode of transistor M1 can be the data potential of dataX.

[0174] When the potential of the gate electrode of transistor M1 becomes the data potential of dataX, the power supply voltage supplied to inverter circuit 111 can be controlled.

[0175] When transistor MT is in the ON state according to the data potential of dataX, inverter circuit 111 has the function of supplying the inverted signal of control signal S2 to node M2. For example, when control signal S2 is at level H, transistor 111P becomes non-ON, while transistors 111N and MT become ON, thus node M2 ​​becomes voltage V1, i.e., level L. Alternatively, for example, when control signal S2 is at level L, transistors 111P and MT become ON, while transistor 111N becomes non-ON, thus node M2 ​​becomes voltage V2, i.e., level H.

[0176] According to the data potential of dataX, when transistor MT is in a non-conducting state, node M2 ​​becomes either H level or an indeterminate state. For example, when control signal S2 is H level, transistor 111P becomes non-conducting, transistors 111N and MT become non-conducting, thus node M2 ​​becomes an indeterminate state. Therefore, node M2 ​​maintains its previous state. Alternatively, for example, when control signal S2 is L level, transistor 111P becomes conducting, transistors 111N and MT become non-conducting, thus node M2 ​​becomes voltage V2, i.e., H level.

[0177] The potential of node M2 ​​is supplied to one terminal of switching circuit 112 through inverter circuit 113. In switching circuit 112, the conduction or deconduction state between one terminal and another terminal is controlled by control signal S3. The other terminal of switching circuit 112 is connected to terminal D of storage circuit 101. OUT Connection. Terminal D OUT The same logic data potential is supplied as the data dataX held in node M1 of semiconductor device 10.

[0178] Note that the storage circuit 101 is a storage circuit constructed using Si transistors. The storage circuit 101 is a storage element capable of storing one bit of data. The storage circuit 101 is, for example, a circuit used as a flip-flop circuit or latch circuit included in a register or cache within a processor. The flip-flop circuit or latch circuit can operate at high speed according to a clock signal, etc. On the other hand, during periods when no power supply voltage is available, the flip-flop circuit or latch circuit struggles to retain data. Furthermore, during periods when data is not being updated, the power consumption required for data retention by the flip-flop circuit or latch circuit is high. During periods of low data update frequency, by backing up the data to a semiconductor device and then restoring it, a period during which the power supply voltage to the storage circuit 101 is stopped can be set, thereby reducing power consumption.

[0179] In addition, signal processing circuits including storage circuit 101, CPU (central processing unit), microprocessor, image processing circuit, DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), and LSI (Large Scale Integrated Circuit) all fall under its category.

[0180] Alternatively, the switching circuit 112 can also be constructed using a transistor. This transistor can be either an n-channel transistor or a p-channel transistor. Furthermore, an n-channel transistor and a p-channel transistor can be combined. For example, the switching circuit 112 can be an analog switch.

[0181] The above describes the structure of the signal processing circuit 100. Next, the following will be explained... FIG. 7A The driving method of the signal processing circuit 100 shown is described below. Specifically, in the signal processing circuit 100, after supplying the power supply voltage, the power supply voltage is stopped to reduce power consumption while holding data, and then the power supply voltage is supplied again.

[0182] FIG. 7B The timing diagram shows FIG. 7A The signals and potentials in the signal processing circuit 100 shown. FIG. 7B In the diagram, 101 shows the data stored in the storage circuit 101, S1 shows the potential of control signal S1, S2 shows the potential of control signal S2, S3 shows the potential of control signal S3, V1 shows voltage V1, and V2 shows voltage V2. When the potential difference V between voltage V1 and voltage V2 is 0, it is equivalent to the case where no power supply voltage is supplied. M1 represents the potential of node M1, and M2 represents the potential of node M2.

[0183] Note that in the driving method shown below, in FIG. 7A In the structure shown, transistors VT and MT are n-channel transistors. That is, an example is shown where transistor VT is turned on when control signal S1 is at level H, and turned off when control signal S1 is at level L. Additionally, an example is shown where voltage V1 is set to voltage VSS and voltage V2 is switched to either voltage VDD or voltage VSS.

[0184] exist FIG. 7B The following describes the operation during period T01. During period T01, a power supply voltage is supplied to the signal processing circuit 100. Here, voltage V2 is VDD. During the period when the power supply voltage is supplied to the signal processing circuit 100, the storage circuit 101 retains data (in... FIG. 7B In this case, it is recorded as dataX). At this time, the control signal S3 is set to L level, so that one terminal of the switching circuit 112 is in a non-conductive state with respect to the other terminal. Note that during period T02, the control signal S2 can be H level or L level (in FIG. 7B In the diagram, it is recorded as A). Furthermore, the state of transistor VT (conducting or de-conducting) can be either any state. That is, the potential of control signal S1 can be either H level or L level (in the diagram). FIG. 7B In the middle, it is recorded as A). During period T01, node M1 can have any potential (in FIG. 7B In the middle, it is recorded as A). During period T01, node M2 ​​can have any potential (in FIG. 7B In the text, it is recorded as A). The work during period T01 is called normal work.

[0185] exist FIG. 7B The following describes the operation of T02 during the process. Before stopping the supply of power voltage to the signal processing circuit 100, the control signal S1 is set to level H, causing transistor VT to be in the conducting state. Thus, the data potential corresponding to the data (dataX) held in the storage circuit 101 is input to capacitor C1 through transistor VT. When the potential of one electrode of capacitor C1 changes, the potential of the gate of transistor MT also changes. The signal input to the gate of transistor MT is held by capacitor C1. Thus, the potential of node M1 becomes the signal potential corresponding to the data held in the storage circuit 101 (in...). FIG. 7BIn the diagram, it is referred to as VX). Then, the control signal S1 is set to the L level, causing the transistor VT to be in a non-conducting state. Thus, the data potential corresponding to the data held in the storage circuit 101 is maintained in the semiconductor device 10. During period T02, according to the control signal S3, one terminal of the switching circuit 112 is in a non-conducting state with respect to the other terminal. Note that during period T02, the control signal S2 can be either the H level or the L level (in the diagram). FIG. 7B In the middle, it is recorded as A). During period T02, node M2 ​​can have any potential (in FIG. 7B In the text, it is recorded as A). The work during period T02 is referred to as the work before the power supply voltage is stopped.

[0186] exist FIG. 7B The following describes the operation during period T03. After the operation prior to stopping the power supply voltage, the power supply voltage to the signal processing circuit 100 is stopped at the start of period T03. Voltage V2 becomes VSS. When the power supply voltage is stopped, the data (dataX) stored in the storage circuit 101 disappears. However, after the power supply voltage to the signal processing circuit 100 is stopped, the signal potential (VX) corresponding to the data (dataX) stored in the storage circuit 101 is still held in node M1 by capacitor C1. Transistor VT is an OS transistor. Transistor VT can be an enhancement-mode (normally off) n-channel transistor with a very small current flowing through it in the non-conducting state (off-state current). By employing a structure in which the ground potential (0V) is continuously input to the gate of transistor VT when the power supply voltage to the signal processing circuit 100 is stopped, the non-conducting state of transistor VT can also be maintained after the power supply voltage to the signal processing circuit 100 is stopped. As a result, the potential (potential VX at node M2) held by capacitor C1 can be maintained for a long period of time. Therefore, the signal processing circuit 100 is able to retain the data (dataX) even after the power supply voltage is stopped. Period T03 corresponds to the period during which the power supply voltage to the signal processing circuit 100 is stopped.

[0187] exist FIG. 7B The following describes the operation during period T04. To restart the supply of power voltage to the signal processing circuit 100, voltage V2 is set to VDD. Additionally, control signal S2 is set to low level (L). At this time, control signal S1 is at low level, and transistor VT remains in a non-conducting state. Furthermore, control signal S3 is at low level, and one terminal of switching circuit 112 is in a non-conducting state with respect to the other terminal. Thus, the voltage V2, i.e., VDD, when the power supply voltage is supplied, is input to inverter circuit 111. Therefore, in inverter circuit 111, transistor 111P becomes conductive, and the potential of node M2 ​​can be set to a fixed potential (e.g., VDD) (hereinafter referred to as pre-charge operation).

[0188] After the pre-charging operation described above, during period T05, control signal S2 is set to level H. At this time, control signal S1 remains at level L, and transistor VT remains in a non-conducting state. Additionally, control signal S3 is at level L, and one terminal of switching circuit 112 is in a non-conducting state with respect to the other terminal.

[0189] The signal held in capacitor C1 (potential VX of node M2) determines whether transistor MT is in an on or off state, thus deciding whether to supply an L-level potential to inverter circuit 111. When transistor MT is on and transistor 111N in inverter circuit 111 is also on, a voltage V1 (e.g., VSS) is input to node M2. As a result, node M2 ​​becomes L-level. On the other hand, when transistor MT is off and transistor 111N in inverter circuit 111 is also on, no L-level potential is supplied to node M2, and the potential of node M2 ​​remains at a fixed potential (e.g., VDD) determined by the pre-charge operation described above.

[0190] Thus, corresponding to the on or off state of transistor MT, the potential of node M2 ​​becomes VDD or VSS. For example, when the signal held in storage circuit 101 is "1" and corresponds to an H-level potential (VDD), the potential of node M2 ​​is an L-level potential (VSS) corresponding to the signal "0". Conversely, when the signal held in storage circuit 101 is "0" and corresponds to an L-level potential (VSS), the potential of node M2 ​​is an H-level potential (VDD) corresponding to the signal "1". In other words, node M2 ​​holds the inverted signal of the data (dataX) stored in storage circuit 101. FIG. 7A In this context, this potential is recorded as VXb. That is, the signal corresponding to the data (dataX) input from the storage circuit 101 during period T02 is converted into the potential (VXb) of node M2.

[0191] Then, during period T06, the potential of control signal S3 is set to level H, making one terminal of switching circuit 112 conduct with the other terminal. At this time, the potential of control signal S2 remains at level H. Additionally, control signal S1 remains at level L, and transistor VT remains in a non-conducting state. Thus, the potential (VXb) of node M2 ​​becomes an inverted signal through inverter circuit 113, which can be input to storage circuit 101. That is, the potential (VXb) of node M2 ​​can be the logic of logically inverted data (dataX). Therefore, storage circuit 101 can again retain the data (dataX) held before the power supply voltage to signal processing circuit 100 was stopped.

[0192] During the transit period, the pre-charge operation in T04 sets the potential of node M2 ​​to a fixed potential (in FIG. 8 After VDD), during period T05, it is set to the potential VXb corresponding to the data (dataX). Because of the pre-charge operation, the time until the potential of node M2 ​​reaches the specified potential VXb can be shortened. Therefore, the time until the storage circuit 101 retains the original data after the power supply voltage is restarted can be shortened.

[0193] The above describes the driving method of the signal processing circuit 100. In the above driving method, during the period when the signal processing circuit 100 is not supplied with a power supply voltage, the data stored in the storage circuit 101, which is equivalent to a volatile memory, can be retained by the capacitor C1 provided in the semiconductor device 10.

[0194] In one embodiment of the semiconductor device 10 of the present invention, the OS transistor is a vertical transistor. Compared to a lateral transistor, a vertical transistor can reduce the channel length and increase the channel width. Therefore, even if the OS transistor is miniaturized in the same way as the Si transistor, the driving voltage can be reduced. Thus, although the current flowing through the transistor in the off state is extremely small, it can be a semiconductor device with a device structure having a low driving voltage.

[0195] Furthermore, in the structure of the semiconductor device 10 according to one aspect of the present invention, the capacitor has a trench structure, and one of its electrodes is connected to the gate of the Si transistor. Since the capacitor electrodes are arranged in the openings of the trench structure capacitor, a capacitor with a large storage capacitance per unit area can be achieved. Additionally, in the structure of the semiconductor device according to one aspect of the present invention, since a structure is adopted for data readout using capacitive coupling with the gate of the Si transistor in an electrically floating state, the circuit area can be reduced without increasing the number of openings, such as the connection between the capacitor and the gate of the Si transistor, or the connection between one of the source and drain electrodes of the Si transistor and the gate of the Si transistor.

[0196] In the semiconductor device 10, the signal held by capacitor C1 is input to the gate of transistor MT. Therefore, after the power supply voltage to the signal processing circuit 100 is resumed, the state of transistor MT (on or off) can be determined based on the signal held by capacitor C1, and the signal can be read from the semiconductor device 10. Thus, even if the potential corresponding to the signal held in capacitor C1 changes slightly, the original signal can be read accurately.

[0197] By incorporating this signal processing circuit 100 into storage devices such as registers or cache memories within a processor, data within the storage device can be prevented from being lost due to a power supply interruption. Furthermore, the system can quickly restore the state to which it was before the power supply was interrupted after the power supply is resumed. Therefore, even for a short period, power can be interrupted in the signal processing circuit as a whole or in one or more logic circuits constituting the signal processing circuit, thus providing a signal processing circuit capable of suppressing power consumption.

[0198] exist FIG. 8 When the signal processing circuit 100 shown is represented by component layer 20 and component layer 30 as described in Embodiment 1 above, it can be used as follows: FIG. 8 As shown in the diagram.

[0199] exist FIG. 1B In the diagram, the structures disposed in the component layer 20 are shown as inverter circuit 111, inverter circuit 113, switching circuit 112, storage circuit 101, and transistor MT. Additionally, in... FIG. 9A In the diagram, the structure disposed in component layer 30 is shown as capacitor C1 and transistor VT. Component layers 20 and 30 are as follows... FIG. 8 As shown, they can be stacked in the Z direction.

[0200] In the structure of a signal processing circuit 100 according to one embodiment of the present invention, a capacitor C1 and a transistor MT are disposed in a component layer 30 above a component layer 20 of a storage circuit 101, etc. Therefore, the wiring distance between the capacitor C1 and the transistor MT can be shortened. Consequently, the parasitic capacitance of the gate electrode of the transistor MT is significantly reduced, thereby reducing power consumption and signal delay.

[0201] FIG. 9A Showing with FIG. 9A Examples of different structures for component layer 20 and component layer 30 are illustrated. FIG. 9B In the diagram, the inverter circuit 111, inverter circuit 113, switching circuit 112, storage circuit 101, and transistor MT in component layer 20 are shown as circuit section 120. Additionally, the capacitor C1 and transistor MT in component layer 30 are shown as circuit section 130.

[0202] exist FIG. 9AIn the structure shown, one electrode of capacitor C1 is connected to the terminal of the supply voltage V1. One of the source and drain of transistor VT is connected to the gate of transistor MT. The connection between the source and drain of transistor VT and the gate of transistor MT is made in the connection portion 150A provided between element layer 20 and element layer 30. Additionally, one electrode of capacitor C1 is connected to the terminal of the supply voltage V1 in the connection portion 150B provided between element layer 20 and element layer 30.

[0203] FIG. 9A Explanation shown FIG. 9B This is a schematic diagram showing the positional relationship between the connecting portions 150A and 150B. The circuit portion 120 disposed in the component layer 20 has an area overlapping with the circuit portion 130 disposed in the component layer 30. The connecting portion 150 may be disposed in the area where the circuit portions 120 and 130 overlap. Alternatively, the connecting portion 150B is preferably disposed in an area where neither the circuit portions 120 nor 130 are disposed.

[0204] By adopting FIG. 10A to FIG. 11D and FIG. 10A With this structure, the connection portions for connecting capacitor C1 to transistor VT and transistor VT to transistor MT can be respectively arranged in the regions where circuit portions 120 and 130 are provided and in the regions outside the circuit portions 120 and 130. Therefore, even if a structure is adopted for connecting capacitor to the gate of Si transistor and connecting one of the source and drain of OS transistor to the gate of Si transistor, the circuit area can be reduced without increasing the number of openings used to provide the connection portions between component layer 20 and component layer 30.

[0205] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0206] (Implementation Method 3)

[0207] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer for a transistor is described.

[0208] [Oxide semiconductor layer]

[0209] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include the CAAC (c-axis aligned crystal) structure, the polycrystalline structure, and the nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Therefore, the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention can be improved, and the reliability of semiconductor devices in which transistors are mounted can be improved.

[0210] In one embodiment of the present invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure refers to a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are oriented along the c-axis and connected on the ab plane in a manner where the multiple microcrystals are not oriented. Furthermore, when a cross-section of the oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that the metal atoms are arranged in layers within the crystalline regions. Therefore, the oxide semiconductor layer having a CAAC structure can also be described as a structure with layered crystalline regions.

[0211] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, it can be analyzed by combining several of the above methods.

[0212] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and crystalline semiconductors other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in a portion thereof). When the oxide semiconductor layer is crystalline, it can sometimes suppress the degradation of transistor characteristics.

[0213] The metal oxide comprising the oxide semiconductor layer of one aspect of the present invention can include, for example, indium oxide, gallium oxide, and zinc oxide. The metal oxide of one aspect of the present invention preferably comprises at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. Additionally, element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one aspect of the present invention preferably comprises any one or more selected from indium, gallium, and zinc. Note that in this specification and other documents, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and other documents sometimes include half-metallic elements.

[0214] As one embodiment of the present invention, the metal oxide may be indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. In addition, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon.

[0215] By increasing the proportion of indium atoms in a metal oxide relative to the total number of atoms of all metal elements, transistors can achieve large on-state current and high frequency characteristics.

[0216] In addition, metal oxides can also contain one or more of the periodically numbered metals in the periodic table instead of indium. Alternatively, metal oxides can contain one or more of the periodically numbered metals in the periodic table besides indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including periodically numbered metals, the field-effect mobility of transistors can sometimes be improved. Examples of periodically numbered metals include those belonging to the fifth period and those belonging to the sixth period. Specific examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0217] In addition, metal oxides may also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0218] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0219] Furthermore, by increasing the proportion of element M atoms in the metal oxide relative to the total number of atoms of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. In addition, variations in the transistor's electrical characteristics are suppressed, thereby improving reliability.

[0220] In this embodiment, In-Ga-Zn oxides are sometimes used as an example to illustrate metal oxides.

[0221] In one embodiment of the present invention, the oxide semiconductor layer is crystalline. Furthermore, in another embodiment of the present invention, the oxide semiconductor layer preferably has a CAAC structure.

[0222] An oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using at least two deposition methods. For example, an oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0223] An oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. In this case, as the first deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the second deposition method. When a deposition method that causes less damage to the surface to be formed is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, the incorporation of impurities such as silicon into the second layer can be suppressed, thereby improving the crystallinity of the oxide semiconductor layer.

[0224] Examples of first deposition methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet deposition methods. Examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photochemical CVD, and metal-organic CVD (MOCVD). Examples of wet deposition methods include spraying. Compared to sputtering methods described later, ALD and CVD methods can suppress damage to the surface being formed, making them suitable as first deposition methods.

[0225] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0226] The ALD method allows for atomic deposition layer by layer, resulting in advantages such as: extremely thin deposition; the ability to deposit on structures with high aspect ratios or surfaces with large steps; deposition with fewer defects such as pinholes; high coverage; and the ability to deposit at low temperatures. Furthermore, the PEALD method, utilizing plasma, allows for deposition at even lower temperatures, making it sometimes preferred. Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films deposited using the ALD method sometimes contain more carbon or chlorine than films deposited using other methods. It should be noted that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Furthermore, in a metal oxide deposition method according to one aspect of the present invention, the ALD method employs one or both of the following conditions: a high substrate temperature during deposition and an impurity removal process. Compared to the case where the ALD method is used without employing the aforementioned conditions and processes, the carbon and chlorine content in the film is sometimes lower.

[0227] Unlike deposition methods that deposit particles released from a target or similar material, the ALD (Advanced Layer Deposition) method forms a film through a reaction on the surface of the workpiece. Therefore, the ALD method is a deposition method with good step coverage, less affected by the shape of the workpiece. In particular, the ALD method exhibits good step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings, etc.

[0228] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, thermal CVD, because it does not use plasma, is a deposition method that reduces plasma damage to the workpiece. Moreover, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0229] Examples of secondary deposition methods include sputtering and pulsed laser deposition (PLD). Metal oxides formed using these secondary deposition methods tend to have a CAAC structure.

[0230] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, having a lower crystallinity than the CAAC structure, is sometimes formed. By forming a second layer with higher crystallinity on the first layer with lower crystallinity, or by performing heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the nucleus. As a result, the crystallinity of the oxide semiconductor layer as a whole, including the interface with the surface to which it is formed, can be improved.

[0231] Furthermore, a third layer can also be formed on the second layer. Because the second layer has high crystallinity, the third layer can crystallize and grow using the crystals of the second layer as nuclei or seeds. Thus, even if the deposition method for the third layer does not utilize a deposition method that readily produces crystals, the third layer can still be crystallized. Here, for example, when the third layer is formed using a deposition method with higher coverage than the second layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer.

[0232] As an example, an oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and then forming a metal oxide as a third layer using the first deposition method. Specifically, the first deposition method can be the ALD method, and the second deposition method can be the sputtering method. Compared with the sputtering method, the ALD method is a deposition method with excellent coverage. When the ALD method is used as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with high aspect ratios.

[0233] [Manufacturing method of oxide semiconductor layer]

[0234] The oxide semiconductor 230 of the oxide semiconductor layer can be manufactured, for example, by the following steps: forming oxide semiconductor 230a on layer 229 of the surface to be formed using the ALD method, forming oxide semiconductor 230b on oxide semiconductor 230a using the sputtering method, and forming oxide semiconductor 230c on oxide semiconductor 230b using the ALD method. Furthermore, it is preferable to perform heat treatment after forming the oxide semiconductor 230. By performing heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. The heat treatment described herein is not limited to heating treatment. For example, it can also be heat applied during the manufacturing process.

[0235] The oxide semiconductor 230 can be used for semiconductor layer 270, etc. Additionally, layer 229 corresponds to the insulating layer 280, etc., described in the above embodiments.

[0236] Layer 229 may also be non-crystalline. Furthermore, if layer 229 is crystalline, it may have a crystal structure with low lattice integration with the metal oxide contained in the oxide semiconductor 230.

[0237] Reference FIG. 10B An example illustrating the manufacturing method of oxide semiconductor 230.

[0238] When depositing metal oxide films using sputtering, alloying of the components contained in the metal oxide film and the components contained in the layer on the surface to be formed can sometimes occur due to damage caused by sputtering particles on the surface to be formed or by energy applied to the substrate side by sputtering particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even after heat treatment described later. When using an oxide semiconductor layer with alloyed regions in a transistor, there are concerns about negatively impacting the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer on the surface to be formed.

[0239] Therefore, oxide semiconductor 230a is first formed on layer 229 using the ALD method. FIG. 10A Next, oxide semiconductor 230b is formed on oxide semiconductor 230a using a sputtering method. FIG. 10B ).

[0240] In one embodiment of the present invention, an oxide semiconductor layer manufacturing method is used to form an oxide semiconductor 230a between an oxide semiconductor 230b and a layer 229 using a deposition method that causes minimal damage to the surface to be formed. This suppresses the alloying of the components contained in the oxide semiconductor 230 with the components contained in the layer 229, thereby further improving the crystallinity of the oxide semiconductor 230.

[0241] By employing the above structure, the thickness of the alloyed region can be reduced to a point where it is not observable. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that... FIG. 10A and FIG. 10C An example is shown where no alloying region is formed between layer 229 and oxide semiconductor 230a.

[0242] Note that the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0243] For example, using the direction perpendicular to the surface to which the oxide semiconductor 230a is formed as the depth direction, a linear EDX analysis is performed on the aforementioned region and its surrounding area. Next, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth at which the quantitative value of a metal that is a major component of the oxide semiconductor 230a but not a major component of the layer forming the surface (here, layer 229) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element that is a major component of the layer forming the surface but not a major component of the oxide semiconductor 230a (e.g., Si) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer forming the surface. Through these steps, the thickness of the alloyed region can be calculated.

[0244] In one aspect of the oxide semiconductor layer of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0245] Additionally, for example, when using a silicon oxide layer as layer 229 and performing SIMS analysis on the oxide semiconductor 230 formed on layer 229, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration in layer 229, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 Preferably 5.0×10 20 atoms / cm 3 More preferably 1.0×10 20 atoms / cm 3 The distance between the depth and the interface is the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0246] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the range mentioned above.

[0247] Furthermore, by reducing the alloying region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region in a substantially perpendicular direction that is greater than 0 nm and less than 3 nm from the surface to be formed of the oxide semiconductor 230, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0248] Note that CAAC structures near the formed surface can sometimes be identified during TEM observation. For example, when performing cross-sectional observation of oxide semiconductor 230 using high-resolution TEM, layered bright spots arranged in a direction parallel to the formed surface were identified near the formed surface.

[0249] Furthermore, when forming oxide semiconductor 230a using the ALD method, sometimes oxide semiconductor layers with microcrystalline or amorphous structures that have lower crystallinity than the CAAC structure are formed. That is, in FIG. 10D In the manufacturing stages shown, oxide semiconductor 230a sometimes includes regions whose crystallinity is lower than that of oxide semiconductor 230b.

[0250] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0251] When forming the oxide semiconductor 230b using a sputtering method, a mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, due to sputtered particles during the formation of the oxide semiconductor 230b, or energy supplied to the substrate side by sputtered particles, small crystalline regions may sometimes form in the mixed layer 231. In subsequent heat treatment processes, at least a portion of the oxide semiconductor 230a may crystallize by using the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 as nuclei.

[0252] When depositing oxide semiconductor 230b using sputtering, it is preferable to heat the substrate. When forming metal oxides, by increasing the substrate temperature (stage temperature) during metal oxide formation, it is sometimes possible to form highly crystalline metal oxides.

[0253] Next, oxide semiconductor 230c is formed on oxide semiconductor 230b using the ALD method. FIG. 10D For the formation of oxide semiconductor 230c using the ALD method, please refer to the formation method of oxide semiconductor 230a.

[0254] When forming oxide semiconductor 230c on oxide semiconductor 230b having a CAAC structure using the ALD method, oxide semiconductor 230c is sometimes epitaxially grown with oxide semiconductor 230b as the core. Therefore, when forming oxide semiconductor 230c, oxide semiconductor 230c sometimes includes a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed throughout oxide semiconductor 230c.

[0255] Next, a heat treatment process can be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c is sometimes improved. Furthermore, after deposition using the ALD method, when this region is only formed below the oxide semiconductor 230c, it sometimes extends upwards due to this heat treatment process. FIG. 10A to FIG. 10D In other words, by performing this heat treatment, regions with CAAC structures are sometimes formed throughout the oxide semiconductor 230c.

[0256] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a undergoes CAAC treatment via this heat treatment process. FIG. 10A to FIG. 10D CAAC formation is expected to readily occur using the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of oxide semiconductor 230b as a core or seed. The CAAC formation region in the oxide semiconductor 230a is preferably large, and preferably extends to the vicinity of layer 229.

[0257] Furthermore, since CAAC formation occurs from the upper to the lower portion of the oxide semiconductor 230a, it is not limited by the material or crystallinity of layer 229 and can reach the vicinity of layer 229. For example, even if layer 229 has an amorphous structure, a highly crystalline oxide semiconductor 230a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0258] Notice, FIG. 10A to FIG. 10D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention. Furthermore, FIG. 11A to FIG. 11D This can also be viewed as a schematic diagram illustrating a metal oxide deposition model of one aspect of the present invention. For example... FIG. 11A As shown, oxide semiconductors 230a and 230c respectively enhance their crystallinity by using highly crystallinity oxide semiconductor 230b as a core or seed. Specifically, the crystallinity of oxide semiconductor 230a is sometimes improved by heat treatment during or after the deposition of oxide semiconductor 230b. Furthermore, the crystallinity of oxide semiconductor 230c is sometimes improved by heat treatment during or after the deposition of oxide semiconductor 230c. Note that the aforementioned heat treatment plays an auxiliary role in improving crystallinity.

[0259] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductors 230a and 230c) can be improved by using a highly crystalline oxide semiconductor 230b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using oxide semiconductor 230b as a nucleus or seed to grow the upper and lower oxide semiconductors in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, i.e., the CAAC film, can be referred to as axially grown CAAC (AG CAAC). Note that... FIG. 11B The diagram shows a structure including oxide semiconductors 230a, 230b, and 230c, but is not limited thereto. For example, AG CAAC can also be formed in a structure including oxide semiconductors 230a and 230b.

[0260] In oxide semiconductor 230, regions with CAAC structures are preferably widely present throughout the entire layer. FIG. 11C The diagram shows a state where oxide semiconductors 230a, 230b, and 230c are all crystallized. In this state, sometimes the boundary between oxide semiconductors 230a and 230b is not observed. Furthermore, sometimes the boundary between oxide semiconductors 230b and 230c is not observed. Oxide semiconductor 230 can sometimes be described as a layer without a clearly observed interface. Oxide semiconductor 230 can sometimes be described as a single layer.

[0261] In addition, sometimes a portion of oxide semiconductor 230a or oxide semiconductor 230c is not crystallized. FIG. 11D The example shown illustrates the case where the oxide semiconductor 230a does not crystallize near the interface with layer 229. FIG. 12A This illustrates the case where the oxide semiconductor 230c does not crystallize near its surface. FIG. 12A This shows the case where the area near the interface between oxide semiconductor 230a and layer 229, as well as the area near the surface of oxide semiconductor 230c, is not crystallized.

[0262] By improving the crystallinity of the oxide semiconductor layer, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize transistors suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0263] In one embodiment of the present invention, the oxide semiconductor layer exhibits high overall crystallinity. Therefore, in oxide semiconductor 230, the boundaries between the stacked films in oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are sometimes not identified. In particular, after heat treatment, it is sometimes difficult to identify the boundaries between the stacked films. For example, cross-sectional TEM, cross-sectional STEM, etc., can be used to confirm the presence or absence of boundaries between the stacked films.

[0264] As described above, using metal oxides with a high In content ratio in transistors can improve the transistor's field-effect mobility. On the other hand, oxide semiconductors with a high In content ratio tend to polycrystalline. When using metal oxides with polycrystalline structures in transistors, it negatively impacts the transistor's initial characteristics or reliability. Therefore, by using oxide semiconductors with a high In content ratio in one or both of oxide semiconductors 230a and 230c, forming a crystal that reflects the orientation of the crystals contained in oxide semiconductor 230b, polycrystalline formation can be suppressed.

[0265] Furthermore, the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is preferably small. Therefore, oxide semiconductor 230a or oxide semiconductor 230c can form a crystal that reflects the orientation of the crystal contained in oxide semiconductor 230b. At this time, for example, when observing a cross-section of oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in oxide semiconductor 230a or oxide semiconductor 230c.

[0266] There are no particular restrictions on the crystal structure of oxide semiconductor 230a or oxide semiconductor 230c, provided that the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is small. The crystal structure of oxide semiconductor 230a or oxide semiconductor 230c can also be any of the cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal crystal systems.

[0267] [Composition of the oxide semiconductor layer]

[0268] As described above, the composition of the oxide semiconductor 230b is preferably suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed, for example, using a sputtering method. The oxide semiconductor 230b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be obtained. Furthermore, the oxide semiconductor 230b preferably contains element M in addition to zinc. By including element M in the oxide semiconductor 230b, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using the oxide semiconductor layer can be improved. Specifically, as an oxide semiconductor 230b, metal oxides with the following compositions can be used: In:M:Zn = 1:1:1 [atomic ratio] or similar, In:M:Zn = 1:1:1.2 [atomic ratio] or similar, In:M:Zn = 1:1:0.5 [atomic ratio] or similar, In:M:Zn = 1:1:2 [atomic ratio] or similar, In:M:Zn = 4:2:3 [atomic ratio] or similar, In:M:Zn = 1:3:2 [atomic ratio] or similar, In:M:Zn = 1:3:4 [atomic ratio] or similar. Note that "similar" includes a range of ±30% of the desired atomic ratio. Furthermore, one or more of gallium, aluminum, and tin are preferably used as element M.

[0269] The oxide semiconductor 230b may also not contain element M. For example, In-Zn oxide may be used. Specifically, it may be an In:Zn composition of 1:1 (atomic ratio) or near, In:Zn composition of 2:1 (atomic ratio) or near, or In:Zn composition of 4:1 (atomic ratio) or near. Alternatively, indium oxide may be used. Furthermore, it may contain trace amounts of element M. For example, it may be an In:Ga:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Ga:Zn composition of 2:0.1:1 (atomic ratio) or near. Additionally, it may be an In:Sn:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Sn:Zn composition of 2:0.1:1 (atomic ratio) or near.

[0270] Oxide semiconductors 230a and 230c can use metal oxides with a high In content. Oxide semiconductors 230a and 230c can be formed, for example, using the ALD method. Furthermore, metal oxides with a higher In content than element M are particularly preferred. By using metal oxides with a high In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics improved.

[0271] Alternatively, oxide semiconductors 230a and 230c may not contain element M. For example, In-Zn oxide may also be used. Specifically, it may be an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide may also be used. Furthermore, oxide semiconductors 230a and 230c may also contain trace amounts of element M. Specifically, it may be an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0272] Furthermore, increasing the zinc content of the oxide semiconductor can improve its crystallinity. In particular, the oxide semiconductor 230a preferably contains zinc. For example, when the oxide semiconductor 230a is formed using the ALD method and the oxide semiconductor 230b is formed using sputtering, sometimes the zinc contained in the oxide semiconductor 230a diffuses into the oxide semiconductor 230b. Note that this diffusion occurs due to heat treatment during or after sputtering. Improved crystallinity can be expected due to the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b. Alternatively, lateral growth of c-axis oriented crystal portions can be expected due to the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b, thereby promoting CAAC formation.

[0273] Furthermore, oxide semiconductors 230a and 230c can use metal oxides with a higher proportion of In than oxide semiconductor 230b.

[0274] Furthermore, for example, metal oxides with a higher Ga content than oxide semiconductor 230b can be used as oxide semiconductors 230a and 230c. For example, oxide semiconductors 230a and 230c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga content, the band gap of oxide semiconductors 230a and 230c can sometimes be made larger than that of oxide semiconductor 230b. Thus, oxide semiconductor 230b is sandwiched between oxide semiconductors 230a and 230c with larger band gaps, and oxide semiconductor 230b primarily serves as a current path (channel). By sandwiching oxide semiconductor 230b between oxide semiconductors 230a and 230c, the trap energy levels at and near the interface of oxide semiconductor 230b can be reduced. This allows for the creation of buried-channel transistors with the channel located far from the insulating layer interface, thereby improving field-effect mobility.

[0275] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the oxide semiconductors 230a and 230c employ a composition that makes it difficult to form a CAAC structure when forming a monolayer, the entire oxide semiconductor layer including oxide semiconductors 230a and 230c can have a CAAC structure by crystal growth with oxide semiconductor 230b as the nucleus. Alternatively, regions including at least a portion of each of oxide semiconductors 230a and 230c extending to the region of oxide semiconductor 230b can have a CAAC structure.

[0276] In particular, when the oxide semiconductors 230a and 230c employ a high In ratio, a crystallinity suitable for transistors can be obtained. In one embodiment of the oxide semiconductor layer of the present invention, while increasing the In ratio to improve the transistor's turn-on characteristics, reliability can be improved by employing a highly crystallinity CAAC structure.

[0277] Note that the composition of oxide semiconductor 230a can also be different from that of oxide semiconductor 230c.

[0278] In addition, oxide semiconductors 230a and 230c can also use metal oxides with the same composition as oxide semiconductor 230b.

[0279] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0280] The composition of the metal oxides used in oxide semiconductor 230 can be analyzed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content ratio of elements with low abundance ratios may differ from the analytically obtained ratio due to the limitations of analytical precision. For example, when the abundance ratio of element M is low, the analytically obtained content ratio of element M may sometimes be lower than the actual content ratio.

[0281] [c-axis orientation]

[0282] One embodiment of the present invention has an oxide semiconductor layer with a CAAC structure. For example, crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0283] Crystal orientation can be obtained from TEM images by performing a Fast Fourier Transform (FFT). Specifically, the crystal axis orientation can be obtained from the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal lattice space information as the electron diffraction pattern.

[0284] By performing FFT processing on each region within a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region over a certain area, a map showing the crystal orientation can be formed. Specifically, two high-intensity spots are observed in the FFT pattern of a region with layered crystals. The crystal axis orientation of this region can be obtained from the angle of the line segment connecting these two spots.

[0285] The degree of c-axis orientation can be calculated by determining the proportion of the c-axis orientation region in a diagram showing crystal orientation. Note that here, the c-axis orientation region refers to the region whose orientation coincides with the c-axis and whose difference from the c-axis is within 20°.

[0286] In one embodiment of the present invention, the c-axis orientation rate can be calculated, for example, by performing cross-sectional or planar TEM observation of the oxide semiconductor layer. Furthermore, the region for performing the FFT (also called the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0287] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation is preferably 60% or more, more preferably 70% or more, even more preferably 80% or more, even more preferably 90% or more, and still more preferably 95% or more.

[0288] Furthermore, the c-axis orientation degrees of the regions deposited as oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are preferably 60% or more, more preferably 70% or more, further preferably 80% or more, even more preferably 90% or more, and still more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0289] Note that sometimes the boundaries of oxide semiconductors 230a, 230b and 230c are not clearly observed after the oxide semiconductor 230 is manufactured.

[0290] In one embodiment of the present invention, the oxide semiconductor 230 can be sequentially divided into three regions—a first region, a second region, and a third region—from one side of layer 229. Each region is a layered region.

[0291] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation degree of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation degree of the second region is preferably higher than that of the first region. Moreover, the c-axis orientation degree of both the second and third regions is preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0292] The first region is located on the top surface of the delamination layer 229 at a distance of 0 nm to 3 nm, and the third region is located on the top surface of the delamination oxide semiconductor 230 at a distance of 0 nm to 3 nm.

[0293] Alternatively, the thickness of the layers in each region may be approximately the same.

[0294] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0295] (Implementation Method 4)

[0296] In this embodiment, electronic components, electronic devices, and mainframe computers that can be used with the semiconductor devices described in the above embodiments are explained. Electronic components, electronic devices, and mainframe computers using a semiconductor device according to one aspect of the present invention are highly effective in achieving high performance, such as low power consumption.

[0297] [Electronic Components]

[0298] FIG. 12A A perspective view of a substrate (circuit board 704) on which electronic components 709 are mounted is shown. FIG. 12B The electronic component 709 shown includes a semiconductor device 710 within the mold 711. FIG. 12B In this description, a portion of the electronic component 709 is omitted to indicate its internal structure. The electronic component 709 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is electrically connected to an electrode pad 713, which is electrically connected to a semiconductor device 710 via a lead 714. The electronic component 709 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702, a circuit board 704 is completed.

[0299] Furthermore, the semiconductor device 710 includes a layer 715 with a computing core and a layer 716 with memory. The memory layer 716 has a structure with multiple memory cell arrays stacked on top of each other. The stacked structure of the computing core layer 715 and the memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or direct Cu-Cu bonding technologies. When using a monolithic stacked structure of the computing core layer 715 and the memory layer 716, for example, a so-called on-chip memory structure, where memory is directly formed on the processor, can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0300] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to through-electrode techniques such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0301] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in layer 716 with memory, stacking these multiple memory cell arrays monolithically. When multiple memory cell arrays are stacked monolithically, one or both of memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in layer 716 with memory, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0302] Furthermore, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0303] then, FIG. 13A to FIG. 13D A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are disposed on the interposer 731.

[0304] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0305] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is electrically connected to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0306] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0307] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0308] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set the required wiring to achieve a wider memory bandwidth. Thus, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can also be used.

[0309] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the insert 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0310] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. FIG. 12A An example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0311] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0312] FIG. 12B This is an explanation of the above. FIG. 13A to FIG. 13D and FIG. 13A The diagram shows different structural examples of electronic components 709 and 730. FIG. 13A The electronic components 730A to 730D shown have a structure in which a layer 715 with a computing core and a layer 716 with a memory are disposed on a plate 731 on which the electrodes 733 are provided.

[0313] exist FIG. 13B In the structure of the electronic component 730A shown, a layer 715 with a processing core is disposed on a plug-in board 731 and connected to electrode pads (not shown) via leads 714. A memory layer 716 formed on the processing core layer 715 has the above-described monolithic stacked structure. In the monolithic stacked structure, the memory layer 716 is electrically connected to the processing core layer 715. Therefore, since the leads 714 between the plug-in board 731 and the processing core layer 715 can also serve as wiring between the memory layers 716 of each layer and the plug-in board 731, the number of leads can be reduced.

[0314] Note that in FIG. 13A The structural example illustrates a single monolithic stacked structure, but it's also possible to use a structure where monolithic stacked electronic components overlap with other electronic components. For example, as... FIG. 13C As shown in the electronic component 730B, multiple layers 716A (containing memory) and 715A (containing processing core), as well as layers 716B (containing memory) and 715B (containing processing core) forming a monolithic stacked structure, can also be stacked. The monolithic stacked structure, overlapping with other electronic components, has a structure fixed to a resin sheet 744 by an adhesive layer 743. By employing this structure, it is possible to realize a structure that stacks multiple memory cell arrays with different circuit structures. By having different circuit structures, semiconductor devices with different memory bandwidths and memory access delays can be realized, and this is preferably applied to structures with layered structures, such as cache memories.

[0315] also, FIG. 13C Structural examples can be stacked with other electronic components. For example, such as... FIG. 13D As shown in the electronic component 730C, an electronic component 730C can be adopted in which the aforementioned electronic component 730A and an electronic component including a processor or other processing core with a layer 715C are stacked and disposed within a mold 711 between insert plates 731A and 731B. The circuit layers can be connected by conductive materials such as electrodes 733. By adopting this structure, high-speed operation of the interface between the processor and the memory can be achieved. Furthermore, a gap (space) can be provided between the mold including the processing core layer 715C and the mold of the electronic component 730A, thereby preventing heat generated in the processing core layer 715C from easily being transferred to the electronic component 730A.

[0316] In addition, FIG. 14A In the structural examples, a structure can also be adopted where a memory layer including OS transistors is set on the 715C layer, which includes the processing core such as the processor. For example, as... FIG. 14B As shown in the electronic component 730D, a memory layer 716C can be disposed on the layer 715C having the computing core and stacked with the electronic component 730A. By adopting this structure, high-speed operation of the interface portion between the so-called on-chip memory structure, in which memory is directly formed on the processor, and the structure of the semiconductor device including the stacked memory layers can be achieved.

[0317] [Electronic Devices]

[0318] FIG. 15A This is an external image showing an example of a portable electronic device. FIG. 15B This is a simplified diagram of data delivery within a portable electronic device. The portable electronic device 595 includes a printed circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0319] In the portable electronic device 595, the aforementioned electronic component 709 can be mounted on the printed circuit board 596. By utilizing the electronic component 709, the portable electronic device 595 can process and analyze multiple data obtained through the speaker 597, camera 598, microphone 599, etc., thereby improving user convenience. Furthermore, it can also be used for systems such as voice guidance and image retrieval.

[0320] In electronic component 709, the obtained image data is processed by neural network operations, such as image resolution, image noise reduction, face recognition (for security purposes), object recognition (for autonomous driving purposes), image compression, image correction (wide dynamic range), image restoration of lensless image sensors, position alignment, text recognition, and reduction of reflected glare.

[0321] FIG. 15C The portable game console 1100 shown includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connector 1105, and operation keys 1107. Housings 1101, 1102, and 1103 are detachable. By mounting the connector 1105 provided on housing 1101 to housing 1108, the image output to display unit 1104 can be output to other video display devices. Alternatively, by mounting housings 1102 and 1103 to housing 1109, housings 1102 and 1103 can be integrated and used as an operation unit. The aforementioned electronic components 709 can be assembled onto chips or the like on the substrates of housings 1102 and 1103.

[0322] FIG. 16 This is a USB-connected, strip-shaped electronic device 1120. The electronic device 1120 includes a housing 1121, a cover 1122, a USB connector 1123, and a substrate 1124. The substrate 1124 is housed within the housing 1121. For example, a memory chip 1125 and a control chip 1126 are mounted on the substrate 1124. The aforementioned electronic components 709 can be assembled onto the controller chip 1126, etc., on the substrate 1124.

[0323] ​ It is a humanoid robot 1130. Robot 1130 includes sensors 2101 to 2106 and control circuit 2110. For example, the aforementioned electronic component 709 can be assembled into the control circuit 2110.

[0324] [Mainframe Computer]

[0325] The aforementioned electronic component 709 can be used in a system 3000 that includes a large computer that communicates with the electronic device, without being housed within the electronic device. In this case, the computing system is composed of the electronic device and the large computer. ​ This shows a structural example of System 3000.

[0326] System 3000 consists of electronic device 3001 and mainframe computer 3002. Communication between electronic device 3001 and mainframe computer 3002 can be carried out via Internet cable 3003.

[0327] The mainframe computer 3002 has multiple racks 3004. Multiple substrates 3005 are arranged on these racks, and the electronic components 709 described in the above embodiments can be mounted on these substrates 3005. Thus, a neural network is formed in the mainframe computer 3002. Furthermore, the mainframe computer 3002 can perform neural network operations using data input from the electronic device 3001 via the Internet cable 3003. The operation results of the mainframe computer 3002 can be transmitted to the electronic device 3001 via the Internet cable 3003 as needed. This reduces the computational burden on the electronic device 3001.

[0328] This embodiment can be appropriately combined with descriptions of other embodiments.

[0329] Additional notes regarding the contents of this instruction manual, etc.

[0330] Below, additional notes are added to the descriptions of the above embodiments and the structures in those embodiments.

[0331] The structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments to constitute a mode of the present invention. Furthermore, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0332] Furthermore, the content (or a portion thereof) described in one embodiment may be applied, combined, or replaced with other content (or a portion thereof) described in that embodiment and / or content (or a portion thereof) described in one or more other embodiments.

[0333] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0334] Furthermore, more drawings can be formed by combining the drawings (or a portion thereof) shown in one embodiment with other portions of the drawings, other drawings (or a portion thereof) shown in that embodiment, and / or drawings (or a portion thereof) shown in one or more other embodiments.

[0335] In this specification, components are categorized according to function and represented by independent boxes in block diagrams. However, in actual circuits, it is difficult to categorize components according to function; sometimes a circuit involves multiple functions or multiple circuits involve a single function. Therefore, the division of boxes in block diagrams is not limited to the components described in the specification and may vary appropriately depending on the circumstances.

[0336] Furthermore, in the accompanying drawings, sizes, layer thicknesses, or areas are arbitrarily shown for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Note that the drawings are schematic for clarity and are not limited to the shapes or values ​​shown. For example, non-uniformity of signals, voltages, or currents caused by noise or timing deviations may be included.

[0337] In this specification and other documents, when describing the connection relationships of transistors, the terms "one of the source and drain" (or the first electrode or the first terminal) and "the other of the source and drain" (or the second electrode or the second terminal) are used. This is because the source and drain of a transistor are interchangeable depending on the transistor's structure or operating conditions. Note that, depending on the circumstances, the source and drain of a transistor may be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0338] Furthermore, in this specification and other documents, the terms "electrode" and "wiring" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Moreover, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0339] Furthermore, voltage and potential can be interchanged appropriately in this instruction manual and other documents. Voltage refers to the potential difference between the voltage and a reference potential. For example, when the reference potential is ground voltage (grounding voltage), voltage can be referred to as potential. Grounding potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc., sometimes varies depending on the reference potential.

[0340] In this instruction manual and other documents, the terms "film" and "layer" may be interchanged depending on the circumstances. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0341] In this specification and the like, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches the current path.

[0342] In this specification, for example, the channel length of a planar transistor refers to the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate overlap or the region forming the channel in a planar view of the transistor.

[0343] In this specification, for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap, or the length of the portion of the region in which the source and drain electrodes of the channel are opposite each other.

[0344] Furthermore, in this specification and other materials, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, impurity regions, etc., depending on the circuit structure, device structure, etc. Additionally, terminals, wiring, etc., may also be referred to as nodes.

[0345] In this specification, "A connected to B" means that A and B are electrically connected. Here, "A connected to B" refers to a connection where an object (a switch, transistor, diode, or other component, or a circuit including such an object and wiring) exists between A and B, allowing the transmission of electrical signals between them. Note that the case of an electrical connection between A and B includes the case of a direct connection between A and B. Here, a direct connection between A and B means a connection where A and B can transmit electrical signals between them through wiring (or electrodes) without passing through the aforementioned object. In other words, a direct connection is a connection that can be considered as the same circuit diagram when represented using equivalent circuits.

[0346] [Symbol Explanation]

[0347] BGL: Electrode; BSD: Electrode; GE: Electrode; LE: Electrode; MT: Transistor; TGE: Electrode; TSD: Electrode; VDD: Voltage; VT: Transistor; 10: Semiconductor Device; 20: Component Layer; 30: Component Layer; 100: Signal Processing Circuit

Claims

1. A semiconductor device, comprising: First transistor; Capacitor; as well as Second transistor, The first transistor includes a silicon layer having a channel formation region. The capacitor includes a first electrode and a second electrode. The second transistor includes an oxide semiconductor layer having a channel formation region. The first electrode is electrically connected to the first gate electrode of the first transistor. The second electrode is electrically connected to one of the source and drain electrodes of the second transistor. The first electrode is disposed along the side and bottom of the first opening in the first insulating layer disposed on the first gate electrode. The oxide semiconductor layer is disposed along the side and bottom of the second opening in the second insulating layer disposed on the second electrode. Furthermore, the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions.

2. The semiconductor device according to claim 1, The second transistor comprises a source electrode and a drain electrode, the other of which is disposed on the upper layer of the first electrode, separated by the second insulating layer.

3. The semiconductor device according to claim 1, The silicon layer is disposed on a substrate containing monocrystalline silicon. Furthermore, the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions in a direction perpendicular to the surface of the substrate.

4. The semiconductor device according to claim 3, The second transistor includes a second gate electrode. Furthermore, the second gate electrode has a region that overlaps with the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer in a direction perpendicular to the surface of the substrate.

5. The semiconductor device according to claim 1, The capacitor is disposed on the upper layer of the first transistor. The second transistor is disposed on the upper layer of the capacitor. Furthermore, the first transistor, the capacitor, and the second transistor have overlapping regions.

6. The semiconductor device according to claim 1, The first electrode is directly connected to the gate electrode of the first transistor.

7. The semiconductor device according to claim 1, The oxide semiconductor layer contains at least In.

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