Semiconductor device and method for manufacturing semiconductor device

Abstract

A micro-sized transistor is provided. A normally off transistor is provided. The semiconductor device includes an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer on the first conductive layer, and a second insulating layer on the first insulating layer, the oxide semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the second conductive layer, and a side surface of the first insulating layer, the second insulating layer is located on the oxide semiconductor layer, and the third conductive layer is located on the second insulating layer and overlaps the oxide semiconductor layer via the second insulating layer. The first insulating layer has a first region in contact with the oxide semiconductor layer, and the first region contains a halogen element.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device, a memory device, a display device, and an electronic device. Further, one embodiment of the present application relates to a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present application is not limited to the above technical field. As one example of a technical field to which one embodiment of the present application pertains, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof can be given.

[0003] Note that in this specification and the like, a semiconductor device generally means a device that utilizes semiconductor characteristics, and includes a circuit including a semiconductor element (a transistor, a diode, a photodiode, and the like) and a device including the circuit. Further, a semiconductor device means all devices that can function by utilizing semiconductor characteristics. For example, as examples of a semiconductor device, integrated circuits, chips including integrated circuits, electronic components in which chips are mounted in packages can be given. In addition, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, and the like themselves or parts of the above devices are sometimes semiconductor devices or include semiconductor devices. BACKGROUND

[0004] In recent years, semiconductor devices have been developed, and LSIs, CPUs, memories, and the like are mainly used for semiconductor devices. A CPU is a collection of semiconductor integrated circuits (at least including transistors and memories) and semiconductor elements formed with electrodes as connection terminals, which are processed from semiconductor wafers to form chips.

[0005] Semiconductor circuits (IC chips) of LSIs, CPUs, memories, and the like are mounted on circuit boards such as printed wiring boards and are used as one of components of various electronic devices.

[0006] Further, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs), display devices, and the like. As a semiconductor material applicable to the transistor, a silicon-based semiconductor material is widely known, and an oxide semiconductor is attracting attention as another material.

[0007] Further, it is known that a transistor using an oxide semiconductor has extremely small off-state current. For example, Patent Document 1 has disclosed a low-power CPU and the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor. Further, for example, Patent Document 2 has disclosed a memory device and the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor to achieve long-term retention of stored contents.

[0008] Further, in recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integration of integrated circuits has increased. Further, there is a demand for increasing the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which a plurality of memory cells are provided in a stacked manner by using a first transistor including an oxide semiconductor film and a second transistor including an oxide semiconductor film, whereby high-density integration of integrated circuits is achieved. Further, Patent Document 4 discloses a technique in which channels of transistors including oxide semiconductor films are arranged in a vertical direction, whereby high-density integration of integrated circuits is achieved.

[0009] [Prior Art Documents]

[0010] [Patent Documents]

[0011] [Patent Document 1] Japanese Published Patent Application No. 2012-257187

[0012] [Patent Document 2] Japanese Published Patent Application No. 2011-151383

[0013] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0014] [Patent Document 4] Japanese Published Patent Application No. 2013-211537

[0015] [Non-Patent Documents]

[0016] [Non-Patent Document 1] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72 nm”, IEDM Tech. Dig., 2019, pp. 50-53 SUMMARY

[0017] PROBLEMS TO BE SOLVED BY THE INVENTION

[0018] One of objects of one embodiment of the present application is to provide a transistor with small parasitic capacitance. Further, one of objects of one embodiment of the present application is to provide a transistor with good electric characteristics. Further, one of objects of one embodiment of the present application is to provide a transistor with large on-state current. Further, one of objects of one embodiment of the present application is to provide a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. Further, one of objects of one embodiment of the present application is to provide a display device with high definition or high aperture ratio. Further, one of objects of one embodiment of the present application is to provide a transistor, a semiconductor device, a display device, or a memory device with high reliability. Further, one of objects of one embodiment of the present application is to provide a semiconductor device, a display device, or a memory device with low power consumption. Further, one of objects of one embodiment of the present application is to provide a memory device with high operation speed. Further, one of objects of one embodiment of the present application is to provide a method for manufacturing the above transistor, semiconductor device, display device, or memory device.

[0019] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all the above objects. Further, objects other than the above can be extracted from the description, drawings, and claims.

[0020] Means for solving the technical problem

[0021] One embodiment of the present application is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer is positioned over the first conductive layer, the second conductive layer is positioned over the first insulating layer, the oxide semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the second conductive layer, and a side surface of the first insulating layer, the second insulating layer is positioned over the oxide semiconductor layer, the third conductive layer is positioned over the second insulating layer and overlaps with the oxide semiconductor layer with the second insulating layer interposed therebetween, and the first insulating layer has a first region in contact with the oxide semiconductor layer, and the first region contains a halogen element.

[0022] Further, one embodiment of the present application is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer, the first insulating layer is positioned over the first conductive layer, the second conductive layer is positioned over the first insulating layer, the first insulating layer and the second insulating layer include a first opening portion reaching the first conductive layer, the oxide semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the second conductive layer, and a side surface of the first insulating layer in the first opening portion, the second insulating layer is positioned over the oxide semiconductor layer in the first opening portion, the third conductive layer overlaps with the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion, the first insulating layer has a first region in contact with the oxide semiconductor layer, and the first region contains a halogen element.

[0023] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and is more preferably chlorine or fluorine.

[0024] It is preferable that the oxide semiconductor layer have a second region in contact with a top surface of the first conductive layer and a third region in contact with a top surface of the second conductive layer, the second region and the third region contain a first element, and the first element is boron or phosphorus.

[0025] Further, one embodiment of the present application is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first insulating layer is positioned over the first conductive layer, the second conductive layer is positioned over the first insulating layer, the first insulating layer and the second insulating layer include a first opening portion reaching the first conductive layer, the oxide semiconductor layer is in contact with a top surface of the second conductive layer and is in contact with a top surface of the first conductive layer, a side surface of the second conductive layer, and a side surface of the first insulating layer in the first opening portion, the second insulating layer has a portion overlapping with the top surface of the second conductive layer with the oxide semiconductor layer interposed therebetween and a portion positioned over the oxide semiconductor layer in the first opening portion, the third insulating layer is positioned over the second insulating layer and includes a second opening portion reaching the second insulating layer at a position overlapping with the first opening portion, the fourth insulating layer is in contact with a side surface of the third insulating layer in the second opening portion and overlaps with the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion, and the third conductive layer is positioned over the fourth insulating layer and overlaps with the oxide semiconductor layer with the second insulating layer and the fourth insulating layer interposed therebetween in the first opening portion.

[0026] In a cross-sectional view, a maximum value of a width of the third conductive layer in the second opening portion is preferably smaller than a minimum value of a width of the first opening portion in the second conductive layer.

[0027] The semiconductor device of the above structure preferably includes the first insulating layer over the fifth insulating layer. It is preferable that side surfaces in the first opening portion of the first insulating layer have a first surface and a second surface above the first surface, and that the angle formed by the first surface and the top surface of the fifth insulating layer be smaller than the angle formed by the second surface and the top surface of the fifth insulating layer in a cross-sectional view. Further, it is preferable that the first insulating layer include a first layer and a second layer over the first layer, and that the angle formed by the side surfaces in the first opening portion of the first layer and the top surface of the fifth insulating layer be smaller than the angle formed by the side surfaces in the first opening portion of the second layer and the top surface of the fifth insulating layer in a cross-sectional view.

[0028] The region of the first conductive layer which is in contact with the oxide semiconductor layer preferably has a portion where the thickness is smaller than that of the region in contact with the first insulating layer.

[0029] The angle formed by the side surfaces in the first opening portion of the first insulating layer and the top surface of the fifth insulating layer is preferably greater than or equal to 65 degrees and less than or equal to 90 degrees.

[0030] The maximum value of the width of the second opening portion in a cross-sectional view is preferably smaller than the minimum value of the width of the first opening portion in the second conductive layer.

[0031] The third conductive layer preferably overlaps with the top surface of the third insulating layer with the fourth insulating layer interposed therebetween.

[0032] The semiconductor device of the above structure preferably includes the fourth conductive layer. The fourth conductive layer preferably makes contact with the top surface of the third insulating layer, the top surface of the fourth insulating layer, and the top surface of the third conductive layer.

[0033] The semiconductor device of the above structure preferably includes the fifth conductive layer. It is preferable that the first insulating layer include a first layer and a second layer over the first layer, that the fifth conductive layer be positioned over the first layer, that the second layer cover the top surface and the side surfaces of the fifth conductive layer, and that the oxide semiconductor layer have a region overlapping with the fifth conductive layer with the second layer interposed therebetween and overlapping with the third conductive layer with the second insulating layer and the fourth insulating layer interposed therebetween in a cross-sectional view.

[0034] The maximum value of the width of the first conductive layer in a direction perpendicular to the direction in which the first conductive layer extends is preferably smaller than the minimum value of the width of the first opening portion in the second conductive layer.

[0035] It is preferable that the first insulating layer have a first region in contact with the oxide semiconductor layer, and that the first region contain a halogen element. The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and is more preferably chlorine or fluorine.

[0036] It is preferable that the oxide semiconductor layer have a second region in contact with the top surface of the first conductive layer and a third region in contact with the top surface of the second conductive layer, that the second region and the third region contain a first element, and that the first element be boron or phosphorus.

[0037] One embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of: forming a first conductive layer over a substrate; forming a first insulating film over the first conductive layer; forming a second conductive layer including a first opening portion in a region overlapping with the first conductive layer over the first insulating film; processing the first insulating film to form a first insulating layer including a second opening portion reaching the first conductive layer; supplying a halogen element to a side surface in the second opening portion of the first insulating layer; forming an oxide semiconductor layer in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer; forming a second insulating layer over the oxide semiconductor layer; forming a third insulating layer including a third opening portion in a region overlapping with the first opening portion and the second opening portion over the second insulating layer; forming a fourth insulating layer over the third insulating layer; forming a third conductive layer over the fourth insulating layer; processing the third conductive layer and the fourth insulating layer by a chemical mechanical polishing method to expose a top surface of the third insulating layer; and forming a fourth conductive layer over the third insulating layer, the fourth insulating layer, and the third conductive layer.

[0038] It is preferable to supply the first element to the oxide semiconductor layer after the oxide semiconductor layer is formed and before the second insulating layer is formed. Further, it is preferable to supply the first element to the top surface of the first conductive layer and the top surface of the second conductive layer after the first insulating layer is formed and before the oxide semiconductor layer is formed. Further, it is preferable that a second insulating film be formed over the second insulating layer, the first element be supplied to the oxide semiconductor layer through the second insulating film, and the second insulating film be processed after the first element is supplied to form the second insulating layer. The first element is preferably boron or phosphorus. Further, the first element is preferably supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate.

[0039] Effects of Invention

[0040] According to one embodiment of the present application, a transistor with small parasitic capacitance can be provided. Further, according to one embodiment of the present application, a transistor with high electric characteristics can be provided. Further, according to one embodiment of the present application, a transistor with high on-state current can be provided. Further, according to one embodiment of the present application, a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated can be provided. Further, according to one embodiment of the present application, a display device with high definition or high aperture ratio can be provided. Further, according to one embodiment of the present application, a transistor, a semiconductor device, a display device, or a memory device with high reliability can be provided. Further, according to one embodiment of the present application, a semiconductor device, a display device, or a memory device with low power consumption can be provided. Further, according to one embodiment of the present application, a memory device with high operation speed can be provided. Further, according to one embodiment of the present application, a method for manufacturing the above transistor, semiconductor device, display device, or memory device can be provided.

[0041] Note that the description is not limiting to the effects. One embodiment of the present application does not necessarily have all the effects described above. In addition, an effect other than those described above can be extracted from the description, drawings, or claims. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1A is a plan view of one embodiment of a semiconductor device. FIGS. 1B-1D is a cross-sectional view of one embodiment of a semiconductor device.

[0043] FIG. 2A and FIG. 2B is a cross-sectional view of one embodiment of a semiconductor device.

[0044] FIGS. 3A-3C is a cross-sectional view of one embodiment of a semiconductor device.

[0045] FIGS. 4A-4C is a cross-sectional view of one embodiment of a semiconductor device.

[0046] FIGS. 5A-5D is a cross-sectional view of one embodiment of a semiconductor device.

[0047] FIG. 6A and FIG. 6B is a cross-sectional view of one embodiment of a semiconductor device.

[0048] FIG. 7A is a plan view of one embodiment of a semiconductor device. FIGS. 7B-7D is a cross-sectional view of one embodiment of a semiconductor device.

[0049] FIG. 8A is a plan view of one embodiment of a semiconductor device. FIGS. 8B-8D is a cross-sectional view of one embodiment of a semiconductor device.

[0050] FIGS. 9A-9D is a cross-sectional view of one embodiment of a semiconductor device.

[0051] FIG. 10A is a plan view of one embodiment of a semiconductor device. FIG. 10B and FIG. 10C is a cross-sectional view of one embodiment of a semiconductor device.

[0052] FIG. 11A is a plan view of one embodiment of a semiconductor device. FIGS. 11B-11E is a cross-sectional view of one embodiment of a semiconductor device.

[0053] FIGS. 12A-12D is a cross-sectional view of one embodiment of a semiconductor device.

[0054] FIGS. 13A-13F is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0055] FIGS. 14A-14D is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0056] FIGS. 15A-15D is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0057] FIGS. 16A-16C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0058] FIGS. 17A-17E is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0059] FIG. 18A is a plan view showing one example of a memory device. FIG. 18B and FIG. 18C is a cross-sectional view showing one example of a memory device.

[0060] FIG. 19A is a plan view showing one example of a memory device. FIG. 19B is a cross-sectional view showing one example of a memory device.

[0061] FIG. 20 is a cross-sectional view showing one example of a memory device.

[0062] FIG. 21 is a cross-sectional view showing one example of a memory device.

[0063] FIG. 22 is a block diagram showing one example of a structure of a semiconductor device.

[0064] FIGS. 23A-23H is a diagram showing one example of a circuit structure of a memory cell.

[0065] FIG. 24A and FIG. 24B is a perspective view showing one example of a structure of a semiconductor device.

[0066] FIG. 25 is a block diagram showing a CPU.

[0067] FIG. 26A and FIG. 26B is a perspective view of a semiconductor device.

[0068] FIG. 27A and FIG. 27B is a perspective view of a semiconductor device.

[0069] FIG. 28A andFIG. 28B is a diagram in which various storage devices are shown in tiers.

[0070] FIG. 29A and FIG. 29B is a perspective view showing one example of a display device.

[0071] FIG. 30 is a cross-sectional view showing one example of a display device.

[0072] FIG. 31 is a cross-sectional view showing one example of a display device.

[0073] FIGS. 32A-32C is a diagram showing a structure example of a display device.

[0074] FIG. 33A and FIG. 33B is a diagram showing one example of an electronic component.

[0075] FIGS. 34A-34C is a diagram showing one example of a large computer. FIG. 34D is a diagram showing one example of a space device. FIG. 34E is a diagram showing one example of a storage system which can be used for a data center.

[0076] FIGS. 35A-35F is a diagram showing one example of an electronic device.

[0077] FIGS. 36A-36G is a diagram showing one example of an electronic device.

[0078] FIGS. 37A-37F is a diagram showing one example of an electronic device.

[0079] Embodiment of Invention

[0080] Embodiments are described in detail with reference to the accompanying drawings. Note that the present application is not limited to the following description, and it is readily apparent to those skilled in the art that the present application can be carried out in various changes and modifications of the embodiments. Therefore, the present application is not to be restricted to the following given embodiment but to include all modifications within the scope and equivalent thereof.

[0081] Note that, in the structure of the present application described below, the same reference numerals are used for the same parts or parts having the same function throughout the different drawings, and repeated description is omitted. Further, the same hatching line is used when indicating parts having the same function, and a sign is not particularly added.

[0082] Further, in some cases, the positions, sizes, ranges, and the like of the respective components shown in the drawings are not necessarily to scale and are presented for purposes of convenience and for clarity. Thus, the disclosed application should not necessarily be limited to the specific positions, sizes, ranges, and the like of the components disclosed in the drawings.

[0083] Note that in this specification and the like, the terms "first", "second", and "third" are used, and so on to simply distinguish between objects having the same name and not to describe a sequence for or amounts of the objects. In addition, terms such as "first", "second", and "third" are not used in a limiting sense and do not denote or imply a relationship between the elements to which "first", "second", "third", or the like are applied and / or the relative position or order of the elements to which "first", "second", "third", or the like are applied and / or the relative importance of the elements to which "first", "second", "third", or the like are applied.

[0084] A transistor is one of semiconductor elements, and functions such as amplification of current or voltage, switching operation of on or off, and the like can be implemented. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0085] In this specification and the like, a transistor in which an oxide semiconductor or a metal oxide is used for a semiconductor layer and a transistor including an oxide semiconductor or a metal oxide in a channel formation region is referred to as an OS transistor. Further, a transistor including silicon in a channel formation region is referred to as an Si transistor.

[0086] In this specification and the like, a transistor refers to an element including at least a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) in which a channel is formed between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region where a current flows.

[0087] Further, the functions of the "source" and the "drain" are sometimes replaced with each other in this specification and the like. Therefore, the "source" and the "drain" in this specification can be replaced with each other.

[0088] Note that an impurity of a semiconductor refers to, for example, an element other than the main component of a semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, for example, an increase in the defect density of a semiconductor or a decrease in crystallinity or the like is sometimes caused. When a semiconductor is an oxide semiconductor, as an impurity which changes the characteristics of a semiconductor, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor are given. Specifically, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given. In addition, water sometimes functions as an impurity. Furthermore, for example, the formation of an oxygen vacancy (also referred to as V O ) in an oxide semiconductor is sometimes caused by the mixture of an impurity.

[0089] Note that in this specification and the like, an oxynitride refers to a material whose composition contains oxygen more than nitrogen. A nitride oxide refers to a material whose composition contains nitrogen more than oxygen.

[0090] The content of elements such as hydrogen, oxygen, carbon, and nitrogen in a film can be analyzed by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS), for example. XPS is suitable when the content of a target element is high (e.g., 0.5 atomic % or more or 1 atomic % or more). On the other hand, SIMS is suitable when the content of a target element is low (e.g., 0.5 atomic % or less or 1 atomic % or less). When the contents of elements are compared, it is more preferable to perform composite analysis using both SIMS and XPS analysis techniques.

[0091] Note that "film" and "layer" can be interchanged with each other depending on the situation or state, for example. For example, a "conductive layer" can be changed into a "conductive film". Furthermore, an "insulating film" can be changed into an "insulating layer".

[0092] In this specification and the like, "parallel" indicates a state in which two straight lines are arranged at an angle of greater than or equal to -10 degrees and less than or equal to 10 degrees. Thus, the angle is also included in a range of greater than or equal to -5 degrees and less than or equal to 5 degrees. In addition, "substantially parallel" indicates a state in which two straight lines are arranged at an angle of greater than or equal to -30 degrees and less than or equal to 30 degrees. Furthermore, "perpendicular" indicates a state in which two straight lines are arranged at an angle of greater than or equal to 80 degrees and less than or equal to 100 degrees. Thus, the angle is also included in a range of greater than or equal to 85 degrees and less than or equal to 95 degrees. In addition, "substantially perpendicular" indicates a state in which two straight lines are arranged at an angle of greater than or equal to 60 degrees and less than or equal to 120 degrees.

[0093] In this specification and the like, "electrically connected" includes the case where "an element having some kind of function" is connected. Here, "an element having some kind of function" is not particularly limited as long as it can receive and transmit an electric signal between connection objects. For example, "an element having some kind of function" includes a switching element such as a transistor, a resistor, a coil, an element having another function, and the like in addition to an electrode or a wiring.

[0094] In this specification and the like, in the case where there is no particular description, an off-state current refers to a leakage current between a source and a drain when a transistor is in an off state (also referred to as a non-conducting state, a blocking state). In the case where there is no particular description, in an n-channel transistor, the off state refers to a state where a voltage V gs is lower than a threshold voltage V th ( V gs is higher than V th ).

[0095] In this specification and the like, always on refers to a state where a channel exists even when no voltage is applied to a gate, and a current flows through a transistor. Furthermore, always off refers to a state where a current does not flow through a transistor when no potential is applied to a gate or a ground potential is supplied to the gate.

[0096] Note that in this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a component is inclined with respect to a substrate surface or a formed surface. For example, a region in which an angle (also referred to as a taper angle) formed by the inclined side surface and the substrate surface or the formed surface is greater than 0 degrees and less than 90 degrees is preferably included. Here, the side surface of the component, the substrate surface, and the formed surface do not necessarily have to be completely flat, and can be an approximately planar shape with a slight curvature or an approximately planar shape with fine irregularities.

[0097] In this specification and the like, in the case where it is stated that A is positioned on B, at least a part of A is positioned on B. Thus, for example, it can be stated that A has a region positioned on B. Similarly, in the case where it is stated that A is in contact with B or A overlaps with B, at least a part of A is in contact with B or overlaps with B. Thus, for example, it can be stated that A has a region in contact with B or A has a region overlapping with B. Similarly, in the case where it is stated that A covers B, at least a part of A covers B. Thus, for example, it can be stated that A has a region covering B.

[0098] In this specification and the like, a device using a metal mask or an FMM (Fine Metal Mask) for manufacturing is sometimes referred to as a device having a MM (Metal Mask) structure. Further, in this specification and the like, a device not using a metal mask or an FMM for manufacturing is sometimes referred to as a device having a MML (Metal Mask Less) structure.

[0099] In this specification and the like, a structure in which light-emitting layers are separately manufactured in light-emitting elements (also referred to as light-emitting devices) in which light-emitting wavelengths are different is sometimes referred to as an SBS (Side By Side) structure. The SBS structure can improve the freedom of selection of materials and structures because the materials and structures can be optimized for each light-emitting element, and can easily achieve improvement in luminance and reliability.

[0100] In this specification and the like, a hole or an electron is sometimes referred to as a "carrier". Specifically, a hole-injection layer or an electron-injection layer is sometimes referred to as a "carrier-injection layer", a hole-transport layer or an electron-transport layer is sometimes referred to as a "carrier-transport layer", and a hole-blocking layer or an electron-blocking layer is sometimes referred to as a "carrier-blocking layer". Note that the above-described carrier-injection layer, carrier-transport layer, and carrier-blocking layer cannot be clearly distinguished in some cases. Further, one layer sometimes has the functions of two or all of a carrier-injection layer, a carrier-transport layer, and a carrier-blocking layer.

[0101] In this specification and the like, a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, as a layer included in the EL layer (also referred to as a functional layer), a light-emitting layer, a carrier-injection layer (a hole-injection layer and an electron-injection layer), a carrier-transport layer (a hole-transport layer and an electron-transport layer), and a carrier-blocking layer (a hole-blocking layer and an electron-blocking layer) can be given. In this specification and the like, one of a pair of electrodes is referred to as a pixel electrode and the other is referred to as a common electrode.

[0102] In this specification and the like, a sacrificial layer (also referred to as a mask layer) is positioned at least over a light-emitting layer (more specifically, a layer included in an EL layer and processed into an island shape) and has a function of protecting the light-emitting layer in a manufacturing process.

[0103] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape of a formed surface (e.g., a step or the like).

[0104] Note that arrows indicating an X direction, a Y direction, and a Z direction are attached to some drawings in this specification and the like. Note that in this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction thereof are sometimes not distinguished unless explicitly indicated. The "Y direction" and the "Z direction" are also the same. Further, the X direction, the Y direction, and the Z direction are directions intersecting with one another. For example, the X direction, the Y direction, and the Z direction are orthogonal to one another. (Embodiment 1)

[0105] In this embodiment, a semiconductor device of one embodiment of the present application and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 17.

[0106] A semiconductor device of one embodiment of the present application includes an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer.

[0107] The oxide semiconductor layer is used as a semiconductor layer of a transistor, the first conductive layer is used as one of a source electrode and a drain electrode of the transistor, the second conductive layer is used as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is used as a gate electrode of the transistor, and the second insulating layer is used as a gate insulating layer of the transistor.

[0108] The first insulating layer is positioned on the first conductive layer, and the second conductive layer is positioned on the first insulating layer. The oxide semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the second conductive layer, and a side surface of the first insulating layer. The second insulating layer is positioned on the oxide semiconductor layer. The third conductive layer is positioned on the second insulating layer and overlaps with the semiconductor layer with the second insulating layer interposed therebetween.

[0109] In the semiconductor device of one embodiment of the present application, it is preferable that the first insulating layer be in contact with the oxide semiconductor layer and have a first region containing a halogen element. The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and is more preferably chlorine or fluorine. Further, from the viewpoint of substitution of oxygen, it is preferable to use fluorine which has a higher electronegativity than oxygen.

[0110] By including the halogen element in the first insulating layer, the halogen element can be supplied from the first insulating layer to the oxide semiconductor layer. The halogen element (X) has a function of becoming a defect (VoX) in which the halogen element enters an oxygen vacancy (Vo) in the oxide semiconductor layer to generate an electron as a carrier. For example, when chlorine (Cl) is used as the halogen element, Cl stably exists in the oxide semiconductor layer in a state of VoCl. At this time, it is possible that Cl becomes in the state of VoCl not only by entering an existing Vo but also by substituting oxygen.

[0111] On the other hand, oxygen substituted with Cl (also referred to as excess oxygen) has a function of trapping an electron. Furthermore, carrier trapping by oxygen occurs preferentially compared to carrier generation by VoCl. Thus, a negative charge (also referred to as a negative fixed charge) is formed at and near the interface between the first insulating layer and the oxide semiconductor layer. The above first region is in contact with a channel formation region in the oxide semiconductor layer. By the presence of the negative charge in the channel formation region, the threshold voltage of the transistor can be shifted in the positive direction. Thus, even in the case of manufacturing a minute transistor or a transistor with an extremely small channel length, the transistor can be made to be normally off.

[0112] In the semiconductor device of one embodiment of the present application, a halogen element can be added to the first insulating layer, and then the halogen element can be supplied from the first insulating layer to the oxide semiconductor layer, so that damage to a channel formation region of the oxide semiconductor layer due to an added element and a decrease in crystallinity of the channel formation region due to an added element can be suppressed. Thus, the reliability of the transistor can be improved.

[0113] The first insulating layer and the second conductive layer can also include an opening portion reaching the first conductive layer. In this case, the third conductive layer preferably overlaps with the oxide semiconductor layer with the second insulating layer interposed therebetween at a position overlapping with the opening portion. Alternatively, a groove (slit) can be provided instead of the opening portion.

[0114] The source electrode and the drain electrode of the transistor of one embodiment of the present application are positioned at different levels, and thus current flowing through the semiconductor layer flows in the vertical direction. In other words, the channel length direction has a component of the vertical direction, and thus the transistor of one embodiment of the present application can also be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0115] The source electrode, the semiconductor layer, and the drain electrode of the transistor of one embodiment of the present application can be provided to overlap with each other, which can greatly reduce the occupied area compared to a so-called planar transistor in which the semiconductor layer is provided in a planar shape.

[0116] Further, since a parasitic capacitance is generated in a region where the second conductive layer and the third conductive layer overlap with each other, the operation of the transistor is slowed down, and in some cases, the frequency characteristics of a circuit are decreased.

[0117] Thus, the transistor of one embodiment of the present application preferably has a structure in which a parasitic capacitance between the second conductive layer and the third conductive layer is reduced. With this structure, high-speed operation of the transistor can be achieved. Further, a semiconductor device with good electrical characteristics can be provided.

[0118] Specifically, a semiconductor device of one embodiment of the present application includes an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0119] The oxide semiconductor layer is used as a semiconductor layer of a transistor, the first conductive layer is used as one of a source electrode and a drain electrode of the transistor, the second conductive layer is used as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is used as a gate electrode of the transistor, and the second insulating layer and the fourth insulating layer are used as a gate insulating layer of the transistor.

[0120] The first insulating layer is positioned over the first conductive layer, the second conductive layer is positioned over the first insulating layer, the first insulating layer and the second conductive layer include a first opening portion reaching the first conductive layer, the oxide semiconductor layer is in contact with a top surface of the second conductive layer and is in contact with a top surface of the first conductive layer, a side surface of the second conductive layer, and a side surface of the first insulating layer in the first opening portion, the second insulating layer has a portion overlapping with the top surface of the second conductive layer with the oxide semiconductor layer interposed therebetween and a portion positioned over the oxide semiconductor layer in the first opening portion, the third insulating layer is positioned over the second insulating layer and includes a second opening portion reaching the second insulating layer at a position overlapping with the first opening portion, the fourth insulating layer is in contact with a side surface of the third insulating layer in the second opening portion and overlaps with the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion, and the third conductive layer is positioned over the fourth insulating layer and overlaps with the oxide semiconductor layer with the second insulating layer and the fourth insulating layer interposed therebetween in the first opening portion.

[0121] In the semiconductor device of one embodiment of the present application, it is preferable that, in a cross-sectional view, a maximum value of the width of the third conductive layer in the second opening portion be less than or equal to a minimum value of the width of the first opening portion in the second conductive layer. With such a structure, the parasitic capacitance between the second conductive layer and the third conductive layer can be extremely small.

[0122] Note that in this specification and the like, a simple "cross-sectional view" is also referred to as a "cross-sectional view taken in the same direction", specifically, in some cases. For example, in a case where the relationship between a plurality of components is described, the relationship in a cross-sectional view taken in the same direction is described. At this time, the relationship between the plurality of components can be described with reference to one cross-sectional view.

[0123] In addition, a transistor of one embodiment of the present application preferably has a structure in which parasitic capacitance between the first conductive layer and the second conductive layer is reduced. With such a structure, high-speed operation of the transistor can be achieved. Furthermore, a semiconductor device with favorable electrical characteristics can be provided.

[0124] In the semiconductor device of one embodiment of the present application, it is preferable that the maximum value of the width of the first conductive layer in a cross section taken in a direction perpendicular to the extension direction of the first conductive layer be smaller than the minimum value of the width of the first opening portion in the second conductive layer. With such a structure, the parasitic capacitance between the first conductive layer and the second conductive layer can be small.

[0125] <Structure Example 1 of Semiconductor Device>

[0126] Reference FIGS. 1A-1D , FIG. 2A and FIG. 2B The structure of a semiconductor device of one embodiment of the present application is described.

[0127] [Transistor 200A]

[0128] FIG. 1A is a plan view of a semiconductor device including the transistor 200A. FIG. 1B and FIG. 2 are cross-sectional views along the dot-dash line A1-A2 in FIG. FIG. 1A FIG. 2A is an enlarged view of a portion of FIG. FIG. 1B corresponding to the oxide semiconductor layer 230, and illustrates a structure example of each layer in more detail. FIG. 2B is an enlarged view of the region P1 in FIG. FIG. 2A FIG. 1C is a cross-sectional view along the dot-dash line A3-A4 in FIG. FIG. 1A FIG. 1D is a cross-sectional view along the dot-dash line A5-A6 in FIG. FIG. 1B and FIG. 1C FIG. 1D can also be said to be a cross-sectional view of the XY plane including the insulating layer 280. Note that in the plan view of FIG. FIG. 1A , part of the components is omitted for clarity. Part of the components is also omitted in some of the plan views below.

[0129] FIGS. 1A-1D and FIG. 2A The semiconductor device illustrated in FIGS. 1A and 1B includes the insulating layer 210 over a substrate (not shown), the transistor 200A over the insulating layer 210, the insulating layer 280 over the insulating layer 210, the insulating layer 285 over the transistor 200A, and the conductive layer 265 over the insulating layer 285. The insulating layer 210, the insulating layer 280, and the insulating layer 285 are used as interlayer films.

[0130] The transistor 200A includes the conductive layer 220, the conductive layer 240 over the insulating layer 280, the oxide semiconductor layer 230, the insulating layer 250a over the oxide semiconductor layer 230, the insulating layer 250b over the insulating layer 250a, and the conductive layer 260 over the insulating layer 250b.

[0131] ​​​​In transistor 200A, oxide semiconductor layer 230 is used as a semiconductor layer, conductive layer 260 is used as a gate electrode, insulating layers 250a and 250b are used as gate insulating layers, conductive layer 220 is used as one of the source electrode and drain electrode, and conductive layer 240 is used as the other of the source electrode and drain electrode. Furthermore, conductive layer 265 is used as gate wiring.

[0132] At least a portion of the region of the oxide semiconductor layer 230 that contacts the insulating layer 280 is used as the channel formation region of the transistor 200A. One of the regions of the oxide semiconductor layer 230 that contacts the conductive layer 220 and the regions of the oxide semiconductor layer 230 that contacts the conductive layer 240 is used as the source region and the other is used as the drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0133] like FIG. 1B and FIG. 1C As shown, the insulating layer 280 and the conductive layer 240 are provided with openings 290 that reach the conductive layer 220. Here, the bottom of the opening 290 includes the top surface of the conductive layer 220, and the sidewalls of the opening 290 include the sidewalls of the insulating layer 280 and the conductive layer 240. The opening 290 includes openings in both the insulating layer 280 and the conductive layer 240. In other words, the opening in the region of the insulating layer 280 that overlaps with the conductive layer 220 is part of the opening 290, and the opening in the region of the conductive layer 240 that overlaps with the conductive layer 220 is the remaining part of the opening 290.

[0134] At least a portion of the components of transistor 200A are disposed within opening 290. Specifically, oxide semiconductor layer 230, insulating layer 250a, insulating layer 250b, and conductive layer 260 are all disposed such that at least a portion of each is located within opening 290. Oxide semiconductor layer 230 is in contact with the top surface of conductive layer 220, the side surface of insulating layer 280, and the side surface of conductive layer 240 within opening 290.

[0135] Furthermore, the oxide semiconductor layer 230, insulating layer 250a, and insulating layer 250b are disposed within the opening 290 in a manner that reflects the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is disposed to cover the bottom and sidewalls of the opening 290, the insulating layer 250a is disposed to cover the oxide semiconductor layer 230, and the insulating layer 250b is disposed to cover the insulating layer 250a. Additionally, the conductive layer 260 is disposed such that at least a portion of the recess in the insulating layer 250b, which reflects the shape of the opening 290, is embedded.

[0136] Here, it is preferable that the insulating layer 280 be in contact with the oxide semiconductor layer 230 and have a region 280i containing a halogen element. The region 280i includes the side wall of the opening portion 290.

[0137] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and is more preferably chlorine or fluorine. Furthermore, from the viewpoint of substitution of oxygen, it is preferable to use fluorine, which has a higher electronegativity than oxygen.

[0138] By including the halogen element in the region 280i, the halogen element can be supplied from the region 280i into the oxide semiconductor layer 230. The halogen element (X) has a function of becoming a defect (VoX) in which the halogen element enters an oxygen vacancy (Vo) in the oxide semiconductor layer 230 to generate an electron as a carrier. For example, when chlorine (Cl) is used as the halogen element, Cl stably exists in the oxide semiconductor layer 230 in a state of VoCl. At this time, it is possible that Cl becomes in the state of VoCl not only by entering an existing Vo but also by substituting oxygen.

[0139] On the other hand, oxygen substituted with Cl (also referred to as excess oxygen) has a function of trapping an electron. Furthermore, carrier trapping by oxygen occurs preferentially compared to carrier generation by VoCl. Thus, a negative charge (also referred to as a negative fixed charge) is formed at and near the interface between the insulating layer 280 and the oxide semiconductor layer 230. The region 280i is in contact with a channel formation region in the oxide semiconductor layer 230. By the presence of the negative charge in the channel formation region, the threshold voltage of the transistor 200A can be shifted in the positive direction. Thus, even if the transistor 200A has a microstructure or the channel length of the transistor 200A is extremely short, the transistor 200A can be made to be normally off.

[0140] In addition, the conductive layer 240 and the conductive layer 220 sometimes contain a halogen element. Furthermore, a halogen element is sometimes supplied from the conductive layer 240 or the conductive layer 220 to the oxide semiconductor layer 230. In FIG. 1B 、 FIG. 1C and FIG. 2A In the drawings, the side surface of the conductive layer 240 on the side of the opening portion 290 and part of the surface of the conductive layer 220 overlapping with the opening portion 290 are also shaded similarly to the region 280i.

[0141] As FIG. 1B and FIG. 1CAs shown, in the insulating layer 285, an opening portion 270 reaching the insulating layer 250a is provided at a position overlapping with the opening portion 290. At least a part of the constituent elements of the transistor 200A is arranged in the opening portion 270. Specifically, the insulating layer 250b and the conductive layer 260 are arranged so that at least a part thereof is positioned in the opening portion 270. The insulating layer 250b is in contact with the insulating layer 250a and the insulating layer 285 in the opening portion 270.

[0142] Here, the insulating layer 250a is used not only as a gate insulating layer but also as an etching stopper layer at the time of forming the opening portion 270 in the insulating layer 285. Further, the insulating layer 250b serving as a gate insulating layer is provided in the opening portion 270. When the insulating layer 250a is required to have the functions of a gate insulating layer and an etching stopper layer, the range of choice of the material of the insulating layer 250a is sometimes narrowed. Further, the insulating layer 250a can be damaged at the time of forming the opening portion 270. By using both the insulating layer 250a and the insulating layer 250b as gate insulating layers, the range of choice of the material of each of the insulating layer 250a and the insulating layer 250b is widened, so that the quality of the gate insulating layer can be improved, which is preferable. Thus, both good characteristics of the transistor and high manufacturing yield can be achieved.

[0143] Further, the portion of the insulating layer 250b arranged in the opening portion 270 reflects the shape of the opening portion 270. Specifically, the insulating layer 250b is provided so as to cover the side wall (side surface of the insulating layer 285) of the opening portion 270. Further, the conductive layer 260 is provided so as to at least partly fill the recess portion of the insulating layer 250b which reflects the shape of the opening portion 270.

[0144] When the conductive layer 265 is used as a gate wiring, the conductive layer 260 does not need to be widely provided outside the opening portion 290, so that the area where the conductive layer 240 overlaps with the conductive layer 260 can be reduced. Thus, the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced. Especially in the case where the conductive layer 240 is used as a source wiring and the conductive layer 260 is used as a gate wiring, the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced. FIG. 1B and FIG. 1C In the transistor 200A shown, since the conductive layer 260 is not on the conductive layer 240, the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be further reduced. As shown in FIG. 2B, the conductive layer 260 is provided so as to at least partly fill the recess portion of the insulating layer 250b which reflects the shape of the opening portion 270. FIG. 1B and FIG. 1C As shown in the cross-sectional view, the maximum value of the width of the conductive layer 260 is the width Da in the opening portion 270. This width Da is smaller than the width D of the opening portion 290. Thus, when the maximum value of the width of the conductive layer 260 is smaller than the width D of the opening portion 290, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable. Further, for example, as shown in FIG. 2B, the conductive layer 260 is provided so as to at least partly fill the recess portion of the insulating layer 250b which reflects the shape of the opening portion 270. FIG. 1B or FIG. 1CThe size relationship between the two widths in the semiconductor device of one embodiment of the present application can be confirmed with one cross section parallel to the Z direction.

[0145] Note that the width D of the opening portion 290 is sometimes changed in the depth direction. Here, in particular, the shortest distance between the two side surfaces of the opening portion 290 of the conductive layer 240 at the time of cross section is used as the width D. In other words, the minimum value of the width of the opening portion 290 in the conductive layer 240 is used as the width D of the opening portion 290.

[0146] FIG. 1B FIG. 2A An example in which the width of the opening portion 270 is the same as the width of the opening portion 290 (equal to the width D) is shown. The width of the opening portion 270 is preferably equal to or smaller than the width of the opening portion 290. With this structure, the top surface of the conductive layer 260 does not overlap with the top surface of the conductive layer 240, and thus the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable.

[0147] Note that the width of the opening portion 270 is sometimes changed in the depth direction. Here, in particular, the maximum value of the width of the opening portion 270 in the insulating layer 285 at the time of cross section is used as the width of the opening portion 270.

[0148] The height of the top surface of the conductive layer 260 is preferably the same as or substantially the same as the height of the top surface of the insulating layer 285. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 250b, and the conductive layer 260 and is in contact with the top surface of the conductive layer 260. The conductive layer 260 and the conductive layer 265 can be said to be electrically connected to each other. The insulating layer 250a and the insulating layer 285 are positioned between the conductive layer 265 and the conductive layer 240. With this structure, the physical distance between the conductive layer 265 and the conductive layer 240 can be increased, and thus the parasitic capacitance between the conductive layer 265 and the conductive layer 240 can be reduced.

[0149] That is, the transistor 200A has a structure in which the parasitic capacitance between the other of the source and drain electrodes and the gate electrode and the parasitic capacitance between the other of the source and drain electrodes and the gate wiring are reduced. Thus, the frequency characteristics of a circuit can be improved.

[0150] In addition, as FIG. 2B FIG. 15A ​​As shown, the width Dc of the conductive layer 220 in a cross section in a direction perpendicular to the direction in which the conductive layer 220 extends (A1-A2 direction) is preferably equal to or smaller than the minimum value of the width of the opening portion 290 in the conductive layer 240 (i.e., equal to or smaller than the width D). With this structure, the area of the conductive layer 220 overlapping with the conductive layer 240 can be reduced, and thus the parasitic capacitance generated between the conductive layer 220 and the conductive layer 240 can be reduced. That is, the transistor 200A has a structure in which the parasitic capacitance generated between the source electrode and the drain electrode is reduced. Thus, the frequency characteristics of a circuit including the transistor 200A can be improved.

[0151] Note that the maximum value of the width of the conductive layer 220 in a cross section in the direction perpendicular to the direction in which the conductive layer 220 extends (A1-A2 direction) is used as the width Dc of the conductive layer 220.

[0152] On the other hand, when the opening portion 290 reaches the top surface of the insulating layer 210, there is a possibility that the shape of the oxide semiconductor layer 230 provided in the opening portion 290 is not good. Further, it is sometimes difficult to form the opening portion 290 in such a manner that the side surface of the conductive layer 240 in the opening portion 290 is aligned with the side surface of the conductive layer 220 (or in such a manner that the width D is equal to the width Dc).

[0153] Thus, the side surface of the opening portion 290 in the insulating layer 280 preferably has at least a first surface and a second surface positioned above the first surface. As FIG. 15B As shown, the angle θa formed by the first surface and the top surface of the insulating layer 210 is preferably smaller than the angle θb formed by the second surface and the top surface of the insulating layer 210. With this structure, the opening portion 290 can be formed in such a manner that the opening portion 290 does not reach the top surface of the insulating layer 210 and the width D is larger than the width Dc. Thus, it is easy to manufacture a transistor having a structure in which the parasitic capacitance is reduced, and thus this structure is preferable. Note that a method for manufacturing the transistor 200A will be described later (see Embodiment Mode 5). FIG. 1B FIG. 1B

[0154] ​​The side wall of the opening portion 290 is preferably perpendicular or substantially perpendicular to the top surface of the insulating layer 210. By employing such a structure, miniaturization or high integration of the semiconductor device can be achieved. The angle θa is preferably 65 degrees or more and 90 degrees or less. Further, it is more preferable that both the angle θa and the angle θb be 65 degrees or more and 90 degrees or less. At this time, it is preferable that the film provided inside the opening portion 290 be formed using an atomic layer deposition (ALD) method. The ALD method can deposit atoms one layer at a time, and thus has effects such as being able to deposit an extremely thin film, being able to deposit a structure with a high aspect ratio, being able to deposit with few defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperature. Thus, the film can be deposited on the side of the opening portion 290 with high coverage. For example, the oxide semiconductor layer 230, the insulating layer 250a, the insulating layer 250b, and the conductive layer 260 are each preferably formed using the ALD method.

[0155] FIG. 1C A structure in which the end portion of the conductive layer 240 and the end portion of the oxide semiconductor layer 230 are aligned on the outside of the opening portion 290 is illustrated. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured by processing using the same mask, as in the manufacturing method example described later. Thus, the number of masks needed for manufacturing the semiconductor device can be reduced, which is preferable. Note that the present application is not limited to this. For example, in the X direction or the Y direction, any of the end portion of the oxide semiconductor layer 230, the end portion of the conductive layer 240a, and the end portion of the conductive layer 240b can be positioned on the inside or the outside of the other.

[0156] The conductive layer 240 has the opening portion 290 in a region overlapping with the conductive layer 220. Further, the conductive layer 240 is preferably not provided inside the opening portion 290 included in the insulating layer 280. That is, the conductive layer 240 preferably has no region in contact with the side surface of the insulating layer 280 in the opening portion 290. By employing such a structure, the opening portion 290 can be formed at once in the conductive layer 240 and the insulating layer 280. Further, when the side surface of the conductive layer 240 in the opening portion 290 is aligned with at least a part of the side surface of the insulating layer 280 in the opening portion 290 (specifically, the second surface described above), the thickness distribution of the oxide semiconductor layer 230 provided inside the opening portion 290 can be made uniform. Further, the oxide semiconductor layer 230 can be prevented from being broken by the step of the conductive layer 240 and the insulating layer 280.

[0157] Although in the above embodiment the oxide semiconductor layer 230 is provided inside the opening portion 290, the present application is not limited to this. For example, the oxide semiconductor layer 230 can be provided outside the opening portion 290. FIG. 1B and FIG. 1CThe side surface of the conductive layer 240 in the opening portion 290 is flush (also referred to as aligned, substantially aligned) with a portion (second surface) of the side surface of the insulating layer 280 in the opening portion 290, as shown in FIG. 12, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening portion 290 can not be continuous with the side surface of the insulating layer 280 in the opening portion 290. Further, the inclination of the side surface of the conductive layer 240 in the opening portion 290 can be different from the inclination of the side surface of the insulating layer 280 in the opening portion 290. At this time, for example, the taper angle of the side surface of the conductive layer 240 in the opening portion 290 is preferably smaller than the taper angle of the side surface of the insulating layer 280 in the opening portion 290. With such a structure, the coverage of the oxide semiconductor layer 230 over the side surface of the conductive layer 240 in the opening portion 290 is improved, so that defects such as voids can be reduced.

[0158] In addition, as shown in FIG. 13A, a recess 290a which overlaps with the opening portion 290 can be provided in the top surface of the conductive layer 220. With such a structure, the oxide semiconductor layer 230, the insulating layer 250a, the insulating layer 250b, and at least a portion of the conductive layer 260 can be formed so as to fill the recess 290a. Thus, the gate electric field of the conductive layer 260 can be easily applied to the oxide semiconductor layer 230 in the vicinity of the conductive layer 220. FIG. 2B 、 FIG. 1B and FIG. 1C In addition, as shown in FIG. 13A, a recess 290a which overlaps with the opening portion 290 can be provided in the top surface of the conductive layer 220. With such a structure, the oxide semiconductor layer 230, the insulating layer 250a, the insulating layer 250b, and at least a portion of the conductive layer 260 can be formed so as to fill the recess 290a. Thus, the gate electric field of the conductive layer 260 can be easily applied to the oxide semiconductor layer 230 in the vicinity of the conductive layer 220.

[0159] Specifically, the conductive layer 220 has a portion with a smaller thickness in a region in contact with the oxide semiconductor layer 230 than in a region in contact with the insulating layer 280. When the conductive layer 220 includes a recess, the contact area of the conductive layer 220 with the oxide semiconductor layer 230 can be further increased. In this case, the contact resistance can be reduced, which is preferable. Note that the conductive layer 220 can not include a recess.

[0160] The transistor 200A preferably contains a metal oxide (also referred to as an oxide semiconductor) serving as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. In other words, the transistor 200A is an OS transistor.

[0161] In an OS transistor, when oxygen vacancies (V O ) and impurities exist in a channel formation region of an oxide semiconductor, electrical characteristics easily fluctuate and reliability can be reduced. Further, hydrogen in the vicinity of an oxygen vacancy forms a defect (hereinafter referred to as a V OH) and thus can generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor has a normally-on characteristic. Thus, in the channel formation region of the oxide semiconductor, it is preferable that oxygen vacancies and impurities be reduced as much as possible. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor be reduced and be i-type (intrinsic) or substantially i-type.

[0162] On the other hand, the source region and the drain region of the OS transistor are preferably regions in which the number of oxygen vacancies is larger than that in the channel formation region, V O H) and thus can generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor has a normally-on characteristic. Thus, in the channel formation region of the oxide semiconductor, it is preferable that oxygen vacancies and impurities be reduced as much as possible. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor be reduced and be i-type (intrinsic) or substantially i-type.

[0163] When the oxide semiconductor layer 230 is in contact with the conductive layer 220, a metal compound or an oxygen vacancy is formed, and the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 is low-resistance. Thus, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced. Similarly, when the oxide semiconductor layer 230 is in contact with the conductive layer 240, the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 is low-resistance. Thus, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0164] As described above, the oxide semiconductor layer 230 is provided inside the opening portion 290 of the insulating layer 280. Further, in the transistor 200A, one of the source electrode and the drain electrode (here, the conductive layer 220) is positioned below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is positioned above, and thus current flows in the up-down direction. That is, a channel is formed along the side surface of the opening portion 290 of the insulating layer 280.

[0165] The oxide semiconductor layer 230 is in contact with the top surface of the conductive layer 220 and the side surface of the conductive layer 240 inside the opening portion 290. The oxide semiconductor layer 230 is also in contact with part of the top surface of the conductive layer 240. Thus, by making the oxide semiconductor layer 230 in contact with the side surface and the top surface of the conductive layer 240, the area of the oxide semiconductor layer 230 in contact with the conductive layer 240 can be increased. Thus, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0166] In addition, as described above, the oxide semiconductor layer 230 has a region in contact with the top surface of the conductive layer 220 and a region in contact with the top surface of the conductive layer 240, one of which is used as a source region and the other of which is used as a drain region.

[0167] The source and drain regions preferably contain impurity elements. The first element is preferably used as the impurity element. Alternatively, a combination of the first element and hydrogen is preferably used as the impurity element.

[0168] exist FIG. 2A , FIG. 1B and FIG. 1C In the diagram, a portion of the region in the oxide semiconductor layer 230 that contacts the top surface of the conductive layer 220 and a portion of the region that contacts the top surface of the conductive layer 240 are shown as region 230n. In particular, region 230n preferably contains impurity elements.

[0169] In addition, conductive layers 240 and 220 sometimes contain impurity elements. FIG. 2A , FIG. 1D and FIG. 1D In the same way, the regions of conductive layer 240 that are in contact with oxide semiconductor layer 230 and the regions of conductive layer 220 that are in contact with oxide semiconductor layer 230 are also shaded in the same way as region 230n.

[0170] As the primary element, one or more of the following are preferred: boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and rare gases (helium, neon, argon, krypton, xenon, etc.).

[0171] In addition, the first element is not limited to the elements mentioned above, and may be one or more elements included in the first transition element (3d transition element, 3d transition metal), the second transition element (4d transition element, 4d transition metal), the third transition element (5d transition element, 5d transition metal), alkaline earth metal elements and rare earth elements.

[0172] By supplying a first element to the source and drain regions, the first element removes oxygen and other substances from these regions, thereby creating oxygen vacancies. These oxygen vacancies bond with hydrogen in the film to generate charge carriers, thus reducing the resistance of the source and drain regions. This reduces the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. Consequently, the on-state current of the transistor can be increased. By increasing the on-state current, the operating voltage of the transistor can be reduced. This, in turn, reduces the power consumption of the semiconductor device.

[0173] In the case where an element that easily bonds with oxygen is used as the first element, the first element exists in a state of bonding with oxygen in the semiconductor layer. Further, when an element that is stabilized by bonding with oxygen is used as the first element, the first element in the semiconductor layer stably exists in a state of being oxidized, and thus is not easily detached by heating or the like in a manufacturing process of the semiconductor device, and thus a low-resistance region that is stable in a state of low resistance can be realized. Thus, as the first element, an element of which oxide exists as a solid at 25 °C and 1 atm is preferably used. Specifically, as the preferred first element, a typical nonmetal element other than hydrogen, a typical metal element, and a transition element (transition metal) can be given, and as the particularly preferred first element, boron, phosphorus, magnesium, aluminum, and silicon can be given.

[0174] Thus, boron, phosphorus, magnesium, aluminum, or silicon is preferably used as one of the first elements. Further, boron or phosphorus is particularly preferably used as one of the first elements.

[0175] Further, in addition to the above function of generating an oxygen vacancy, hydrogen has a function of bonding with an oxygen vacancy, and thus is suitable for use as an impurity element.

[0176] By using both the first element and hydrogen as the impurity element, the resistance of the source region and the drain region in the oxide semiconductor layer 230 can be easily reduced, and a state of low resistance can be stably maintained.

[0177] Further, when both the first element and hydrogen are supplied, ions generated from a source gas can be added without mass separation, and thus productivity can be improved, and thus is preferable. For example, by using B2H6gas, boron and hydrogen can be supplied as the impurity element. Further, for example, by using PH3gas, phosphorus and hydrogen can be supplied as the impurity element. Further, the method of supplying the impurity element is not limited thereto. For example, a source gas can be ionized and a specific element can be added by mass separation of the ions. For example, boron can be added to the region 230n after mass separation using B2H6gas.

[0178] The region 230n preferably includes the impurity element at a concentration of 1 x 10 19 atoms / cm 3 The above and 1 x 10 23 atoms / cm 3 The following, preferably 5 x 10 19 atoms / cm 3 The above and 5 x 10 22 atoms / cm 3 The following, more preferably 1 x 10 20 atoms / cm 3 The above and 1 x 10 22 atoms / cm 3The following regions. In the case where a plurality of impurity elements are contained, the concentration of each impurity element is preferably within the above range.

[0179] Further, the channel formation region in the oxide semiconductor layer 230 is sometimes supplied with an impurity element. Alternatively, part of the impurity element contained in the region 230n diffuses to the channel formation region due to the influence of heating in a manufacturing process or the like. The concentration of the impurity element in the channel formation region is preferably lower than one-tenth of the concentration of the impurity element in the region 230n, further preferably lower than one percent.

[0180] The concentration of the impurity element contained in the oxide semiconductor layer 230 (including the region 230n) can be analyzed by SIMS or XPS or the like, for example. In the case of XPS analysis, the concentration distribution in the depth direction can be known by combining XPS analysis and ion sputtering from the surface side or the back surface side.

[0181] When a semiconductor device of one embodiment of the present application is manufactured, the source region and the drain region of the oxide semiconductor layer 230 are preferably more easily added with an impurity element than the channel formation region. Thus, it is preferable to add an impurity element in a direction perpendicular or substantially perpendicular to the top surface of the substrate. At this time, in the oxide semiconductor layer 230, a surface inclined to the top surface of the substrate is added with less impurity element than a surface parallel or substantially parallel to the top surface of the substrate. In other words, in the oxide semiconductor layer 230, the source region and the drain region are added with more impurity element than the channel formation region. Thus, the source region and the drain region can be preferentially low-resistance.

[0182] Further, when a semiconductor device of one embodiment of the present application is manufactured, it is preferable to add an impurity element to the oxide semiconductor layer 230 through the insulating layer 250a. At this time, the thickness of the insulating layer 250a in the direction of addition of the impurity element is thicker in a region provided along the side surface of the insulating layer 280 than in a region provided along the top surface of the conductive layer 220 or the top surface of the conductive layer 240. Thus, the amount of addition of the impurity element in the oxide semiconductor layer 230 is larger in a region provided along the top surface of the conductive layer 220 or the top surface of the conductive layer 240 than in a region provided along the side surface of the insulating layer 280. In this manner, the entry of the impurity element into the channel formation region of the oxide semiconductor layer 230 can be suppressed, and the resistance of the source region and the drain region can be preferentially reduced.

[0183] When an impurity element is added to the oxide semiconductor layer 230 through the insulating layer 250a, the insulating layer 250a sometimes contains an impurity element. The region 230n preferably has a portion where the concentration of the impurity element is higher than that of the insulating layer 250a, whereby the resistance of the region 230n can be further reduced.

[0184] As FIG. 1BAs illustrated, the insulating layer 280 is in contact with the entire periphery of the oxide semiconductor layer 230. Thus, the channel formation region of the transistor 200A can be formed in the entire periphery of the oxide semiconductor layer 230 (the entire region in contact with the insulating layer 280) in the opening 290. Further, the channel formation region of the transistor 200A can be formed in the entire periphery of the oxide semiconductor layer 230 in the opening 290. FIG. 1C The cross-sectional view of the XY plane including the channel formation region of the oxide semiconductor layer 230 can also be said to be a cross-sectional view of the XY plane.

[0185] The channel length of the transistor 200A is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200A is determined depending on the thickness of the insulating layer 280 over the conductive layer 220. In the case where the channel length is determined depending on the thickness of the insulating layer 280, the channel length can be set to be longer than in the case where the channel length is determined depending on the exposure limit of a photolithography technique. FIG. 1D In the case where the channel length is determined depending on the thickness of the insulating layer 280, the channel length can be set to be longer than in the case where the channel length is determined depending on the exposure limit of a photolithography technique. FIGS. 1B-1D In the case where the channel length is determined depending on the thickness of the insulating layer 280, the channel length can be set to be longer than in the case where the channel length is determined depending on the exposure limit of a photolithography technique.

[0186] In a planar transistor, the channel length is limited by the exposure limit of a photolithography technique and cannot be further miniaturized, but in the present application, the channel length can be set depending on the thickness of the insulating layer 280. Thus, the channel length of the transistor 200A can be set to be a very fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less and 0.1 nm or more, 1 nm or more, or 5 nm or more) below the exposure limit of a photolithography technique. Thus, the on-state current of the transistor 200A is increased, so that the frequency characteristics can be improved.

[0187] Further, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. Thus, the transistor 200A can have a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided in the XY plane. By this means, high integration of a semiconductor device can be achieved. Further, when the semiconductor device of one embodiment of the present application is used for a memory device, the memory capacity per unit area can be increased.

[0188] Further, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. Thus, the transistor 200A can have a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided in the XY plane. By this means, high integration of a semiconductor device can be achieved. Further, when the semiconductor device of one embodiment of the present application is used for a memory device, the memory capacity per unit area can be increased. FIG. 1DAs shown in FIG. 2A, the oxide semiconductor layer 230, the insulating layer 250a, the insulating layer 250b, and the conductive layer 260 are provided in a concentric circular shape. Thus, the side surface of the conductive layer 260 provided at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250a and the insulating layer 250b interposed therebetween. In other words, the entire outer periphery of the oxide semiconductor layer 230 is a channel formation region in a plan view. At this time, for example, the channel width of the transistor 200A is determined in accordance with the length of the outer periphery of the oxide semiconductor layer 230. In other words, the channel width of the transistor 200A is determined in accordance with the size of the width (the diameter in the case where the shape of the opening portion 290 in a plan view is circular) of the opening portion 290. In FIG. 1A In FIG. 2A, the width D of the opening portion 290 is represented by a double-headed arrow with a dotted line. In FIG. 1B In FIG. 2A, the channel width W of the transistor 200A is represented by a double-headed arrow with a dashed line. By increasing the width D of the opening portion 290, the channel width per unit area can be increased, so that the on-state current can be increased.

[0189] In the case where the opening portion 290 is formed by photolithography, the width D of the opening portion 290 is determined in accordance with the exposure limit of photolithography. Further, the width D of the opening portion 290 is determined in accordance with the thickness of each of the oxide semiconductor layer 230, the insulating layer 250a, the insulating layer 250b, and the conductive layer 260 provided in the opening portion 290. The width D of the opening portion 290 is preferably, for example, greater than or equal to 5 nm, greater than or equal to 10 nm, or greater than or equal to 20 nm and less than or equal to 100 nm, less than or equal to 60 nm, less than or equal to 50 nm, less than or equal to 40 nm, or less than or equal to 30 nm. Note that in the case where the opening portion 290 has a circular shape in a plan view, the width D of the opening portion 290 corresponds to the diameter of the opening portion 290, and the channel width W can be calculated as "D x π".

[0190] Further, the channel length L of the transistor 200A is preferably smaller than the channel width W of the transistor 200A at least. The channel length L of the transistor 200A is preferably greater than or equal to 0.1 times and less than or equal to 0.99 times the channel width W of the transistor 200A, further preferably greater than or equal to 0.5 times and less than or equal to 0.8 times the channel width W of the transistor 200A. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0191] Further, by forming the opening portion 290 in a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250a, the insulating layer 250b, and the conductive layer 260 are provided in a concentric circular shape. Thus, the distance between the conductive layer 260 and the oxide semiconductor layer 230 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 substantially uniformly.

[0192] Note that although an example in which the shapes of the opening portion 290 and the opening portion 270 are circular in plan view is described in this embodiment, the present application is not limited to this. The shapes of the opening portion 290 and the opening portion 270 in plan view can be, for example, a circular shape, an elliptical shape, or the like, an approximately circular shape such as a triangular shape, a quadrangular shape (including a rectangular shape, a rhombic shape, a square shape), a pentagonal shape, a star polygonal shape, or the like, or a shape in which the corners of such a polygonal shape are rounded. The polygonal shape can be a concave polygonal shape (a polygonal shape in which at least one internal angle is greater than 180 degrees) or a convex polygonal shape (a polygonal shape in which all internal angles are less than or equal to 180 degrees). As described in, for example, Patent Document Nos. 1 to 3, the shapes of the opening portion 290 and the opening portion 270 in plan view are preferably circular. FIG. 1C As described in, for example, Patent Document Nos. 1 to 3, the shapes of the opening portion 290 and the opening portion 270 in plan view are preferably circular. By being circular, the processing precision at the time of forming the opening portion can be improved, and a fine opening portion can be formed. Note that in this specification and the like, a circular shape is not limited to a perfect circle.

[0193] <Materials for semiconductor devices>

[0194] Materials for the semiconductor device of this embodiment are described below. Note that each layer included in the semiconductor device of this embodiment can have a single-layer structure or a stacked-layer structure. FIG. 2A and FIG. 2A An example in which the conductive layer 220, the oxide semiconductor layer 230, the conductive layer 240, the insulating layer 250a, the insulating layer 250b, and the conductive layer 260 each have a single-layer structure is described. Note that, FIG. 2A An example in which the conductive layer 220, the oxide semiconductor layer 230, the conductive layer 240, the insulating layer 250b, and the conductive layer 260 have a stacked-layer structure is described.

[0195] [Oxide semiconductor layer 230]

[0196] As described above, the oxide semiconductor layer 230 has a channel formation region. The channel formation region is i-type (intrinsic) or substantially i-type. The oxide semiconductor layer 230 also has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) in which the carrier concentration is higher than that of the channel formation region.

[0197] There is no particular limitation on the crystallinity of the semiconductor material used for the oxide semiconductor layer 230, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor in which part of the semiconductor has a crystalline region) can be used. The use of a single crystal semiconductor or a semiconductor having crystallinity can suppress deterioration of the characteristics of the transistor, and is thus preferable.

[0198] The band gap of the metal oxide used as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a large band gap, the off-state current of the transistor can be reduced. Since the off-state current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, since the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0199] As the metal oxide that can be used for the oxide semiconductor layer 230, for example, an indium oxide, a gallium oxide, an aluminum oxide, a zinc oxide, or a tin oxide can be given. The metal oxide preferably contains at least indium (In) or zinc (Zn). Further, the metal oxide preferably contains two or more kinds selected from indium, an element M, and zinc. Note that the element M is a metal element or a semi-metal element having high bonding energy to oxygen, such as a metal element or a semi-metal element having higher bonding energy to oxygen than indium. Specifically, as the element M, an aluminum, a gallium, a tin, a yttrium, a titanium, a vanadium, a chromium, a manganese, an iron, a cobalt, a nickel, a zirconium, a molybdenum, a hafnium, a tantalum, a tungsten, a lanthanum, a cerium, a neodymium, a magnesium, a calcium, a strontium, a barium, a boron, a silicon, a germanium, an antimony, or the like can be given. The element M contained in the metal oxide is preferably one or more kinds selected from the above elements, more preferably one or more kinds selected from an aluminum, a gallium, a tin, and a yttrium, and further preferably a gallium. Note that in this specification and the like, a metal element and a semi-metal element are sometimes collectively referred to as a "metal element", and the "metal element" described in this specification and the like sometimes includes a semi-metal element.

[0200] The oxide semiconductor layer 230 can be formed using, for example, an indium oxide (In oxide), an indium-zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), an indium-tin oxide (In-Sn oxide), an indium-titanium oxide (In-Ti oxide), an indium-gallium oxide (In-Ga oxide), an indium-gallium-aluminum oxide (In-Ga-Al oxide), an indium-gallium-tin oxide (In-Ga-Sn oxide, also referred to as IGTO), a gallium-zinc oxide (Ga-Zn oxide, also referred to as GZO), an aluminum-zinc oxide (Al-Zn oxide, also referred to as AZO), an indium-aluminum-zinc oxide (In-Al-Zn oxide, also referred to as IAZO), an indium-tin-zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), an indium-titanium-zinc oxide (In-Ti-Zn oxide), an indium-gallium-zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), an indium-gallium-tin-zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), an indium-gallium-aluminum-zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), or the like. Alternatively, an indium-tin oxide containing silicon, a gallium-tin oxide (Ga-Sn oxide), an aluminum-tin oxide (Al-Sn oxide), or the like can be used.

[0201] By increasing the ratio of the number of atoms of indium to the sum of the number of atoms of all metal elements in the metal oxide, the field-effect mobility of the transistor can be increased. In addition, a transistor with a large on-state current can be realized.

[0202] Note that the metal oxide can also contain one or plural metal elements having a large period number in the periodic table instead of or in addition to indium. There is a tendency that the larger the orbital overlap of the metal elements, the larger the carrier conduction in the metal oxide. Thus, by containing a metal element having a large period number, the field-effect mobility of the transistor can be increased in some cases. As the metal element having a large period number, a metal element belonging to the 5th period and a metal element belonging to the 6th period, and the like can be given. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, and the like can be given. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0203] In addition, the metal oxide can also contain one or plural non-metal elements. When the metal oxide contains a non-metal element, the field-effect mobility of the transistor can be increased in some cases due to an increase in carrier concentration or a narrowing of a band gap, or the like. As the non-metal element, carbon, nitrogen, phosphorus, sulfur, selenium, bromine, hydrogen, and the like can be given.

[0204] In addition, by increasing the ratio of the number of atoms of zinc to the sum of the number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is increased, whereby diffusion of impurities in the metal oxide can be suppressed. Thus, fluctuation in electrical characteristics of the transistor is suppressed, whereby reliability can be increased.

[0205] In addition, by increasing the ratio of the number of atoms of the element M to the sum of the number of atoms of all metal elements in the metal oxide, a metal oxide with a large band gap can be obtained. In addition, formation of an oxygen vacancy in the metal oxide can be suppressed. Thus, generation of carriers due to the oxygen vacancy is suppressed, whereby a transistor with a small off-state current can be realized. In addition, drift of the threshold voltage of the transistor can be suppressed. Furthermore, fluctuation in electrical characteristics of the transistor is suppressed, whereby reliability can be increased.

[0206] The electrical characteristics and the reliability of the transistor vary depending on the composition of the metal oxide used for the oxide semiconductor layer 230. Thus, by making the composition of the metal oxide different in accordance with the electrical characteristics and the reliability required for the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0207] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably higher than or equal to the atomic ratio of M. As the atomic ratio of metal elements of such an In-M-Zn oxide, for example, In:M:Zn = 1:1:0.5, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:1:2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and the like, or compositions in the vicinity thereof can be given. Further, the composition in the vicinity includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or the field-effect mobility of the transistor, or the like can be increased.

[0208] The atomic ratio of In in the In-M-Zn oxide can also be lower than the atomic ratio of M. As the atomic ratio of metal elements of such an In-M-Zn oxide, for example, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and the like, or compositions in the vicinity thereof can be given. By increasing the proportion of the atomic number of M in the metal oxide, generation of oxygen vacancies can be suppressed.

[0209] Note that when a plurality of metal elements are included as the element M, the total of the proportions of the atomic numbers of the metal elements can be the proportion of the atomic number of the element M.

[0210] In this specification and the like, the proportion of the atomic number of indium with respect to the total of the atomic numbers of all the metal elements contained is sometimes referred to as the indium content. The same applies to other metal elements.

[0211] Further, in the case where the metal oxide is an In-Zn oxide, as the atomic ratio of metal elements of such an In-Zn oxide, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, and the like, or compositions in the vicinity thereof can be given. Further, the In-Zn oxide can include a small amount of the element M. For example, in the case where Sn is included as the element M, as the atomic ratio of metal elements of such a metal oxide, for example, In:Sn:Zn = 2:0.1:1, In:Sn:Zn = 4:0.1:1, and the like, or compositions in the vicinity thereof can be given.

[0212] As analysis of the composition of the metal oxide serving as the oxide semiconductor layer 230, for example, an energy dispersive X-ray spectrometry (EDX), an X-ray photoelectron spectrometry (XPS), an inductively coupled plasma-mass spectrometry (ICP-MS), or an inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used. Alternatively, a plurality of the above methods can be combined and used for analysis. Note that the content of an element with a low content ratio is sometimes affected by the analysis accuracy, and the actual content ratio can be different from the content ratio obtained by analysis. For example, when the content of the element M is low, the content of the element M obtained by analysis is sometimes lower than the actual content. Further, when it is difficult to quantitatively analyze the element M, the element M can not be detected.

[0213] The metal oxide can be formed by a sputtering method or an ALD method as appropriate. Note that in the case where the metal oxide is formed by a sputtering method, the composition of the metal oxide after deposition is sometimes different from that of the target. In particular, the content of zinc in the metal oxide after deposition is sometimes reduced to about 50 % of the content of zinc in the target. Further, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or the like can be used to deposit the metal oxide.

[0214] The oxide semiconductor layer 230 can also have a stacked structure including two or more metal oxide layers. The composition of the two or more metal oxide layers included in the oxide semiconductor layer 230 can be the same or substantially the same. By using a stacked structure of metal oxide layers with the same composition, the same sputtering target can be used, for example, so that the manufacturing cost can be reduced.

[0215] The composition of the two or more metal oxide layers included in the oxide semiconductor layer 230 can be different from one another.

[0216] FIG. 2A An example is shown in which the oxide semiconductor layer 230 has a two-layer structure of an oxide layer 230a and an oxide layer 230b over the oxide layer 230a.

[0217] For example, the oxide layer 230a preferably uses a material with higher conductivity than the oxide layer 230b. By using a material with higher conductivity for the oxide layer 230a in contact with the source and drain electrodes (the conductive layers 220 and 240), the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and thus a transistor with a large on-state current can be implemented.

[0218] In this case, in the case where a material with higher conductivity is used for the oxide layer 230b provided on the side of the conductive layer 260 serving as a gate electrode, the threshold voltage of the transistor 200A is sometimes shifted, and thus the drain current flowing when the gate voltage is 0 V (hereinafter also referred to as off-state current) becomes large. Specifically, in the case where the transistor 200A is an n-channel transistor, the threshold voltage is sometimes lowered. Thus, the oxide layer 230b preferably uses a material with lower conductivity than the oxide layer 230a. In the case where the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and thus a transistor with a small off-state current can be implemented. Note that a state where the off-state current is small is sometimes referred to as always off.

[0219] By making the oxide semiconductor layer 230 have a stacked-layer structure as described above and using a material with higher conductivity than the oxide layer 230b for the oxide layer 230a, a transistor that is always off and has a large on-state current can be implemented. Thus, a semiconductor device that has both low power consumption and high performance can be implemented.

[0220] Further, the carrier concentration of the oxide layer 230a is preferably higher than that of the oxide layer 230b. By increasing the carrier concentration of the oxide layer 230a, the conductivity is increased, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and thus a transistor with a large on-state current can be implemented. Further, by decreasing the carrier concentration of the oxide layer 230b, the conductivity is decreased, and thus a transistor that is always off can be implemented.

[0221] Note that the oxide semiconductor layer 230 is not limited to the above structure, and a material with lower conductivity than the oxide layer 230b can be used for the oxide layer 230a. Further, the carrier concentration of the oxide layer 230a can be lower than that of the oxide layer 230b.

[0222] Further, the band gap of the first metal oxide used for the oxide layer 230a is preferably different from that of the second metal oxide used for the oxide layer 230b. For example, the difference between the band gap of the first metal oxide and that of the second metal oxide is preferably 0.1 eV or more, further preferably 0.2 eV or more, and still further preferably 0.3 eV or more.

[0223] The band gap of the first metal oxide used for the oxide layer 230a is preferably smaller than the band gap of the second metal oxide used for the oxide layer 230b. By this means, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor with high on-state current can be achieved. Furthermore, in the case where the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and a normally-off transistor can be achieved. Moreover, since the band gap of the second metal oxide is large, generation and induction of carriers in the oxide layer 230b and at the interface between the oxide layer 230b and the insulating layer 250a can be suppressed. Thus, the reliability of the transistor can be improved.

[0224] For example, the content of the element M of the first metal oxide is preferably lower than that of the second metal oxide. Specifically, for example, a metal oxide with a composition of In:M:Zn = 1:1:1 [atom ratio] or its neighborhood is used as the oxide layer 230a, and a metal oxide with a composition of In:M:Zn = 1:3:2 [atom ratio] or its neighborhood is used as the oxide layer 230b. At this time, as the element M, one or more of gallium, aluminum, and tin is preferably used.

[0225] Note that the oxide semiconductor layer 230 is not limited to the above structure, and the band gap of the first metal oxide can be larger than that of the second metal oxide.

[0226] Furthermore, the content of the element M of the first metal oxide is preferably lower than that of the second metal oxide. The first metal oxide can contain a small amount of the element M or can not contain the element M. For example, the first metal oxide used for the oxide layer 230a is preferably an In-Zn oxide, and the second metal oxide used for the oxide layer 230b is preferably an In-M-Zn oxide. Specifically, the first metal oxide can be an In-Zn oxide, and the second metal oxide can be an In-Ga-Zn oxide.

[0227] For example, as the oxide layer 230a, a metal oxide of In:Zn = 1:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Zn = 2:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Sn:Zn = 2:0.1:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Zn = 4:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Sn:Zn = 4:0.1:1 [atomic ratio] or a neighborhood thereof, or an indium oxide is preferably used. Further, as the oxide layer 230b, a metal oxide of In:Ga:Zn = 1:1:1 [atomic ratio] or a neighborhood thereof, a metal oxide of In:Ga:Zn = 1:3:2 [atomic ratio] or a neighborhood thereof, or a metal oxide of In:Ga:Zn = 1:3:4 [atomic ratio] or a neighborhood thereof is preferably used. With this, the on-state current of the transistor 200A can be increased, and thus a transistor structure with low unevenness and high reliability can be achieved.

[0228] For example, in the case where a metal oxide is used for the conductive layer 220 or the conductive layer 240 (a layer in contact with the oxide semiconductor layer 230 in the case of a stacked-layer structure), an In-Zn oxide or an In-Sn-Zn oxide is preferably used for the oxide semiconductor layer 230 (or the oxide layer 230a), whereby the contact resistance can be reduced as compared to the case where an In-Ga-Zn oxide is used for the oxide semiconductor layer 230 (or the oxide layer 230a). For example, it is preferable that an indium tin oxide (also referred to as ITO) or an indium tin oxide to which silicon is added (also referred to as ITSO) be used for the layer of the conductive layer 220 or the conductive layer 240 which is in contact with the oxide semiconductor layer 230, an In-Zn oxide or an In-Sn-Zn oxide be used for the oxide layer 230a, and an In-Ga-Zn oxide be used for the oxide layer 230b.

[0229] The oxide semiconductor layer 230 is not limited to the above structure, and the content of the element M of the first metal oxide can be higher than that of the second metal oxide.

[0230] The oxide semiconductor layer 230 preferably includes a metal oxide layer having crystallinity. As a structure of a metal oxide having crystallinity, a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or an nc (nano-crystal) structure can be given, for example. By using a metal oxide layer having crystallinity for the oxide semiconductor layer 230, the density of defect states in the oxide semiconductor layer 230 can be reduced, and thus a semiconductor device with high reliability can be achieved.

[0231] The higher the crystallinity of the metal oxide layer used for the oxide semiconductor layer 230, the lower the defect state density in the oxide semiconductor layer 230 can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be implemented.

[0232] The higher the substrate temperature (stage temperature) at the time of formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer can be. Further, the higher the flow rate ratio of oxygen gas (hereinafter also referred to as oxygen flow ratio) to the entire deposition gas used at the time of formation, the higher the crystallinity of the metal oxide layer can be.

[0233] The crystallinity of the oxide semiconductor layer 230 can be analyzed by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), for example. Alternatively, a plurality of the above methods can be combined for analysis.

[0234] The oxide semiconductor layer 230 can also have a stacked-layer structure of two or more metal oxide layers with different crystallinity. For example, the oxide semiconductor layer can have a stacked-layer structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, and the second metal oxide layer can have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have a region with lower crystallinity than the first metal oxide layer. In this case, the compositions of the first and second metal oxide layers can be different, the same, or substantially the same.

[0235] For example, as the oxide layer 230a, a metal oxide with a composition of In:M:Zn = 1:3:2 [atom ratio] or its neighborhood or a metal oxide with a composition of In:M:Zn = 1:3:4 [atom ratio] or its neighborhood is preferably used, and as the oxide layer 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atom ratio] or its neighborhood is preferably used. By using a metal oxide with a large ratio of Zn to In as the oxide layer 230a, the crystallinity of the oxide layer 230a can be increased. Further, by forming the oxide layer 230b over the oxide layer 230a with high crystallinity, the crystallinity of the oxide layer 230b can be easily increased. Thus, the crystallinity of the entire oxide semiconductor layer 230 can be increased, which is preferable. In this case, as the element M, gallium, aluminum, or tin is particularly preferable. For example, two IGZO layers with different compositions from each other can be stacked. Further, for example, a stacked-layer structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0236] Further, the oxide semiconductor layer 230 can have a stacked-layer structure of three or more layers. For example, the oxide semiconductor layer 230 can have a three-layer structure including an oxide layer, the oxide layer 230a over the oxide layer, and the oxide layer 230b over the oxide layer 230a.

[0237] The oxide layer 230a and the oxide layer 230b can have the above structure. The oxide layer positioned under the oxide layer 230a can have the same structure as that of the oxide layer 230b. Hereinafter, a pair of oxide layers sandwiching the oxide layer 230a is described.

[0238] For example, as the oxide layer 230a, a metal oxide of an In:Zn = 1:1 [atomic ratio] or its neighborhood, a metal oxide of an In:Zn = 2:1 [atomic ratio] or its neighborhood, a metal oxide of an In:Sn:Zn = 2:0.1:1 [atomic ratio] or its neighborhood, a metal oxide of an In:Zn = 4:1 [atomic ratio] or its neighborhood, a metal oxide of an In:Sn:Zn = 4:0.1:1 [atomic ratio] or its neighborhood, or an indium oxide is preferably used. Further, as a pair of oxide layers sandwiching the oxide layer 230a, a metal oxide of an In:Ga:Zn = 1:1:1 [atomic ratio] or its neighborhood, a metal oxide of an In:Ga:Zn = 1:3:2 [atomic ratio] or its neighborhood, or a metal oxide of an In:Ga:Zn = 1:3:4 [atomic ratio] or its neighborhood is preferably used.

[0239] The band gaps of the pair of oxide layers sandwiching the oxide layer 230a are preferably each larger than that of the oxide layer 230a. By the pair of oxide layers having a larger band gap sandwiching the oxide layer 230a, the oxide layer 230a is mainly used as a current path (channel). By sandwiching the oxide layer 230a with the pair of oxide layers, the trap level at the interface of the oxide layer 230a and its vicinity can be reduced. Thus, an embedded channel type transistor in which a channel is away from an interface of an insulating layer can be implemented, and the field-effect mobility can be increased. Further, the influence of an interface state which can be formed on the back channel side can be reduced to suppress light degradation (e.g., photo-bias-temperature degradation) of the transistor, and the reliability of the transistor can be increased.

[0240] The thickness of the oxide semiconductor layer 230 is preferably greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 5 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 70 nm, more preferably greater than or equal to 15 nm and less than or equal to 70 nm, more preferably greater than or equal to 15 nm and less than or equal to 50 nm, and more preferably greater than or equal to 20 nm and less than or equal to 50 nm. In a transistor for a more miniaturized semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0241] Hydrogen contained in the oxide semiconductor sometimes reacts with oxygen bonded to a metal atom to generate water, and thus oxygen vacancies (V O ) are formed in the oxide semiconductor. O Further, a defect (hereinafter referred to as V O H) in which hydrogen enters an oxygen vacancy is used as a donor to generate an electron as a carrier. In addition, an electron as a carrier is sometimes generated because a part of hydrogen is bonded to oxygen bonded to a metal atom. Thus, a transistor using an oxide semiconductor containing a large amount of hydrogen easily has a normally-on characteristic (i.e., a threshold voltage is negative). Further, because hydrogen in the oxide semiconductor easily moves due to heat, an electric field, or the like, the reliability of a transistor can be reduced when the oxide semiconductor contains a large amount of hydrogen.

[0242] It is preferable to reduce V O H in the oxide semiconductor layer 230 as much as possible so that the oxide semiconductor layer 230 is high-purity intrinsic or substantially high-purity intrinsic. In order to obtain such an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies. By using an oxide semiconductor in which impurities such as V 18 H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be given. Note that the treatment in which oxygen is supplied to the oxide semiconductor to repair oxygen vacancies is referred to as oxidation treatment.

[0243] The carrier concentration of the oxide semiconductor used for the region serving as a channel formation region is preferably greater than or equal to 1 x 1010 -3 cm 17 -3 and less than or equal to 1 x 1012 -3 cm 16 -2, more preferably less than or equal to 1 x 1011 -3 cm 13 -1, and further preferably less than or equal to 1 x 1010 -3atoms / cm 12 atoms / cm -3 Note that the lower limit value of the carrier concentration of the oxide semiconductor used for the region serving as the channel formation region is not particularly limited, and for example, it can be set to 1 x 1010 -9 atoms / cm -3 .

[0244] Here, the influence of each impurity in a metal oxide (oxide semiconductor) is described.

[0245] When the oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor is set to 1 x 1010 20 atoms / cm 3 or higher, preferably 5 x 1010 19 atoms / cm 3 or higher, more preferably 3 x 1010 19 atoms / cm 3 or higher, more preferably 1 x 1010 19 atoms / cm 3 or higher, more preferably 3 x 1010 18 atoms / cm 3 or higher, further preferably 1 x 1010 18 atoms / cm 3 or lower. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor is set to 1 x 1010 20 atoms / cm 3 or higher, preferably 5 x 1010 19 atoms / cm 3 or higher, more preferably 3 x 1010 19 atoms / cm 3 or higher, more preferably 1 x 1010 19 atoms / cm 3 or higher, more preferably 3 x 1010 18 atoms / cm 3 or higher, further preferably 1 x 1010 18 atoms / cm 3 or lower.

[0246] Further, when the oxide semiconductor contains nitrogen, electrons serving as carriers are generated, so that the carrier concentration is increased, and the oxide semiconductor is easily n- doped. As a result, a transistor using an oxide semiconductor containing nitrogen easily has a normally-on characteristic. Alternatively, when the oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electric characteristics of the transistor are sometimes unstable. Thus, the concentration of nitrogen in the channel formation region of the oxide semiconductor is preferably set to be lower than or equal to 1 x 10 20 atoms / cm 3 Further, the concentration of nitrogen in the channel formation region of the oxide semiconductor is preferably set to be lower than or equal to 5 x 10 19 atoms / cm 3 Further, the concentration of nitrogen in the channel formation region of the oxide semiconductor is more preferably set to be lower than or equal to 1 x 10 19 atoms / cm 3 Further, the concentration of nitrogen in the channel formation region of the oxide semiconductor is more preferably set to be lower than or equal to 5 x 10 18 atoms / cm 3 Further, the concentration of nitrogen in the channel formation region of the oxide semiconductor is more preferably set to be lower than or equal to 1 x 10 18 atoms / cm 3 Further, the concentration of nitrogen in the channel formation region of the oxide semiconductor is further preferably set to be lower than or equal to 5 x 10 17 atoms / cm 3 .

[0247] Further, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, and thus an oxygen vacancy is sometimes formed. When hydrogen enters the oxygen vacancy, an electron serving as a carrier is sometimes generated. Further, an electron serving as a carrier is sometimes generated because a part of hydrogen is bonded to oxygen bonded to a metal atom. Thus, a transistor using an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Thus, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the concentration of hydrogen in the channel formation region of the oxide semiconductor is preferably set to be lower than or equal to 1 x 10 20 atoms / cm 3 , more preferably lower than or equal to 5 x 10 19 atoms / cm 3 , further more preferably lower than or equal to 1 x 10 19 atoms / cm 3 , still more preferably lower than or equal to 5 x 10 18 atoms / cm 3 , and even more preferably lower than or equal to 1 x 10 18 atoms / cm 3 .

[0248] Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a trap state is sometimes formed to generate a carrier. Thus, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has a normally-on characteristic. Thus, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor is preferably set to be lower than or equal to 1 x 1018 atoms / cm 3 The following is preferably 2 x 10 16 atoms / cm 3 The following is preferably 2 x 10

[0249] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, a transistor with stable electric characteristics can be obtained.

[0250] In addition, a transistor using another semiconductor material in the channel formation region can be used for the semiconductor device of this embodiment. As the other semiconductor material, for example, a semiconductor composed of a single element or a compound semiconductor can be given. As the semiconductor composed of a single element, for example, silicon or germanium can be given. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be given. In addition, as the compound semiconductor, for example, an organic semiconductor and a nitride semiconductor can be given. Note that the above oxide semiconductor is one of the compound semiconductors. Further, these semiconductor materials can include impurities as dopants.

[0251] As the silicon which can be used as a semiconductor material of a transistor, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be given. As the polycrystalline silicon, for example, low-temperature polysilicon (LTPS: Low Temperature Poly Silicon) can be given.

[0252] The semiconductor layer of the transistor can also include a layered material which functions as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by a bond such as a van der Waals bond which is weaker than a covalent bond and an ionic bond. The layered material has high conductivity in a unit layer, i.e., has high two-dimensional conductivity. By using a material which functions as a semiconductor and has high two-dimensional conductivity for a channel formation region, a transistor with a large on-state current can be provided.

[0253] As the above layered material, for example, graphene, silicene, a chalcogenide, and the like can be given. The chalcogenide is a compound including an oxygen group element (a group 16 element). In addition, as the chalcogenide, a transition metal chalcogenide, a group 13 chalcogenide, and the like can be given. The transition metal chalcogenide which can be used for the semiconductor layer of the transistor can be specifically given as molybdenum sulfide (typically, MoS2), molybdenum selenide (typically, MoSe2), molybdenum telluride (typically, MoTe2), tungsten sulfide (typically, WS2), tungsten selenide (typically, WSe2), tungsten telluride (typically, WTe2), hafnium sulfide (typically, HfS2), hafnium selenide (typically, HfSe2), zirconium sulfide (typically, ZrS2), zirconium selenide (typically, ZrSe2), and the like.

[0254] [Insulating layer]

[0255] As the insulating layer (the insulating layer 210, the insulating layer 250a, the insulating layer 250b, the insulating layer 280, the insulating layer 285, and the like) included in the semiconductor device, an inorganic insulating film is preferably used. As the inorganic insulating film, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film can be given. As the silicon oxide film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film can be given. As the silicon nitride film, for example, a silicon nitride film and an aluminum nitride film can be given. As the silicon oxynitride film, for example, a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and a hafnium oxynitride film can be given. As the silicon nitride oxide film, for example, a silicon nitride oxide film and an aluminum nitride oxide film can be given. Further, as the insulating layer included in the semiconductor device, an organic insulating film can be used.

[0256] For example, when miniaturization and high integration of a transistor are performed, a problem such as a leakage current is sometimes caused due to thinning of a gate insulating layer. By using a high-k material as the gate insulating layer, low voltage during operation of the transistor can be achieved while the physical thickness is maintained. Further, an equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with low relative dielectric constant for an insulating layer serving as an interlayer film, a parasitic capacitance generated between wirings can be reduced. Thus, it is preferable to select a material depending on a function of the insulating layer. Further, a material with low relative dielectric constant is also a material with high dielectric strength.

[0257] As a material with high relative dielectric constant (high-k), for example, an aluminum oxide, a gallium oxide, a hafnium oxide, a tantalum oxide, a zirconium oxide, a hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be given.

[0258] As a material with low relative dielectric constant, for example, an inorganic insulating material such as a silicon oxide, a silicon oxynitride, and a silicon nitride oxide, a resin such as a polyester, a polyolefin, a polyamide (nylon, an aromatic polyamide, and the like), a polyimide, a polycarbonate, and an acrylic resin can be given. Further, as the inorganic insulating material with low relative dielectric constant, for example, a silicon oxide to which fluorine is added, a silicon oxide to which carbon is added, a silicon oxide to which carbon and nitrogen are added, and the like can be given. Further, a porous silicon oxide can be given. Further, these silicon oxides can contain nitrogen.

[0259] Further, as the insulating layer included in the semiconductor device, a material which can have ferroelectricity can be used. As the material which can have ferroelectricity, a hafnium oxide, a zirconium oxide, HfZrO X(X is a real number greater than 0) and the like. Further, as a material that can have ferroelectricity, a material to which an element J1 (here, the element J1 is one or a plurality of elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to hafnium oxide can be given. Here, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be appropriately set, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set to 1:1 or the vicinity thereof. Further, as a material that can have ferroelectricity, a material to which an element J2 (here, the element J2 is one or a plurality of elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to zirconium oxide or the like can be given. Further, the ratio of the number of atoms of zirconium to the number of atoms of the element J2 can be appropriately set, and for example, the ratio of the number of atoms of zirconium to the number of atoms of the element J2 can be set to 1:1 or the vicinity thereof. Further, as a material that can have ferroelectricity, a lead titanate (PbTiO X

[0260] Further, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2, and nitrogen can be given. Here, the element M1 is one or a plurality of elements selected from aluminum, gallium, indium, and the like. Further, the element M2 is one or a plurality of elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Further, the ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be appropriately set. Further, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if the element M2 is not contained. Further, as a material that can have ferroelectricity, a material to which an element M3 is added to the above-described metal nitride can be given. Note that the element M3 is one or a plurality of elements selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of the element M1, the element M2, and the element M3 can be appropriately set.

[0261] Further, as a material that can have ferroelectricity, a perovskite-type oxynitride such as SrTaO2N, BaTaO2N, and the like, GaFeO3 which is a κ-type aluminum oxide, and the like can be given.

[0262] Note that in the above description, although examples of a metal oxide and a metal nitride are shown, the present technology is not limited thereto. For example, a metal oxynitride to which nitrogen is added to the above-described metal oxide or a metal nitride oxide to which oxygen is added to the above-described metal nitride or the like can be used.

[0263] ​Further, as a material which can have ferroelectricity, for example, a mixture or a compound composed of a plurality of materials selected from the above-described materials can be used. Further, the insulating layer can have a stacked structure composed of a plurality of materials selected from the above-described materials. Note that the crystal structure (property) of the above-described listed materials and the like can be changed not only depending on deposition conditions but also depending on various processes and the like, and thus in this specification and the like, a material exhibiting ferroelectricity is not only referred to as a ferroelectric but also as a material which can have ferroelectricity.

[0264] A metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if it is processed into a thin film of several nm. Further, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if its area is small. Thus, by using a metal oxide containing one or both of hafnium and zirconium, miniaturization of a semiconductor device can be achieved.

[0265] Note that in this specification and the like, a material which can have ferroelectricity formed in a layer is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Further, in this specification and the like, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0266] Further, ferroelectricity is considered to be exhibited because oxygen or nitrogen of a crystal included in a ferroelectric layer is displaced by an applied electric field. Further, it is estimated that the exhibition of ferroelectricity depends on the crystal structure of a crystal included in a ferroelectric layer. Thus, in order for an insulating layer to exhibit ferroelectricity, the insulating layer needs to include a crystal. In particular, the insulating layer preferably includes a crystal having an orthorhombic crystal structure, whereby ferroelectricity is exhibited. The crystal structure of a crystal included in an insulating layer can be one or more selected from a cubic crystal system, a tetragonal crystal system, an orthorhombic crystal system, a monoclinic crystal system, and a hexagonal crystal system. Further, the insulating layer can have an amorphous structure. At this time, the insulating layer can have a composite structure of an amorphous structure and a crystal structure.

[0267] Further, by adding a Group 3 element (also referred to as IIIa element) in the periodic table to the oxide containing one or both of hafnium and zirconium, the concentration of oxygen vacancies in the oxide increases, whereby a crystal having an orthorhombic crystal structure is easily formed. Thus, the proportion of the crystal having an orthorhombic crystal structure increases, and the remanent polarization can be enhanced, so it is preferable. On the other hand, when the amount of the Group 3 element added is too much, the crystallinity of the oxide can decrease, whereby ferroelectricity can not be easily exhibited. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and further preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the proportion of the number of atoms of the Group 3 element in the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0268] Further, by surrounding the transistor using a metal oxide with an insulating layer having a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, a single layer or a stack of an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as the material of the insulating layer having a function of suppressing the permeation of impurities and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, an aluminum nitride, silicon nitride oxide, and a silicon nitride can be used.

[0269] Specifically, as the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be given. Further, as the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be given. Further, as the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, a metal nitride such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon nitride oxide, and silicon nitride can be given.

[0270] Further, an insulating layer in contact with the oxide semiconductor layer, such as a gate insulating layer, or an insulating layer provided in the vicinity of the oxide semiconductor layer preferably has a region containing oxygen which is released by heating (hereinafter referred to as excess oxygen). For example, by bringing the insulating layer having a region containing excess oxygen into contact with or in the vicinity of the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. As the insulating layer in which a region containing excess oxygen is easily formed, silicon oxide, silicon oxynitride, silicon oxide having a vacancy, or the like can be given.

[0271] The insulating layer 210 is used as an interlayer film, and thus its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Since silicon oxide and silicon oxynitride have thermal stability, they are suitable for use as the insulating layer 210.

[0272] Further, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. By this means, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230 can be inhibited.

[0273] Further, as the insulating layer 210, a hydrogen-blocking insulating layer is preferably used. By providing the insulating layer 210 which is outside the oxide semiconductor layer 230 with hydrogen-blocking properties, the diffusion of hydrogen into the oxide semiconductor layer 230 can be inhibited.

[0274] As a material of the hydrogen-blocking insulating layer, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, silicon nitride oxide, or the like can be given.

[0275] Note that in this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. Further, the barrier properties refer to a property of not easily allowing the diffusion of a corresponding substance (also referred to as a property of not easily allowing the passage of a corresponding substance, a property of low permeability to a corresponding substance, or a function of inhibiting the diffusion of a corresponding substance). Further, hydrogen referred to as a corresponding substance, for example, refers to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, and a substance which is bonded to hydrogen, and the like. Further, unless particularly stated otherwise, an impurity referred to as a corresponding substance refers to an impurity in a channel formation region or a semiconductor layer, and for example, refers to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), a copper atom, and the like. Further, oxygen referred to as a corresponding substance, for example, refers to at least one of an oxygen atom and an oxygen molecule. -

[0276] For example, as the insulating layer 210, a silicon nitride film is preferably used.

[0277] ​The insulating layer 280 preferably includes the hydrogen-blocking insulating layer described above. The insulating layer 280 is provided in a manner so as to surround the oxide semiconductor layer 230. By providing the insulating layer 280 having hydrogen-blocking properties outside the oxide semiconductor layer 230, diffusion of hydrogen into the oxide semiconductor layer 230 can be inhibited. For example, the insulating layer 280 preferably includes one or both of an aluminum oxide film and a silicon nitride film.

[0278] Further, silicon nitride has oxygen-blocking properties. Thus, by using silicon nitride for the insulating layer 280, extraction of oxygen from the oxide semiconductor layer 230 and formation of excess oxygen vacancies in the oxide semiconductor layer 230 can be inhibited.

[0279] Further, by using silicon nitride for the insulating layer 280, excess oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Thus, oxygen excess in the channel formation region of the oxide semiconductor layer 230 can be prevented, so that the reliability of the transistor 200A can be improved.

[0280] Further, the insulating layer 280 preferably includes the oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen described above.

[0281] For example, the insulating layer having a region containing excess oxygen can be formed by a sputtering method in an atmosphere containing oxygen. By using a sputtering method that does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing at least a part of the insulating layer 280, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, and oxygen vacancies and VoH can be reduced.

[0282] Further, the impurity concentration of water, hydrogen, or the like in the insulating layer 280 is preferably reduced. Thus, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230 can be inhibited.

[0283] Note that the thickness of the insulating layer 280 over the conductive layer 220 corresponds to the channel length of the transistor 200A, and thus the thickness of the insulating layer 280 is set as appropriate in accordance with the design value of the channel length of the transistor 200A.

[0284] For example, as the insulating layer 280, a single-layer structure of a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film is preferably used. Alternatively, for example, as the insulating layer 280, a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are sequentially stacked is preferably used. For example, as the insulating layer 280, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are sequentially stacked is preferably used.

[0285] One or both of the insulating layer 250a and the insulating layer 250b preferably has a function of trapping and fixing hydrogen. By this means, the hydrogen concentration of the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Thus, the V O H to make the channel formation region i-type or substantially i-type.

[0286] As a material of the insulating layer having a function of trapping or fixing hydrogen, a metal oxide such as an oxide containing hafnium, an oxide containing magnesium, an oxide containing aluminum, an oxide containing aluminum and hafnium (hafnium aluminate), and the like can be given. Further, the metal oxide can contain zirconium, for example, an oxide containing hafnium and zirconium, and the like can be given. Here, in the metal oxide having an amorphous structure, a part of oxygen atoms has a dangling bond, and thus the ability of trapping or fixing hydrogen is high. Thus, the metal oxide preferably has an amorphous structure. For example, by containing silicon in the oxide, an amorphous structure can be achieved. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Further, a part of the metal oxide sometimes has one or both of a crystal region and a grain boundary.

[0287] Further, the function of trapping or fixing the corresponding substance can be said to have a property that the corresponding substance is less likely to diffuse. Thus, the function of trapping or fixing the corresponding substance can be referred to as a barrier property.

[0288] FIG. 2A An example in which a layer serving as a gate insulating layer has a three-layer structure of the insulating layer 250a, the insulating layer 250b1 over the insulating layer 250a, and the insulating layer 250b2 over the insulating layer 250b1 is shown.

[0289] In the case where the gate insulating layer has a stacked-layer structure, a layer in contact with the oxide semiconductor layer 230 preferably has a function of trapping and fixing hydrogen. That is, in the case where the gate insulating layer has a stacked-layer structure, the insulating layer 250a is preferably in contact with the oxide semiconductor layer 230. FIG. 2A In the case where the gate insulating layer has a stacked-layer structure, a layer in contact with the oxide semiconductor layer 230 preferably has a function of trapping and fixing hydrogen. That is, in the case where the gate insulating layer has a stacked-layer structure, the insulating layer 250a is preferably in contact with the oxide semiconductor layer 230.

[0290] Further, the insulating layer 250a is used as an etching stopper layer when the opening portion 270 is formed in the insulating layer 285, and thus a material having a high etching selectivity with respect to the insulating layer 285 is used as the insulating layer 250a. For example, it is preferable that hafnium oxide, hafnium silicate, aluminum oxide, or silicon nitride be used as the insulating layer 250a and silicon oxide be used as the insulating layer 285.

[0291] Further, as the insulating layer 250b, the above hydrogen-blocking insulating layer is preferably used. By using a hydrogen-blocking insulating layer as the insulating layer 250b, diffusion of impurities included in the conductive layer 260 to the oxide semiconductor layer 230 can be inhibited. For example, silicon nitride has high hydrogen-blocking properties and is thus suitable for use as the insulating layer 250b. Furthermore, the insulating layer 250b can include an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride. For example, it is preferable that silicon oxide be used as the insulating layer 250b1 and silicon nitride be used as the insulating layer 250b2.

[0292] With such a structure, a semiconductor device with good electrical characteristics can be provided. Further, a highly reliable semiconductor device can be provided. Furthermore, a semiconductor device in which the electrical characteristics of transistors are less likely to be non-uniform can be provided. Further, a semiconductor device with a large on-state current can be provided.

[0293] Further, one or both of the insulating layer 250a and the insulating layer 250b preferably include an oxygen-blocking insulating layer. By this means, oxidation of the conductive layer 240 and the conductive layer 260 and the like can be inhibited. In the case where the insulating layer 250a has a stacked-layer structure, the layer in contact with the conductive layer 240 is preferably an oxygen-blocking insulating layer. In particular, the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 among the layers included in the insulating layer 250a and the insulating layer 250b are preferably both oxygen-blocking insulating layers.

[0294] For example, by using a hydrogen- and oxygen-blocking insulating layer as the insulating layer 250b, oxidation of the conductive layer 260 can be inhibited. Further, formation of oxygen vacancies in the oxide semiconductor layer 230 due to diffusion of oxygen included in the oxide semiconductor layer 230 to the conductive layer 260 can be inhibited.

[0295] As the oxygen-blocking insulating layer, for example, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium-zinc oxide, silicon nitride, and silicon oxynitride can be given. Further, as the oxide containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be given.

[0296] The layer in the insulating layer 250a in contact with the conductive layer 240 is preferably less likely to transmit oxygen than the insulating layer 280. When the layer has oxygen-blocking properties, formation of an oxide film on the side surface of the conductive layer 240 due to oxidation of the side surface can be inhibited. Thus, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200A can be inhibited.

[0297] Further, the insulating layer 250a and the insulating layer 250b are preferably thin films. For example, by setting the thickness of the insulating layer 250a and the insulating layer 250b to be greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 3 nm and less than or equal to 10 nm, a subthreshold swing value (also referred to as S value) which is one of transistor characteristics can be reduced. Note that the S value refers to the amount of change in the gate voltage when the drain current is changed by one digit at a constant drain voltage in a subthreshold region.

[0298] Further, the thickness of each layer included in the insulating layer 250a and the insulating layer 250b is preferably small. The thickness of each layer included in the insulating layer 250a and the insulating layer 250b is greater than or equal to 0.1 nm and less than or equal to 10 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 5 nm, more preferably greater than or equal to 0.5 nm and less than or equal to 5 nm, more preferably greater than or equal to 1 nm and less than 5 nm, and further preferably greater than or equal to 1 nm and less than or equal to 3 nm. Note that at least a part of each layer included in the insulating layer 250a and the insulating layer 250b can include a region having the above thickness.

[0299] The insulating layer 285 is used as an interlayer film, and thus a material with a low relative dielectric constant described above is preferably used. For example, the insulating layer 285 preferably has a silicon oxide film.

[0300] [Conductive Layer]

[0301] As a conductive layer (the conductive layer 220, the conductive layer 240, the conductive layer 260, the conductive layer 265, and the like) included in a semiconductor device, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy including the above metal element, or an alloy including a plurality of the above metal elements, and the like is preferably used. As the alloy including the above metal element, a nitride of the alloy or an oxide of the alloy can be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride including titanium and aluminum, a nitride including tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide including strontium and ruthenium, an oxide including lanthanum and nickel, and the like are preferably used. Further, a semiconductor having high conductivity typified by polysilicon including an impurity element such as phosphorus and a silicide such as nickel silicide can be used.

[0302] Further, a conductive material containing nitrogen such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum, a conductive material containing oxygen such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, and a material containing a metal element such as titanium, tantalum, or ruthenium is a conductive material which is not easily oxidized, a conductive material having a function of inhibiting diffusion of oxygen, or a material which absorbs oxygen and maintains conductivity, and is thus preferable. As the conductive material containing oxygen, for example, an indium oxide containing tungsten oxide, an indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), an indium tin oxide containing titanium oxide, indium tin oxide to which silicon is added (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and an indium zinc oxide containing tungsten oxide can be given. In this specification and the like, a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0303] A conductive material whose main component is tungsten, copper, or aluminum has high conductivity and is thus preferable.

[0304] Further, a plurality of conductive layers formed of the above-described materials can be stacked. For example, a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined can be employed. Further, a stacked structure in which a material containing the above-described metal element and a conductive material containing nitrogen are combined can be employed. Further, a stacked structure in which a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined can be employed.

[0305] Further, in the case where a metal oxide is used for a channel formation region of a transistor, a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is preferably employed for a conductive layer used as a gate electrode. In this case, the conductive material containing oxygen is preferably provided on the side of the channel formation region. By providing the conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.

[0306] The conductive layer 220 and the conductive layer 240 are both conductive layers in contact with the oxide semiconductor layer 230, and thus a conductive material which is not easily oxidized, a conductive material which maintains low resistance even if oxidized, an oxide conductive material, or a conductive material having a function of inhibiting diffusion of oxygen is preferably used. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be given. By this means, the conductivity of the conductive layer 220 and the conductive layer 240 can be inhibited from decreasing.

[0307] By using a conductive material containing oxygen as the conductive layer 220 or the conductive layer 240, even if the conductive layer 220 or the conductive layer 240 absorbs oxygen, the conductivity can be maintained. Further, in the case where an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 can maintain the conductivity, and is thus preferable. As the conductive layer 220 and the conductive layer 240, for example, ITO, ITSO, IZO (registered trademark), or the like is preferably used.

[0308] FIG. 2B An example in which the conductive layer 220 has a three-layer structure of a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, and a conductive layer 220c over the conductive layer 220b is shown. At this time, for example, it is preferable that a conductive material which is not easily oxidized or a conductive material having a function of suppressing diffusion of oxygen be used as the conductive layer 220a, a material having high conductivity be used as the conductive layer 220b, and a conductive material containing oxygen be used as the conductive layer 220c. Specifically, for example, it is preferable that titanium nitride be used as the conductive layer 220a, tungsten be used as the conductive layer 220b, and ITO or ITSO be used as the conductive layer 220c. In this case, the titanium nitride is in contact with the insulating layer 210, and the ITO or the ITSO is in contact with the oxide semiconductor layer 230. With such a structure, even if the conductive layer 220 is in contact with the oxide semiconductor layer 230, the conductivity can be maintained. Further, in the case where an oxide insulating layer is used as the insulating layer 210, the conductive layer 220 can be prevented from being excessively oxidized by the insulating layer 210. Furthermore, by using tungsten having high conductivity as the conductive layer 220b, the conductivity of the conductive layer 220 can be increased.

[0309] FIG. 2A and FIG. 3A An example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b over the conductive layer 240a is shown. At this time, it is preferable that a material having higher conductivity than the conductive layer 240b be used as the conductive layer 240a and a conductive material containing oxygen be used as the conductive layer 240b, for example. Specifically, it is preferable that ruthenium, tungsten, titanium nitride, or tantalum nitride be used as the conductive layer 240a and ITO or ITSO be used as the conductive layer 240b, for example. In this case, the area of the oxide semiconductor layer 230 in contact with the conductive layer 240b is larger than the area in contact with the conductive layer 240a, and the ITO or the ITSO is mainly in contact with the oxide semiconductor layer 230. With such a structure, even if the conductive layer 240 is in contact with the oxide semiconductor layer 230, the conductivity can be maintained. Furthermore, by using a material having higher conductivity than the conductive layer 240b as the conductive layer 240a, the conductivity of the conductive layer 240 can be increased.

[0310] As the conductive layer 260, a material with high conductivity such as tungsten is preferably used. Further, as the conductive layer 260, a conductive material which is not easily oxidized or a conductive material which has a function of suppressing diffusion of oxygen, or the like is preferably used. As the conductive material, a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide) can be given, as described above. Thus, the conductivity of the conductive layer 260 can be suppressed from decreasing.

[0311] In addition, as the conductive layer 260, a conductive material containing a metal element and oxygen included in the metal oxide in which the channel is formed is preferably used. Further, a conductive material containing the above metal element and nitrogen (e.g., titanium nitride, tantalum nitride, or the like) can be used. Further, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added can be used. Further, indium gallium zinc oxide containing nitrogen can be used. By using the above material, hydrogen included in the metal oxide in which the channel is formed can be sometimes trapped. Alternatively, hydrogen mixed from the outside from the insulating layer or the like can be sometimes trapped.

[0312] FIG. 3B An example in which the conductive layer 260 has a two-layer structure of a conductive layer 260a and a conductive layer 260b over the conductive layer 260a is shown. At this time, for example, it is preferable that titanium nitride be used as the conductive layer 260a and tungsten be used as the conductive layer 260b. Alternatively, it is preferable that tantalum nitride be used as the conductive layer 260a and copper be used as the conductive layer 260b. By adopting such a structure, the conductivity of the conductive layer 260 can be increased.

[0313] Further, the conductive layer 260 can have a stacked-layer structure of three or more layers. The conductive layer 260 can have, for example, a three-layer structure of tantalum nitride, titanium nitride over the tantalum nitride, and tungsten over the titanium nitride.

[0314] Since the conductive layer 265 is a layer used as a gate wiring, it is preferable to have high conductivity. The conductive layer 265 preferably uses tungsten. Further, the conductive layer 265 can have the same structure as the conductive layer 260. For example, a two-layer structure of titanium nitride and tungsten can be adopted.

[0315] [Substrate]

[0316] As a substrate for forming a transistor, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. As an insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (a yttria-stabilized zirconia substrate or the like), a resin substrate, or the like can be given. Further, as a semiconductor substrate, a semiconductor substrate using silicon or germanium as a material, or a compound semiconductor substrate formed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like can be given. Further, a semiconductor substrate having an insulator region in the above-described semiconductor substrate, such as an SOI (Silicon On Insulator) substrate or the like can be given. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like can be given. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, or the like can be given. Further, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be given. Alternatively, a substrate provided with an element on the above-described substrate can be used. As an element provided on a substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like can be given.

[0317] <Structure Example 2 of Semiconductor Device>

[0318] The structure of a semiconductor device of another embodiment of the present application will be described with reference to FIGS. 3 to 11.

[0319] [Transistor 200B and Transistor 200C]

[0320] FIG. 4A and FIG. 4B is a cross-sectional view of a semiconductor device including the transistor 200B. FIG. 3B and FIG. 4B is a cross-sectional view of a semiconductor device including the transistor 200C. FIG. 1A and FIG. 3C are cross-sectional views along the dot-and-dash line Al-A2 shown in FIG. 6A. FIG. 4C and FIG. 1A are cross-sectional views along the dot-and-dash line A3-A4 shown in FIG. 6B. Note that the above-described FIG. 1D corresponds to a cross-sectional view between the dot-and-dash lines A5-A6 shown in FIG. 6C. FIG. 3A FIG. 3B FIG. 4A FIG. 4B FIG. 3A and FIG. 3B are cross-sectional views along the dot-and-dash line A5-A6 shown in FIG. 6C.

[0321] FIG. 4A and FIG. 4B are cross-sectional views of a semiconductor device and FIGS. 1A-1D and FIG. 4A ​​​​The semiconductor device shown does not include the insulating layer 280 but includes the insulating layer 280a and the insulating layer 280b, which is different from the semiconductor device shown in FIG. 4B The semiconductor device shown is different from the semiconductor device shown in

[0322] In the semiconductor device shown in FIG. 3A and FIG. 3B The top surface of the insulating layer 280a is planarized in the semiconductor device shown in FIG. 3C and FIG. 3A The semiconductor device shown is different from the semiconductor device shown in

[0323] The insulating layer 280a is provided over the insulating layer 210 and the conductive layer 220, and the insulating layer 280b is provided over the insulating layer 280a. The insulating layer 280a and the insulating layer 280b are provided with an opening portion 290 reaching the top surface of the conductive layer 220.

[0324] FIG. 4C is an enlarged view of the region P2 surrounded by a dashed line in FIG. 4A FIG. 3C is an enlarged view of the region P3 surrounded by a dashed line in FIG. 4C

[0325] As shown in FIG. 2B and FIGS. 16A-16C The angle θc formed by the side surface of the opening portion 290 of the insulating layer 280a and the top surface of the insulating layer 210 is preferably smaller than the angle θd formed by the side surface of the opening portion 290 of the insulating layer 280b and the top surface of the insulating layer 210. By employing such a structure, the opening portion 290 can be formed so that the opening portion 290 does not reach the top surface of the insulating layer 210 and the width D is larger than the width of the conductive layer 220. Thus, it is easy to manufacture a transistor of a structure in which parasitic capacitance is reduced, and thus is preferable. Further, as shown in FIGS. 17A-17E and the like, the thickness of the structure in which the insulating layer 280a and the insulating layer 280b are stacked is higher in controllability than the structure in which the insulating layer 280 has the first surface and the second surface, and the channel length is easy to control, and thus is preferable. Note that a method for manufacturing a semiconductor device including the transistor 200B will be described later (see FIG. 5A ). Similarly, a method for manufacturing a semiconductor device including the transistor 200C will be described later (see FIG. 5B ).

[0326] The angle θc is preferably greater than or equal to 65 degrees and less than or equal to 90 degrees. More preferably, both the angle θc and the angle θd are greater than or equal to 65 degrees and less than or equal to 90 degrees.

[0327] ​​Insulating layers 280a and 280b can each be made of materials suitable for insulating layer 280. Insulating layer 280a uses a material with a high etch selectivity compared to insulating layer 280b. For example, it is preferred that silicon nitride, hafnium oxide, or aluminum oxide is used as insulating layer 280a, and silicon oxide is used as insulating layer 280b.

[0328] [Transistor 200D]

[0329] FIG. 5A and FIG. 1A It is a cross-sectional view of a semiconductor device including transistor 200D. FIG. 5B It is along FIG. 1A The cross-sectional view of the dotted line A1-A2 shown. FIG. 1D It is along FIG. 5A The cross-sectional view of the dotted-dotted lines A3-A4 is shown. Furthermore, the above... FIG. 5B It is along FIG. 5A and FIG. 5B The cross-sectional view shown is the dotted-dash line A5-A6.

[0330] FIGS. 1A-1D and FIG. 5A The semiconductor device shown is FIG. 5B The semiconductor device shown differs in that it includes insulating layers 280a, 280b, and 280c but does not include insulating layer 280.

[0331] exist FIG. 5C and FIG. 5D The insulating layer 280 in the semiconductor device shown includes an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.

[0332] Insulating layer 280a has a region that contacts the top surface of insulating layer 210, a region that contacts the side surface of conductive layer 220, and a region that contacts the top surface of conductive layer 220. Insulating layer 280c has a region that contacts the bottom surface of conductive layer 240.

[0333] The insulating layer 280b is in contact with the channel formation region of the oxide semiconductor layer 230. By using an oxygen-containing insulating layer as the insulating layer 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0334] The insulating layer 280b preferably has a region with a higher oxygen content compared to at least one of the insulating layers 280a and 280c. In particular, the insulating layer 280b preferably has a region with a higher oxygen content compared to each of the insulating layers 280a and 280c. By increasing the oxygen content of the insulating layer 280b, it is easier to form an i-type region in the oxide semiconductor layer 230 near the insulating layer 280b.

[0335] As the insulating layer 280b, a film that releases oxygen by heating is more preferably used. Since the insulating layer 280b releases oxygen by heating in the manufacturing process of the transistor 200D, oxygen can be supplied to the oxide semiconductor layer 230. By supplying oxygen from the insulating layer 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and V O H, a transistor with good electric characteristics and high reliability can be implemented.

[0336] Further, in order to improve the electric characteristics and the reliability of the OS transistor, it is important to optimize the amount of oxygen supplied to the oxide semiconductor in a state where the hydrogen concentration in the oxide semiconductor is sufficiently reduced.

[0337] Especially in the case where the channel length of the transistor 200D is short, oxygen vacancies and V O H have a particularly large effect on the electric characteristics and the reliability. Thus, by optimizing the amount of oxygen supplied to the oxide semiconductor layer 230 in a state where the hydrogen concentration in the oxide semiconductor layer 230 is sufficiently reduced, a short-channel-length transistor with good electric characteristics and high reliability can be implemented.

[0338] The insulating layer 280b is preferably formed by a deposition method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, when a sputtering method is used, hydrogen need not be used as a deposition gas, whereby a film with a very small amount of hydrogen can be implemented. Thus, the supply of hydrogen to the oxide semiconductor layer 230 can be inhibited, leading to stabilization of the electric characteristics of the transistor 200D.

[0339] In the case where the amount of oxygen supplied to the oxide semiconductor layer 230 is increased, for example, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere is preferably performed after the formation of the insulating layer 280b. Further, an oxide film can be deposited on the top surface of the insulating layer 280b by a sputtering method in an oxygen atmosphere to supply oxygen. Then, the oxide film can be removed. By such treatment, oxygen can be supplied to the insulating layer 280b to increase the amount of oxygen supplied to the oxide semiconductor layer 230.

[0340] Furthermore, in the oxide semiconductor layer 230, the oxygen supply to the regions contacting the insulating layers 280a and 280c is smaller compared to the region contacting the insulating layer 280b. Therefore, the regions of the oxide semiconductor layer 230 contacting the insulating layers 280a and 280c are sometimes made to have low resistance. In other words, by adjusting the thickness of the insulating layer 280a, the range of the region used as one of the source and drain regions can be controlled. Similarly, by adjusting the thickness of the insulating layer 280c, the range of the other region used as the source and drain regions can be controlled. Thus, the thicknesses of the insulating layers 280a and 280c can be appropriately set according to the required characteristics of the transistor.

[0341] Furthermore, a material with a low relative permittivity is preferably used as the insulating layer 280b. This reduces parasitic capacitance generated between wirings. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280b.

[0342] Oxygen-barrier insulating layers are preferably used as insulating layers 280a and 280c. By providing insulating layer 280a between insulating layer 280b and conductive layer 220, the increase in resistance of conductive layer 220 due to oxidation of conductive layer 220 can be suppressed. Furthermore, by providing insulating layer 280c between insulating layer 280b and conductive layer 240, the increase in resistance of conductive layer 240 due to oxidation of conductive layer 240 can be suppressed.

[0343] Furthermore, an insulating layer with hydrogen trapping or fixing function can be used as insulating layer 280a. By employing this structure, hydrogen diffusion from below insulating layer 280a to oxide semiconductor layer 230 can be suppressed, and hydrogen contained in oxide semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in oxide semiconductor layer 230 can be reduced. Magnesium oxide, aluminum oxide, hafnium oxide, or oxides containing hafnium and silicon can be used as insulating layer 280a. Furthermore, for example, a laminate of aluminum oxide and silicon nitride on the aluminum oxide can be used as insulating layer 280a. Similarly, an insulating layer with hydrogen trapping or fixing function can be used as insulating layer 280c.

[0344] For example, silicon nitride can be used for insulating layers 280a and 280c, and silicon oxide can be used for insulating layer 280b.

[0345] [Transistor 200E]

[0346] FIG. 5C and FIG. 1A This is a cross-sectional view of a semiconductor device including transistor 200E. FIG. 5D It is along FIG. 1A The cross-sectional view of the dotted line A1-A2 shown.FIG. 1D It is along FIG. 5C The cross-sectional view of the dotted-dotted lines A3-A4 is shown. Additionally, the above... FIG. 5D It is also equivalent to along FIG. 5C and FIG. 5D The cross-sectional view shown is the dotted-dash line A5-A6.

[0347] FIGS. 1A-1D and FIG. 5C The semiconductor device shown is FIG. 5D The difference in the semiconductor device shown is that the former includes an insulating layer 222.

[0348] exist FIG. 6A and FIG. 6B In the semiconductor device shown, an insulating layer 222 is disposed on the insulating layer 210, and a conductive layer 220 and an insulating layer 280 are disposed on the insulating layer 222.

[0349] As the insulating layer 222, it is preferable to use an insulating layer that has the function of trapping or fixing hydrogen. Thus, hydrogen in the oxide semiconductor layer 230 can diffuse through the conductive layer 220 to the insulating layer 222, allowing the insulating layer 222 to trap or fix the hydrogen. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0350] For example, it is preferable to use a silicon nitride film as the insulating layer 210 and an oxide film (hafnium silicate film) containing hafnium and silicon as the insulating layer 222.

[0351] [Transistor 200F]

[0352] FIG. 6A and FIG. 1A This is a cross-sectional view of a semiconductor device including transistor 200F. FIG. 6B It is along FIG. 1A The cross-sectional view of the dotted line A1-A2 shown. FIG. 1D It is along FIG. 6A The cross-sectional view of the dotted-dotted lines A3-A4 is shown. Additionally, the above... FIG. 6B Equivalent to along FIG. 6A and FIG. 6B The cross-sectional view shown is the dotted-dash line A5-A6.

[0353] exist FIG. 15C and FIG. 15D The top surface of the conductive layer 220 in the transistor 200F shown is flat, which is different from that of the transistor 200A.

[0354] Depending on the material of the conductive layer 220, sometimes a recess is not formed on the top surface of the conductive layer 220. The manufacturing method of the transistor 200F will be explained later (mainly referring to...). FIG. 7A and FIG. 7BEven with the above structure, it is easy to manufacture transistors with reduced parasitic capacitance, so it is preferred.

[0355] [Transistor 200G]

[0356] FIG. 7A It is a plan view of a semiconductor device including 200G transistors. FIG. 7C It is along FIG. 7A The cross-sectional view of the dotted line A1-A2 shown. FIG. 7D It is along FIG. 7B The cross-sectional view shown is the dotted-dash line A3-A4. FIG. 7C It is along FIGS. 7A-7D and FIG. 7B The cross-sectional view shown is the dotted-dash line A5-A6.

[0357] exist FIG. 8A In the semiconductor device shown, the side surfaces of the conductive layer 240, the insulating layer 280, and the conductive layer 220 within the opening 290 are aligned in cross-section. FIG. 8B As shown, the width of the opening 290 in the insulating layer 280 is the same as the width D of the opening 290 in the conductive layer 240, and the width of the conductive layer 220 is also the same as this width D. With the above structure, the parasitic capacitance between the conductive layer 220 and the conductive layer 240 can be reduced, so it is preferred.

[0358] [Transistor 200H]

[0359] FIG. 8A It is a plan view of a semiconductor device including transistor 200H. FIG. 8C It is along FIG. 8A The cross-sectional view of the dotted line A1-A2 shown. FIG. 8D It is along FIG. 8B The cross-sectional view shown is the dotted-dash line A3-A4. FIG. 8C It is along FIGS. 8A-8D and FIG. 9A The cross-sectional view shown is the dotted-dash line A5-A6.

[0360] exist FIG. 9B In the semiconductor device shown, the width of the opening 270 provided in the insulating layer 285 when viewed in cross section is smaller than the width of the opening 290 provided in the insulating layer 280, etc.

[0361] In cross-sectional view, the minimum width of the opening 270 is preferably less than or equal to the minimum width of the opening 290. This suppresses the overlap of the top surfaces of the conductive layer 260 and the conductive layer 240, thereby reducing the parasitic capacitance generated between the conductive layers 260 and 240.

[0362] On the other hand, when the width of the opening 270 is too small, the insulating layer 285 is located in the opening 290, sometimes unintentionally leading to an increase in the thickness of the gate insulating film. Therefore, the difference between the width of the opening 270 and the width of the opening 290 is preferably less than the sum of the thickness of the oxide semiconductor layer 230 in the A1-A2 direction and the thickness of the insulating layer 250a. This allows for a structure in which the insulating layer 250a and the insulating layer 250b are in contact in the opening 290.

[0363] [Transistor 200I and Transistor 200J]

[0364] FIG. 9C and FIG. 9D This is a cross-sectional view of a semiconductor device including transistor 200I. FIG. 1B and FIG. 7B This is a cross-sectional view of a semiconductor device including transistor 200J.

[0365] Transistor 200I and Transistor 200A ( FIG. 10A The difference between transistor 200I and transistor 280I is that transistor 200I does not include insulating layer 280, but includes insulating layer 280d, insulating layer 280e and conductive layer 255.

[0366] Transistor 200J and Transistor 200G ( FIG. 10B The difference between transistors 200J and 200J is that transistor 200J does not include insulating layer 280 but includes insulating layer 280d, insulating layer 280e and conductive layer 255.

[0367] In transistors 200I and 200J, conductive layer 255 is located on insulating layer 280d, and insulating layer 280e covers the top and side surfaces of conductive layer 255. Furthermore, in cross-section, oxide semiconductor layer 230 has a region that overlaps with conductive layer 255 across insulating layer 280e and with conductive layer 260 across insulating layers 250a and 250b.

[0368] Transistors 200I and 200J include a conductive layer 255 serving as a back gate. By including a back gate, the threshold voltage can be easily controlled, and fluctuations in the threshold voltage can be suppressed, thereby improving the electrical characteristics and reliability of the transistor.

[0369] The conductive layer 255 can use the same material as the conductive layer 260. Furthermore, the insulating layers 280d and 280e can use the same material as the insulating layer 280.

[0370] [Transistor 200K]

[0371] FIG. 10A It is a plan view of a semiconductor device including 200K transistors. FIG. 10C It is along FIG. 10AThe cross-sectional view of the dotted line A1-A2 shown. FIG. 1D It is along FIG. 10B The cross-sectional view of the dotted-dotted lines A3-A4 is shown. Furthermore, the above... FIG. 10C It is also equivalent to along FIGS. 10A-10C and FIG. 10B The cross-sectional view shown is the dotted-dash line A5-A6.

[0372] FIG. 10C The semiconductor device shown differs from the semiconductor devices described above in that it does not include the conductive layer 265.

[0373] exist FIG. 11A and FIGS. 11B-11E In this configuration, conductive layer 260 has a portion located within an opening 270 disposed in insulating layer 285 and a portion contacting the top surface of insulating layer 285. The width Da of conductive layer 260 within opening 270 is smaller than the width D of opening 290. Therefore, the parasitic capacitance between conductive layer 260 and conductive layer 240 can be reduced, which is preferable. Furthermore, conductive layer 260 has a portion overlapping the top surface of conductive layer 240, but insulating layers 250a, 250b, and 285 are located between this portion of conductive layer 260 and conductive layer 240. This increases the physical distance between conductive layer 260 and conductive layer 240, thereby reducing the parasitic capacitance between conductive layer 260 and conductive layer 240.

[0374] [Transistor 200L and Transistor 200M]

[0375] FIG. 11A It is a plan view of a semiconductor device including transistor 200L. FIG. 11C It is along FIG. 11A The cross-sectional view of the dotted line A1-A2 shown. FIG. 11D It is along FIG. 11E The cross-sectional view shown is the dotted-dash line A3-A4.

[0376] FIG. 11D and FIG. 11A It is a cross-sectional view of a semiconductor device including 200M transistors. FIG. 11E It is along FIG. 11A The cross-sectional view of the dotted line A1-A2 shown. FIG. 11B It is along FIG. 11C The cross-sectional view shown is the dotted-dash line A3-A4.

[0377] When the insulating layer 280 contacts the oxide semiconductor layer 230 and has a region 280i containing halogen elements in a semiconductor device according to one embodiment of the present invention, there are no limitations on the structure of the transistor. For example, vertical transistors such as transistors 200L and 200M are also an embodiment of the present invention.

[0378] Specifically, the conductive layer 220 can also have a portion overlapping with the conductive layer 240 when a cross section in a direction perpendicular to the extension direction of the conductive layer 220 (A1-A2 direction) is taken. Further, the conductive layer 260 can also overlap with the top surface of the conductive layer 240 with the oxide semiconductor layer 230 and the insulating layer 250 interposed therebetween.

[0379] The side wall of the opening portion 290 is preferably perpendicular or substantially perpendicular to the top surface of the insulating layer 210. By employing such a structure, miniaturization or high integration of the semiconductor device can be achieved. FIG. 11B and FIG. 11C An example in which the opening portion 290 is provided so that the side wall thereof is perpendicular to the top surface of the insulating layer 210 is shown.

[0380] Alternatively, the side wall of the opening portion 290 can also be a tapered shape. FIGS. 7A-7D and FIG. 12A An example in which the side wall of the opening portion 290 has a tapered shape is shown. By making the side wall of the opening portion 290 have a tapered shape, the coverage of the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, whereby defects such as voids can be reduced. When the side wall of the opening portion 290 has a tapered shape, for example, the taper angle θ280 of the side surface of the insulating layer 280 in the opening portion 290 is preferably 45 degrees or more and less than 90 degrees. Specifically, when the taper angle is 80 degrees or more and less than 90 degrees, as described above, miniaturization or high integration of the semiconductor device can be achieved, and is thus preferable. Further, when the taper angle is 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening portion 290 is improved, and is thus preferable.

[0381] Alternatively, for example, the side wall of the opening portion 290 can also have an inverse tapered shape. In other words, the taper angle θ280 of the side surface of the insulating layer 280 in the opening portion 290 can also be greater than 90 degrees.

[0382] <Manufacturing method of semiconductor device>

[0383] Next, a manufacturing method of a semiconductor device of one embodiment of the present application will be described with reference to FIGS. 12 to 17. Note that the description of the same portions as those described above is omitted in some cases with regard to the materials and the formation methods of the respective components.

[0384] The thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute the semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a PLD method, an ALD method, or the like.

[0385] In addition, examples of sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0386] Furthermore, CVD methods can be categorized into plasma CVD (PECVD), thermal CVD (TCVD), and photo CVD. Additionally, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0387] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage these wiring, electrodes, and components. On the other hand, since thermal CVD, which does not use plasma, does not produce this plasma damage, the yield of semiconductor devices can be improved. Moreover, since thermal CVD does not generate plasma damage during formation, films with fewer defects can be obtained.

[0388] As ALD methods, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0389] CVD and ALD methods differ from sputtering methods that deposit particles released from a target or similar material. Therefore, CVD and ALD are deposition methods with good step coverage, less affected by the shape of the workpiece. In particular, ALD offers high step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0390] Further, when the CVD method is used, a film of an arbitrary composition can be deposited in accordance with the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while deposition is performed. When deposition is performed while the flow ratio of the source gas is changed, the deposition time can be shortened as compared to the case where deposition is performed using a plurality of deposition chambers because the time required for transfer or adjustment of pressure is not needed. Thus, the productivity of semiconductor devices can be improved in some cases.

[0391] When the ALD method is used, a film of an arbitrary composition can be deposited by simultaneously introducing different kinds of precursors. Alternatively, a film of an arbitrary composition can be deposited by controlling the number of cycles of each precursor when different kinds of precursors are introduced.

[0392] The thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute the semiconductor device can be formed using a wet deposition method such as a spin coating method, a dip coating method, a spray coating method, an inkjet method, a dispenser method, a screen printing method, an offset printing method, a doctor knife method, a slit coating method, a roll coating method, a curtain coating method, or a blade coating method.

[0393] Further, when the thin films that constitute the semiconductor device are processed, a photolithography method or the like can be used. Alternatively, the thin films can be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like. Further, the thin films can be directly formed in an island shape by a deposition method using a metal mask or the like as a masking mask.

[0394] The photolithography method typically has two methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a thin film having photosensitivity is deposited, exposure and development are performed, and the thin film is processed into a desired shape.

[0395] In the photolithography method, as light for exposure, i-line (wavelength: 365 nm), g-line (wavelength: 436 nm), h-line (wavelength: 405 nm), or light in which these rays are mixed can be used, for example. Further, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure can be performed using a liquid immersion exposure technique. Further, as light for exposure, extreme ultraviolet (EUV) light or X-ray can be used. Further, instead of light for exposure, an electron beam can be used. When extreme ultraviolet light, X-ray, or an electron beam is used, extremely fine processing can be performed, and thus is preferable. Note that when exposure is performed by scanning using a light beam such as an electron beam, a photomask is not needed.

[0396] As an etching method for the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0397] [Example of manufacturing method of transistor 200G]

[0398] An example of a manufacturing method of a semiconductor device including the above-described transistor 200G (see FIG. 1) will be described with reference to FIGS. 12 to 14. FIG. 12B

[0399] First, as shown in FIG. 12, an insulating layer 210 is formed over a substrate (not shown), a conductive layer 220 is formed over the insulating layer 210, an insulating layer 280 is formed over the conductive layer 220, and a conductive layer 240 is formed over the insulating layer 280. FIG. 12B

[0400] Further, it is preferable to perform planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method to planarize the top surface of the insulating layer 280 after the insulating layer 280 is deposited. By performing planarization treatment of the insulating layer 280, the surface on which the conductive layer 240 is formed can be planarized, whereby disconnection of the conductive layer 240 can be suppressed. Further, the planarization treatment can not be performed, in which case manufacturing cost can be reduced.

[0401] Next, as shown in FIG. 13, an opening portion 290 is formed in the conductive layer 240 and the insulating layer 280 at a position overlapping with the conductive layer 220. FIG. 12B

[0402] In a cross section in a direction perpendicular to the direction in which the conductive layer 220 extends (corresponding to the A1-A2 direction), it is preferable to set the opening portion 290 so that the minimum value of the width of the opening portion 290 in the conductive layer 240 is equal to or smaller than the maximum value of the width of the conductive layer 220. FIG. 12C An example in which the width of the conductive layer 220 is the same as the width D of the opening portion 290 in the conductive layer 240 is shown. Further, FIG. 12C An example in which the side surface of the conductive layer 220, the side surface of the conductive layer 240 in the opening portion 290, and the side surface of the insulating layer 280 in the opening portion 290 are aligned is shown.

[0403] Since the aspect ratio of the opening portion 290 is high, it is preferable to process a part of the conductive layer 240 and a part of the insulating layer 280 using anisotropic etching. In particular, processing using a dry etching method is suitable for fine processing and is thus preferable. Further, the processing can be performed under different conditions for the layers. Note that depending on the processing conditions of the conductive layer 240 and the insulating layer 280, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 in the opening portion 290 are not necessarily the same.

[0404] ​​​Next, heat treatment can also be performed. As the heat treatment, for example, it can be performed at 250 °C or higher and 650 °C or lower, preferably at 300 °C or higher and 500 °C or lower, more preferably at 320 °C or higher and 450 °C or lower.

[0405] The heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1 % or more, or 10 % or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas is preferably about 20 %. The heat treatment can also be performed in a reduced-pressure state. Alternatively, the heat treatment can be performed in an atmosphere of a nitrogen gas or an inert gas and then, in order to compensate for the escaped oxygen, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1 % or more, or 10 % or more of an oxidizing gas. By performing the above heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before deposition of the oxide semiconductor layer 230 which will be described later.

[0406] Further, the gas used in the above heat treatment is preferably high-purity. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably 1 ppb or lower, more preferably 0.1 ppb or lower, and further preferably 0.05 ppb or lower. By performing the heat treatment using a gas with high purity, moisture and the like can be prevented from being absorbed by the insulating layer 280 and the like as much as possible.

[0407] Next, as illustrated in FIG. 2B, the halogen element 188 is supplied to the side surface of the opening portion 290 in the insulating layer 280. The region of the insulating layer 280 to which the halogen element 188 is supplied is referred to as a region 280i. The region 280i includes at least the side surface of the opening portion 290 in the insulating layer 280. In some cases, the halogen element 188 is also supplied to a region including the top surface of the conductive layer 240 and a region including the side surface of the opening portion 290. FIG. 12C

[0408] In this embodiment, the side wall of the opening portion 290 is perpendicular to the top surface of the substrate. In the case where the side wall of the opening portion 290 is perpendicular or substantially perpendicular to the top surface of the substrate or has a tapered shape, it is difficult to uniformly supply the halogen element 188 to a desired region in some cases. FIG. 12C

[0409] Thus, as illustrated in FIG. 2B, the halogen element 188 is preferably added in a direction inclined at greater than or equal to 0 degrees and less than 90 degrees with respect to the top surface of the substrate. FIG. 12D ​ ​​​An example of adding the halogen element 188 in a state where the inclination angle θ 188 with respect to the top surface of the insulating layer 210 is shown. The angle θ 188 is preferably greater than 0 degree and less than 90 degrees, further preferably greater than or equal to 15 degrees and less than or equal to 80 degrees. With this structure, the halogen element can be easily supplied to the side surface in the opening portion 290 of the insulating layer 280. Further, it is not limited to addition from one direction, and by changing the rotation angle and supplying the halogen element 188 in stages, the halogen element 188 can be more uniformly supplied to a desired region, and is thus preferable.

[0410] The element which can be used as the halogen element 188 is as described above.

[0411] The halogen element 188 can be supplied by a plasma ion doping method or an ion implantation method as appropriate. By using these methods, the concentration distribution in the depth direction can be controlled with high precision depending on the ion acceleration voltage and the dose.

[0412] In addition, for example, by inclining one or both of the substrate to be processed and the ion irradiation portion in the apparatus, the angle θ 188 can be within the above range.

[0413] By using an ion implantation method in which a source gas is ionized and the ions are added after mass separation, the purity of the halogen element 188 to be supplied can be improved. The region 280i is in contact with the channel formation region of the oxide semiconductor layer 230. Thus, if other impurity elements are also supplied to the region 280i at the time of supplying the halogen element 188, the impurity elements diffuse into the channel formation region of the oxide semiconductor layer 230, which is concerned with the characteristics and reliability of the transistor. Thus, it is preferable to supply the region 280i with the halogen element 188 of high purity by using an ion implantation method.

[0414] Further, by using a plasma ion doping method in which a source gas is ionized and the ions are added without mass separation, the productivity can be improved.

[0415] The ion implantation apparatus or the ion doping apparatus used for supplying the halogen element 188 is also used for the manufacture of Si transistors such as LTPS transistors, and thus an existing LTPS production line apparatus can be used, and no new apparatus investment is needed, which is preferable. Thus, the equipment investment cost for the manufacture of semiconductor devices can be reduced.

[0416] As the source gas for halogen element 188, a gas containing the aforementioned halogen element can be used. This gas can be either a gas of elemental halogen or a halide gas. When fluorine is supplied, F2, BF3, C4F6, C5F6, C4F8, CF4, SF6, CHF3, CH2F2, and CH3F gases can typically be used. Furthermore, when chlorine is supplied, Cl2, BCl3, SiCl4, and CCl4 gases can typically be used. Additionally, a mixture of these source gases diluted with hydrogen or a rare gas can also be used. Furthermore, the ion source is not limited to a gas; a solid or liquid can also be vaporized by heating.

[0417] The supply of halogen element 188 can be controlled by setting conditions such as accelerating voltage and dosage according to the composition, density and thickness of insulating layer 280.

[0418] Note that there are no restrictions on the method of supplying halogen element 188; for example, plasma treatment or treatment using thermal diffusion caused by heating can also be performed. In the case of plasma treatment, the halogen element can be supplied by first generating plasma in a gas atmosphere containing the supplied halogen element, and then performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, or high-density plasma CVD apparatus can be used, etc.

[0419] Furthermore, the halogen element 188 can be supplied simultaneously with heating the substrate. This allows for the repair of damage to the insulating layer 280 caused by the addition of halogen element 188. In other words, the addition of halogen element 188 to the insulating layer 280 and the repair of any damage resulting from that addition can be performed concurrently.

[0420] The substrate temperature in the halogen element 188 supply process is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and lower than 500°C, more preferably 200°C or higher and lower than 450°C, more preferably 250°C or higher and lower than 400°C, more preferably 250°C or higher and lower than 350°C, or preferably 300°C or higher and lower than 400°C, more preferably 300°C or higher and lower than 350°C.

[0421] Next, as ​ As shown, an oxide semiconductor layer 230 is formed to cover the opening 290. The oxide semiconductor layer 230 is disposed in contact with the top surface of the conductive layer 220, the side surface of the insulating layer 280 (especially region 280i), and the top and side surfaces of the conductive layer 240.

[0422] The oxide semiconductor layer 230 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, for example.

[0423] The oxide semiconductor layer 230 is preferably formed as a film with a uniform thickness as much as possible along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240 in the opening portion 290. By depositing the oxide semiconductor layer 230 using an ALD method, a thin film can be deposited with high controllability. Thus, the oxide semiconductor layer 230 is preferably formed using an ALD method.

[0424] Further, when the oxide semiconductor layer 230 has high crystallinity, diffusion of impurities in the oxide semiconductor layer 230 is inhibited, so that the electrical characteristics of the transistor are not easily changed, which can improve the reliability. By depositing the oxide semiconductor layer 230 using a sputtering method, a layer with high crystallinity can be easily formed compared to the case of using an ALD method, and is thus preferable.

[0425] In the case where the oxide semiconductor layer 230 is deposited by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen included in the sputtering gas, excess oxygen in the deposited oxide film can be increased. Further, in the case where the above oxide film is deposited by a sputtering method, an In-M-Zn oxide target or the like can be used.

[0426] In the case where the oxide semiconductor layer 230 is formed by a sputtering method, when deposition is performed at a proportion of oxygen included in a sputtering gas of more than 30 % and 100 % or less, preferably 70 % or more and 100 % or less, an oxygen-excess oxide semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region can have relatively high reliability. Note that one embodiment of the present application is not limited to this. When deposition is performed at a proportion of oxygen included in a sputtering gas of 1 % or more and 30 % or less, preferably 5 % or more and 20 % or less, an oxygen-deficient oxide semiconductor is formed. A transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region can have high field-effect mobility. Further, by performing deposition while heating a substrate, the crystallinity of the oxide semiconductor layer can be improved.

[0427] In the case where the oxide semiconductor layer 230 is deposited while a substrate is heated, a halogen element can be supplied from the region 280i to the oxide semiconductor layer 230. In this manner, by supplying a halogen element from the insulating layer 280 to the oxide semiconductor layer 230 after the halogen element 188 is supplied to the insulating layer 280 in advance, the oxide semiconductor layer 230 can be prevented from being damaged. Thus, the crystallinity of the oxide semiconductor layer 230 can be prevented from being decreased, which can improve the reliability of the transistor.

[0428] Next, a heat treatment is preferably performed. During this heat treatment, halogen elements may sometimes be supplied to the oxide semiconductor layer 230 from region 280i. In this case, halogen elements can be supplied to the oxide semiconductor layer 230 while suppressing damage to the oxide semiconductor layer 230. Therefore, it can be considered that halogen elements are supplied to the oxide semiconductor layer 230 from region 280i during various heat treatments performed after the deposition of the oxide semiconductor layer 230.

[0429] The heat treatment is preferably performed within a temperature range in which the oxide semiconductor layer 230 is not polycrystalline. The heat treatment temperature is preferably 100°C or higher and 650°C or lower, more preferably 250°C or higher and 600°C or lower, and even more preferably 350°C or higher and 550°C or lower. For details regarding the heat treatment, please refer to the above description.

[0430] Furthermore, the gas used in the above-mentioned heat treatment is preferably of high purity. By using a high-purity gas for heat treatment, the absorption of moisture and other substances by the oxide semiconductor layer 230 can be prevented as much as possible.

[0431] In this embodiment, as a heat treatment, a process is performed for 1 hour at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 450°C. This oxygen-containing heat treatment reduces impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230. By reducing impurities in the film, the crystallinity of the oxide semiconductor layer 230 is improved, resulting in a denser structure with higher density. Therefore, the crystalline region in the oxide semiconductor layer 230 can be increased, and the in-plane non-uniformity of the crystalline region in the oxide semiconductor layer 230 can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0432] Furthermore, when the insulating layer 280 contains oxygen, it is preferable to supply oxygen from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 through heat treatment. This reduces oxygen vacancies and VoH.

[0433] Thus, oxygen (also known as excess oxygen) that is removed by heating is sometimes supplied to the oxide semiconductor layer 230 from an insulating layer in contact with or near the oxide semiconductor layer 230. Excess oxygen also has the function of trapping electrons, so it readily forms a negative charge. Therefore, a normally-off transistor can be achieved by shifting the threshold voltage of the transistor in the positive direction.

[0434] Next, as Figure 13A As shown, it is preferable to add (implant) impurity element 189 to the oxide semiconductor layer 230.

[0435] By adding the impurity element 189 to the oxide semiconductor layer 230, the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0436] By depositing the insulating layer 250a on the oxide semiconductor layer 230 after the direct addition of the impurity element 189 to the oxide semiconductor layer 230, the insulating layer 250a can be prevented from being damaged by the addition of the impurity element 189.

[0437] As described above, the impurity element 189 is preferably added in a direction perpendicular or substantially perpendicular to the top surface of the substrate. At this time, as described above, in the oxide semiconductor layer 230, the plane inclined to the top surface of the substrate or the plane perpendicular or substantially perpendicular to the top surface of the substrate is added with less impurity element than the plane parallel or substantially parallel to the top surface of the substrate. In other words, in the oxide semiconductor layer 230, the source region and the drain region are added with more impurity element than the channel formation region. Thus, the source region and the drain region can be preferentially made low-resistance.

[0438] Figure 13A An example in which the region 230n is formed at and near the interface between the top surface of the oxide semiconductor layer 230 and the conductive layer 220 and the interface between the top surface of the oxide semiconductor layer 230 and the conductive layer 240 is shown.

[0439] The element which can be used as the impurity element 189 is as described above.

[0440] The impurity element 189 can be supplied by plasma ion doping or ion implantation as appropriate. By using these methods, the concentration distribution in the depth direction can be controlled with high precision depending on the ion acceleration voltage and the dose.

[0441] By ion implantation in which a source gas is ionized and the ions are mass-separated, the purity of the supplied impurity element can be increased. In the case of using ion implantation, the first element described above is preferably used as the impurity element 189, and boron or phosphorus is more preferably used. By using an element which is stabilized by bonding to oxygen as the impurity element 189, a stable region 230n in a low-resistance state can be realized.

[0442] Furthermore, productivity can be improved by utilizing plasma ion doping, which involves ionizing the source gas and adding the ions without mass separation. When using plasma ion doping, the impurity element 189 is preferably a combination of the first element and hydrogen, more preferably a combination of boron or phosphorus and hydrogen. By using the combination of an element stabilized by bonding with oxygen and hydrogen as impurity element 189, the resistance of region 230n is easily reduced, and a stable low resistance state can be maintained.

[0443] The ion implantation or ion doping equipment used to supply impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors. Therefore, it is preferred to use equipment from existing LTPS production lines without requiring new equipment investment. This reduces the equipment investment costs for manufacturing semiconductor devices.

[0444] In the supply processing of impurity element 189, it is preferable to control the processing conditions so that the concentration of the impurity element in the portion of the oxide semiconductor layer 230 that overlaps with the top surface of the conductive layer 220 or the top surface of the conductive layer 240 is higher than the concentration of the same impurity element in other regions. This allows for the supply of an optimal concentration of impurity element 189 to the source and drain regions of the oxide semiconductor layer 230.

[0445] As the source gas for impurity element 189, a gas containing the aforementioned impurity element can be used. When supplying boron, B₂H₆ gas or BF₃ gas is typically used. Furthermore, when supplying phosphorus, PH₃ gas is typically used. Alternatively, a mixture of these source gases diluted with hydrogen or a rare gas can also be used.

[0446] In addition to the above, source gases can include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. Furthermore, the ion source is not limited to gases; solids or liquids can also be heated to vaporize them.

[0447] For example, it is preferable to use a gas supply containing boron and hydrogen as impurity element 189. In this case, impurity element 189 can be added without mass separation, and the resistance of the oxide semiconductor layer 230 can be easily reduced, thus improving the productivity and characteristics of the semiconductor device, which is therefore preferred.

[0448] The supply of impurity element 189 can be controlled by setting conditions such as acceleration voltage and dosage according to the composition, density and thickness of oxide semiconductor layer 230.

[0449] Note that there are no restrictions on the method of supplying impurity element 189; for example, plasma treatment or treatment using thermal diffusion caused by heating can also be performed. When using plasma treatment, the impurity element can be supplied by first generating plasma in a gas atmosphere containing the supplied impurity element, and then performing plasma treatment. As the apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, or a high-density plasma CVD apparatus can be used.

[0450] Furthermore, it is preferable to supply the impurity element 189 while heating the substrate. This allows for the repair of damage to the oxide semiconductor layer 230 caused by the addition of the impurity element 189. In other words, the addition of the impurity element 189 and the repair of any accompanying damage can be performed on the oxide semiconductor layer 230 in parallel.

[0451] The substrate temperature in the supply process of impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and lower than 500°C, more preferably 200°C or higher and lower than 450°C, more preferably 250°C or higher and lower than 400°C, more preferably 250°C or higher and lower than 350°C, or preferably 300°C or higher and lower than 400°C, more preferably 300°C or higher and lower than 350°C.

[0452] Alternatively, a heat treatment can be performed after the supply of impurity element 189. This heat treatment can repair any damage to the oxide semiconductor layer 230 that occurred during the supply process of impurity element 189.

[0453] By using an element stabilized by bonding with oxygen as impurity element 189, the detachment of impurity element 189 due to heating or other processes during semiconductor device manufacturing can be suppressed. Therefore, even if heat treatment is performed after the addition of impurity element 189 or a deposition process is performed while the substrate is heated, a low resistance state can be maintained in region 230n.

[0454] In addition, the above description can also be used as a reference for heat treatment.

[0455] Next, as Figure 13B As shown, by processing the oxide semiconductor layer 230 and the conductive layer 240 into island shapes, a portion of the top surface of the insulating layer 280 is exposed. The oxide semiconductor layer 230 and the conductive layer 240 can be processed using the same mask. Therefore, the number of masks required for manufacturing the semiconductor device can be reduced, which is preferable.

[0456] Next, an insulating layer 250a is formed on the insulating layer 280, the oxide semiconductor layer 230, and the conductive layer 240. Figure 13C), and the top surface of the insulating layer 285 is planarized by performing CMP treatment (S4). Figure 13D ).

[0457] The insulating layer 250a is formed so as to be in contact with the oxide semiconductor layer 230 provided in the opening portion 290 having a large aspect ratio. Therefore, it is preferable to use a deposition method with good coverage when depositing the insulating layer 250a, and it is more preferable to use a CVD method or an ALD method or the like.

[0458] Next, a resist mask (not shown) is formed over the insulating layer 285. Then, using the resist mask, an opening portion 270 reaching the insulating layer 250a is formed in the insulating layer 285. At this time, the insulating layer 250a is used as an etching stopper. Therefore, a material having a high etching selectivity with respect to the insulating layer 285 is used as the insulating layer 250a.

[0459] Here, it is preferable that the width of the opening portion of the resist mask be smaller than or equal to the minimum value of the width of the opening portion 290 in the conductive layer 240 when the structure is cut. By doing so, the area of the conductive layer 240 overlapping with the conductive layer 260 to be formed later can be reduced, and the parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 can be reduced.

[0460] Figure 13E An example in which the width of the opening portion 290 and the width of the opening portion 270 are both the width D is shown.

[0461] Next, an insulating layer 250b is formed over the insulating layer 250a and the insulating layer 285, and a conductive layer 260 is formed over the insulating layer 250b. Then, by performing CMP treatment, the portions of the insulating layer 250b and the conductive layer 260 overlapping with the top surface of the insulating layer 285 are removed. Then, a conductive layer 265 is formed over the insulating layer 285, the insulating layer 250b, and the conductive layer 260 (S5). Figure 13F ).

[0462] The insulating layer 250b is formed so as to be in contact with the insulating layer 250a provided in the opening portion 290 and the opening portion 270 having a large aspect ratio. Therefore, it is preferable to use a deposition method with good coverage when depositing the insulating layer 250b, and it is more preferable to use a CVD method or an ALD method or the like.

[0463] The conductive layer 260 is formed so as to be in contact with the insulating layer 250b provided in the opening portion 290 and the opening portion 270 having a large aspect ratio. Therefore, it is preferable to use a deposition method with good coverage when depositing the conductive layer 260, and it is more preferable to use a CVD method or an ALD method or the like.

[0464] By performing the CMP treatment, the portion of the conductive layer 260 overlapping with the top surface of the conductive layer 240 can be removed. In a cross section, the maximum value of the width of the conductive layer 260 is the width Da in the opening portion 270. The width Da is smaller than the width D of the opening portion 290. Thus, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be suppressed.

[0465] By removing the portion of the conductive layer 260 overlapping with the top surface of the conductive layer 240 with the CMP treatment, damage due to plasma can be suppressed compared to the case where dry etching is used.

[0466] As Figure 13F illustrated, the height of the top surface of the insulating layer 285 and the height of the top surface of the conductive layer 260 are preferably the same. Alternatively, one of the height of the top surface of the insulating layer 285 and the height of the top surface of the conductive layer 260 can be higher than the other. Depending on the difference in polishing rate of the materials of the insulating layer 285 and the conductive layer 260, the height of the top surface of the two layers can be controlled.

[0467] The insulating layer 250a and the insulating layer 285 are positioned between the conductive layer 265 and the conductive layer 240. Thus, the physical distance between the conductive layer 265 and the conductive layer 240 can be increased, and the parasitic capacitance between the conductive layer 265 and the conductive layer 240 can be reduced.

[0468] Through the above steps, the semiconductor device of one embodiment of the present application can be manufactured.

[0469] In the example illustrated in Figure 13A , the impurity element 189 is added to the oxide semiconductor layer 230 after the oxide semiconductor layer 230 is formed and before the insulating layer 250a is formed, but the timing of adding the impurity element 189 is not limited thereto.

[0470] For example, the top surface of the conductive layer 220 and the top surface of the conductive layer 240 can be added with the impurity element 189 after the insulating layer 280 is formed and before the oxide semiconductor layer 230 is formed.

[0471] For example, the process of supplying the impurity element 189 illustrated in Figure 12C may be performed after the process of supplying the halogen element 188 illustrated in Figure 14A . The region of the conductive layer 220 to which the impurity element 189 is supplied is denoted as a region 220n. Similarly, the region of the conductive layer 240 to which the impurity element 189 is supplied is denoted as a region 240n.

[0472] Further, for example, the process of supplying the halogen element 188 illustrated in Figure 14B may be performed after the process of supplying the impurity element 189 illustrated in Figure 14C .

[0473] Then, by depositing the oxide semiconductor layer 230 and performing heat treatment, halogen element 188 can be supplied from region 280i of the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230. In addition, impurity element 189 can be supplied from region 220n of the conductive layer 220 and region 240n of the conductive layer 240 to the source region and drain region of the oxide semiconductor layer 230.

[0474] By supplying impurity element 189 to the oxide semiconductor layer 230 through conductive layer 220 or conductive layer 240, the decrease in crystallinity of the oxide semiconductor layer 230 can be suppressed compared to the case where impurity element 189 is directly added to the oxide semiconductor layer 230. Therefore, the increase in resistance caused by the decrease in crystallinity can be suppressed.

[0475] In addition, such as Figure 14D As shown, impurity element 189 can also be added to oxide semiconductor layer 230 through insulating layer 250a. Note that, in this case, sometimes impurity element 189 is also supplied to insulating layer 250a.

[0476] By supplying impurity element 189 to the oxide semiconductor layer 230 through insulating layer 250a, the decrease in crystallinity of the oxide semiconductor layer 230 can be suppressed compared to the case where impurity element 189 is directly added to the oxide semiconductor layer 230. Therefore, the increase in resistance caused by the decrease in crystallinity can be suppressed.

[0477] Furthermore, there is a concern about contamination of the deposition chamber of the insulation layer 250a when the impurity element 189 is added. Therefore, it is preferable to add the impurity element 189 after the insulation layer 250a is deposited.

[0478] [Examples of manufacturing methods for transistors 200A and 200F]

[0479] Reference Figure 15A and Figure 15B An example of a manufacturing method for a semiconductor device including the aforementioned transistor 200A (see Figures 1 and 2) is provided. Furthermore, refer to... Figure 15C and Figure 15D Explain the transistor 200F mentioned above (refer to...) Figure 6A and Figure 6B Examples of manufacturing methods are provided below. Note that detailed descriptions of the same parts as in the examples above are sometimes omitted in the manufacturing methods below.

[0480] First, such as Figure 12A As shown, an insulating layer 210, a conductive layer 220, an insulating layer 280, and a conductive layer 240 are formed on a substrate (not shown).

[0481] Next, an opening is formed at the position where the conductive layer 240 overlaps with the conductive layer 220, and a recess is formed at the position where the insulating layer 280 overlaps with the conductive layer 220. Figure 15A or Figure 15C At this point, the openings in the conductive layer 240 and the recesses in the insulating layer 280 can be formed using the same photoresist mask. For example... Figure 15A and Figure 15C As shown, the top surface of the conductive layer 220 is not exposed at this time.

[0482] Next, an opening is formed at the position where the insulating layer 280 overlaps with the conductive layer 220. Figure 15B or Figure 15D By performing a tapered etching on the recess of the insulating layer 280, a portion of the opening 290 in the insulating layer 280 can be provided with a width smaller than the width of the opening 290 in the conductive layer 240.

[0483] like Figure 15B As shown, a portion of the conductive layer 220 can also be removed to create a recess in the conductive layer 220. Additionally, as... Figure 15D As shown, it is also possible not to form a recess in the conductive layer 220.

[0484] Thus, by processing the insulating layer 280 in two steps during the formation of the opening 290, the opening 290 can be formed in a manner that prevents it from reaching the top surface of the insulating layer 210 and makes the width D of the opening 290 larger than the width of the conductive layer 220. Therefore, it is preferable to manufacture a transistor with a structure that reduces parasitic capacitance.

[0485] Then, by proceeding in sequence Figures 12C to 13F The process shown can be used to manufacture a semiconductor device according to one aspect of the present invention.

[0486] [Example of transistor 200B manufacturing method]

[0487] Reference Figures 16A to 16C Explanation of the above transistor 200B (refer to) Figures 3A to 3C Examples of manufacturing methods for ( ).

[0488] First, such as Figure 16A As shown, an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220 is formed on the insulating layer 210, an insulating layer 280a is formed on the conductive layer 220, an insulating layer 280b is formed on the insulating layer 280a, and a conductive layer 240 is formed on the insulating layer 280b. Here, the insulating layer 280a uses a material with a high etch selectivity compared to the insulating layer 280b.

[0489] Next, as Figure 16BAs shown, an opening extending to the insulating layer 280a is formed at the location where the conductive layer 240 and the insulating layer 280b overlap with the conductive layer 220. In this case, the openings in the conductive layer 240 and the insulating layer 280b can be formed using the same photoresist mask. Figure 16B As shown, at this time, the top surface of the insulating layer 280a is exposed in the opening, while the top surface of the conductive layer 220 is not exposed. Note that a portion of the insulating layer 280a may also be etched.

[0490] Next, an opening is formed at the position where the insulating layer 280a overlaps with the conductive layer 220. Figure 16C By performing a tapered etching on the insulating layer 280a, an opening 290 in the insulating layer 280a can be provided with a portion whose width is smaller than that of the opening 290 in the conductive layer 240.

[0491] Note that in Figure 16C In the example shown, a portion of the conductive layer 220 is removed and a recess is formed in the conductive layer 220, but it is not limited to this and the recess may not be formed in the conductive layer 220.

[0492] Thus, by processing insulating layers 280a and 280b separately when forming opening 290, opening 290 can be formed in a manner that prevents it from reaching the top surface of insulating layer 210 and makes the width D of opening 290 in conductive layer 240 larger than the width of conductive layer 220. Therefore, it is preferable to manufacture a transistor with a structure that reduces parasitic capacitance.

[0493] Then, by conducting Figures 12C to 13F The process shown can be used to manufacture a semiconductor device according to one aspect of the present invention.

[0494] [Example of transistor 200C manufacturing method]

[0495] Reference Figures 17A to 17E Explanation of the above transistor 200C (refer to) Figures 4A to 4C Examples of manufacturing methods for ( ).

[0496] First, such as Figure 17A As shown, an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220 is formed on the insulating layer 210, and an insulating layer 280a is formed on the conductive layer 220. Here, the insulating layer 280a uses a material with a high etching selectivity to the insulating layer 280b that will be formed later.

[0497] Next, as Figure 17B As shown, CMP treatment is performed to planarize the top surface of the insulating layer 280a. At this time, the insulating layer 280a covers the top surface of the conductive layer 220 so that the top surface of the conductive layer 220 is not exposed.

[0498] Next, as illustrated in FIG. 27A, an insulating layer 280b is formed over the insulating layer 280a, and a conductive layer 240 is formed over the insulating layer 280b. Figure 17C

[0499] Next, as illustrated in FIG. 27B, an opening portion reaching the insulating layer 280a is formed in the conductive layer 240 and the insulating layer 280b at a position overlapping with the conductive layer 220. At this time, the opening portion of the conductive layer 240 and the opening portion of the insulating layer 280b can be formed using the same resist mask. As illustrated in FIG. 27C, at this time, the top surface of the insulating layer 280a is exposed in the opening portion, and the top surface of the conductive layer 220 is not exposed. Note that part of the insulating layer 280a can also be etched. Figure 17D Figure 17D

[0500] Next, an opening portion 290 is formed in the insulating layer 280a at a position overlapping with the conductive layer 220 (FIG. 27D). By taper etching the insulating layer 280a, a portion where the width of the opening portion 290 in the insulating layer 280a is smaller than the width of the opening portion 290 in the conductive layer 240 can be provided. Figure 17E Note that in the example illustrated in FIG. 27, part of the conductive layer 220 is removed to provide a recess in the conductive layer 220, but the present invention is not limited to this, and a recess can not be formed in the conductive layer 220.

[0501] Figure 17E Thus, by processing the insulating layer 280a and the insulating layer 280b separately when forming the opening portion 290, the opening portion 290 can be formed so that the opening portion 290 does not reach the top surface of the insulating layer 210 and the width D of the opening portion 290 in the conductive layer 240 is larger than the width of the conductive layer 220. Thus, a transistor of a structure in which parasitic capacitance is reduced can be easily manufactured, and is thus preferable.

[0502] Then, by performing the steps illustrated in FIG. 28, a semiconductor device of one embodiment of the present invention can be manufactured.

[0503] Figures 12C to 13F As described above, the semiconductor device of one embodiment of the present invention includes a halogen element in a region of the insulating layer 280 in contact with the oxide semiconductor layer 230. Thus, a negative charge can be formed in a channel formation region of the oxide semiconductor layer 230, and the threshold voltage of the transistor can be shifted in the positive direction. Accordingly, even in the case of forming a minute transistor or a transistor with an extremely small channel length, the transistor can be made normally off.

[0504]

[0505] ​​​​​​Further, the semiconductor device of one embodiment of the present application has a structure in which parasitic capacitance between a source electrode or a drain electrode and a gate electrode and parasitic capacitance between a source electrode or a drain electrode and a gate wiring are reduced. Thus, the frequency characteristics of a circuit can be improved.

[0506] This embodiment mode can be combined as appropriate with other embodiment modes. Further, in this specification, in the case where a plurality of structural examples are shown in one embodiment mode, the structural examples can be combined as appropriate.

[0507] (Embodiment 2)

[0508] In this embodiment, reference is made to FIG. 18 to FIG. 21. Figure 21 A storage device of one embodiment of the present application is described. The storage device of one embodiment of the present application includes a storage unit. The storage unit includes a transistor and a capacitor.

[0509] <Structure Example 1 of Storage Device>

[0510] Reference is made to Figures 18A to 18C A structure of a storage device including a transistor and a capacitor is described. Figure 18A is a plan view of a storage device including a transistor 200A and a capacitor 100. Figure 18B is a cross-sectional view taken along the dot-dash line A1-A2 in FIG. 18. Figure 18A is a cross-sectional view taken along the dot-dash line A3-A4 in FIG. 18. Figure 18C Figure 18A

[0511] Figures 18A to 18C The storage device illustrated in FIG. 18 includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a storage unit 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280, an insulating layer 285, and a conductive layer 265 over the insulating layer 285. The insulating layer 140, the insulating layer 180, the insulating layer 280, and the insulating layer 285 are used as interlayer films. The conductive layer 110 and the conductive layer 265 are used as wirings.

[0512] The storage unit 150 includes a capacitor 100 over the conductive layer 110 and a transistor 200A over the capacitor 100.

[0513] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 120 over the insulating layer 130. The conductive layer 120 is used as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 is used as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 is used as a dielectric. That is, the capacitor 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.​​

[0514] As Figure 18B and Figure 18C shown, the insulating layer 180 is provided with an opening portion 190 reaching the conductive layer 110. At least a part of the conductive layer 115 is arranged in the opening portion 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening portion 190, a region in contact with the side surface of the insulating layer 180 in the opening portion 190, and a region in contact with at least a part of the top surface of the insulating layer 180. The insulating layer 130 is arranged so that at least a part thereof is positioned in the opening portion 190. The conductive layer 120 is arranged so that at least a part thereof is positioned in the opening portion 190. Further, as Figure 18B and Figure 18C shown, the conductive layer 120 is preferably provided so as to be embedded in the opening portion 190. Further, the films provided inside the opening portion 190 are each preferably formed using an ALD method. With this, the films have good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are each preferably formed using an ALD method.

[0515] The capacitor 100 has a structure in which the upper electrode and the lower electrode face each other with the dielectric therebetween not only on the bottom surface but also on the side surface in the opening portion 190, and thus the electrostatic capacitance per unit area can be increased. With this, the deeper the depth of the opening portion 190, the larger the electrostatic capacitance of the capacitor 100 can be. Thus, by increasing the electrostatic capacitance per unit area of the capacitor 100, the reading operation of the memory device can be stabilized. Further, the miniaturization or high integration of the memory device can be promoted.

[0516] Figure 18B and Figure 18C An example in which the side wall of the opening portion 190 is perpendicular to the top surface of the conductive layer 110 is shown. At this time, the opening portion 190 has a cylindrical shape. With this structure, the miniaturization or high integration of the memory device can be achieved.

[0517] The conductive layer 115 and the insulating layer 130 are provided in layers along the side wall of the opening portion 190 and the top surface of the conductive layer 110. Further, the conductive layer 120 is provided on the insulating layer 130 so as to be embedded in the opening portion 190. The capacitor 100 having such a structure can be referred to as a trench-type capacitor or a trench capacitor.

[0518] Further, the capacitor 100 is provided with an insulating layer 280. The insulating layer 280 is positioned on the insulating layer 130. The insulating layer 280 can also include a portion positioned on the conductive layer 120.

[0519] The transistor 200A includes the conductive layer 120 (corresponding to Figure 1BThe conductive layer 220, the conductive layer 240 over the insulating layer 280, the oxide semiconductor layer 230, the insulating layer 250a over the oxide semiconductor layer 230, the insulating layer 250b over the insulating layer 250a, and the conductive layer 260 over the insulating layer 250b are used. The oxide semiconductor layer 230 is used as a semiconductor layer, the conductive layer 260 is used as a gate electrode, the insulating layer 250a and the insulating layer 250b are used as gate insulating layers, the conductive layer 120 is used as one of a source electrode and a drain electrode, and the conductive layer 240 is used as the other of the source electrode and the drain electrode.

[0520] As for the transistor 200A, the description in Embodiment 1 (FIGS. 1A to 2B) can be referred to, and thus detailed description is omitted. Note that the transistor included in the memory cell 150 is not limited to the transistor 200A, and each of the transistors described in Embodiment 1 can be used.

[0521] As Figures 18A to 18C indicated in FIG. 2B, the transistor 200A overlaps with the capacitor 100. Further, the opening 290 and the opening 270 of the components included in the portion where the transistor 200A is provided have an area overlapping with the opening 190 of the components included in the portion where the capacitor 100 is provided. In particular, the conductive layer 120 is used as one of a source electrode and a drain electrode of the transistor 200A and as an upper electrode of the capacitor 100, whereby the transistor 200A and the capacitor 100 share a part of the components. With such a structure, the transistor 200A and the capacitor 100 can be provided without significantly increasing the area occupancy in plan view. Thus, the area occupancy of the memory cell 150 can be reduced, and thus the memory cells 150 can be arranged at high density to increase the storage capacity of the memory device. In other words, high integration of the memory device can be achieved. Figure 18B and Figure 18C An example in which the width of the opening 190 is smaller than the width of the opening 290 and the width of the opening 270 is shown. There is no particular limitation on the size relationship between the width of the opening 190 and the width of the opening 290 or the width of the opening 270. From the viewpoint of miniaturization, the width of the opening 190 is preferably equal to or smaller than the width of the opening 290. Similarly, the width of the opening 190 is preferably equal to or smaller than the width of the opening 270.

[0522] Further, by providing the transistor 200A above the capacitor 100, the transistor 200A is not affected by the heat history at the time of manufacturing the capacitor 100. Thus, deterioration of the electrical characteristics of the transistor 200A, such as variation in threshold voltage and increase in parasitic resistance, and increase in unevenness of the electrical characteristics due to the deterioration of the electrical characteristics can be suppressed.

[0523] Figure 23A A circuit diagram of the memory device described in this embodiment is shown. As Figure 23A indicated in FIG. 2B, the transistor 200A overlaps with the capacitor 100. Further, the opening 290 and the opening 270 of the components included in the portion where the transistor 200A is provided have an area overlapping with the opening 190 of the components included in the portion where the capacitor 100 is provided. In particular, the conductive layer 120 is used as one of a source electrode and a drain electrode of the transistor 200A and as an upper electrode of the capacitor 100, whereby the transistor 200A and the capacitor 100 share a part of the components. With such a structure, the transistor 200A and the capacitor 100 can be provided without significantly increasing the area occupancy in plan view. Thus, the area occupancy of the memory cell 150 can be reduced, and thus the memory cells 150 can be arranged at high density to increase the storage capacity of the memory device. In other words, high integration of the memory device can be achieved. Figures 18A to 18C The structure shown is used as a memory cell. The memory cell 951 includes a transistor Ml and a capacitor CA. Here, the transistor Ml corresponds to the transistor 200A, and the capacitor CA corresponds to the capacitor 100.

[0524] One of a source and a drain of the transistor Ml is connected to one of a pair of electrodes of the capacitor CA. The other of the source and the drain of the transistor Ml is connected to a wiring BIL. A gate of the transistor Ml is connected to a wiring WOL. The other of the pair of electrodes of the capacitor CA is connected to a wiring CAL.

[0525] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 265, and the wiring CAL corresponds to the conductive layer 110. As Figures 18A to 18C As shown, it is preferable that the conductive layer 265 extend in the X direction and the conductive layer 240 extend in the Y direction. By employing such a structure, the wiring BIL and the wiring WOL cross each other. Further, in Figure 18A the wiring CAL (the conductive layer 110) is provided in a planar shape, but the present application is not limited to this. For example, the wiring CAL can be parallel to the wiring WOL (the conductive layer 265) or the wiring BIL (the conductive layer 240).

[0526] Note that the memory cell will be described in detail in later embodiments.

[0527] [Capacitor 100]

[0528] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120. Further, a conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0529] The conductive layer 110 is provided over the insulating layer 140. The conductive layer 110 is used as the wiring CAL and can be provided in a planar shape, for example. As the conductive layer 110, the conductive material described in [Conductive layer] of Embodiment 1 can be used to be formed in a single layer or a stacked layer. As the conductive layer 110, a conductive material with high conductivity such as tungsten can be used, for example. By using a conductive material with high conductivity in this manner, the conductivity of the conductive layer 110 can be improved so that the conductive layer 110 sufficiently functions as the wiring CAL.

[0530] Further, as the conductive layer 115, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen, or the like in a single layer or a stacked layer. For example, titanium nitride or indium tin oxide to which silicon is added, or the like can be used. Alternatively, for example, a structure in which tungsten is stacked with titanium nitride can be provided. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked in this order can be provided. By adopting such a structure, oxidation of the conductive layer 115 by the insulating layer 130 when the insulating layer 130 is made of an oxide can be suppressed. Further, oxidation of the conductive layer 115 by the insulating layer 180 when the insulating layer 180 is made of an oxide can be suppressed.

[0531] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to contact the top surface and the side surface of the conductive layer 115. That is, the insulating layer 130 preferably covers the side end portion of the conductive layer 115. By this, short-circuiting of the conductive layer 115 and the conductive layer 120 can be prevented.

[0532] Further, a structure in which the side end portion of the insulating layer 130 is aligned with the side end portion of the conductive layer 115 can be adopted. By adopting such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, and thus the manufacturing process of the storage device can be simplified.

[0533] As the insulating layer 130, a material having a high relative dielectric constant (high-k) is preferably used. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a degree at which leakage current can be suppressed and the electrostatic capacity of the capacitor 100 can be sufficiently ensured.

[0534] Further, as the insulating layer 130, it is preferable to use an insulating layer composed of a high-k material, and a stacked structure of a material having a high relative dielectric constant (high-k) and a material having a dielectric strength larger than that of the high-k material is preferably used. For example, as the insulating layer 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Further, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Further, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in this order can be used. By using an insulating layer having a large dielectric strength such as aluminum oxide in a stacked manner, the dielectric strength can be increased and the electrostatic breakdown of the capacitor 100 can be suppressed.

[0535] Further, as the insulating layer 130, a material that can have ferroelectricity can be used. Details of the material that can have ferroelectricity can be found in the description of Embodiment 1.

[0536] A metal oxide containing one or both of hafnium and zirconium has ferroelectricity even if it is a thin film with a thickness of several nm, and thus is preferably used for the insulating layer 130. The thickness of the insulating layer 130 can be 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and still further preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Further, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with a semiconductor element such as a transistor that is miniaturized to form a semiconductor device.

[0537] Further, a metal oxide containing one or both of hafnium and zirconium has ferroelectricity even if the area thereof is small, and thus is preferably used for the insulating layer 130. For example, a ferroelectric layer has ferroelectricity even if the area (occupied area) thereof when viewed from above is 100 μm 2 10 μm or less 2 1 μm or less 2 0.1 μm or less 2 10000 nm or less 2 1000 nm or less 2 Also has ferroelectricity. By making the area of the ferroelectric layer small, the occupied area of the capacitor 100 can be reduced.

[0538] A ferroelectric body is an insulator, has a property of being polarized inside by an applied electric field, and retains the polarization even when the electric field is 0. Thus, by using a capacitor in which this material is used as a dielectric (hereinafter, sometimes referred to as a ferroelectric capacitor), a nonvolatile memory element can be formed. A nonvolatile memory element using a ferroelectric capacitor is sometimes referred to as a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of a source and a drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, in the case where the ferroelectric capacitor is used as the capacitor 100, the storage device shown in the present embodiment is used as a ferroelectric memory.

[0539] The conductive layer 120 is provided so as to contact a part of the top surface of the insulating layer 130. The side end portion of the conductive layer 120 is preferably positioned inside the side end portion of the conductive layer 115 in both the X direction and the Y direction. Note that in the case where the insulating layer 130 covers the side end portion of the conductive layer 115, the side end portion of the conductive layer 120 can also be positioned outside the side end portion of the conductive layer 115.

[0540] As described above, conductive layer 120 corresponds to conductive layer 220 described in Embodiment 1, and therefore can be referred to the description in Embodiment 1.

[0541] Insulating layer 180 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layer 180, a single layer or a stack of insulating layers containing a material with a low relative permittivity can be used. Silicon oxide and silicon oxynitride have thermal stability and are therefore preferred.

[0542] Note that in Figure 18B and Figure 18C The diagram shows that the insulating layer 180 has a single-layer structure, but the invention is not limited to this. The insulating layer 180 may also have a two-layer stacked structure, or a three-layer or more stacked structure.

[0543] <Example 2 of storage device structure>

[0544] The memory cell 150, including transistor 200A and capacitor 100, shown in this embodiment, can be used as a memory cell of a memory device. Transistor 200A is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200A has a small off-state current, its use in a memory device allows for long-term retention of stored content. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the memory device can be significantly reduced. Furthermore, due to the high frequency characteristics of transistor 200A, high-speed read and write operations of the memory device are possible.

[0545] A storage cell array can be constructed by arranging the storage cells 150 in a three-dimensional and matrix manner.

[0546] Figure 19A This is a floor plan of the storage device. Figure 19A An example is shown where two × two storage cells (storage cells 150a to 150d) are arranged in the X and Y directions.

[0547] Figure 19B It is along Figure 19A The cross-sectional view shown is along the dashed-dot line A3-A4. Figure 19A and Figure 19B In the middle, two storage units (in Figure 19B In this configuration, storage cells 150a and 150b are connected to a common wiring (conductive layer 246).

[0548] Here, Figure 19A and Figure 19BThe storage units 150a and 150b each have the same structure as the storage unit 150. The storage unit 150a includes the capacitor 100a and the transistor 200a, and the storage unit 150b includes the capacitor 100b and the transistor 200b. Note that Figure 19A The storage units 150c and 150d each have the same structure as the storage unit 150. Thus, in the storage units 150c and 150d, Figure 19A and Figure 19B In the storage device, components having the same functions as the components of the storage device illustrated in FIG. 18 are denoted by the same reference numerals. Note that the details of the storage units 150a to 150d can be referred to the description of the storage unit 150 in <Structure Example 1 of Storage Device>.

[0549] As illustrated in Figure 19A and Figure 19B The conductive layer 265 serving as the wiring WOL is provided in each of the storage units 150a and 150b. Further, as illustrated in Figure 19A One conductive layer 265 is provided in common between the storage unit 150a and the storage unit 150c, and another conductive layer 265 is provided in common between the storage unit 150b and the storage unit 150d. Further, one conductive layer 240 serving as part of the wiring BIL is provided in common between the storage unit 150a and the storage unit 150b. In other words, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the storage unit 150a and the oxide semiconductor layer 230 of the storage unit 150b. Further, another conductive layer 240 is provided in common between the storage unit 150c and the storage unit 150d.

[0550] Figure 19B An example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b over the conductive layer 240a is illustrated. As described in Embodiment 1, it is preferable that a material having higher conductivity than the conductive layer 240b be used as the conductive layer 240a, and a conductive material containing oxygen be used as the conductive layer 240b.

[0551] Here, Figure 19A and Figure 19BThe storage units each include a conductive layer 245 and a conductive layer 246 serving as a plug (which can also be referred to as a connection electrode) electrically connected to the storage unit 150a and the storage unit 150b. The conductive layer 245 is provided in contact with a bottom surface of the conductive layer 240a in an opening portion formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, and the insulating layer 280. Further, the conductive layer 246 is provided in contact with a top surface of the conductive layer 240a in an opening portion formed in the insulating layer 287, the insulating layer 285, the insulating layer 250a, the oxide semiconductor layer 230, and the conductive layer 240b. As the conductive layer 245 and the conductive layer 246, a conductive material or the like which can be used for the conductive layer 240 can be used.

[0552] The conductive layer 246 can also be in contact with a top surface of the conductive layer 240b. Alternatively, the conductive layer 246 can also be in contact with a top surface of the oxide semiconductor layer 230. That is, the conductive layer 240b and the oxide semiconductor layer 230 can not have an opening portion at a position overlapping with the conductive layer 246. Among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230, a layer having lower contact resistance with the conductive layer 246 is preferably in contact with the conductive layer 246 as a connection portion of the storage unit and the plug.

[0553] Similarly, the conductive layer 245 can also be in contact with a bottom surface of the conductive layer 240b or a bottom surface of the oxide semiconductor layer 230. That is, the conductive layer 240a can have an opening portion at a position overlapping with the conductive layer 246. Among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230, a layer having lower contact resistance with the conductive layer 245 is preferably in contact with the conductive layer 245.

[0554] Further, among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230, a layer having lower wiring resistance is preferably in contact with the conductive layer 245 and the conductive layer 246.

[0555] The insulating layer 287 is used as an interlayer film, and thus its relative dielectric constant is preferably low. By using a material having a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0556] Further, the impurity concentration of water, hydrogen, or the like in the insulating layer 287 is preferably reduced. Thus, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230 can be suppressed.

[0557] The conductive layer 245 and the conductive layer 246 are used as plugs or wirings for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals to the storage unit 150a and the storage unit 150b. For example, a structure in which the conductive layer 245 is in contact with the conductive layer 240a provided in the insulating layer 287 and the conductive layer 246 is in contact with the conductive layer 240b provided in the insulating layer 285 can be employed. Figure 19BThe readout amplifier (not shown) under the storage device is electrically connected, and the conductive layer 246 is electrically connected with the readout amplifier provided under the storage device. Figure 19B The same storage device (not shown) on the storage device is electrically connected. In this case, the conductive layer 245 and the conductive layer 246 are used as part of the wiring BIL. In this way, by providing a storage device or the like above or below the storage device, Figure 19B The storage device shown above or below the storage device can increase the storage capacity per unit area.

[0558] Further, the storage unit 150a and the storage unit 150b are linearly symmetrical with the vertical bisector of the dotted line A3-A4 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged symmetrically with the conductive layer 245 and the conductive layer 246 sandwiched therebetween. Here, the conductive layer 240 serves as the other of the source electrode and the drain electrode of the transistor 200a and the other of the source electrode and the drain electrode of the transistor 200b. Further, the transistor 200a and the transistor 200b share the conductive layer 245 and the conductive layer 246 serving as the plug. In this way, by adopting the above structure as the connection relationship of two transistors and a plug, a storage device that can achieve miniaturization or high integration can be provided.

[0559] Further, the conductive layer 110 serving as the wiring CAL can be provided in the storage unit 150a and the storage unit 150b, respectively, or can be provided in the storage unit 150a and the storage unit 150b in common. Note that, as Figure 19B As shown, the conductive layer 110 is provided in a manner separated from the conductive layer 245 so as not to short-circuit the conductive layer 110 and the conductive layer 245.

[0560] Further, Figure 20 An example of four storage units stacked in the Z direction is shown. Figure 19A An example of four storage units stacked in the Z direction is shown. Figure 20 is a cross-sectional view along the dotted line A3-A4 shown. Figure 19A is a cross-sectional view along the dotted line A3-A4 shown.

[0561] Figure 20 The storage device shown includes n layers of storage layers 160. Specifically, the storage layer 160[1] has the storage layer 160[2] provided thereon, the storage layer 160[2] has (n-2) layers of storage layers provided thereon, and the storage layer 160[n] is provided as the uppermost layer. The number of storage units included in one storage layer 160 is not particularly limited and can include two or more storage units. The storage units included in the n layers of storage layers 160 are electrically connected with the readout amplifier (not shown) provided under the n layers of storage layers 160 by the conductive layer 245, the conductive layer 246, the conductive layer 247, and the conductive layer 248, and the like.

[0562] Figure 20An example is shown in which the conductive layer 245 is in contact with the bottom surface of the conductive layer 240 and the conductive layer 246 is in contact with the top surface of the oxide semiconductor layer 230. As described above, the plug of the conductive layer 245 and the conductive layer 246 and the like can be connected to each storage unit in various ways, and is not limited to Figure 20 the structure.

[0563] As Figure 20 shown, a plurality of storage units can be stacked to configure a unit in an integrated manner without increasing the area occupied by the array of storage units. That is, a 3D array of storage units can be formed.

[0564] Figure 21 A cross-sectional structure example of a storage device in which a layer provided with a drive circuit including a read amplifier is stacked with a layer including a storage unit is shown.

[0565] In Figure 21 , the storage unit 150 (transistor 200A and capacitor 100) is provided above the transistor 300.

[0566] The transistor 300 is one of the transistors included in the read amplifier.

[0567] Regarding the storage unit 150 shown in Figure 21 , the description of the storage unit 150 in <Structure Example 1 of Storage Device> can be referred to.

[0568] As shown in Figure 21 , by using a structure in which the read amplifier is provided so as to overlap the storage unit 150, the bit line can be shortened. Thus, the bit line capacitance can be reduced, and high-speed driving of the storage device can be achieved.

[0569] Figure 21 The storage device shown in can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the read amplifier 927 in the semiconductor device 900. Further, the storage unit 150 corresponds to the storage unit 950.

[0570] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 serving as a gate electrode, an insulating layer 315 serving as a gate insulating layer, a semiconductor region 313 formed of a part of the substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. The transistor 300 can be of a p-channel type or an n-channel type.

[0571] Figure 21In the transistor 300 illustrated, the semiconductor region 313 (a portion of the substrate 311) forming a channel has a convex shape. Further, a conductive layer 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulating layer 315 interposed therebetween. Further, the conductive layer 316 can also use a material that adjusts a work function. Since the convex portion of the semiconductor substrate is utilized, such a transistor 300 is also referred to as a FIN transistor. Further, the insulating layer that is used as a mask when the convex portion is formed can be in contact with the upper portion of the convex portion. Further, although the case where a portion of the semiconductor substrate is processed to form the convex portion is illustrated here, a semiconductor film having a convex portion can also be formed by processing an SOI substrate.

[0572] Note that, Figure 21 The structure of the transistor 300 illustrated is just an example, and the above structure is not limiting, and an appropriate transistor can be used depending on the circuit structure or the driving method.

[0573] A wiring layer including an interlayer film, a wiring, and a plug, and the like can be provided between the structures. Further, the wiring layer can be provided in multiple layers depending on the design. Here, in the conductive layer having a function of a plug or a wiring, the same reference numerals are sometimes used to indicate a plurality of structures. Further, in this specification and the like, a wiring and a plug electrically connected to a wiring can be one component. That is, part of a conductive layer is sometimes used as a wiring, and part of a conductive layer is sometimes used as a plug.

[0574] For example, over the transistor 300, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are provided in this order as an interlayer film. Further, a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. Further, the conductive layer 328 and the conductive layer 330 are used as a plug or a wiring.

[0575] Further, the insulating layer used as an interlayer film can be used as a planarization film that covers a concavo-convex shape thereunder. For example, in order to improve the planarity of the top surface of the insulating layer 322, the top surface thereof can be planarized by a planarization treatment such as a CMP method.

[0576] Further, a wiring layer can also be formed over the insulating layer 326 and the conductive layer 330. For example, in Figure 21 the insulating layer 350, the insulating layer 352, and the insulating layer 354 are provided in this order. Further, a conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 is used as a plug or a wiring.

[0577] As the insulating layer 352 and the insulating layer 354, and the like used as an interlayer film, the above insulating layer that can be used for a semiconductor device or a memory device can be used.

[0578] As the conductive layer 328, the conductive layer 330, and the conductive layer 356, which are used as a plug or a wiring, a conductive material that can be used for the conductive layer 240 can be used. A high melting point material such as tungsten or molybdenum, which has heat resistance and conductivity, is preferably used, and tungsten is particularly preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, the resistance of a wiring can be reduced.

[0579] The conductive layer 240 included in the transistor 200A is electrically connected to the low-resistance region 314b serving as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0580] The conductive layer 643 is embedded in the insulating layer 280. The conductive layer 642 is provided over the insulating layer 130 and is embedded in the insulating layer 641. The conductive layer 642 can be formed using the same material and process as the conductive layer 120. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 is embedded in the insulating layer 180. The conductive layer 645 can be formed using the same material and process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The transistor 300 and the conductive layer 110 are electrically insulated from each other by the insulating layer 648.

[0581] As described above, the storage device of this embodiment includes a transistor in which a parasitic capacitance is reduced, and thus the operation speed can be increased. Further, since the storage device of this embodiment has a capacitor and a transistor stacked thereover, the area occupied by the storage unit in plan view can be reduced, and thus a storage device with high integration can be achieved.

[0582] This embodiment can be combined with other embodiments as appropriate.

[0583] (Embodiment 3)

[0584] In this embodiment, a semiconductor device 900 according to one embodiment of the present application will be described. The semiconductor device 900 can be used as a storage device.

[0585] Figure 22 is a block diagram illustrating a structure example of the semiconductor device 900. Figure 22 The semiconductor device 900 illustrated in the drawing includes a driver circuit 910 and a memory array 920. The memory array 920 includes one or more storage units 950. Figure 22 An example in which the memory array 920 includes a plurality of storage units 950 arranged in a matrix is illustrated.

[0586] As the storage unit 950, the storage device described in Embodiment 2 (the storage unit 150 or the like) can be used.

[0587] The drive circuit 910 includes PSWs 931 (power switches), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes the peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0588] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately omitted as needed. Alternatively, other circuits or other signals can be added. The signal BW, the signal CE, the signal GW, the signal CLK, the signal WAKE, the signal ADDR, the signal WDA, the signal PON1, and the signal PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0589] Further, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. Further, the signal PON1 and the signal PON2 can be generated in the control circuit 912.

[0590] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (e.g., a write operation, a read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal of the peripheral circuit 911 to perform the above-described operation mode.

[0591] The voltage generation circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a signal of an H level is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0592] The peripheral circuit 911 is a circuit for performing data write and read to and from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0593] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0594] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0595] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high power supply potential of the semiconductor device 900 is V. DD The low power supply potential is GND (ground potential). Additionally, V HM It is a high power supply potential used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. Figure 22 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be one, but it can also be multiple. In this case, power switches can be set for each power domain.

[0596] Reference Figures 23A to 23H This section describes an example of the structure of a storage cell that can be used in storage cell 950.

[0597] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state; therefore, the above situations are included within the scope of electrical connections.

[0598] [DOSRAM]

[0599] Figure 23A An example circuit structure of a DRAM-type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0600] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may be connected to a wiring supplied with a constant potential or signal, or it may be connected to the front gate.

[0601] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0602] The BIL (Bite Line) wiring is used as the bit line, and the WOL (Word Line) wiring is used as the word line. The CAL (Chip Line) wiring is used to apply a predetermined potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL wiring.

[0603] By applying a high-level potential to the wiring WOL, transistor M1 is turned on, which in turn makes the wiring BIL and the first terminal of capacitor CA a conductive state (a state that allows current to flow), enabling data writing and reading.

[0604] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used... Figure 23B The storage cell 952 is shown. Storage cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0605] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0606] Further, as the transistor Ml, an OS transistor is preferably used. The OS transistor has a characteristic of having a very small off-state current. By using the OS transistor as the transistor Ml, the leakage current of the transistor Ml can be made very low. That is, the transistor Ml can hold written data for a long time, and thus the refresh frequency of the memory cell can be reduced. Further, the refresh operation of the memory cell can be omitted. Furthermore, since the leakage current is very low, multi-value data or analog data can be held in the memory cell 951 and the memory cell 952.

[0607] [NOSRAM]

[0608] Figure 23C A circuit structure example of a memory cell of a gain cell type including two transistors and one capacitor is shown. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device including a memory cell of a gain cell type in which an OS transistor is used as the transistor M2 is sometimes referred to as an NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0609] The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to a wiring WBL, and the gate of the transistor M2 is connected to a wiring WOL. The second terminal of the capacitor CB is connected to a wiring CAL. The first terminal of the transistor M3 is connected to a wiring RBL, the second terminal of the transistor M3 is connected to a wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0610] The wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. At the time of data writing, at the time of data holding, and at the time of data reading, a low-level potential (sometimes referred to as a reference potential) is preferably applied to the wiring CAL.

[0611] Data is written by making the transistor M2 into an on state by applying a high-level potential to the wiring WOL, and making the wiring WBL and the first terminal of the capacitor CB into a conduction state. Specifically, when the transistor M2 is in an on state, a potential corresponding to information to be recorded is applied to the wiring WBL, and thus the first terminal of the capacitor CB and the gate of the transistor M3 are written with the potential. Then, the transistor M2 is made into an off state by applying a low-level potential to the wiring WOL, whereby the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3 are held.

[0612] The reading of data is performed by applying a predetermined potential to the wiring SL. Since the current flowing between the source and the drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. That is, the information written in the memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0613] For example, a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL can be employed. Figure 23D A circuit structure example of the memory cell in this case is shown. In the memory cell 954, the wiring WBL and the wiring RBL of the memory cell 953 are combined into one wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. That is, the memory cell 954 operates with the write bit line and the read bit line combined into one wiring BIL.

[0614] Figure 23E The memory cell 955 shown is an example in which the capacitor CB and the wiring CAL in the memory cell 953 are omitted. In addition, Figure 23F The memory cell 956 shown is an example in which the capacitor CB and the wiring CAL in the memory cell 954 are omitted. By employing such a structure, the degree of integration of the memory cell can be increased.

[0615] Note that it is preferable that the OS transistor be used at least as the transistor M2. In particular, it is preferable that the OS transistor be used as the transistor M2 and the transistor M3.

[0616] Since the OS transistor has a characteristic of having a very small off-state current, the transistor M2 can hold written data for a long time, which can reduce the refresh frequency of the memory cell. In addition, the refresh operation of the memory cell can be omitted. Furthermore, since the leakage current is very low, the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956 can hold multi-value data or analog data.

[0617] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956 in which the OS transistor is used as the transistor M2 are one embodiment of an NOSRAM.

[0618] As the transistor M3, a Si transistor can be used. The Si transistor can increase the field-effect mobility and can be a p-channel transistor, so the degree of freedom in circuit design can be increased.

[0619] Further, when the OS transistor is used as the transistor M3, the storage unit can be constituted by unipolar circuits.

[0620] Further, Figure 23G A gain cell type storage unit 957 including three transistors and one capacitor is shown. The storage unit 957 includes transistors M4 to M6 and a capacitor CC.

[0621] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor CC is connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0622] The wiring BIL is used as a bit line, the wiring WOL is used as a write word line, and the wiring RWL is used as a read word line. The wiring GNDL is a wiring supplying a low potential.

[0623] Data is written by making the transistor M4 an on state by applying a high potential to the wiring WOL, and making the wiring BIL and the first terminal of the capacitor CC an on state. Specifically, when the transistor M4 is in an on state, a potential corresponding to information to be recorded is applied to the wiring BIL to write the potential to the first terminal of the capacitor CC and the gate of the transistor M5. Then, the transistor M4 is made an off state by applying a low potential to the wiring WOL, whereby the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5 are held.

[0624] Data is read by making the wiring BIL electrically floating after precharging the wiring BIL to a predetermined potential, and applying a high potential to the wiring RWL. The transistor M6 is made an on state by making the wiring RWL a high potential, and the wiring BIL and the second terminal of the transistor M5 are made an on state. At this time, the potential of the second terminal of the transistor M5 is applied with the potential of the wiring BIL, but the potential of the second terminal of the transistor M5 and the potential of the wiring BIL are changed in correspondence with the potential held by the first terminal of the capacitor CC (or the gate of the transistor M5). Here, the potential held by the first terminal of the capacitor CC (or the gate of the transistor M5) can be read by reading the potential of the wiring BIL. That is, information written to the storage unit can be read from the potential held by the first terminal of the capacitor CC (or the gate of the transistor M5).

[0625] Note that it is preferable that the OS transistor be used at least as the transistor M4.

[0626] As the transistors M5 and M6, Si transistors can be used. As described above, depending on the crystal state of silicon used for the semiconductor layer and the like, the field-effect mobility of the Si transistor is sometimes higher than that of the OS transistor.

[0627] Further, when the OS transistor is used as the transistors M5 and M6, the storage unit can be constituted by unipolar circuits.

[0628] [OS-SRAM]

[0629] Figure 23H An example of an SRAM (Static Random Access Memory) using the OS transistor is shown. In this specification and the like, the SRAM using the OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Further, Figure 23H The storage unit 958 shown is a storage unit of an SRAM type capable of backup.

[0630] The storage unit 958 includes transistors M7 to M10, transistors MS1 to MS4, a capacitor CD1, and a capacitor CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0631] The first terminal of the transistor M7 is connected to a wiring BIL, and the second terminal of the transistor M7 is connected to the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, the gate of the transistor MS4, and the first terminal of the transistor M10. The gate of the transistor M7 is connected to a wiring WOL. The first terminal of the transistor M8 is connected to a wiring BILB, and the second terminal of the transistor M8 is connected to the first terminal of the transistor MS2, the first terminal of the transistor MS4, the gate of the transistor MS1, the gate of the transistor MS3, and the first terminal of the transistor M9. The gate of the transistor M8 is connected to the wiring WOL.

[0632] The second terminal of the transistor MS1 is connected to a wiring VDL. The second terminal of the transistor MS2 is connected to the wiring VDL. The second terminal of the transistor MS3 is connected to a wiring GNDL. The second terminal of the transistor MS4 is connected to the wiring GNDL.

[0633] The second terminal of the transistor M9 is connected to the first terminal of the capacitor CD1, and the gate of the transistor M9 is connected to a wiring BRL. The second terminal of the transistor M10 is connected to the first terminal of the capacitor CD2, and the gate of the transistor M10 is connected to the wiring BRL.

[0634] The second terminal of the capacitor CD1 is connected to the wiring GNDL, and the second terminal of the capacitor CD2 is connected to the wiring GNDL.

[0635] The wiring BIL and the wiring BILB are used as bit lines, the wiring WOL is used as a word line, and the wiring BRL is a wiring for controlling the on state and the off state of the transistor M9 and the transistor M10.

[0636] The wiring VDL is a wiring for supplying a high-level potential, and the wiring GNDL is a wiring for supplying a low-level potential.

[0637] The writing of data is performed by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in the on state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the side of the second terminal of the transistor M10.

[0638] The storage unit 958 configures an inverter loop with the transistors MS1 to MS2, so an inverted signal of a data signal corresponding to the potential is input to the side of the second terminal of the transistor M8. Since the transistor M8 is in the on state, the potential applied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL is output to the wiring BILB. Further, since the transistor M9 and the transistor M10 are in the on state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held by the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Then, the potential of the first terminal of the capacitor CD1 and the potential of the first terminal of the capacitor CD2 are held by making the transistors M7 to M10 into the off state by applying a low-level potential to the wiring WOL and a low-level potential to the wiring BRL.

[0639] The reading of data is performed by the following method: first, the wiring BIL and the wiring BILB are precharged to a predetermined potential, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL, whereby the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the storage unit 958 and is output to the wiring BILB. Further, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the storage unit 958 and is output to the wiring BIL. Since the wiring BIL and the wiring BILB change from the precharged potential to the potential of the first terminal of the capacitor CD2 and the potential of the first terminal of the capacitor CD1, respectively, the potential held by the storage unit can be read from the potential of the wiring BIL or the wiring BILB.

[0640] Further, the transistors M7 to M10 are preferably OS transistors. By this, the transistors M7 to M10 can hold the written data for a long time, and thus the refresh frequency of the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be omitted.

[0641] Further, the transistors MS1 to MS4 are preferably Si transistors.

[0642] The driving circuit 910 and the memory array 920 included in the semiconductor device 900 are provided on the same plane. Further, as illustrated in FIG. 9B, the driving circuit 910 and the memory array 920 can also overlap with each other. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 24A As illustrated in FIG. 9C, a plurality of memory arrays 920 can also be stacked over the driving circuit 910. Figure 24B

[0643] Next, one example of an arithmetic processing device including the semiconductor device such as the memory device described above will be described.

[0644] Figure 25 is a block diagram of an arithmetic device 960. Figure 25 The arithmetic device 960 illustrated in FIG. 10A can be used for a CPU (Central Processing Unit), for example. Further, the arithmetic device 960 can also be used for a GPU (Graphics Processing Unit) including a plurality of (tens to hundreds) processor cores capable of parallel processing, a TPU (Tensor Processing Unit), an NPU (Neural Processing Unit), and the like.

[0645] Figure 25 The arithmetic device 960 illustrated in FIG. 10B includes, over a substrate 990, an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. As the substrate 990, a semiconductor substrate, an SOI substrate, a glass substrate, and the like are used. A rewritable ROM and a ROM interface can also be included. The cache 999 and the cache interface 989 can also be provided on different chips.

[0646] ​The cache 999 is connected to the main memory provided on a different chip through the cache interface 989. The cache interface 989 has a function of supplying a portion of data stored in the main memory to the cache 999. Further, the cache interface 989 has a function of outputting a portion of data held in the cache 999 to the ALU 991 or the register 996 or the like through the bus interface 998.

[0647] As described later, the memory array 920 can be provided in a manner of being stacked on the arithmetic device 960. The memory array 920 can be used as a cache. At this time, the cache interface 989 can have a function of supplying data held in the memory array 920 to the cache 999. Further, at this time, it is preferable that a portion of the cache interface 989 include the drive circuit 910.

[0648] Note that the cache 999 can not be provided and only the memory array 920 can be used as a cache.

[0649] Figure 25 The illustrated arithmetic device 960 is only one example of a simplified structure thereof, and an actual arithmetic device 960 has various structures according to its use. For example, it is preferable to adopt a structure including a plurality of cores provided in a so-called multi-core structure and made to operate simultaneously. Figure 25 The structure of the illustrated arithmetic device 960 is one core, and a plurality of cores are provided and made to operate simultaneously in a so-called multi-core structure. The more the number of cores, the higher the arithmetic performance can be improved. The more the number of cores, the more preferable, for example, it is preferable to be 2, more preferable to be 4, further preferable to be 8, more further preferable to be 12, still further preferable to be 16 or more. Further, when a very high arithmetic performance is required in a case of use in a server or the like, it is preferable to adopt a multi-core structure including 16 or more, preferably including 32 or more, more preferably including 64 or more cores. Further, the number of bits that can be processed in the internal arithmetic circuit, the data bus, or the like of the arithmetic device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

[0650] The instruction input to the arithmetic device 960 through the bus interface 998 is input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

[0651] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and reads and writes register 996 according to the state of the arithmetic unit 960.

[0652] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0653] exist Figure 25 In the illustrated arithmetic unit 960, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten on the capacitors, and the power supply potential to the memory cells in register 996 can be stopped.

[0654] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 26A and Figure 26B This is a perspect...

Claims

1. A semiconductor device, comprising: Oxide semiconductor layer; First conductive layer; Second conductive layer; Third conductive layer; First insulating layer; as well as Second insulating layer, The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The oxide semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the second conductive layer, and the side surface of the first insulating layer. The second insulating layer is located on the oxide semiconductor layer. The third conductive layer is located on the second insulating layer and overlaps with the oxide semiconductor layer through the second insulating layer. The first insulating layer has a first region that contacts the oxide semiconductor layer. Furthermore, the first region contains halogen elements.

2. A semiconductor device, comprising: Oxide semiconductor layer; First conductive layer; Second conductive layer; Third conductive layer; First insulating layer; as well as Second insulating layer, The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer include a first opening extending into the first conductive layer. The oxide semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the second conductive layer, and the side surface of the first insulating layer within the first opening. The second insulating layer is located on the oxide semiconductor layer within the first opening. The third conductive layer overlaps with the oxide semiconductor layer within the first opening, separated by the second insulating layer. The first insulating layer has a first region that contacts the oxide semiconductor layer. Furthermore, the first region contains halogen elements.

3. The semiconductor device according to claim 1 or 2, The halogen element is selected from one or more of chlorine, fluorine, bromine and iodine.

4. The semiconductor device according to claim 1 or 2, The halogen element mentioned therein is chlorine or fluorine.

5. The semiconductor device according to claim 1 or 2, The oxide semiconductor layer has a second region that contacts the top surface of the first conductive layer and a third region that contacts the top surface of the second conductive layer. The second region and the third region contain the first element. And the first element is boron or phosphorus.

6. A semiconductor device, comprising: Oxide semiconductor layer; First conductive layer; Second conductive layer; Third conductive layer; First insulating layer; Second insulating layer; Third insulating layer; as well as Fourth insulating layer The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer include a first opening extending into the first conductive layer. The oxide semiconductor layer is in contact with the top surface of the second conductive layer, and within the first opening, it is in contact with the top surface of the first conductive layer, the side surface of the second conductive layer, and the side surface of the first insulating layer. The second insulating layer has a portion that overlaps with the top surface of the second conductive layer across the oxide semiconductor layer and a portion located on the oxide semiconductor layer within the first opening. The third insulating layer is located on the second insulating layer, and includes a second opening that reaches the second insulating layer at a position overlapping with the first opening. The fourth insulating layer contacts the side of the third insulating layer within the second opening, and overlaps with the oxide semiconductor layer within the first opening, separated by the second insulating layer. The third conductive layer is located on the fourth insulating layer and overlaps with the oxide semiconductor layer within the first opening, separated by the second insulating layer and the fourth insulating layer.

7. The semiconductor device according to claim 6, In cross-section, the maximum width of the third conductive layer within the second opening is less than or equal to the minimum width of the first opening within the second conductive layer.

8. The semiconductor device according to claim 6, The first insulating layer is included on the fifth insulating layer. The first opening in the first insulating layer has a first surface and a second surface above the first surface. Furthermore, when viewed in section, the angle formed between the first surface and the top surface of the fifth insulating layer is smaller than the angle formed between the second surface and the top surface of the fifth insulating layer.

9. The semiconductor device according to claim 6, The first insulating layer is included on the fifth insulating layer. The first insulating layer includes a first layer and a second layer on top of the first layer. Furthermore, when viewed in cross-section, the angle formed between the side surface of the first opening in the first layer and the top surface of the fifth insulating layer is smaller than the angle formed between the side surface of the first opening in the second layer and the top surface of the fifth insulating layer.

10. The semiconductor device according to claim 6, The first conductive layer has a portion in the region that contacts the oxide semiconductor layer with a thickness smaller than that in the region that contacts the first insulating layer.

11. The semiconductor device according to claim 6, The first insulating layer is included on the fifth insulating layer. Furthermore, the angle formed between the side surface of the first opening of the first insulating layer and the top surface of the fifth insulating layer is more than 65 degrees and less than 90 degrees.

12. The semiconductor device according to claim 6, The maximum width of the second opening in cross-section is less than or equal to the minimum width of the first opening in the second conductive layer.

13. The semiconductor device according to claim 6, The third conductive layer overlaps with the top surface of the third insulating layer, which is separated from the fourth insulating layer.

14. The semiconductor device of claim 6, further comprising: Fourth conductive layer The fourth conductive layer is in contact with the top surface of the third insulating layer, the top surface of the fourth insulating layer, and the top surface of the third conductive layer.

15. The semiconductor device of claim 6, further comprising: Fifth conductive layer The first insulating layer includes a first layer and a second layer on the first layer. The fifth conductive layer is located on the first layer. The second layer covers the top and side surfaces of the fifth conductive layer. In cross-section, the oxide semiconductor layer has a region that overlaps with the fifth conductive layer through the second layer and with the third conductive layer through the second insulating layer and the fourth insulating layer.

16. The semiconductor device according to claim 6, When viewed in section perpendicular to the extension direction of the first conductive layer, the maximum width of the first conductive layer is less than or equal to the minimum width of the first opening in the second conductive layer.

17. The semiconductor device according to any one of claims 6 to 16, The first insulating layer has a first region that contacts the oxide semiconductor layer. Furthermore, the first region contains halogen elements.

18. The semiconductor device according to claim 17, The halogen element is selected from one or more of chlorine, fluorine, bromine and iodine.

19. The semiconductor device according to claim 17, The halogen element mentioned therein is chlorine or fluorine.

20. The semiconductor device according to any one of claims 6 to 16, The oxide semiconductor layer has a second region that contacts the top surface of the first conductive layer and a third region that contacts the top surface of the second conductive layer. The second region and the third region contain the first element. And the first element is boron or phosphorus.

21. A method for manufacturing a semiconductor device, comprising the following steps: A first conductive layer is formed on the substrate; A first insulating film is formed on the first conductive layer; A second conductive layer, including a first opening, is formed on the first insulating film in a region overlapping with the first conductive layer; The first insulating film is processed to form a first insulating layer including a second opening reaching the first conductive layer; Halogen elements are supplied to the side of the second opening in the first insulating layer; An oxide semiconductor layer is formed that is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the top surface and side surface of the second conductive layer. A second insulating layer is formed on the oxide semiconductor layer; A third insulating layer is formed on the second insulating layer in a region that overlaps with the first opening and the second opening, including the third opening; A fourth insulating layer is formed on the third insulating layer; A third conductive layer is formed on the fourth insulating layer; The third conductive layer and the fourth insulating layer are processed using chemical mechanical polishing to expose the top surface of the third insulating layer; and A fourth conductive layer is formed on the third insulating layer, the fourth insulating layer, and the third conductive layer.

22. The method for manufacturing a semiconductor device according to claim 21, The first element is supplied to the oxide semiconductor layer after the formation of the oxide semiconductor layer and before the formation of the second insulating layer. The first element is boron or phosphorus. The first element is supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate.

23. The method for manufacturing a semiconductor device according to claim 21, The first element is supplied to the top surface of the first conductive layer and the top surface of the second conductive layer after the formation of the first insulating layer and before the formation of the oxide semiconductor layer. The first element is boron or phosphorus. The first element is supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate.

24. The method for manufacturing a semiconductor device according to claim 21, A second insulating film is formed on the second insulating layer. The first element is supplied to the oxide semiconductor layer via the second insulating film. After the first element is supplied, the second insulating film is processed to form the second insulating layer. The first element is boron or phosphorus. The first element is supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate.

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