Semiconductor device, power conversion device, monomous package, and method for manufacturing monomous package

Abstract

Provided is a semiconductor device in which the design of a printed wiring board for connecting a plurality of semiconductor elements to each other is easier than in the prior art. The semiconductor device (101) is characterized by comprising a printed wiring substrate (17), a monolithic package (201), and a relay substrate (3). The sum of the number of first regions (62) on the surface of the printed wiring board and the number of second regions (63) on the surface of the printed wiring board included in the printed wiring board surface pattern (32) is smaller than the sum of the number of first electrodes (22) and the number of second electrodes (23) included in the plurality of semiconductor elements (14) included in the plurality of monolithic packages (201). The sum of the number of first regions (82) on the relay substrate surface and the number of second regions (83) on the relay substrate surface included in the relay substrate surface pattern (34) is smaller than the sum of the number of first regions (62) on the printed wiring substrate surface and the number of second regions (63) on the plurality of printed wiring substrate surfaces.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, a power conversion device, a monolithic package, and a manufacturing method of a monolithic package. BACKGROUND

[0002] In the related art, a power module in which an electrode portion for connecting an electrode and a printed wiring board is provided on an upper portion of a semiconductor chip is disclosed (for example, Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2003-133514 SUMMARY

[0004] However, in the related art, in a case where a plurality of semiconductor elements are arranged to form a circuit, there are a plurality of electrodes on a directly upper portion of the semiconductor elements, that is, on a side where an emitter and a gate are provided. In order to connect the plurality of electrodes to each other, a circuit for connecting the plurality of electrodes to each other by a printed wiring board becomes complicated, and design of the printed wiring board also becomes complicated.

[0005] The present application has been made in view of the above-described problems, and has an object to provide a semiconductor device in which design of a printed wiring board for connecting a plurality of semiconductor elements to each other is facilitated compared to the related art.

[0006] The semiconductor device according to the present application includes a heat sink, and a plurality of semiconductor elements provided on the heat sink, the semiconductor elements having a first electrode and a second electrode, the second electrode being on a side of the heat sink, and the first electrode being on a side opposite to the heat sink.

[0007] Further, the semiconductor device according to the present application includes a printed wiring board having a printed wiring board back surface pattern and a printed wiring board surface pattern, the printed wiring board back surface pattern being provided on a side opposite to the heat sink with respect to the semiconductor elements, including a first region of the printed wiring board back surface electrically connected to the first electrode, and a second region of the printed wiring board back surface electrically connected to the second electrode via a conductive spacer provided on the heat sink, the printed wiring board surface pattern being provided on a side opposite to the semiconductor elements with respect to the printed wiring board back surface pattern, including a first region of the printed wiring board surface and a second region of the printed wiring board surface electrically connected to the first region of the printed wiring board back surface and the second region of the printed wiring board back surface, respectively.

[0008] Further, the semiconductor device according to the present application includes a plurality of monolithic packages having a heat sink, a plurality of semiconductor elements, and a printed wiring.

[0009] Further, the semiconductor device according to the present application includes a relay substrate having a relay substrate back surface pattern and a relay substrate surface pattern, the relay substrate back surface pattern electrically connecting a plurality of single package components, the relay substrate back surface pattern being disposed on the opposite side of the semiconductor element with respect to the printed wiring substrate, the relay substrate back surface pattern including a first region of the relay substrate back surface and a second region of the relay substrate back surface that are electrically connected to a first region of the printed wiring substrate surface and a second region of the printed wiring substrate surface, respectively, the relay substrate surface pattern being disposed on the opposite side of the relay substrate back surface pattern with respect to the semiconductor element, the relay substrate surface pattern including a first region of the relay substrate surface and a second region of the relay substrate surface that are electrically connected to the first region of the relay substrate back surface and the second region of the relay substrate back surface, respectively.

[0010] Further, the semiconductor device according to the present application is characterized in that the sum of the number of the first region of the printed wiring substrate surface and the second region of the printed wiring substrate surface included in the printed wiring substrate surface pattern is smaller than the sum of the number of the first electrode and the second electrode possessed by the plurality of semiconductor elements included in the plurality of single package components, and the sum of the number of the first region of the relay substrate surface and the second region of the relay substrate surface included in the relay substrate surface pattern is smaller than the sum of the number of the first region of the printed wiring substrate surface and the second region of the printed wiring substrate surface.

[0011] Further, the single package component according to the present application includes a heat sink, and a plurality of semiconductor elements disposed on the heat sink, the semiconductor element having a first electrode and a second electrode, the second electrode being on the side of the heat sink, and the first electrode being on the opposite side of the heat sink.

[0012] Further, the single package component according to the present application includes a printed wiring substrate having a printed wiring substrate back surface pattern and a printed wiring substrate surface pattern, the printed wiring substrate back surface pattern being disposed on the opposite side of the semiconductor element with respect to the heat sink, the printed wiring substrate back surface pattern including a first region of the printed wiring substrate back surface electrically connected to the first electrode and a second region of the printed wiring substrate back surface electrically connected to the second electrode via a spacer disposed on the heat sink, the printed wiring substrate surface pattern being disposed on the opposite side of the printed wiring substrate back surface pattern with respect to the semiconductor element, the printed wiring substrate surface pattern including a first region of the printed wiring substrate surface and a second region of the printed wiring substrate surface that are electrically connected to the first region of the printed wiring substrate back surface and the second region of the printed wiring substrate back surface, respectively.

[0013] Further, the single package component according to the present application is characterized in that the sum of the number of the first region of the printed wiring substrate surface and the second region of the printed wiring substrate surface included in the printed wiring substrate surface pattern is smaller than the sum of the number of the first electrode and the second electrode possessed by the plurality of semiconductor elements included in the plurality of single package components.

[0014] Further, the manufacturing method of the single-package semiconductor device according to the present application includes the steps of: disposing a plurality of semiconductor elements on a heat sink, the semiconductor elements having a first electrode and a second electrode, the second electrode being on the side of the heat sink, and the first electrode being on the side opposite to the heat sink.

[0015] Further, the manufacturing method of the single-package semiconductor device according to the present application includes the steps of: disposing a printed wiring substrate on the side opposite to the semiconductor elements with respect to the heat sink, the printed wiring substrate having a printed wiring substrate back surface pattern and a printed wiring substrate surface pattern, the printed wiring substrate back surface pattern including a first region of the printed wiring substrate back surface electrically connected to the first electrode and a second region of the printed wiring substrate back surface electrically connected to the second electrode via a spacer disposed on the heat sink, and the printed wiring substrate surface pattern being disposed on the side opposite to the semiconductor elements with respect to the printed wiring substrate back surface pattern, including a first region of the printed wiring substrate surface electrically connected to the first region of the printed wiring substrate back surface and a second region of the printed wiring substrate surface electrically connected to the second region of the printed wiring substrate back surface.

[0016] Further, the manufacturing method of the single-package semiconductor device according to the present application is characterized in that the sum of the number of the first region of the printed wiring substrate surface and the second region of the printed wiring substrate surface included in the printed wiring substrate surface pattern is smaller than the sum of the number of the first electrode and the second electrode possessed by the plurality of semiconductor elements.

[0017] Effects of the Invention

[0018] According to the semiconductor device according to the present application, the design of the printed wiring substrate for connecting the plurality of semiconductor elements to each other can be easily performed compared to the past. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present application.

[0020] Figure 2 is a cross-sectional view of a single-package semiconductor device according to Embodiment 1 of the present application.

[0021] Figure 3 is a plan view of a semiconductor element and a heat sink included in the single-package semiconductor device according to Embodiment 1 of the present application.

[0022] Figure 4 is a plan view of a semiconductor element and a heat sink included in the single-package semiconductor device according to Embodiment 1 of the present application.

[0023] Figure 5 is a circuit pattern of a printed wiring substrate included in the single-package semiconductor device according to Embodiment 1 of the present application.

[0024] Figure 6 is a schematic view of the upper surface of a printed wiring substrate included in a single package of Embodiment 1 of the present application.

[0025] Figure 7 is a schematic view of the lower surface of a plurality of semiconductor elements and a printed wiring substrate included in a single package of Embodiment 1 of the present application.

[0026] Figure 8 is a schematic view of the upper surface of a single package of Embodiment 1 of the present application.

[0027] Figure 9 is a schematic view of the circuit pattern of a relay substrate of Embodiment 1 of the present application.

[0028] Figure 10 is a schematic view of the upper surface of a plurality of single packages and the lower surface of a relay substrate of Embodiment 1 of the present application.

[0029] Figure 11 is a schematic view of the side surface of a single package of Embodiment 2 of the present application.

[0030] Figure 12 is a schematic view of the circuit pattern of a printed wiring substrate included in a single package of Embodiment 2 of the present application.

[0031] Figure 13 is a schematic view of the upper surface of a single package of Embodiment 2 of the present application.

[0032] Figure 14 is a schematic view of the circuit pattern of a relay substrate of Embodiment 2 of the present application.

[0033] Figure 15 is a schematic view of the upper surface of a plurality of single packages and the lower surface of a relay substrate of Embodiment 2 of the present application.

[0034] Figure 16 is a schematic view of the cross section of a semiconductor device of Embodiment 3 of the present application.

[0035] Figure 17 is a schematic view of the cross section of a semiconductor device of Embodiment 4 of the present application.

[0036] Figure 18 is a schematic view of the cross section of a relay substrate of Embodiment 4 of the present application.

[0037] Figure 19 is a schematic view of the upper surface of a plurality of printed wiring substrates of Embodiments 1 to 4 of the present application.

[0038] Figure 20is a schematic view of the upper surface of a plurality of monolithic packages to which Embodiments 1 to 4 of the present application relate.

[0039] Figure 21 is a schematic view of the upper surface of a monolithic package to which Embodiments 1 to 4 of the present application relate.

[0040] Figure 22 is a block diagram showing the structure of a power conversion system to which the power conversion device according to Embodiment 5 of the present application is applied. DETAILED DESCRIPTION

[0041] Embodiments of the present application will be described below with reference to the drawings. Note that the drawings are schematic views, and the mutual relationship of the sizes and positions shown in each of the drawings is not necessarily accurately depicted, and can be appropriately changed. In addition, in the following description, the same reference numerals are assigned to the same structural elements and illustrated, and their names and functions are also the same or similar. Thus, detailed description thereof will be omitted at times.

[0042] Embodiment 1

[0043] Use Figures 1 to 10 The semiconductor device 101 in Embodiment 1 will be described. Figure 1 is a schematic view of the cross section of the semiconductor device 101 according to Embodiment 1.

[0044] As Figure 1 shown, the semiconductor device 101 according to the present embodiment includes a cooler 1, a base bonding material 2 provided on the upper surface of the cooler 1, a plurality of monolithic packages 201 provided on the upper surface of the base bonding material 2, a relay substrate 3 provided on the upper surface of the plurality of monolithic packages 201, a packaging resin (second packaging resin) 4 filled between the plurality of monolithic packages 201 and the relay substrate 3, and a conductive bonding material 5 electrically connecting a circuit pattern provided in the monolithic package 201 and a circuit pattern provided in the relay substrate 3. As Figure 1 shown, two monolithic packages 201 are provided on the upper surface of the cooler 1, and a single relay substrate 3 connected to each of the monolithic packages 201 is provided. Note that the number of monolithic packages 201 is not limited to two, and three or more can be provided in the horizontal direction of the drawing, or a plurality of monolithic packages 201 can be provided in the depth direction of the drawing.

[0045] The upper surface is a surface on which the base bonding material 2 and the like are provided, with the cooler 1 as a reference. The lower surface is a surface opposite to the upper surface. Note that the upper surface is sometimes referred to as a surface, and the lower surface is sometimes referred to as a back surface. The same applies to the following description.

[0046] The cooler 1 is formed of a metal member such as aluminum or copper. The cooler 1 is, for example, a structure in the shape of a heat sink. The cooler 1 can also be a water-cooling structure in which a liquid such as water flows through the inside of the cooler 1 to perform cooling. The liquid that flows through the inside of the cooler 1 can also not be water, and can be, for example, a refrigerant, oil, or the like. In addition, the cooler 1 can also be an air-cooling structure in which a gas such as air is supplied to the inside of the cooler 1 to perform cooling. In the case of the air-cooling structure, the gas that is supplied to the inside of the cooler 1 can also not be air, and can be, for example, a refrigerant gas such as propane gas.

[0047] The base joining material 2 connects the cooler 1 and the single-package 201. The base joining material 2 is formed of, for example, sintered silver, a silver paste, or a solder.

[0048] Figure 2 is a cross-sectional view of the single-package 201 according to Embodiment 1. As shown in Figure 2 the single-package 201 according to the present embodiment includes a thermally conductive member 11, a heat sink 12 provided on the upper surface of the thermally conductive member 11, and a plurality of chip bonding materials 13 provided on the upper surface of the heat sink 12.

[0049] In addition, the single-package 201 according to the present embodiment includes a plurality of semiconductor elements 14 provided on the upper surfaces of the plurality of chip bonding materials 13, a conductive spacer 15 provided on the upper surface of the heat sink 12 in parallel with the chip bonding materials 13, and a joining material 16 that electrically connects the heat sink 12 and the conductive spacer 15.

[0050] In addition, the single-package 201 according to the present embodiment includes a printed wiring substrate 17 provided on the upper surfaces of the plurality of semiconductor elements 14 and the conductive spacer 15, a plurality of joining materials 16 that electrically connect the printed wiring substrate 17 and the electrodes included in the semiconductor elements 14 and that electrically connect the printed wiring substrate 17 and the conductive spacer 15, and a first encapsulation resin 18.

[0051] The thermally conductive member 11 includes a metal foil 19 and an insulating sheet 20 provided on the upper surface of the metal foil. The thermally conductive member 11 is an insulating layer having high heat dissipation properties. The insulating sheet 20 insulates the metal foil 19 and the heat sink 12. In addition, the insulating sheet 20 conducts heat generated by the semiconductor elements 14 to the metal foil 19.

[0052] The metal foil 19 is formed of, for example, a copper plate, an aluminum plate, or a copper foil, or the like, which has high thermal conductivity. The insulating sheet 20 is formed of, for example, a thermosetting resin such as an epoxy resin. In addition, the insulating sheet 20 includes, for example, a high-conductivity filler such as silicon dioxide, aluminum oxide, or boron nitride.

[0053] A heat sink 12 is disposed on the upper surface of the heat-conducting component 11. The heat sink 12 is formed, for example, in a cuboid shape. The heat sink 12 is formed, for example, from a metal component. The heat sink 12 is electrically connected to the electrode (second electrode 23 described later) on the back side of the semiconductor element 14 via a chip bonding material 13. In addition, the heat sink 12 and the semiconductor element 14 are electrically connected side-by-side to the conductive spacer 15 via a bonding material 16.

[0054] The heat sink 12 is formed, for example, from metals such as copper or aluminum or composite materials with high thermal conductivity.

[0055] Chip bonding material 13 connects heat sink 12 and semiconductor element 14.

[0056] The chip bonding material 13 is formed, for example, from solder, sintered silver, or silver paste. Preferably, the melting point of the chip bonding material 13 is higher than that of the substrate bonding material 2. By making the melting point of the chip bonding material 13 higher than that of the substrate bonding material 2, the substrate bonding material 2 can be formed without melting the chip bonding material 13, even when the chip bonding material 13 is formed first and the substrate bonding material 2 is formed later.

[0057] like Figure 2 As shown, the monolithic package 201 includes a plurality of semiconductor elements 14. The monolithic package 201 includes, for example, two semiconductor elements 14.

[0058] Semiconductor element 14 can be, for example, a diode used in a converter section that converts input AC power to DC power, a bipolar transistor used in an inverter section that converts DC power to AC power, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a GTO (Gate Turn-Off thyristor), or an SBD (Schottky Barrier Diode).

[0059] Semiconductor element 14 is disposed on the upper surface of heat sink 12. Although not in Figure 2 As illustrated in the diagram, semiconductor element 14 includes a third electrode 21, a first electrode 22, and a second electrode 23. Alternatively, semiconductor element 14 may not include a third electrode. The first and second electrodes are electrodes of the main circuit. The third electrode may include a control electrode, a current sensing electrode, or a temperature sensing electrode, etc. Furthermore, the current sensing electrode or temperature sensing electrode may be a different electrode from the third electrode, for example, it may be provided as a sensing electrode.

[0060] The third electrode 21 and the first electrode 22 are provided on the side of the semiconductor element 14 opposite the heat sink 12. That is, the third electrode 21 and the first electrode 22 are provided on the upper surface of the semiconductor element 14, that is, on the surface of the semiconductor element 14. The second electrode 23 is provided on the side of the semiconductor element 14 opposite the heat sink 12. That is, the second electrode 23 is provided on the lower surface of the semiconductor element 14, that is, on the back surface of the semiconductor element 14.

[0061] Embodiments of the first electrode, the second electrode, and the third electrode will be described. The first electrode, the second electrode, and the third electrode can be appropriately selected depending on the type of the semiconductor element. For example, in the case where the semiconductor element 14 is a diode, the first electrode corresponds to the anode or the cathode. In addition, the second electrode corresponds to the anode or the cathode. In the case where the first electrode is the anode, the second electrode is the cathode. In the case where the first electrode is the cathode, the second electrode is the anode. In addition, the third electrode can be an arbitrary electrode, and the third electrode can not be provided.

[0062] In addition, in the case where the semiconductor element 14 is a bipolar transistor, the first electrode corresponds to the emitter electrode. In addition, the second electrode corresponds to the collector electrode. In addition, the third electrode corresponds to the base electrode. In addition, a current sensing electrode or a temperature sensing electrode or the like can be provided as a fourth electrode.

[0063] In addition, in the case where the semiconductor element 14 is an IGBT, the first electrode corresponds to the emitter electrode. In addition, the second electrode corresponds to the collector electrode. In addition, the third electrode corresponds to the gate electrode or the like. In addition, a current sensing electrode or a temperature sensing electrode or the like can be provided as a fourth electrode.

[0064] In addition, in the case where the semiconductor element 14 is a MOSFET, the first electrode corresponds to the source electrode. In addition, the second electrode corresponds to the drain electrode. In addition, the third electrode corresponds to the gate electrode. In addition, a current sensing electrode or a temperature sensing electrode or the like can be provided as a fourth electrode.

[0065] In addition, in the case where the semiconductor element 14 is a GTO, the first electrode corresponds to the anode or the cathode. In addition, the second electrode corresponds to the anode or the cathode. In the case where the first electrode is the anode, the second electrode is the cathode. In the case where the first electrode is the cathode, the second electrode is the anode. In addition, the third electrode corresponds to the gate electrode. In addition, a current sensing electrode or a temperature sensing electrode or the like can be provided as a fourth electrode.

[0066] Further, in the case where the semiconductor element 14 is an SBD, the first electrode corresponds to the anode or the cathode. In addition, the second electrode corresponds to the anode or the cathode. In the case where the first electrode is the anode, the second electrode is the cathode. In the case where the first electrode is the cathode, the second electrode is the anode. In addition, the third electrode can be an arbitrary electrode, and the third electrode can not be provided.

[0067] The second electrode 23 provided on the lower surface of the semiconductor element 14 is electrically connected to the heat sink 12 via the die bonding material 13. That is, the second electrode 23 and the heat sink 12 electrically connected to the second electrode 23 via the die bonding material 13 are at the same potential.

[0068] In addition, the heat sink 12 and the conductive spacer 15 electrically connected to the heat sink 12 via the bonding material 16 are at the same potential. That is, the second electrode 23 and the conductive spacer 15 are at the same potential. Figure 2 The two semiconductor elements shown are connected in parallel between the heat sink 12 and the printed wiring substrate 17.

[0069] Further, the conductive spacer 15 can be formed using another member to form a portion at the same potential as the second electrode 23.

[0070] The third electrode 21 and the first electrode 22 provided on the upper surface of the semiconductor element 14 are electrically connected to the printed wiring substrate 17 via the bonding material 16.

[0071] The conductive spacer 15 is provided on the upper surface of the heat sink 12. The conductive spacer 15 is connected to the heat sink 12 via the bonding material 16. The conductive spacer 15 is electrically connected to the heat sink 12 via the bonding material 16, for example. That is, the conductive spacer 15 and the heat sink 12 are at the same potential.

[0072] In addition, the conductive spacer 15 is connected to the printed wiring substrate 17 via the bonding material 16. The conductive spacer 15 is electrically connected to the printed wiring substrate 17 via the bonding material 16, for example. That is, the heat sink 12 and the printed wiring substrate 17 are electrically connected via the conductive spacer 15. In the present embodiment, the conductive spacer 15 is provided side by side with the plurality of semiconductor elements 14.

[0073] It is preferable that the conductive spacer 15 be made of a copper pin or a copper plate.

[0074] The bonding material 16 is an electrically conductive member that electrically connects the third electrode 21 or the first electrode 22 provided on the upper surface of the semiconductor element 14 to the printed wiring substrate 17.

[0075] Additionally, bonding material 16 connects the heat sink 12 and the conductive spacer 15. Furthermore, bonding material 16 connects the conductive spacer 15 and the printed wiring board 17. Alternatively, the heat sink 12 and the printed wiring board 17 may not be electrically connected to the conductive spacer 15, but rather electrically connected through components other than the conductive spacer 15.

[0076] The bonding material 16 is formed, for example, from a conductive material such as solder, low-temperature solder, sintered silver, or silver paste.

[0077] like Figure 2 As shown, a printed wiring substrate 17 is disposed on the upper surface of a semiconductor device 14. The printed wiring substrate 17 includes a printed wiring substrate back pattern 31, a printed wiring substrate surface pattern 32, and a first insulating plate 43.

[0078] The printed wiring substrate back pattern 31 is disposed on the lower surface of the first insulating plate 43, i.e., the back surface of the first insulating plate 43. The printed wiring substrate back pattern 31 is connected to a plurality of semiconductor elements 14. In this embodiment, as... Figure 2 As shown, the pattern 31 on the back of the printed wiring board is connected to two semiconductor elements 14.

[0079] The pattern 31 on the back of the printed wiring board is electrically connected to the third electrode 21 and the first electrode 22 of the semiconductor element 14 via bonding material 16.

[0080] Additionally, the pattern 31 on the back side of the printed wiring board is connected to the conductive spacer 15 via a bonding material 16. The conductive spacer 15 and the pattern 31 on the back side of the printed wiring board may or may not be electrically connected. In this embodiment, the conductive spacer 15 and the pattern 31 on the back side of the printed wiring board are electrically connected.

[0081] The printed wiring board surface pattern 32 is disposed on the upper surface of the first insulating plate 43, i.e. the surface of the first insulating plate 43.

[0082] Regarding the back pattern 31 and the surface pattern 32 of the printed wiring board, the corresponding patterns among the multiple patterns included in each circuit pattern are electrically connected to each other. The connection of the circuit patterns will be explained in detail later.

[0083] Preferably, a solder resist layer is formed on the portion of the printed wiring substrate 17 other than the portions forming the back pattern 31 and the surface pattern 32 of the printed wiring substrate. By forming the solder resist layer, the wetting and spreading of solder can be suppressed, thereby improving the bonding between the circuit pattern and the object connected to the circuit pattern, such as an electrode.

[0084] In addition, Figure 2Only two circuit patterns are shown in the diagram: the back pattern 31 and the surface pattern 32 of the printed wiring board. However, the printed wiring board 17 may contain more than or equal to three circuit patterns.

[0085] like Figure 2 As shown, the first encapsulating resin 18 integrally encapsulates the thermally conductive component 11, the heat sink 12, the chip bonding material 13, the semiconductor element 14, the conductive spacer 15, the bonding material 16, and the printed wiring substrate 17.

[0086] The heat sink 12, chip bonding material 13, semiconductor element 14, conductive spacer 15 and bonding material 16 are encapsulated by the first encapsulation resin 18.

[0087] A portion of the thermally conductive component 11 and the printed wiring substrate 17 is exposed from the first encapsulation resin 18. The thermally conductive component 11, in particular the metal foil 19, is exposed from the first encapsulation resin 18.

[0088] The printed wiring board 17, particularly a portion of the surface pattern 32 of the printed wiring board 17, is exposed from the first encapsulation resin 18. In addition, a portion or all of the side surfaces of the printed wiring board 17, other than the upper and lower surfaces, are exposed from the first encapsulation resin 18.

[0089] The first encapsulating resin 18 ensures insulation between the encapsulated components and functions as the housing of the monolithic package 201.

[0090] For example, the first encapsulating resin 18 is molded by methods such as transfer molding, injection molding, or compression molding.

[0091] In addition, the first encapsulating resin 18 is formed, for example, from an epoxy resin or phenolic resin containing a filler.

[0092] like Figure 2 As shown, when viewed from the side, the monolithic package 201 is rectangular, but it is not limited to a cuboid and can be any shape.

[0093] like Figure 1 As shown, the base bonding material 2 contacts the monolithic package 201, particularly the first encapsulating resin 18 and the metal foil 19 exposed from the first encapsulating resin 18. The base bonding material 2 bonds the cooler 1 and the heat-conducting component 11.

[0094] like Figure 1 As shown, the semiconductor device 101 includes a relay substrate 3 disposed on the upper surface of a plurality of monolithic packages 201. The relay substrate 3 includes a relay substrate back pattern 33, a relay substrate surface pattern 34, and a second insulating plate 44.

[0095] The relay substrate back surface pattern 33 is provided on the lower surface of the second insulating board 44, that is, the back surface of the second insulating board 44. The relay substrate back surface pattern 33 is connected to the plurality of single-chip packages 201. In the present embodiment, as shown in FIG. 3, the relay substrate back surface pattern 33 is connected to two single-chip packages 201 via the bonding material 5. Figure 1

[0096] The relay substrate back surface pattern 33 is electrically connected to the area of the printed wiring board surface pattern 32 exposed from the first encapsulation resin 18 via the bonding material 5.

[0097] The bonding material 5 is used to bond the single-chip package 201 and the relay substrate 3, and the dimension in the thickness direction is about 50 to 100 micrometers in the narrow gap portion. On the other hand, the value obtained by adding the thickness between the surface of the single-chip package 201 and the relay substrate back surface pattern 33 of the relay substrate 3 is the maximum gap.

[0098] The second encapsulation resin 4 is filled between the lower surface of the relay substrate 3 and the single-chip package 201. The second encapsulation resin 4 covers the relay substrate back surface pattern 33, the bonding material 5, and the upper surface of the single-chip package 201.

[0099] It is preferable that the thickness of the relay substrate back surface pattern 33 be greater than or equal to 0.1 mm. In the case where the thickness of the relay substrate back surface pattern 33 is less than 0.1 mm, a large current flows through the relay substrate back surface pattern 33 of the relay substrate 3. As a result of the large current flowing through the relay substrate back surface pattern 33, the relay substrate back surface pattern 33 generates self-heating due to Joule heat, and a portion of the relay substrate back surface pattern 33 generates a temperature higher than the maximum junction temperature of the semiconductor element 14. By generating a portion of the relay substrate back surface pattern 33 that generates a temperature higher than the maximum junction temperature of the semiconductor element 14, the reliability of the semiconductor device 101 can be significantly reduced.

[0100] The relay substrate surface pattern 34 is provided on the upper surface of the second insulating board 44, that is, the surface of the second insulating board 44. The relay substrate surface pattern 34 is electrically connected to other subject components, not shown.

[0101] As for the relay substrate back surface pattern 33 and the relay substrate surface pattern 34, respective corresponding patterns among the plurality of patterns included in each circuit pattern are electrically connected to each other. The connection of the circuit patterns will be described in detail later.

[0102] Furthermore, the printed wiring board back surface pattern 31, the printed wiring board surface pattern 32, the relay substrate back surface pattern 33, and the relay substrate surface pattern 34 are, for example, copper patterns formed of copper.

[0103] Figure 3 ​is a top view of the heat sink 12 and the semiconductor element 14 included in the single package 201 according to Embodiment 1. Figure 3 The paper front side is the upper surface. As shown in Figure 3 , the semiconductor element 14 is arranged on the upper surface of the heat sink 12.

[0104] The single package 201 includes, for example, two semiconductor elements 14. The two semiconductor elements 14 are arranged on the upper surface of the heat sink 12.

[0105] The semiconductor element 14 includes a third electrode 21, a first electrode 22, a second electrode 23 (not shown in Figure 3 ), and a fourth electrode 24. As shown in Figure 3 , the third electrode 21, the first electrode 22, and the fourth electrode 24 are arranged on the upper surface of the semiconductor element 14. In Figure 3 , the two fourth electrodes 24 sandwich the third electrode 21, but the arrangement of the third electrode 21 and the fourth electrode 24 is not limited to that shown in Figure 3 . The fourth electrode 24 is, for example, a sensing electrode.

[0106] The third electrode 21, the first electrode 22, and the fourth electrode 24 are connected to the printed wiring board back surface pattern 31 of the printed wiring board 17 via the bonding material 16.

[0107] The second electrode 23 is arranged on the lower surface of the semiconductor element 14. The second electrode 23 is electrically connected to the heat sink 12. That is, the second electrode 23 and the heat sink 12 are at the same potential.

[0108] As shown in Figure 3 , the heat sink 12 is connected to the conductive spacer 15 via the bonding material 16, for example. In addition, the conductive spacer 15 can not be electrically connected to the heat sink 12.

[0109] In addition, the conductive spacer 15 is connected to the printed wiring board back surface pattern 31 of the printed wiring board 17 via the bonding material 16. In addition, the conductive spacer 15 can not be electrically connected to the printed wiring board back surface pattern 31 of the printed wiring board 17.

[0110] In addition, components other than the semiconductor element 14 and the conductive spacer 15 can be arranged on the upper surface of the heat sink 12. The components other than the semiconductor element 14 and the conductive spacer 15 arranged on the upper surface of the heat sink 12 can be electrically connected to the heat sink 12.

[0111] Figure 1 The semiconductor element 14 shown in Figure 2 is schematically shown in cross section when cut by the A-A' line shown in Figure 3 .

[0112] In addition, the semiconductor element 14 can have a plurality of the fourth electrodes 24. The number of the fourth electrodes 24 included in the semiconductor element 14 is not limited to two, and can be three. In addition, the semiconductor element 14 can not include the fourth electrodes 24.

[0113] Figure 4 is a top view of the heat sink 12 and the semiconductor element 14 included in the monolithic package 201 according to Embodiment 1. Figure 4 The semiconductor element 14 illustrated includes three fourth electrodes 24.

[0114] Figure 5 is a schematic view of the printed wiring board back surface pattern 31 and the printed wiring board surface pattern 32 of the printed wiring board 17 included in the monolithic package 201 according to Embodiment 1. The printed wiring board back surface pattern 31 provided on the lower surface of the printed wiring board 17 is indicated by a broken line, and the printed wiring board surface pattern 32 provided on the upper surface of the printed wiring board 17 is indicated by a solid line. For the convenience of observation, the solid line and the broken line are indicated in a staggered manner even when they overlap.

[0115] Hereinafter, the first to fourth regions are described in the description of the printed wiring board back surface pattern 31, the printed wiring board surface pattern 32, the relay board back surface pattern 33, and the relay board surface pattern 34, but for example, the first to fourth regions indicate regions electrically connected to the first to fourth electrodes, respectively.

[0116] The printed wiring board back surface pattern 31 includes the third region 51 of the printed wiring board back surface, the first region 52 of the printed wiring board back surface, the second region 53 of the printed wiring board back surface, and the fourth region 54 of the printed wiring board back surface. The third region 51 of the printed wiring board back surface, the first region 52 of the printed wiring board back surface, the second region 53 of the printed wiring board back surface, and the fourth region 54 of the printed wiring board back surface are electrically connected to the third electrode 21, the first electrode 22, the second electrode 23, and the fourth electrode 24 of the semiconductor element 14, respectively.

[0117] The printed wiring board back surface pattern 31 includes, for example, two third regions 51 of the printed wiring board back surface, one first region 52 of the printed wiring board back surface, one second region 53 of the printed wiring board back surface, and six fourth regions 54 of the printed wiring board back surface.

[0118] In addition, the number of the third regions 51 of the printed wiring board back surface, the first regions 52 of the printed wiring board back surface, the second regions 53 of the printed wiring board back surface, and the fourth regions 54 of the printed wiring board back surface is not limited to Figure 5 the number illustrated.

[0119] The printed wiring board surface pattern 32 includes the third printed wiring board surface region 61, the first printed wiring board surface region 62, the second printed wiring board surface region 63, and the fourth printed wiring board surface region 64. The third printed wiring board surface region 61, the first printed wiring board surface region 62, the second printed wiring board surface region 63, and the fourth printed wiring board surface region 64 are electrically connected to the third printed wiring board back surface region 51, the first printed wiring board back surface region 52, the second printed wiring board back surface region 53, and the fourth printed wiring board back surface region 54, respectively.

[0120] The printed wiring board surface pattern 32 includes, for example, two third printed wiring board surface regions 61, one first printed wiring board surface region 62, one second printed wiring board surface region 63, and six fourth printed wiring board surface regions 64.

[0121] In the printed wiring board surface pattern 32, the number of the third printed wiring board surface regions 61 and the fourth printed wiring board surface regions 64 is less than or equal to the number of the third electrodes 21 and the fourth electrodes 24 of the semiconductor elements 14, respectively.

[0122] In addition, the sum of the number of the first printed wiring board surface regions 62 and the second printed wiring board surface regions 63 can be less than the sum of the number of the first electrodes 22 and the second electrodes 23 of the plurality of semiconductor elements 14 included in the single-package 201.

[0123] In addition, the number of the first printed wiring board surface regions 62 and the second printed wiring board surface regions 63 can be less than the number of the first electrodes 22 and the second electrodes 23, respectively.

[0124] By making the sum of the number of the third printed wiring board surface regions 61, the first printed wiring board surface regions 62, the second printed wiring board surface regions 63, and the fourth printed wiring board surface regions 64 less than the sum of the number of the third electrodes 21, the first electrodes 22, the second electrodes 23, and the fourth electrodes 24 of the plurality of semiconductor elements 14 included in the single-package 201, the printed wiring board surface pattern 32 is simplified, the wiring of the printed wiring board 17 is easily routed, and thus the design of the printed wiring board 17 can be facilitated.

[0125] In addition, by making the sum of the number of the third region 61 of the printed wiring board surface, the first region 62 of the printed wiring board surface, the second region 63 of the printed wiring board surface, and the fourth region 64 of the printed wiring board surface smaller than the sum of the number of the third electrode 21, the first electrode 22, the second electrode 23, and the fourth electrode 24 possessed by the plurality of semiconductor elements 14 included in the monolithic package 201, the relay substrate surface pattern 34 is simplified, the wiring of the relay substrate 3 is easily routed, and thus the design of the relay substrate 3 can be easily made.

[0126] In addition, the number of the third region 61 of the printed wiring board surface, the first region 62 of the printed wiring board surface, the second region 63 of the printed wiring board surface, and the fourth region 64 of the printed wiring board surface is not limited to Figure 5 the number shown in the drawing.

[0127] Figure 6 is a schematic view of the upper surface of the printed wiring board 17 included in the monolithic package 201 according to Embodiment 1. The printed wiring board 17 includes the printed wiring board surface pattern 32 on the upper surface. Figure 6 The printed wiring board surface pattern 32 of the printed wiring board 17 shown in the drawing includes the third region 61 of the printed wiring board surface, the first region 62 of the printed wiring board surface, the second region 63 of the printed wiring board surface, and the fourth region 64 of the printed wiring board surface. In addition, Figure 6 The printed wiring board surface pattern 32 of the printed wiring board 17 shown in the drawing includes two fourth regions 64 of the printed wiring board surface. That is, it is also possible to make Figure 6 the number of the third region 61 of the printed wiring board surface and the fourth region 64 of the printed wiring board surface smaller than Figure 5 the number of the third region 61 of the printed wiring board surface and the fourth region 64 of the printed wiring board surface.

[0128] Figure 1 and Figure 2 The printed wiring board surface pattern 32 of the printed wiring board 17 shown in the drawing and the first insulating plate 43 schematically show the cross section in the case where the B-B' line is cut. Figure 6

[0129] Figure 7 is a schematic view for showing the correspondence between the upper surface of the plurality of semiconductor elements 14 included in the monolithic package 201 according to Embodiment 1 and the lower surface of the printed wiring board 17. The upper surface of the plurality of semiconductor elements 14 is shown by a broken line, and the printed wiring board back surface pattern 31 provided on the lower surface of the printed wiring board 17 is shown by a solid line. For the convenience of observation, the solid line and the broken line are also shown in a staggered manner in the case where they overlap. ​

[0130] The upper surfaces of the plurality of semiconductor elements 14 indicated by dotted lines correspond to Figure 4 The printed wiring board back surface pattern 31 indicated by a solid line corresponds to the region indicated by a dotted line in Figure 5 Fig. 2. As shown in Figure 7 Fig. 2, it is understood that the positions of the third electrodes 21, the first electrodes 22, and the fourth electrodes 24 of the upper surfaces of the semiconductor elements 14 overlap the printed wiring board back surface pattern 31. In addition, the second region 53 of the printed wiring board back surface is disposed at a position overlapping the conductive spacer 15 in the stacking direction.

[0131] As shown in Figure 7 Fig. 2, for example, the plurality of first electrodes 22 are gathered to the first region 52 of the printed wiring board back surface by the printed wiring board 17. By gathering the plurality of first electrodes 22 to the first region 52 of the printed wiring board back surface, the printed wiring board surface pattern 32 is simplified, the wiring of the printed wiring board 17 is easily routed, and thus the design of the printed wiring board 17 can be made easy.

[0132] In addition, as shown in Figure 5 Fig. 2, in the printed wiring board surface pattern 32, the number of the third regions 61 of the printed wiring board surface and the fourth regions 64 of the printed wiring board surface is less than or equal to the number of the third electrodes 21 and the fourth electrodes 24 of the semiconductor elements 14, respectively. Therefore, the sum of the number of the third regions 61 of the printed wiring board surface, the first regions 62 of the printed wiring board surface, the second regions 63 of the printed wiring board surface, and the fourth regions 64 of the printed wiring board surface is less than the sum of the number of the third electrodes 21, the first electrodes 22, the second electrodes 23, and the fourth electrodes 24 of the plurality of semiconductor elements 14 included in the monolithic package 201.

[0133] In addition, in Figure 7 Fig. 2, the illustration of the bonding material 16 provided between the monolithic package 201 and the printed wiring board back surface pattern 31 is omitted.

[0134] Figure 8 Fig. 3 is a schematic view of the upper surface of the monolithic package 201 according to Embodiment 1. The monolithic package 201 is encapsulated by the first encapsulation resin 18. In Figure 5 Fig. 3, a portion of the printed wiring board surface pattern 32 of the printed wiring board 17 indicated by a solid line is exposed from the first encapsulation resin 18. In addition, the portion of the printed wiring board surface pattern 32 exposed from the first encapsulation resin 18 can be the entire printed wiring board surface pattern 32 or a portion thereof.

[0135] Figure 9Fig. 1 is a schematic view of the relay substrate back surface pattern 33 and the relay substrate surface pattern 34 of the relay substrate 3 according to Embodiment 1. The relay substrate back surface pattern 33 provided on the lower surface of the relay substrate 3 is indicated by a broken line, and the relay substrate surface pattern 34 provided on the upper surface of the relay substrate 3 is indicated by a solid line. For the convenience of observation, the solid line and the broken line are indicated in a staggered manner even when they overlap.

[0136] The relay substrate 3 is connected to the plurality of single-package devices 201 on the lower surface, i.e., the relay substrate back surface pattern 33 side. In Figure 9 Fig. 1 shows the relay substrate back surface pattern 33 and the relay substrate surface pattern 34 in the case where the relay substrate 3 is connected to three single-package devices 201. In addition, Fig. 1 shows the case where the single-package devices 201 shown in Fig. 1 are connected in a state where they are rotated by 90 degrees to the left. Figure 9 Fig. 1 shows the relay substrate back surface pattern 33 and the relay substrate surface pattern 34 in the case where the relay substrate 3 is connected to three single-package devices 201. In addition, Fig. 1 shows the case where the single-package devices 201 shown in Fig. 1 are connected in a state where they are rotated by 90 degrees to the left. Figure 8 Fig. 1 shows the relay substrate back surface pattern 33 and the relay substrate surface pattern 34 in the case where the relay substrate 3 is connected to three single-package devices 201. In addition, Fig. 1 shows the case where the single-package devices 201 shown in Fig. 1 are connected in a state where they are rotated by 90 degrees to the left.

[0137] The relay substrate back surface pattern 33 includes the third relay substrate back surface region 71, the first relay substrate back surface region 72, the second relay substrate back surface region 73, and the fourth relay substrate back surface region 74. The third relay substrate back surface region 71, the first relay substrate back surface region 72, the second relay substrate back surface region 73, and the fourth relay substrate back surface region 74 are electrically connected to the third printed wiring board surface region 61, the first printed wiring board surface region 62, the second printed wiring board surface region 63, and the fourth printed wiring board surface region 64 of the printed wiring board surface pattern 32, respectively.

[0138] The relay substrate back surface pattern 33 includes, for example, six third relay substrate back surface regions 71, one first relay substrate back surface region 72, three second relay substrate back surface regions 73, and eighteen fourth relay substrate back surface regions 74.

[0139] Furthermore, the number of the third relay substrate back surface regions 71, the first relay substrate back surface regions 72, the second relay substrate back surface regions 73, and the fourth relay substrate back surface regions 74 is not limited to Figure 9 the number shown in Fig. 1.

[0140] The relay substrate surface pattern 34 includes the third relay substrate surface region 81, the first relay substrate surface region 82, the second relay substrate surface region 83, and the fourth relay substrate surface region 84. The third relay substrate surface region 81, the first relay substrate surface region 82, the second relay substrate surface region 83, and the fourth relay substrate surface region 84 are electrically connected to other object components, which are not shown.

[0141] In Figure 9In this case, the third region 71 on the back surface of the relay substrate is electrically connected to the third region 81 on the surface of the relay substrate, the first region 72 on the back surface of the relay substrate is electrically connected to the first region 82 on the surface of the relay substrate, the second region 73 on the back surface of the relay substrate is electrically connected to the second region 83 on the surface of the relay substrate, and the fourth region 74 on the back surface of the relay substrate is electrically connected to the fourth region 84 on the surface of the relay substrate.

[0142] The surface pattern 34 of the relay substrate includes, for example, six third regions 81 on the surface of the relay substrate, one first region 82 on the surface of the relay substrate, one second region 83 on the surface of the relay substrate, and eighteen fourth regions 84 on the surface of the relay substrate.

[0143] The number of the third regions 81 on the surface of the relay substrate and the fourth regions 84 on the surface of the relay substrate is less than or equal to the number of the third electrodes 21 and the fourth electrodes 24 of the semiconductor elements 14, respectively. The total number of the third regions 81 on the surface of the relay substrate, the first regions 82 on the surface of the relay substrate, the second regions 83 on the surface of the relay substrate, and the fourth regions 84 on the surface of the relay substrate is less than the total number of the third regions 61 on the surface of the printed wiring substrate, the first regions 62 on the surface of the printed wiring substrate, the second regions 63 on the surface of the printed wiring substrate, and the fourth regions 64 on the surface of the printed wiring substrate included in the surface pattern 32 of the printed wiring substrate surface included in the plurality of single-package semiconductor devices 201 included in the semiconductor device 101.

[0144] That is, the total number of the third regions 81 on the surface of the relay substrate, the first regions 82 on the surface of the relay substrate, the second regions 83 on the surface of the relay substrate, and the fourth regions 84 on the surface of the relay substrate is less than the total number of the third electrodes 21, the first electrodes 22, the second electrodes 23, and the fourth electrodes 24 of the plurality of semiconductor elements 14 included in the semiconductor device 101.

[0145] In addition, the total number of the first regions 82 on the surface of the relay substrate and the second regions 83 on the surface of the relay substrate is less than the total number of the first regions 62 on the surface of the printed wiring substrate and the second regions 63 on the surface of the printed wiring substrate included in the surface pattern 32 of the printed wiring substrate surface included in the plurality of single-package semiconductor devices 201 included in the semiconductor device 101.

[0146] In addition, the number of the first regions 82 on the surface of the relay substrate and the second regions 83 on the surface of the relay substrate can also be less than the number of the first regions 62 on the surface of the printed wiring substrate and the second regions 63 on the surface of the printed wiring substrate, respectively.

[0147] By making the sum of the number of the third region 81 of the relay substrate surface, the first region 82 of the relay substrate surface, the second region 83 of the relay substrate surface, and the fourth region 84 of the relay substrate surface smaller than the sum of the number of the third region 61 of the printed wiring substrate surface, the first region 62 of the printed wiring substrate surface, the second region 63 of the printed wiring substrate surface, and the fourth region 64 of the printed wiring substrate surface included in the printed wiring substrate surface pattern 32 possessed by the plurality of single-package devices 201 included in the semiconductor device 101, the relay substrate surface pattern 34 is simplified, the wiring of the relay substrate 3 is easily routed, and thus the design of the relay substrate 3 can be made easy.

[0148] In addition, by making the sum of the number of the third region 81 of the relay substrate surface, the first region 82 of the relay substrate surface, the second region 83 of the relay substrate surface, and the fourth region 84 of the relay substrate surface smaller than the sum of the number of the third electrode 21, the first electrode 22, the second electrode 23, and the fourth electrode 24 possessed by the plurality of semiconductor elements 14 included in the semiconductor device 101, the number of the third region 81 of the relay substrate surface, the first region 82 of the relay substrate surface, the second region 83 of the relay substrate surface, and the fourth region 84 of the relay substrate surface connected to other object components not shown can be reduced, and thus the insulation distance can be ensured and the semiconductor device 101 can be downsized.

[0149] In addition, the number of the first region 82 of the relay substrate surface and the second region 83 of the relay substrate surface can be respectively smaller than the number of the first electrode 22 and the second electrode 23.

[0150] Further, the number of the third region 81 of the relay substrate surface, the first region 82 of the relay substrate surface, the second region 83 of the relay substrate surface, and the fourth region 84 of the relay substrate surface is not limited to Figure 9 the number shown.

[0151] Figure 10 is a schematic view of the upper surfaces of the plurality of single-package devices 201 and the lower surface of the relay substrate 3 according to Embodiment 1. The upper surfaces of the plurality of single-package devices 201 are indicated by dotted lines, and the relay substrate back surface pattern 33 provided on the lower surface of the relay substrate 3 is indicated by solid lines. For the convenience of observation, the solid lines and the dotted lines are indicated in a staggered manner even when they overlap.

[0152] The upper surfaces of the plurality of single-package devices 201 indicated by dotted lines correspond to the single-package devices 201 rotated 90 degrees to the left. Figure 8 The relay substrate back surface pattern 33 indicated by solid lines corresponds to that indicated by dotted lines in Figure 9 .

[0153] As Figure 10As shown, the printed wiring board surface pattern 32 provided on the upper surface of the monolithic package 201 is provided at a position corresponding to the relay substrate back surface pattern 33 provided on the relay substrate, and the printed wiring board surface pattern 32 is electrically connected to the relay substrate back surface pattern 33.

[0154] As shown, for example, the plurality of conductive regions 92 are gathered to the first region 72 on the back surface of the relay substrate 3 by the relay substrate 3. By gathering the plurality of conductive regions 92 to the first region 72 on the back surface of the relay substrate 3, the wiring of the relay substrate 3 is simplified, and the design of the relay substrate 3 is facilitated. Figure 10

[0155] Embodiment 2

[0156] Use Figures 11 to 15 The semiconductor device 102 in Embodiment 2 will be described. The description of the same structure as in Embodiment 1 will be omitted. In addition, the same reference numerals as in Embodiment 1 denote the same or corresponding parts. Figures 11 to 15 Figures 1 to 10

[0157] Figure 11 is a side view of a monolithic package 202 included in the semiconductor device 102 to which Embodiment 2 pertains. In Figure 11 , the description of the first encapsulation resin 18 is omitted. As shown in Figure 11 , the pattern of the plurality of semiconductor elements 14 included in the monolithic package 202 to which the present embodiment pertains is different from that of the monolithic package 201 of Embodiment 1. Hereinafter, the description will be made focusing on the difference from the monolithic package 201 of Embodiment 1.

[0158] The monolithic package 202 includes two heat spreaders 12. In addition, the monolithic package 202 includes two semiconductor elements 14. The two heat spreaders 12 are electrically connected to the two semiconductor elements 14, respectively. That is, the heat spreader 12 is divided between the plurality of semiconductor elements 14.

[0159] The monolithic package 202 includes a printed wiring board 17. The printed wiring board 17 includes a printed wiring board back surface pattern 31 and a printed wiring board surface pattern 32. The printed wiring board back surface pattern 31 includes a first region 52 on the back surface of the printed wiring board, a second region 53 on the back surface of the printed wiring board, and a conductor 91.

[0160] The monolithic package 202 includes a conductive spacer 15. The conductive spacer 15 is electrically connected to one of the two heat spreaders 12 located on the right side of the paper. Figure 11

[0161] The conductor 91 is electrically connected to one of the two heat spreaders 12 located on the right side of the paper. Figure 11 ​​​​the paper surface on the right side of the printed wiring board surface pattern 32. The first electrode 22 of the semiconductor element 14 provided on the paper surface on the right side of the heat sink 12 and the second electrode 23 of the semiconductor element 14 provided on the paper surface on the left side of the heat sink 12 are electrically connected. Figure 11 The other heat sink 12 on the paper surface on the left side and not connected to the conductive spacer 15 is electrically connected.

[0162] The printed wiring board surface pattern 32 includes a conductive region 92. The conductor 91 is electrically connected to the conductive region 92. That is, in the printed wiring board surface pattern 32, the conductive region 92 is provided on the paper surface on the right side of the conductor 91. Figure 11 In the printed wiring board surface pattern 32, the conductive region 92 is provided on the paper surface on the right side of the conductor 91. In the printed wiring board surface pattern 32, the conductive region 92 is provided on the paper surface on the right side of the conductor 91. In the printed wiring board surface pattern 32, the conductive region 92 is provided on the paper surface on the right side of the conductor 91.

[0163] Figure 12 is a schematic view of the printed wiring board back surface pattern 31 and the printed wiring board surface pattern 32 of the printed wiring board 17 included in the monolithic package 202 to which Embodiment 2 relates. The printed wiring board back surface pattern 31 provided on the lower surface of the printed wiring board 17 is indicated by a broken line, and the printed wiring board surface pattern 32 provided on the upper surface of the printed wiring board 17 is indicated by a solid line. For the convenience of observation, the solid line and the broken line are indicated in a staggered manner even when they overlap.

[0164] The conductor 91 included in the printed wiring board back surface pattern 31 is electrically connected to the conductive region 92 included in the printed wiring board surface pattern 32. The third region 51, the first region 52, the second region 53, and the fourth region 54 of the printed wiring board back surface included in the printed wiring board back surface pattern 31 and the printed wiring board surface pattern 32 are the same as those of Embodiment 1, and thus the description thereof is omitted.

[0165] Figure 13 is a schematic view of the upper surface of the monolithic package 202 to which Embodiment 2 relates. The monolithic package 202 is encapsulated by the first encapsulation resin 18. In the printed wiring board surface pattern 32 of the printed wiring board 17 indicated by a solid line in Figure 12 part of the printed wiring board surface pattern 32 of the printed wiring board 17 indicated by a solid line in Embodiment 2 is exposed from the first encapsulation resin 18. In addition, the part of the printed wiring board surface pattern 32 exposed from the first encapsulation resin 18 can be the entire printed wiring board surface pattern 32, or can be a part thereof.

[0166] Figure 14is a schematic view of the relay substrate back surface pattern 33 and the relay substrate surface pattern 34 of the relay substrate 3 to which Embodiment 2 is applied. The relay substrate back surface pattern 33 provided on the lower surface of the relay substrate 3 is indicated by a broken line, and the relay substrate surface pattern 34 provided on the upper surface of the relay substrate 3 is indicated by a solid line. For the convenience of observation, the solid line and the broken line are indicated in a staggered manner even when they overlap.

[0167] The relay substrate 3 is connected to the plurality of single-chip packages 202. In Figure 14 is shown a case where the relay substrate 3 is connected to three single-chip packages 202. In Figure 14 is shown a case where the single-chip package 202 shown in Figure 13 is rotated 90 degrees to the left is connected.

[0168] The relay substrate back surface pattern 33 includes a terminal 93 formed in an L shape. The terminal 93 is electrically connected to the conductive region 92 of the printed wiring substrate surface pattern 32. The terminal 93 is connected to other components not shown. The structure other than this is the same as that in Embodiment 1, and thus the description is omitted. Figure 10

[0169] Figure 15 is a schematic view of the upper surfaces of the plurality of single-chip packages 202 and the lower surface of the relay substrate 3 to which Embodiment 2 is applied. The upper surfaces of the plurality of single-chip packages 202 are indicated by broken lines, and the relay substrate back surface pattern 33 provided on the lower surface of the relay substrate 3 is indicated by a solid line. For the convenience of observation, the solid line and the broken lines are indicated in a staggered manner even when they overlap.

[0170] The upper surfaces of the plurality of single-chip packages 202 indicated by broken lines correspond to the single-chip package 201 shown in Figure 13 is rotated 90 degrees to the left. The relay substrate back surface pattern 33 indicated by a solid line corresponds to that indicated by a broken line in Figure 14 .

[0171] Embodiment 3

[0172] The semiconductor device 103 in Embodiment 3 will be described. The description of the same structure as in Embodiment 1 is omitted. In Figure 16 , the same reference numerals are used to denote the same or corresponding parts as in Figure 16 . Figures 1 to 15

[0173] Figure 16 ​​This is a cross-sectional schematic diagram of the semiconductor device 103 according to Embodiment 3. The semiconductor device 103 according to this embodiment differs from the monolithic package 201 of Embodiment 1 in that it has a thermally conductive adhesive layer 6 instead of the base bonding material 2 and the thermally conductive component 11. Hereinafter, the description will focus on the differences from the monolithic package 201 of Embodiment 1.

[0174] The semiconductor device 103 according to this embodiment includes: a cooler 1; a thermally conductive adhesive layer 6 disposed on the upper surface of the cooler 1; a plurality of monolithic packages 203 disposed on the upper surface of the thermally conductive adhesive layer 6; a relay substrate 3 disposed on the upper surface of the plurality of monolithic packages 203; and a second encapsulating resin 4 filling the space between the plurality of monolithic packages 203 and the relay substrate 3. The monolithic packages 203 do not include thermally conductive components 11.

[0175] The monolithic package 203 is formed, for example, by transfer molding. A package body is obtained by encapsulating the monolithic package 203 formed by transfer molding and the relay substrate 3 using a second encapsulating resin 4. The package body, the thermally conductive adhesive layer 6, and the cooler 1 are then bonded together by hot pressing. The monolithic package 203 and the cooler 1 are bonded together via the thermally conductive adhesive layer 6.

[0176] The thermally conductive adhesive layer 6 is formed, for example, from a composite material that uses thermosetting resins such as epoxy resin and fillers with high thermal conductivity such as crystalline silica, alumina, aluminum nitride, boron nitride, and silicon nitride.

[0177] Hot pressing is performed at a temperature greater than or equal to the melting temperature of the resin component of the thermally conductive adhesive layer 6 and at a pressure that sufficiently eliminates the pores contained within the thermally conductive adhesive layer 6.

[0178] Implementation Method 4

[0179] use Figure 17 and Figure 18 The semiconductor device 104 in Embodiment 4 will be described. Descriptions of structures identical to those in Embodiment 1 are omitted. Furthermore, in Figure 17 and Figure 18 Zhongyu Figures 1 to 16 The same label indicates the same or equivalent parts.

[0180] Figure 17 This is a cross-sectional schematic diagram of the semiconductor device 104 according to Embodiment 4. The semiconductor device 104 according to this embodiment differs from the monolithic package 201 of Embodiment 1 in that it has a filling portion 7. Hereinafter, the description will focus on the differences from the monolithic package 201 of Embodiment 1.

[0181] The semiconductor device 103 according to the present embodiment includes a relay substrate 3. The relay substrate 3 includes a relay substrate back surface pattern 33, a relay substrate surface pattern 34, and a second insulating board 44. As shown in FIG. 1, the relay substrate back surface pattern 33 is provided on the upper surface of the second insulating board 44. The relay substrate surface pattern 34 is provided on the lower surface of the second insulating board 44. Figure 17 A filling portion 7 is provided on the second insulating board 44 in a portion where neither the relay substrate back surface pattern 33 nor the relay substrate surface pattern 34 is provided.

[0182] A filling agent such as a solder resist is filled in the filling portion 7. The filling agent is preferably filled in the filling portion 7 before the relay substrate 3 is connected to the monolithic package 201.

[0183] Figure 18 FIG. 6 is a schematic cross-sectional view of the relay substrate 3 according to Embodiment 4. In addition, the description of the relay substrate surface pattern 34 of the relay substrate 3 is omitted in FIG. 6. Figure 18 In addition, the filling portion 7 provided on the upper surface of the relay substrate 3 is not described in FIG. 6. Figure 18 As shown in FIG. 6, the filling portion 7 is provided on the lower surface of the relay substrate 3. The filling portion 7 is provided in a portion where neither the relay substrate back surface pattern 33 nor the relay substrate surface pattern 34 is provided.

[0184] Figure 18 The filling portion 7 can partially cover the relay substrate back surface pattern 33 and the relay substrate surface pattern 34. The filling portion 7 has an opening portion 8. The relay substrate back surface pattern 33 is exposed from the filling portion 7 at the opening portion 8. In addition, the relay substrate back surface pattern 33 is electrically connected to the printed wiring board surface pattern 32 through the portion exposed at the opening portion 8.

[0185] The thickness of the printed wiring board surface pattern 32 of the relay substrate 3 is, for example, greater than or equal to 0.1 mm. Regarding the difference in thickness between a portion of the relay substrate 3 where the printed wiring board surface pattern 32 is provided and a portion where the printed wiring board surface pattern 32 is not provided, the difference is greater when the thickness of the printed wiring board surface pattern 32 is greater than or equal to 0.1 mm than when the thickness of the printed wiring board surface pattern 32 is less than 0.1 mm.

[0186] When the difference in thickness between the portion where the printed wiring board surface pattern 32 is provided and the portion where the printed wiring board surface pattern 32 is not provided is large, holes can be generated between the respective regions included in the printed wiring board surface pattern 32 when the second encapsulation resin 4 is filled. The state where holes are generated is a state where the filling property is poor, and thus is not preferable. Therefore, it is necessary to reduce the difference between the distance (narrow gap) between the relay substrate back surface pattern 33 and the monolithic package 201 and the distance (maximum gap) between the second insulating board 44 and the monolithic package 201 when the encapsulation is performed by the second encapsulation resin 4.

[0187] When the difference in thickness between the portion where the printed wiring board surface pattern 32 is provided and the portion where the printed wiring board surface pattern 32 is not provided is large, holes can be generated between the respective regions included in the printed wiring board surface pattern 32 when the second encapsulation resin 4 is filled. The state where holes are generated is a state where the filling property is poor, and thus is not preferable. Therefore, it is necessary to reduce the difference between the distance (narrow gap) between the relay substrate back surface pattern 33 and the monolithic package 201 and the distance (maximum gap) between the second insulating board 44 and the monolithic package 201 when the encapsulation is performed by the second encapsulation resin 4. ​

[0188] In the present embodiment, as shown in Figure 17 As a result of providing the filling portion 7, even in the case where the thickness of the relay substrate back surface pattern 33 of the relay substrate 3 is large, deterioration of the filling property of the second packaging resin 4 can be suppressed.

[0189] A manufacturing method of the monolithic package 201 will be described. The monolithic package 201 includes Figure 2 the structure shown in FIG. 1.

[0190] First, the semiconductor element 14 is joined to the heat sink 12 using the chip bonding material 13. In addition, the conductive spacer 15 is joined to the heat sink 12 using the joining material 16. Thereafter, the semiconductor element 14 and the conductive spacer 15 are joined to the printed wiring substrate 17. Further, the order of joining can be reversed.

[0191] Next, by transfer molding, the member obtained by joining the heat sink 12, the semiconductor element 14, and the printed wiring substrate 17, and the thermally conductive member 11 are packaged using the first packaging resin 18 (transfer molding resin). At the time of packaging, by using a release film or performing polishing and laser deburring, or the like, the electrodes are exposed so that the lower surface of the thermally conductive member 11, that is, the metal foil 19 and the electrodes of the printed wiring substrate 17 corresponding to the first region 62 and the second region 63 of the printed wiring substrate surface included in the printed wiring substrate surface pattern 32 of the printed wiring substrate surface are exposed.

[0192] Figure 19 is a schematic view of the upper surfaces of the plurality of printed wiring substrates 17 to which Embodiments 1 to 4 are applied. Figure 20 is a schematic view of the upper surfaces of the plurality of monolithic packages 201 to 203 to which Embodiments 1 to 4 are applied. Figure 21 is a schematic view of the upper surfaces of the monolithic packages 201 to 203 to which Embodiments 1 to 4 are applied.

[0193] Figure 19 A repeating pattern in which a plurality of printed wiring substrates 17 are arranged on the same plane is shown. In the case where the monolithic package 201 is molded by transfer molding, a substrate in which two or more wiring substrates are repeatedly arranged on one substrate (repeating pattern) is used in order to obtain a plurality of monolithic packages 201. As shown in Figure 19 between the adjacent substrates, for example, a rectangular gap that divides the printed wiring substrates is formed, and a plurality of suspension portions 25 that connect the patterns to each other are formed in the gap. That is, in terms of the repeating pattern, the plurality of printed wiring substrates 17 are arranged on the plane with a space (gap) therebetween, and are connected to each other via the plurality of suspension portions 25, respectively. That is, the suspension portions 25 are portions that connect the plurality of printed wiring substrates 17 to each other.

[0194] After the transfer molding resin is molded, as shown in Figure 20 a unitary four-sided package with a plurality of single-chip packages 201 continuously arranged is obtained.

[0195] After that, the unitary package is cut by dicing to obtain the single-chip package 201. At the time of dicing, the wiring board and the transfer molding resin are cut at positions corresponding to the plurality of gaps and the plurality of overhangs 25.

[0196] As shown in Figure 21 Because of the overhangs 25, a part of the printed wiring board 17 is cut in the dicing process, and an exposed portion is observed at the side surface of the single-chip package 201. That is, the printed wiring board 17 is exposed from the first encapsulation resin 18 in at least any one of the surfaces perpendicular to the printed wiring board 17 of the single-chip package 201.

[0197] After the cutting, after the plurality of single-chip packages 201 are joined to the relay substrate 3, the single-chip packages 201 and the relay substrate 3 are encapsulated by the second encapsulation resin 4.

[0198] The second encapsulation resin 4 uses a liquid resin containing fine fillers called underfill materials, and encapsulates the narrow gap portion by capillary phenomenon.

[0199] The encapsulation of the second encapsulation resin 4 is performed while the resin filled in the syringe is injected from one direction to flow, and the air between the single-chip package 201 and the relay substrate 3 is removed. At this time, depending on the presence or absence of the circuit pattern of the relay substrate 3, there is a difference between the narrow gap portion and the maximum gap portion of the filling portion 7. When the difference between the gaps is large, in the maximum gap portion, the flow of the encapsulation resin is slow, and thus there is a possibility that a void is entrapped and an underfill occurs. Therefore, it is preferable that the ratio of the narrow gap to the maximum gap be less than or equal to 10 times.

[0200] Before the molding by molding is performed, the metal foil 19 is joined to the cooler 1 by the base joining material 2. The joining can be reflow soldering, fusion, or the use of solder or the like. In the case of using solder, in the case where the cooler 1 is copper or aluminum, it is preferable that plating of nickel or the like be performed on the surface.

[0201] Embodiment 5

[0202] This Embodiment 5 applies the semiconductor device related to the above-described Embodiments 1 to 4 to a power conversion device. The present application is not limited to a specific power conversion device, but in the following, as Embodiment 5, a case where the present application is applied to a three-phase inverter is described.

[0203] Figure 22is a block diagram showing the configuration of a power conversion system to which the power conversion device in Embodiment 5 of the present application is applied.

[0204] Figure 22 The power conversion system shown has a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a direct-current power supply that supplies direct current to the power conversion device 2000. The power supply 1000 can be configured from various power supplies, for example, can be configured from a direct-current system, a solar cell, a storage battery, or can be configured from a rectification circuit connected to an alternating-current system, an AC / DC converter, or the like. In addition, the power supply 1000 can be configured from a DC / DC converter that converts direct current output from a direct-current system into prescribed power.

[0205] The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts direct current supplied from the power supply 1000 into alternating current and supplies the alternating current to the load 3000. As shown in Figure 18 The power conversion device 2000 has a main conversion circuit 2001 that converts direct current input from the power supply 1000 into alternating current and outputs the alternating current, and a control circuit 2003 that outputs a control signal that controls the main conversion circuit 2001 to the main conversion circuit 2001.

[0206] The load 3000 is a three-phase motor that is driven by alternating current supplied from the power conversion device 2000. In addition, the load 3000 is not limited to a specific use, and is a motor mounted on various electric appliances, for example, is used as a motor for a hybrid automobile, an electric automobile, a railway vehicle, an elevator, an air conditioning device, or the like.

[0207] Details of the power conversion device 2000 will be described below. The main conversion circuit 2001 has switching elements and freewheeling diodes (not shown) built into a semiconductor device 2002, and converts direct current supplied from the power supply 1000 into alternating current by switching of the switching elements and supplies the alternating current to the load 3000. The specific circuit structure of the main conversion circuit 2001 is various, but the main conversion circuit 2001 involved in the present embodiment is a 2-level three-phase full-bridge circuit, and can be configured from six switching elements and six freewheeling diodes connected in anti-parallel to the switching elements, respectively. The main conversion circuit 2001 is configured from the semiconductor device 2002 equivalent to any of the above-described Embodiments 1 to 4 in which the switching elements, the freewheeling diodes, and the like are built in. The six switching elements are connected in series two by two to configure upper and lower arms, and each of the upper and lower arms configures each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each of the upper and lower arms, that is, three output terminals of the main conversion circuit 2001 are connected to the load 3000.

[0208] Further, the main conversion circuit 2001 has a drive circuit (not shown) that drives each switching element. The drive circuit can be built into the semiconductor device 2002, or can be configured to have the drive circuit separately from the semiconductor device 2002. The drive circuit generates a drive signal that drives the switching element of the main conversion circuit 2001, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 2001. Specifically, in accordance with a control signal from the control circuit 2003 described later, a drive signal that causes the switching element to be in the on state and a drive signal that causes the switching element to be in the off state are output to the control electrode of each switching element. In the case where the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is higher than the threshold voltage of the switching element, and in the case where the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) that is lower than the threshold voltage of the switching element.

[0209] The control circuit 2003 controls the switching elements of the main conversion circuit 2001 to supply a desired electric power to the load 3000. Specifically, the time (on time) during which each switching element of the main conversion circuit 2001 should be in the on state is calculated on the basis of the electric power that should be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the on time of the switching element in accordance with the voltage that should be output. Further, a control command (control signal) is output to the drive circuit possessed by the main conversion circuit 2001, so that the on signal is output to the switching element that should be in the on state and the off signal is output to the switching element that should be in the off state at each timing. The drive circuit outputs the on signal or the off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.

[0210] In the power conversion device according to the embodiment 5 configured as described above, since the semiconductor device according to the embodiments 1 to 4 is used as the semiconductor device 2002 of the main conversion circuit 2001, reliability can be improved.

[0211] In the present embodiment, an example in which the present application is applied to a three-phase inverter of 2 levels is described, but the present application is not limited thereto, and can be applied to various power conversion devices. In the present embodiment, the power conversion device is configured to be of 2 levels, but can be a power conversion device of 3 levels or a multi-level, and the present application can be applied to a single-phase inverter in the case where electric power is supplied to a single-phase load. Further, in the case where electric power is supplied to a direct-current load or the like, the present application can be applied to a DC / DC converter, an AC / DC converter, or the like.

[0212] In addition, the power conversion device of the present application is not limited to the case where the load is a motor, and can be used as a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, a non-contact power supply system, or the like, and can also be used as a power conditioner for a solar power generation system, an electric storage system, or the like.

[0213] In addition, in each of the embodiments described in the present specification, the material, the material, the size, the shape, the relative arrangement relationship, or the implementation conditions of each structural element, or the like are sometimes described, but these are all examples and are not limited to the contents described in each embodiment. Therefore, countless modifications not exemplified are conceivable within the scope of each embodiment. For example, a case where any structural element is modified, a case where anything is added, or a case where anything is omitted, and a case where at least one structural element in at least one embodiment is extracted and combined with a structural element of another embodiment are included.

[0214] It is needless to say that various design changes can be made within a range capable of achieving the object of the present application and not departing from the gist of the present application.

[0215] Explanation of Reference Numerals

[0216] 3 relay substrate, 12 heat sink, 14 semiconductor element, 15 conductive spacer, 17 printed wiring substrate, 18 first encapsulation resin, 22 first electrode, 23 second electrode, 31 printed wiring substrate back surface pattern, 32 printed wiring substrate surface pattern, 33 relay substrate back surface pattern, 34 relay substrate surface pattern, 52 first region of printed wiring substrate back surface, 53 second region of printed wiring substrate back surface, 62 first region of printed wiring substrate surface, 63 second region of printed wiring substrate surface, 72 first region of relay substrate back surface, 73 second region of relay substrate back surface, 82 first region of relay substrate surface, 83 second region of relay substrate surface, 101, 102, 103, 104, 2002 semiconductor device, 201, 202, 203 single-chip package, 2000 power conversion device, 2001 main conversion circuit, 2003 control circuit

Claims

1. A semiconductor device, characterized in that, It has a relay substrate and multiple monolithic packages. The monolithic package has: heat sink; A plurality of semiconductor elements are disposed on the heat sink, each semiconductor element having a first electrode and a second electrode, the second electrode being located on the side of the heat sink and the first electrode being located on the opposite side of the heat sink; as well as A printed wiring substrate has a back surface pattern and a surface pattern. The back surface pattern is disposed on the side opposite to the semiconductor element and a heat sink, and includes a first region on the back surface of the printed wiring substrate electrically connected to a first electrode and a second region on the back surface of the printed wiring substrate electrically connected to a second electrode via a conductive spacer disposed on the heat sink. The surface pattern is disposed on the side opposite to the semiconductor element and includes a first region on the surface of the printed wiring substrate and a second region on the surface of the printed wiring substrate electrically connected to the first region and the second region on the back surface of the printed wiring substrate, respectively. The relay substrate has a back surface pattern and a front surface pattern. Multiple monolithic packages are electrically connected via the back surface pattern. The back surface pattern is located opposite to the semiconductor element relative to the printed wiring substrate, and includes a first region and a second region on the back surface of the relay substrate that are electrically connected to a first region and a second region on the surface of the printed wiring substrate, respectively. The front surface pattern is located opposite to the back surface pattern and includes a first region and a second region on the surface of the relay substrate that are electrically connected to the first and second regions on the back surface of the relay substrate, respectively. The sum of the number of the first region and the second region on the surface of the printed wiring substrate included in the surface pattern of the printed wiring substrate is less than the sum of the number of the first electrode and the second electrode of the plurality of semiconductor elements included in the plurality of monolithic packages. The sum of the number of the first region and the second region on the surface of the relay substrate included in the surface pattern of the relay substrate is less than the sum of the number of the first region and the second region on the surface of the printed wiring substrate.

2. The semiconductor device according to claim 1, characterized in that, The plurality of the second electrodes of the plurality of semiconductor elements are connected to each other on the heat sink. The first region on the back side of the printed wiring substrate connects the first electrodes of the plurality of semiconductor elements to each other.

3. The semiconductor device according to claim 1, characterized in that, The heat sink is divided between the plurality of said semiconductor elements, and the conductive spacer is connected to one of the divided heat sinks. It also has a conductor that electrically connects the first electrode of the semiconductor element disposed in the heat sink to the heat sink that is not connected to the conductive spacer in the divided heat sink.

4. The semiconductor device according to claim 1, characterized in that, The thickness of the pattern on the back side of the relay substrate is greater than or equal to 0.1 mm.

5. The semiconductor device according to claim 2, characterized in that, A filler is provided on the portion of the side of the relay substrate that is not patterned on the back side of the relay substrate, where the insulating plate included in the relay substrate is provided.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The monolithic package is encapsulated in encapsulating resin, and the printed wiring substrate is exposed from the encapsulating resin on at least one of the faces perpendicular to the printed wiring substrate.

7. A power conversion device, comprising: A main converter circuit having a semiconductor device according to any one of claims 1 to 4, the main converter circuit converting the input power to an output; and The control circuit outputs control signals to the main conversion circuit to control the main conversion circuit.

8. A monolithic package, characterized in that, have: heat sink; A plurality of semiconductor elements are disposed on the heat sink, each semiconductor element having a first electrode and a second electrode, the second electrode being located on the side of the heat sink and the first electrode being located on the opposite side of the heat sink; as well as A printed wiring substrate has a back surface pattern and a surface pattern. The back surface pattern is disposed on the side opposite to the semiconductor element and a heat sink, and includes a first region on the back surface of the printed wiring substrate electrically connected to a first electrode and a second region on the back surface of the printed wiring substrate electrically connected to a second electrode via a spacer disposed on the heat sink. The surface pattern is disposed on the side opposite to the semiconductor element and includes a first region on the surface of the printed wiring substrate and a second region on the surface of the printed wiring substrate electrically connected to the first region and the second region on the back surface of the printed wiring substrate, respectively. The sum of the number of the first region and the second region on the surface of the printed wiring substrate included in the surface pattern of the printed wiring substrate is less than the sum of the number of the first electrode and the second electrode of the plurality of semiconductor elements.

9. A method for manufacturing a monolithic package, characterized in that, It includes the following processes: Multiple semiconductor elements are disposed on a heat sink. Each semiconductor element has a first electrode and a second electrode, wherein the second electrode is located on the side of the heat sink and the first electrode is located on the opposite side of the heat sink. as well as A printed wiring substrate is disposed on the side opposite to the heat sink relative to the semiconductor element. The printed wiring substrate has a back surface pattern and a surface pattern. The back surface pattern includes a first region electrically connected to the first electrode and a second region electrically connected to the second electrode via a spacer disposed on the heat sink. The surface pattern is disposed on the side opposite to the semiconductor element relative to the back surface pattern and includes a first region and a second region on the surface of the printed wiring substrate, respectively electrically connected to the first and second regions on the back surface of the printed wiring substrate. The sum of the number of the first region and the second region on the surface of the printed wiring substrate included in the surface pattern of the printed wiring substrate is less than the sum of the number of the first electrode and the second electrode of the plurality of semiconductor elements.

10. The method for manufacturing a monolithic package according to claim 9, characterized in that, It includes the following processes: Multiple heat sinks and multiple semiconductor elements are encapsulated in a repeating pattern of a printed wiring board by passing molding resin. In the repeating pattern of the printed wiring board, the printed wiring board has gaps and multiple are arranged on a plane, and has multiple suspension portions that connect adjacent multiple printed wiring boards in the gaps. as well as The repeating pattern and the transfer molding resin are cut at the positions corresponding to the gap and the suspension part.

Images