Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; a protective layer disposed on the insulating layer; and a bump portion passing through the protective layer, in which an upper surface of the protective layer has a concave surface recessed toward a lower surface of the protective layer, a thickness of the protective layer at a lowermost end of the concave surface is 1 / 2 or less of a thickness of the bump portion, the bump portion including a plurality of bumps, the concave surface being disposed between the plurality of bumps, the concave surface includes a first portion disposed between the plurality of bumps spaced apart by a first horizontal distance, and a second portion disposed between the plurality of bumps spaced apart by a second horizontal distance different from the first horizontal distance, the first portion and the second portion having different curvatures.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a circuit board and a semiconductor package including the same. BACKGROUND

[0002] High-performance electrical / electronic products are being developed, and thus, techniques for attaching a large number of packages to a substrate having a limited size have been proposed and researched. However, a general package basically includes one semiconductor chip, and thus, there is a limit in terms of having a required performance.

[0003] Therefore, recently, a semiconductor package is provided by arranging a plurality of semiconductor devices using a plurality of substrates. Such a semiconductor package has a structure in which a plurality of semiconductor devices are connected to each other in a horizontal direction and / or a vertical direction on a substrate. Thus, the semiconductor package has an advantage of effectively using a mounting area of the semiconductor devices and transmitting a high-speed signal through a short signal transmission path between the semiconductor devices.

[0004] In addition, a semiconductor package applied to products of Internet of Things (IoT), autonomous vehicles, and high-performance servers increases the number of semiconductor devices and / or the size of each semiconductor device due to high integration. However, due to a limitation of a mask, the concept is expanding to a semiconductor chiplet in which a functional part of a semiconductor device is divided.

[0005] Therefore, mutual communication between semiconductor devices and / or semiconductor chiplets becomes more and more important, and for this, an interposer is disposed between a substrate of a semiconductor package and a semiconductor device.

[0006] To facilitate mutual communication between semiconductor devices and / or semiconductor chiplets or interconnect semiconductor devices and a semiconductor package substrate, an interposer acts as a redistribution layer that gradually increases a width of a circuit pattern from a semiconductor device to a semiconductor package. Thus, the interposer can be used to smooth an electrical signal between a semiconductor device and a semiconductor package substrate having a relatively large circuit pattern compared to a circuit pattern of the semiconductor device.

[0007] Meanwhile, as the number of input terminals and output terminals of a semiconductor device increases, miniaturization of wiring and / or bumps becomes important. Accordingly, the pitch between the bumps decreases. In addition, a substrate includes an electrode portion electrically connected to a semiconductor device and / or a semiconductor chiplet, and a protective layer disposed on the electrode portion. In this case, the electrode portion, the protective layer, and the semiconductor device and / or the semiconductor chiplet are made of different materials. Accordingly, the coefficient of thermal expansion of the electrode portion, the coefficient of thermal expansion of the protective layer, and the coefficient of thermal expansion of the semiconductor device and / or the semiconductor chiplet are different from each other.

[0008] The coefficient of thermal expansion of the protective layer is greater than the coefficient of thermal expansion of each of the electrode portion, the semiconductor device, and / or the semiconductor chiplet, resulting in that the protective layer can expand and / or contract more than the electrode portion, the semiconductor device, and / or the semiconductor chiplet due to thermal stress acting in a use environment of the semiconductor package.

[0009] Further, when the protective layer repeatedly expands and / or contracts due to thermal stress, a crack can occur at an electrical connection point between the electrode portion and the semiconductor device and / or the semiconductor chiplet, stress can be applied to wiring or bumps having a fine pitch, thereby causing a problem such as a crack in the wiring or the bumps, and thus the mechanical reliability and / or the electrical reliability of the semiconductor package can be reduced.

[0010] Further, the bumps protrude on the protective layer. According to the related art, the protective layer is stacked in a state in which the bumps are preferentially disposed, and thus the bumps are made to protrude on the protective layer by performing a process of thinning the thickness of the protective layer. At this time, in the process of thinning the thickness of the protective layer, a filler disposed in the protective layer can be exposed to the upper surface of the protective layer. Further, the exposed filler can cause various physical and / or electrical reliability problems. SUMMARY

[0011] [TECHNICAL PROBLEM]

[0012] Embodiments provide a circuit board having a new structure and a semiconductor package including the same.

[0013] Further, embodiments provide a circuit board capable of shortening a delivery time and improving a product yield and a semiconductor package including the same.

[0014] In addition, embodiments provide a circuit board capable of improving electrical connection reliability between a substrate and a semiconductor device and a semiconductor package including the same.

[0015] Further, the embodiment provides a circuit board including a protective layer capable of reducing thermal strain and a semiconductor package including the circuit board.

[0016] The technical problem to be solved by the proposed embodiment is not limited to the above technical problem, and other technical problems not mentioned can be clearly understood by a person skilled in the art to which the proposed embodiment belongs from the following description.

[0017] [Technical Solution]

[0018] The circuit board according to the embodiment includes: an insulating layer; a protective layer disposed on the insulating layer; and a bump portion passing through the protective layer, wherein an upper surface of the protective layer has a concave surface concaved toward a lower surface of the protective layer, and a thickness of the protective layer at a lowermost end of the concave surface is 1 / 2 or less of a thickness of the bump portion.

[0019] In addition, the bump portion includes a plurality of bumps, and the concave surface is disposed between the plurality of bumps.

[0020] Further, the concave surface includes a first portion disposed between a plurality of bumps spaced apart by a first horizontal distance, and a second portion disposed between a plurality of bumps spaced apart by a second horizontal distance different from the first horizontal distance, wherein the first portion and the second portion have different curvatures.

[0021] Further, the first portion includes a curved surface concaved from the upper surface of the protective layer toward the lower surface of the protective layer and a flat surface extending from the curved surface, and a thickness of the protective layer at a lowermost end of the concave surface is a thickness of the protective layer at the flat surface of the first portion.

[0022] Further, the first horizontal distance is greater than the second horizontal distance, the second portion includes a curved surface concaved from the upper surface of the protective layer toward the lower surface of the protective layer and does not include a flat surface, and a thickness of the protective layer at a lowermost end of the concave surface is a thickness of the protective layer at the lowermost end of the curved surface of the second portion.

[0023] Further, a height of an uppermost end of the protective layer is less than or equal to a height of an upper surface of the bump portion.

[0024] Further, the circuit board further includes a wiring electrode disposed in a recess of an upper surface of the insulating layer, and the wiring electrode includes a first electrode pattern overlapping the bump portion in a vertical direction and a second electrode pattern not overlapping the bump portion in the vertical direction.

[0025] Further, the first portion of the concave surface overlaps the second electrode pattern in the vertical direction.

[0026] Further, each of the first portion and the second portion of the concave surface overlaps the second electrode pattern in the vertical direction, and a number of the second electrode patterns overlapping the first portion in the vertical direction is greater than a number of the second electrode patterns overlapping the second portion in the vertical direction.

[0027] In addition, at least a portion of the curved surface of each of the first portion and the second portion overlaps the first electrode pattern in the vertical direction.

[0028] Further, the circuit board further includes a connection member embedded in the insulating layer, and the first portion of the concave surface does not overlap the connection member in the vertical direction.

[0029] Further, the upper surface of the protective layer further includes a flat surface, and the concave surface of the protective layer is disposed around the flat surface of the protective layer.

[0030] Meanwhile, the circuit board according to an embodiment includes an insulating layer; a protective layer disposed on the insulating layer; and a bump portion passing through the protective layer, wherein an upper surface of the protective layer includes a concave surface recessed toward a lower surface of the protective layer and a flat surface connected to the concave surface, the bump portion includes a plurality of bumps spaced apart from each other in a horizontal direction, the concave surface includes a first portion disposed between a plurality of bumps spaced apart by a first horizontal distance, and a second portion disposed between a plurality of bumps spaced apart by a second horizontal distance different from the first horizontal distance, and a vertical cross-sectional shape of the first portion is different from a vertical cross-sectional shape of the second portion.

[0031] Further, the first horizontal distance is greater than the second horizontal distance, the first portion includes a curved surface recessed from the upper surface of the protective layer toward the lower surface of the protective layer and a flat surface extending from the curved surface, and the second portion includes a curved surface recessed from the upper surface of the protective layer toward the lower surface of the protective layer and does not include the flat surface.

[0032] Further, a thickness of the protective layer at the flat surface of the first portion and a thickness of the protective layer at a lowermost end of the second portion are 1 / 2 or less of a thickness of the bump portion.

[0033] Further, the circuit board further includes a connection member embedded in the insulating layer, and the first portion of the concave surface does not overlap the connection member in the vertical direction.

[0034] Further, the circuit board further includes a wiring electrode disposed in a recess of the upper surface of the insulating layer, the wiring electrode includes a first electrode pattern overlapping the bump portion in the vertical direction and a second electrode pattern not overlapping the bump portion in the vertical direction, and the first portion of the concave surface overlaps the second electrode pattern in the vertical direction.

[0035] Further, each of the first portion and the second portion of the concave surface overlaps the second electrode pattern in the vertical direction, and a number of the second electrode patterns overlapping the first portion in the vertical direction is greater than a number of the second electrode patterns overlapping the second portion in the vertical direction.

[0036] Meanwhile, the semiconductor package according to the embodiment includes: a circuit board; a connection part disposed on the circuit board; and a semiconductor device disposed on the connection part, wherein the circuit board includes: an insulating layer; a protective layer disposed on the insulating layer; and a bump part passing through the protective layer, wherein an upper surface of the protective layer has a concave surface which is concaved toward a lower surface of the protective layer, and a thickness of the protective layer at a lowermost end of the concave surface is 1 / 2 or less of a thickness of the bump part.

[0037] Further, the semiconductor package further includes a molding member for molding the semiconductor device, and a lower surface of the molding member includes a convex surface which is in contact with the concave surface of the protective layer.

[0038] [Advantageous Effects]

[0039] In the embodiment, the circuit board and the semiconductor package include the protective layer and the bump part passing through the protective layer. At this time, in a process of manufacturing the circuit board and the semiconductor package, the protective layer is stacked after the bump part is disposed. In the embodiment, the protective layer is stacked by applying a vacuum lamination method in a state where the bump part is disposed. In the embodiment, the concave surface can be provided on the upper surface of the protective layer. In addition, the embodiment can omit a process of thinning the thickness of the protective layer, and thus the filler can not be exposed to the upper surface of the protective layer.

[0040] For example, in the comparative example, when the protective layer is stacked in a state where the bump part is disposed, the protective layer completely covers the bump part, and thus a process of thinning the thickness of the protective layer is additionally performed. Therefore, in the comparative example, the process of thinning the protective layer is required, which complicates the manufacturing process, thereby increasing the delivery time, and further, the product yield can be deteriorated. Further, in the comparative example, in the process of thinning the thickness of the protective layer, the filler disposed in the protective layer can be exposed to the upper surface of the protective layer. In addition, the exposed filler can remain on the upper surface of the bump part, which can deteriorate the electrical characteristics of the bump part.

[0041] On the contrary, in the embodiment, the protective layer is laminated by applying the vacuum lamination method. Therefore, in the lamination process according to the vacuum lamination method, the protective layer can be provided with a via hole corresponding to the bump part. Therefore, in the embodiment, the process of thinning the thickness of the protective layer can be omitted, and thus the manufacturing process can be simplified, the delivery time can be shortened, and further, the product yield can be improved.

[0042] Further, the embodiment can prevent the filler from being exposed to the upper surface of the protective layer by omitting the process of thinning the thickness of the protective layer. Therefore, the embodiment can prevent the electrical characteristics of the circuit board from being deteriorated due to the filler, and thus the product reliability of the circuit board and the semiconductor package can be further improved.

[0043] In an embodiment, the concave surface provided in the protective layer can increase the surface area of the upper surface of the protective layer. Thereby, the embodiment can solve a problem of a crack of the bump portion that can occur due to thermal stress acting on the circuit board, and thus, can solve a reliability problem of an electrically conductive adhesive such as solder and / or a terminal of a semiconductor device provided on the bump portion being electrically separated from the bump portion.

[0044] For example, when thermal strain such as expansion and / or contraction of the circuit board occurs, stress can occur accordingly, and the stress can be transmitted to the bump portion. When thermal strain of the protective layer is repeated, stress can be applied to the bump portion provided in the protective layer, and due to the stress, a crack can occur in an electrical connection portion between the bump portion and the wiring layer. As a result, the bump portion can be separated from the wiring layer, thereby causing a mechanical reliability and / or an electrical reliability problem.

[0045] In addition, when thermal strain of the protective layer is repeated, stress can be applied to the electrically conductive adhesive such as solder provided on the bump portion, thereby causing a crack in the electrically conductive adhesive. As a result, an electrical disconnection problem can occur between the semiconductor device and the bump portion.

[0046] In this case, the concave surface provided on the upper surface of the protective layer of the embodiment serves to increase the surface area of the upper surface of the protective layer, thereby reducing the degree of thermal strain (e.g., the degree of expansion and / or contraction) of the protective layer caused by thermal stress. Thereby, the concave surface provided on the upper surface of the protective layer can prevent stress generated by thermal strain of the protective layer from being provided to the bump portion. For example, the concave surface can alleviate stress caused by thermal stress and prevent the stress from being transmitted in a direction toward the bump portion.

[0047] Accordingly, the embodiment can allow the semiconductor device to be stably adhered to the circuit board, thereby improving mechanical reliability and electrical reliability between the circuit board and the semiconductor device. Furthermore, the embodiment can allow the semiconductor device to be stably operated, thereby improving operation reliability of an electronic product such as a server to which the semiconductor package is applied.

[0048] In addition, the concave surface has a curved surface that is recessed from the upper surface of the protective layer toward the lower surface. Thereby, the embodiment is capable of further improving the effect of preventing stress from being transmitted by the concave surface. For example, when the concave surface has an angular square shape, stress can be concentrated in the angular portion, thereby causing a decrease in mechanical reliability or a decrease in electrical reliability. In contrast, the embodiment can allow the concave surface to have a curved surface, thereby preventing stress from being concentrated in a specific portion of the concave surface. Accordingly, the embodiment can further improve physical reliability and / or electrical reliability of the semiconductor package.

[0049] Further, the recessed surface of the embodiment includes a first portion and a second portion. In this case, the first portion of the recessed surface and the second portion of the recessed surface can have different widths, and thus can have different shapes.

[0050] The first portion of the recessed surface can include a curved surface and a flat surface. For example, in a region vertically overlapping the flat surface of the first portion of the recessed surface, the height of the protective layer can not change. In this case, the curved surface of the first portion of the recessed surface overlaps the first electrode pattern of the wiring layer disposed in the insulating layer in the vertical direction. Further, the flat surface of the first portion of the recessed surface vertically overlaps the second electrode pattern of the wiring layer disposed in the insulating layer. In this case, the second electrode pattern has a relatively fine width. Further, the number of the second electrode patterns disposed in a region vertically overlapping the second portion of the recessed surface is relatively greater than the number of the second electrode patterns disposed in a region vertically overlapping the first portion of the recessed surface. Thus, when the first portion of the recessed surface is completely curved, the second electrode pattern can not be stably protected, and thus the electrical reliability of the second electrode pattern can deteriorate. Thus, the embodiment allows the first portion of the recessed surface to have a flat surface, thereby stably protecting the second electrode pattern to improve the electrical reliability of the circuit board.

[0051] Further, the second portion of the recessed surface has a relatively small width. At this time, the second portion of the recessed surface is disposed between the protrusions spaced apart at a relatively small horizontal distance. Thus, when the conductive adhesive is applied to the protrusions in contact with the second portion of the recessed surface, an electrical short problem in which the conductive adhesives are connected to each other can occur due to diffusion of the conductive adhesive. Thus, in the embodiment, the second portion of the recessed surface does not have a flat surface, but has only a curved surface. Thus, the embodiment can further increase the surface area of the second portion of the recessed surface, thereby solving the electrical short problem that can occur due to diffusion of the conductive adhesive. For example, the second portion of the recessed surface can function as a dam that prevents the conductive adhesive from expanding in the horizontal direction, thereby further improving the electrical reliability of the circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1a A circuit board according to a first embodiment is illustrated.

[0053] Figure 1b is a plan view of the circuit board of FIG. 1.

[0054] Figure 2 is an enlarged view of a region in which the first portion of the recessed surface is disposed of FIG. 1.

[0055] Figure 3 is an enlarged view of a region in which the second portion of the recessed surface is disposed of FIG. 1.

[0056] Figure 4 is a cross-sectional view illustrating a circuit board according to a second embodiment.

[0057] Figure 5 is a cross-sectional view showing a circuit board according to a third embodiment.

[0058] Figure 6 shows a semiconductor package including the circuit board shown in FIG. 1.

[0059] Figure 7 shows a semiconductor package according to a second embodiment.

[0060] Figures 8 to 17 is a cross-sectional view showing a method of manufacturing the circuit board of FIG. 1 in a process sequence. DETAILED DESCRIPTION

[0061] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0062] However, the spirit and scope of the disclosure are not limited to a part of the described embodiments, and can be implemented in various other forms, and one or more elements of the embodiments can be selectively combined and replaced within the spirit and scope of the disclosure.

[0063] Further, unless explicitly defined and described otherwise, the terms used in the embodiments of the disclosure, including technical and scientific terms, can be interpreted the same as the meanings that one of ordinary skill in the art to which the disclosure belongs and is commonly used, and those terms such as defined in a generally used dictionary can be interpreted as having meanings consistent with their meanings in the context of relevant art. Also, the terms used in the embodiments of the disclosure are used to describe the embodiments, and are not intended to limit the disclosure.

[0064] In this specification, unless specifically stated and described otherwise in the phrase, the singular form can also include the plural form, and when describing "at least one of (or a plurality of) A, B, and C," at least one of all combinations of A, B, and C that can be combined can be included. Also, in describing elements of the embodiments of the disclosure, terms such as first, second, A, B, (a) and (b) can be used.

[0065] These terms are used only to distinguish the elements from other elements, and the terms are not limited to the nature, order or sequence of the elements. Also, when an element is described as being "connected", "coupled" or "contacted" to another element, it can include not only the case where the element is directly "connected", "coupled" or "contacted" to the other element, but also the case where the element is "connected", "coupled" or "contacted" to the other element through another element.

[0066] Also, when described as formed or disposed "on" or "under" each element, "on" or "under" can include not only that the two elements are directly connected to each other, but also that one or more other elements are formed or disposed between the two elements. Also, when described as "on" or "under" based on one element, it can include not only an upward direction but also a downward direction based on the one element.

[0067] [Electronic device]

[0068] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments is applied will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to the semiconductor package of the embodiments. Various semiconductor devices can be mounted on the semiconductor package.

[0069] The semiconductor device can include an active device and / or a passive device. The active device can be a semiconductor device in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device can be a logic chip, a memory chip, etc. The logic chip can be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip can be an application processor (AP) semiconductor device including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-digital converter, an ASIC (application-specific IC), etc., or a chipset including a specific combination of those listed so far.

[0070] The memory chip can be a stacked memory such as an HBM. Also, the memory chip can include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0071] Also, the semiconductor device can be an integrated passive device (IPD). In addition, the semiconductor device can be a multi-layer ceramic condenser (MLCC, Multi Layer Ceramic Condenser, Multi Layer Ceramic Capacitor) or a Si-based condenser.

[0072] On the other hand, a product group of semiconductor packages to which the application implementation is applied includes a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0073] In this case, the electronic device can include a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the implementation is not limited thereto, and can be any other electronic device that processes data other than these.

[0074] [Semiconductor package]

[0075] Figure 1a shows a circuit board according to a first embodiment, Figure 1b is a plan view of the circuit board of FIG. 1, Figure 2 is an enlarged view of a region of the first portion of FIG. 1 provided with a recessed surface, Figure 3 is an enlarged view of a region of the second portion of FIG. 1 provided with a recessed surface.

[0076] Referring to Figure 1a , the circuit board includes an insulating layer 110.

[0077] The insulating layer 110 can include an organic material that does not include a reinforcing member, so as to be able to have excellent processability, thinning of a substrate, and miniaturization of an electrode portion (e.g., the wiring electrode 120) provided in a circuit board. For example, the insulating layer 110 of the circuit board can use a product ABF (Ajinomoto Build-up Film) by Ajinomoto, FR-4, BT (Bismaleimide Triazine), PID (Photo Image-able Dielectric resin), BT, etc., but embodiments are not limited thereto.

[0078] The insulating layer 110 can be provided in a form of a plurality of layers stacked. As shown in FIG. 1, the insulating layer 110 can have a stacked structure of three layers, but is not limited thereto. For example, the insulating layer 110 can have a stacked structure of two layers or less, or can have a stacked structure of four layers or more.

[0079] In embodiments, the plurality of layers of the insulating layer 110 can be formed of the same insulating material, but is not limited thereto, and at least one layer of the plurality of layers of the insulating layer 110 can also include an insulating material different from at least another layer.

[0080] Through the stacked structure of the insulating layer 110 described above, the circuit board of embodiments can electrically connect a semiconductor device to a package substrate and / or a main board.

[0081] At least one layer of the plurality of layers of the insulating layer 110 of embodiments includes a reinforcing member. The reinforcing member in embodiments can refer to glass fiber. In another embodiment, the reinforcing member can refer to GCP (Glass Core Primer). When the reinforcing member refers to glass fiber, at least one layer of the plurality of layers of the insulating layer 110 can be provided as a core layer, and thus the circuit board can be provided as a core substrate.

[0082] Further, at least one layer of the plurality of layers of the insulating layer 110 includes a reinforcing member, and thus the rigidity of the circuit board can be improved. For example, the reinforcing member can be used to prevent the circuit board and the semiconductor package from being greatly bent in a certain direction. Thus, the insulating layer 110 can be prevented from being bent in the process of manufacturing the circuit board, thereby improving the position accuracy of the wiring electrode 120 and the via electrode 130 of the electrode portion, and further improving the matching degree between the wiring electrode 120 and the via electrode 130. Further, since the rigidity of the circuit board is secured, the semiconductor device can be stably coupled to the circuit board, and thus the semiconductor device can be stably operated. Further, embodiments can allow an electronic product such as a server to which the semiconductor package is applied to be stably operated, thereby improving product reliability.

[0083] For example, the plurality of layers of the insulating layer 110 can include a first layer including the reinforcing member 110GF. Also, the plurality of layers of the insulating layer 110 can include at least one second layer disposed on the first layer including the reinforcing member 110GF, the second layer not including the reinforcing member.

[0084] In this case, although FIG. 1 illustrates that the first layer of the insulating layer 110 including the reinforcing member 110GF is disposed in the lowermost layer among the plurality of layers, embodiments are not limited thereto. For example, the first layer including the reinforcing member 110GF can be disposed in the center of the plurality of layers stacked in the thickness direction of the insulating layer 110. In this case, second layers not including the reinforcing member can be respectively disposed in the upper and lower portions of the first layer including the reinforcing member 110GF.

[0085] The circuit board includes an electrode portion. The electrode portion includes a wiring electrode 120, a via electrode 130, and a bump portion 140.

[0086] The wiring electrode 120 can be horizontally disposed between each of the plurality of layers of the insulating layer 110, and the via electrode 130 can be vertically disposed while passing through each of the plurality of layers of the insulating layer 110. The wiring electrode 120 can include a pad and / or a trace. The pad of the wiring electrode 120 can overlap the via electrode 130 in the vertical direction, and thus can represent an electrode directly connected to the via electrode 130. The trace of the wiring electrode 120 can represent an elongated signal line connected to the pad of the wiring electrode 120 and thus transmitting a signal between a plurality of pads.

[0087] The wiring electrode 120 includes a wiring layer 121 disposed in the uppermost side of the insulating layer 110. The wiring layer 121 can refer to a wiring electrode disposed in the uppermost side among the wiring electrodes 120 disposed in different layers.

[0088] The wiring layer 121 can have an ETS (Embedded Trace Substrate) structure. For example, a recess can be provided on the upper surface of the uppermost layer of the insulating layer 110, and the wiring layer 121 can be disposed in the recess of the upper surface of the uppermost layer of the insulating layer 110. The ETS structure can also be referred to as an embedded structure. The ETS structure is advantageous in miniaturization compared to an electrode portion having a general protruding structure. Accordingly, in embodiments, an electrode pattern can be formed to correspond to the size and pitch of a terminal disposed in a semiconductor device. Accordingly, embodiments can improve circuit integration. Also, embodiments can minimize the transmission distance of a signal transmitted through a semiconductor device, and thus can minimize signal transmission loss.

[0089] Accordingly, at least a portion of the side surface of the wiring layer 121 can be covered by the insulating layer 110. Accordingly, the wiring layer 121 can be stably supported and / or protected by the insulating layer 110. Accordingly, the width and / or the pitch of the wiring layer 121 in the horizontal direction can be further refined, and thus, the circuit integration can be improved or the area of the circuit board can be reduced.

[0090] The wiring layer 121 can include a first electrode pattern 121a and a second electrode pattern 121b.

[0091] The first electrode pattern 121a can represent a pad. The first electrode pattern 121a overlaps at least one via electrode 130 passing through the insulating layer 110 in the vertical direction. For example, the first electrode pattern 121a is connected to the via electrode 130. For example, the lower surface of the first electrode pattern 121a directly contacts the upper surface of the via electrode 130. A plurality of first electrode patterns 121a are disposed on the upper surface of the insulating layer 110 to be spaced apart from each other in the horizontal direction.

[0092] The second electrode pattern 121b is disposed on the upper surface of the insulating layer 110. The second electrode pattern 121b can be referred to as a trace, and can be connected to the first electrode pattern 121a. For example, the second electrode pattern 121b can be disposed between a plurality of first electrode patterns spaced apart from each other in the horizontal direction, thereby electrically connecting the plurality of first electrode patterns.

[0093] The first electrode pattern 121a and the second electrode pattern 121b can have different widths and / or different planar shapes in the horizontal direction. For example, the width of the first electrode pattern 121a in the horizontal direction can be greater than the width of the second electrode pattern 121b in the horizontal direction. Accordingly, the first electrode pattern 121a and the second electrode pattern 121b can be distinguished by using the difference in the width in the horizontal direction. In addition, the planar shape of the first electrode pattern 121a can be circular or elliptical, and the second electrode pattern 121b can be square. Accordingly, the first electrode pattern 121a and the second electrode pattern 121b can be distinguished from each other in the planar shape.

[0094] The first electrode pattern 121a can include a plurality of pads. The plurality of pads of the first electrode pattern 121a can be spaced apart at different distances in the horizontal direction on the upper surface of the insulating layer 110.

[0095] For example, the first electrode pattern 121a includes a plurality of pads spaced apart at different horizontal distances according to a circuit arrangement design and / or a terminal pitch of a semiconductor device. For example, at least two pads of the plurality of pads of the first electrode pattern 121a can be spaced apart from each other at a first horizontal distance W1. For example, at least two pads of the plurality of pads of the first electrode pattern 121a can be spaced apart at a second horizontal distance W2 that is smaller than the first horizontal distance W1.

[0096] In this case, N second electrode patterns 121b can be disposed between the plurality of pads of the first electrode pattern 121a that are spaced apart from each other at the first horizontal distance W1. Also, n second electrode patterns 121b that are smaller than N can be disposed between the plurality of pads of the first electrode pattern 121a that are spaced apart from each other at the second horizontal distance W2.

[0097] Accordingly, the embodiments can allow the plurality of pads of the first electrode pattern 121a to be spaced apart at different horizontal distances according to a width and / or a pitch of a terminal of a semiconductor device in a horizontal direction, and also, different numbers of second electrode patterns 121b can be disposed between the plurality of pads having different horizontal distances. Accordingly, the embodiments can dispose a relatively large number of second electrode patterns 121b between the plurality of pads of the first electrode pattern 121a that are spaced apart at a relatively large horizontal distance, thereby improving circuit integration and further miniaturizing a semiconductor package. In addition, a relatively small number of second electrode patterns 121b can be disposed between the plurality of pads of the first electrode pattern 121a that are spaced apart at a relatively small horizontal distance, and thus, an electrical short problem that can occur when the first electrode pattern 121a and the second electrode pattern 121b that should be electrically separated from each other are connected to each other can be addressed.

[0098] The via electrode 130 can be provided by filling a via hole provided in a plurality of layers of the insulating layer 110 with a conductive material. The via electrode 130 is connected to the wiring electrode 120. The via electrode 130 can vertically connect the wiring electrodes provided in different layers.

[0099] Also, the electrode portion of the circuit board includes a bump portion 140. The bump portion 140 is disposed on the wiring electrode 120. For example, the bump portion 140 is disposed on the wiring layer 121 located at the uppermost side of the wiring electrode 120. For example, the bump portion 140 is disposed on the first electrode pattern 121a of the wiring layer 121.

[0100] The bump portion 140 penetrates the first protective layer 150. Also, the bump portion 140 protrudes above the insulating layer 110.

[0101] The bump portion 140 protrudes above the first protective layer 120 of the circuit board to stably couple the terminals of the semiconductor device and the electrode portions of the circuit board using the conductive adhesive. Accordingly, the bump portion 140 can separate the conductive adhesive from the circuit board by a predetermined interval, and can improve the degree of position matching between the bump portion 140 and the terminals of the semiconductor device.

[0102] For example, when the semiconductor device is mounted with the conductive adhesive such as solder, as the width of the terminals of the semiconductor device coupled to the circuit board and the pitch of the terminals become finer, diffusion of the conductive adhesive in the horizontal direction can occur, and thus a problem in which a plurality of conductive adhesives are connected to each other can occur. For example, in an embodiment, Thermal Compression Bonding can be performed to reduce the volume of the conductive adhesive. In this case, when the bump portion 140 is not provided, the conductive adhesive is disposed on the first electrode pattern 121a of the wiring layer 121, and thus it can be difficult to reduce the volume of the conductive adhesive. This can be because the height of the wiring electrode in which the conductive adhesive is disposed is lower than the height of the first protective layer 120, and thus the volume of the conductive adhesive is increased due to the difference between the height of the wiring electrode and the height of the first protective layer 120.

[0103] In particular, the width and the pitch of the terminals of the semiconductor device become finer, and the width and the pitch of the wiring electrode 120 become finer. Accordingly, the pitch between the wiring electrodes 120 can be too narrow, and when the semiconductor device is mounted by applying the conductive adhesive such as solder on the wiring electrode 120, as the pitch between the conductive adhesives becomes smaller, a short circuit problem in which two adjacent conductive adhesives are connected to each other can occur. Accordingly, the embodiment includes the bump portion 140, and the conductive adhesive such as solder is applied on the bump portion 140 to perform a mounting process of the semiconductor device. Preferably, in an embodiment, Thermal Compression Bonding can be performed using the bump portion 140 disposed at the uppermost side of the circuit board. Accordingly, the embodiment can allow the semiconductor device to be stably mounted on the substrate, thereby allowing the semiconductor device to stably operate.

[0104] The upper surface and the lower surface of the bump portion 140 can have the same width. For example, the side surface of the bump portion 140 can have no step difference. For example, the width of the bump portion 140 can not change from the upper surface to the lower surface. Accordingly, the embodiment can reduce the width of the bump portion 140 in the horizontal direction, and further reduce the horizontal distance between the centers of a plurality of bumps spaced apart in the horizontal direction. Accordingly, the embodiment can further improve the degree of circuit integration, and can also miniaturize the semiconductor package.

[0105] In this case, the bump portion 140 can be provided by filling the opening provided in the dry film with an electrically conductive material before the first protective layer 150 is formed. Accordingly, the width of the lower surface of the bump portion 140 can be the same as the width of the upper surface of the bump portion 140, and in addition, the bump portion 140 can have a slope that does not change in width from the upper surface to the lower surface.

[0106] For example, in the first comparative example, a via is formed in the first protective layer, a dry film having an opening is stacked on the first protective layer, and the via of the first protective layer and the opening of the dry film are filled with an electrically conductive material to form a bump portion. In this case, a process of forming a via in the first protective layer is also required. In addition, in the first comparative example, a process of forming a separate seed layer and a process of removing the seed layer by etching are also required in order to plate the bump portion. Accordingly, in the first comparative example, the manufacturing process is complex, thereby increasing the lead time, and thus, there is a problem in that the product yield deteriorates. In addition, it is difficult to match the via width to the opening width 1:1, and thus, the opening width has a width greater than the via width. In this case, the side surface of the bump portion can have a step, and thus, the width of the upper surface of the bump portion can increase, and thus, there is a limit to reducing the horizontal distance between the centers of the plurality of bumps.

[0107] On the contrary, in the embodiment, the bump portion 140 is formed on the first electrode pattern 121a of the wiring layer 121 before the first protective layer 150 is stacked. Accordingly, in the embodiment, the bump portion 140 can be formed using the seed layer for plating the wiring layer 121. Accordingly, in the embodiment, a process of forming a separate seed layer and a process of removing the separate seed layer in order to plate the bump portion 140 are unnecessary, and thus, the manufacturing process can be simplified, the lead time can be reduced, and the product yield can be further improved. In addition, the embodiment can omit a process of forming a via for forming the bump portion 140 in the first protective layer 150.

[0108] The circuit board includes a protective layer.

[0109] For example, the circuit board includes a first protective layer 150 disposed above the insulating layer 110 and a second protective layer 160 disposed below the insulating layer 110.

[0110] The first protective layer 150 is disposed on the insulating layer 110 and the wiring layer 121. In addition, the first protective layer 150 is disposed to surround the side of the bump portion 140 disposed on the first electrode pattern 121a of the wiring layer 121. For example, the bump portion 140 includes a plurality of bumps spaced apart in the horizontal direction, and the first protective layer 150 can be disposed between the plurality of bumps, respectively.

[0111] The first protective layer 150 and the second protective layer 160 can be a solder resist layer including an organic polymer material. For example, the first protective layer 150 and the second protective layer 160 can include an epoxy acrylate-based resin. Also, the first protective layer 150 and the second protective layer 160 can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the first protective layer 150 and the second protective layer 160 can be any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0112] An upper surface of the first protective layer 150 can have a step difference. For example, at least a portion of the upper surface of the first protective layer 150 can be located on the same plane as an upper surface of the bump portion 140. For example, at least a portion of the upper surface of the first protective layer 150 can be lower than the upper surface of the bump portion 140. However, embodiments are not limited thereto, and an uppermost end of the first protective layer 150 can be lower than the upper surface of the bump portion 140.

[0113] The upper surface of the first protective layer 150 has a concave surface 150T. That is, the first protective layer 150 is disposed between the plurality of bumps of the bump portion 140, and thus the concave surface 150T of the first protective layer 150 can be concave between the plurality of bumps in a downward direction or in a direction toward the upper surface of the insulating layer 110. The concave surface 150T of the first protective layer 150 can function to increase a surface area of the upper surface of the first protective layer 150, thereby preventing a stress generated by a thermal cycle such as expansion and / or contraction from being transmitted to the bump portion 140.

[0114] For example, the concave surface 150T disposed on the upper surface of the first protective layer 150 increases a surface area of the upper surface of the first protective layer 150, and thus can function to increase a surface area of the upper surface of the first protective layer 150 between the bump portion 140 compared to a case in which the upper surface of the first protective layer 150 is a flat surface.

[0115] As such, embodiments can address a problem of a crack in the bump portion 140 that can occur due to a thermal stress acting on the circuit board. Accordingly, embodiments can address a reliability problem of an electrically conductive adhesive such as solder disposed on the bump portion 140 and / or a terminal of a semiconductor device being electrically separated from the bump portion 140.

[0116] For example, when a thermal strain such as expansion and / or contraction of the circuit board occurs, a stress can be applied to be transmitted to the bump portion 140. Here, the thermal strain can mean that a volume of the first protective layer 150 is changed due to expansion and / or contraction of the first protective layer 150.

[0117] When thermal strain of the first protective layer 150 is repeated, stress can be applied to the bump portion 140 disposed in the first protective layer 150, and due to the stress, a crack can occur in an electrical connection portion between the bump portion 140 and the wiring layer 121. Accordingly, the bump portion 140 can be separated from the wiring layer 121, thereby causing a mechanical reliability and / or an electrical reliability problem.

[0118] In addition, when thermal strain of the first protective layer 150 is repeated, stress can be applied to a conductive adhesive such as solder disposed on the bump portion 140, and thus a breakage of the conductive adhesive can occur. As a result, an electrical disconnection problem can occur between the semiconductor device and the bump portion.

[0119] The concave surface 150T disposed on the upper surface of the first protective layer 150 serves to increase a surface area of the upper surface of the first protective layer 150, and thus can reduce a degree of thermal strain (e.g., a degree of expansion and / or a degree of contraction) of the first protective layer 150 generated by thermal stress. Accordingly, the concave surface 150T disposed on the upper surface of the first protective layer 150 can prevent stress generated by thermal strain of the first protective layer 150 from acting on the bump portion 140. For example, the concave surface 150T can alleviate stress caused by thermal stress to prevent the stress from being transmitted in a direction toward the bump portion 140.

[0120] Accordingly, embodiments can allow a semiconductor device to be stably adhered to a circuit board, thereby improving mechanical reliability and electrical reliability between the circuit board and the semiconductor device. In addition, embodiments can allow a semiconductor device to be stably operated, thereby improving operational reliability of an electronic product such as a server to which a semiconductor package is applied.

[0121] In addition, the concave surface 150T has a curved surface that is recessed from the upper surface of the first protective layer 150 toward the lower surface. Thereby, embodiments can further improve an effect of preventing stress from acting by using the concave surface 150T. For example, when the concave surface 150T has an angular square shape, stress can be concentrated in an angular portion, which can cause a problem of a decrease in mechanical reliability or electrical reliability. In contrast, in embodiments, the concave surface 150T can have a curved surface that is recessed, and thus stress can be prevented from being concentrated in a specific portion of the concave surface 150T. Accordingly, embodiments can further improve physical reliability and / or electrical reliability of a semiconductor package.

[0122] Further, the first protective layer 150, the bump portion 140, and the semiconductor device include different materials from each other. For example, the first protective layer 150 can be provided with a solder resist, the bump portion 140 can be formed of a metal material such as copper, and the semiconductor device can be formed of a silicon material. In this case, the first protective layer 150, the bump portion 140, and the semiconductor device have different coefficients of thermal expansion from each other. For example, the coefficient of thermal expansion of the first protective layer 150 is greater than the coefficients of thermal expansion of the bump portion 140 and the semiconductor device. Therefore, when the same thermal stress acts on the first protective layer 150, the bump portion 140, and the semiconductor device, the degree of thermal strain of the first protective layer 150 can be greatest compared to the bump portion 140 and the semiconductor device.

[0123] Accordingly, the embodiments allow the concave surface 150T to be provided at the upper surface of the first protective layer 150, and prevent stress caused by thermal strain such as expansion and / or contraction from acting on the electrical connection portion between the circuit board and the semiconductor device, thereby improving the mechanical reliability and / or the electrical reliability of the semiconductor package.

[0124] The concave surface 150T is provided between the plurality of bumps of the bump portion 140. In this case, a plurality of concave surfaces 150T of the first protective layer 150 are provided and have different widths in the horizontal direction.

[0125] Referring to Figure 1b (a), the plurality of bump portions 140 are spaced apart from each other in the horizontal direction. In this case, as shown in (a) of Figure 1b , the bump portions 140 can be arranged in a checkered shape. In this case, the upper surface of the first protective layer 150 can include a concave surface 150Ta provided between a plurality of bumps spaced apart from each other in a first horizontal direction, and a concave surface 150Tb provided between a plurality of bumps spaced apart from each other in a second horizontal direction different from the first horizontal direction. In this case, the upper surface of the first protective layer 150 can have a flat surface 150Tc surrounded by the concave surfaces 150Ta and 150Tb.

[0126] Referring to Figure 1b (b), the plurality of bump portions 140 are spaced apart from each other in the horizontal direction. In this case, as shown in (b) of Figure 1bAs illustrated in (a), the bump portion 140 can have a chessboard shape, and can be disposed to be misaligned in the first horizontal direction and the second horizontal direction. In this case, the upper surface of the first protective layer 150 can include a concave surface 150Ta disposed between a plurality of bumps spaced apart from each other in the first horizontal direction, and a concave surface 150Tb disposed between a plurality of bumps spaced apart from each other in the second horizontal direction different from the first horizontal direction. In this case, the concave surfaces 150Ta and 150Tb of the upper surface of the first protective layer 150 can include overlapping portions 150Tab overlapping each other. In this case, the upper surface of the first protective layer 150 can include a flat surface 150Tc surrounded by the concave surfaces 150Ta and 150Tb.

[0127] In this case, the concave surfaces 150Ta and 150Tb can include first portions 150T1 and second portions 150T2 having different shapes and / or curvatures.

[0128] For example, the bump portion 140 includes a plurality of bumps having different interval distances in the horizontal direction. Also, the concave surface 150T is disposed between the plurality of bumps having different interval distances. Accordingly, the concave surface 150T includes first portions 150T1 having a first width and second portions 150T2 having a second width smaller than the first width.

[0129] For example, the first portions 150T1 of the concave surface vertically overlap with regions between two pads spaced apart from each other by a first horizontal distance W1 among the first electrode patterns 121a of the wiring layer 121. For example, the first portions 150T1 of the concave surface are disposed between two bumps of the bump portion 140 disposed on two pads spaced apart from each other by the first horizontal distance W1.

[0130] Also, the second portions 150T2 of the concave surface vertically overlap with regions between two pads spaced apart from each other by a second horizontal distance W2 among the first electrode patterns 121a of the wiring layer 121. For example, the second portions 150T2 of the concave surface are disposed between two bumps of the bump portion 140 disposed on two pads spaced apart by the second horizontal distance W2.

[0131] In this case, the first portions 150T1 of the concave surface and the second portions 150T2 of the concave surface can have different shapes (e.g., vertical cross-sectional shapes).

[0132] Referring to Figure 2The first portion 150T1 of the concave surface can have a first width w3. The first portion 150T1 of the concave surface can be disposed between the first protrusion 141 and the second protrusion 142 having a relatively large horizontal distance and spaced apart from each other of the protrusion portion 140. For example, the first portion 150T1 of the concave surface can have the first width w3 and be disposed between the first protrusion 141 and the second protrusion 142 spaced apart horizontally from each other.

[0133] In this case, the first portion 150T1 of the concave surface includes a curved portion and a flat portion. The curved portion can refer to a curved surface disposed in the first portion 150T1 of the concave surface and recessed from an upper surface of the first protection layer 150 toward a lower surface, and the flat portion can refer to a flat surface connected to the curved surface in the first portion 150T1 of the concave surface.

[0134] For example, the first portion 150T1 of the concave surface includes a first curved portion 150T1a recessed from an upper surface of the first protrusion 141 toward the insulating layer 110. The first curved portion 150T1a can have one end in contact with a side surface of the first protrusion 141 and the other end extending in a direction from the one end toward the second protrusion 142. In this case, the first curved portion 150T1a can be recessed from the same height as the upper surface of the first protrusion 141 toward the insulating layer 110. For example, the uppermost end of the first curved portion 150T1a can be located on the same plane as the upper surface of the first protrusion 141. Accordingly, the embodiment can completely cover the side surface of the first protrusion 141 with the first protection layer 150. Accordingly, the embodiment can stably support the first protrusion 141 by using the first protection layer 150, and thus, an electrical reliability problem in which the first protrusion 141 is separated from the first electrode pattern 121a due to various factors can be addressed. In this case, the first curved portion 150T1a can have a maximum height at a portion closest to the first protrusion 141 and a minimum height at a portion farthest from the first protrusion 141. However, the embodiment is not limited thereto, and the uppermost end of the first curved portion 150T1a can be lower than the upper surface of the first protrusion 141.

[0135] Further, the first portion 150T1 of the concave surface can include a second curved portion 150T1b recessed from an upper surface of the second bump 142 toward the insulating layer 110. The second curved portion 150T1b can have one end in contact with a side surface of the second bump 142 and another end extending in a direction from the one end toward the first bump 141. In this case, the second curved portion 150T1b can be recessed from the same height as the upper surface of the second bump 142 toward the insulating layer 110. For example, the uppermost end of the second curved portion 150T1b can be located on the same plane as the upper surface of the second bump 142. Accordingly, the side surface of the second bump 142 can be completely covered by the first protective layer 150. Thus, the embodiments can stably support the second bump 142 by using the first protective layer 150, whereby the electrical reliability problem of the second bump 142 being separated from the first electrode pattern 121a due to various factors can be addressed. In this case, the second curved portion 150T1b can have the greatest height at a portion closest to the second bump 142 and can have the least height at a portion farthest from the second bump 142. However, the embodiments are not limited thereto, and the uppermost end of the second curved portion 150T1b can be lower than the upper surface of the second bump 142.

[0136] Further, the first portion 150T of the concave surface can include a flat portion 150T1c disposed between the first curved portion 150T1a and the second curved portion 150T1b. The flat portion 150T1c of the first portion 150T1 of the concave surface can be a flat surface. For example, in a region vertically overlapping the flat portion 150T1c of the first portion 150T1 of the concave surface, the height of the first protective layer 150 can not change. In this case, each of the first curved portion 150T1a and the second curved portion 150T1b of the first portion 150T1 of the concave surface overlaps the first electrode pattern 121a of the wiring layer 121 disposed in the insulating layer 110 in the vertical direction. In addition, the flat portion 150T1c of the first portion 150T1 of the concave surface overlaps the second electrode pattern 121b of the wiring layer 121 disposed in the insulating layer 110 in the vertical direction. In this case, the second electrode pattern 121b has a relatively fine width. Further, a region overlapping the first portion 150T1 of the concave surface in the vertical direction is provided with a relatively greater number of the second electrode pattern 121b than a region overlapping the second portion 150T2 of the concave surface in the vertical direction. Accordingly, when the first portion 150T1 of the concave surface is provided as a curved portion as a whole, the second electrode pattern 121b can not be stably protected, and thus the electrical reliability of the second electrode pattern 121b can deteriorate. Accordingly, in the embodiments, the flat portion 150T1c is provided in the first portion 150T1 of the concave surface, and thus the second electrode pattern 121b can be stably protected, and thus the electrical reliability of the circuit board can be improved.

[0137] In addition, the height of the first portion 150T1 of the concave surface can be determined according to the height of the bump portion 140. For example, the height of the first portion 150T1 of the concave surface can represent the thickness T2 of the first protective layer 150 at the lowermost end of the first portion 150T1 of the concave surface. For example, the height of the first portion 150T1 of the concave surface can represent the thickness T2 of the first protective layer 150 at the flat portion 150T1c of the first portion 150T1 of the concave surface.

[0138] In addition, the thickness T2 of the first protective layer 150 at the lowermost end of the first portion 150T1 of the concave surface can be less than or equal to 1 / 2 of the thickness T1 of the bump portion 140. In this case, when the thickness T2 of the first protective layer 150 at the lowermost end of the first portion 150T1 of the concave surface exceeds 1 / 2 of the thickness T1 of the bump portion 140, the yield in the manufacturing process of stacking the first protective layer 150 can be deteriorated, and in addition, a portion of the first protective layer 150 can remain on the upper surface of the bump portion 140, which can cause a reliability problem of deteriorated electrical characteristics.

[0139] In addition, referring to Figure 3 , the second portion 150T2 of the concave surface can have a second width w4. The second portion 150T2 of the concave surface can be disposed between the third bump 143 and the fourth bump 144 having a relatively small horizontal distance and spaced apart from each other of the bump portion 140. For example, the second portion 150T2 of the concave surface can have the second width w4 and be disposed between the third bump 143 and the fourth bump 144 horizontally spaced apart from each other.

[0140] In this case, the second portion 150T2 of the concave surface can have a different shape from the first portion 150T1 of the concave surface. For example, the second portion 150T2 of the concave surface can have a different curvature from the first portion 150T1 of the concave surface.

[0141] For example, the second portion 150T2 of the concave surface can not include a flat portion. For example, the second portion 150T2 of the concave surface can include only a curved portion.

[0142] That is, one end of the curved portion of the second portion 150T2 of the concave surface can be in contact with the side surface of the third bump 143, and the other end of the curved portion of the second portion 150T2 of the concave surface can be in contact with the side surface of the fourth bump 144. The curved portion of the second portion 150T2 of the concave surface can include only a concave curved portion whose height gradually decreases between the one end and the other end. That is, the curved portion of the second portion 150T2 of the concave surface can be recessed toward the insulating layer 110 from the same height as the third bump 143 and the fourth bump 144. The curved portion of the second portion 150T2 of the concave surface can have the greatest height at portions closest to the third bump 143 and the fourth bump 144, respectively, and can have the least height at portions farthest from the third bump 143 and the fourth bump 144.

[0143] The uppermost end of the second portion 150T2 of the concave surface can be located on the same plane as the upper surfaces of the third bump 143 and the fourth bump 144. Accordingly, in an embodiment, the side surfaces of the third bump 143 and the fourth bump 144 can be completely covered by the first protective layer 150. Accordingly, the third bump 143 and the fourth bump 144 can be stably supported by using the first protective layer 150, and thus, an electrical reliability problem in which the third bump 143 and the fourth bump 144 are separated from the first electrode pattern 121a due to various factors can be addressed. However, embodiments are not limited thereto, and the uppermost end of the second portion 150T2 of the concave surface can be lower than the upper surfaces of the third bump 143 and the fourth bump 144.

[0144] In this case, the second portion 150T2 of the concave surface has a relatively small width. Accordingly, compared to the first portion 150T1 of the concave surface, the second portion 150T2 of the concave surface can overlap with a smaller number of the second electrode patterns 121b in the vertical direction.

[0145] In this case, the second portion 150T2 of the concave surface has a relatively small width and is disposed between the third bump 143 and the fourth bump 144 spaced apart from each other. Accordingly, when the conductive adhesive is applied on the third bump 143 and the fourth bump 144, an electrical short problem in which the conductive adhesive is connected to each other due to diffusion of the conductive adhesive can occur. Accordingly, in an embodiment, the second portion 150T2 of the concave surface does not have a flat portion but only a curved portion. Accordingly, the embodiment can further increase the surface area of the second portion 150T2 of the concave surface, thereby addressing the electrical short problem that can occur due to diffusion of the conductive adhesive. For example, the second portion 150T2 of the concave surface can function as a dam to prevent the conductive adhesive from expanding in the horizontal direction, thereby further improving the electrical reliability of the circuit board.

[0146] Further, the height of the second portion 150T2 of the concave surface can be determined according to the height of the bump portion 140. For example, the height of the second portion 150T2 of the concave surface can represent the thickness T2 of the first protective layer 150 at the lowermost end of the second portion 150T2 of the concave surface. For example, the height of the second portion 150T2 of the concave surface can represent the thickness T2 of the first protective layer 150 at the lowermost end of the curved portion of the second portion 150T2 of the concave surface.

[0147] In addition, the thickness T2 of the first protective layer 150 at the lowermost end of the second portion 150T2 of the concave surface can be less than or equal to 1 / 2 of the thickness T1 of the bump portion 140. In this case, when the thickness T2 of the first protective layer 150 at the lowermost end of the second portion 150T2 of the concave surface exceeds 1 / 2 of the thickness T1 of the bump portion 140, the yield in the manufacturing process of stacking the first protective layer 150 can be deteriorated, and further, a reliability problem in which a portion of the first protective layer 150 remains on the upper surface of the bump portion 140 to deteriorate the electrical characteristics can occur.

[0148] That is, the embodiment stacks the first protective layer 150 after the bump portion 140 is provided. However, in the embodiment, the first protective layer 150 is stacked by applying a vacuum lamination method in a state in which the bump portion 140 is provided. Accordingly, in the embodiment, the filler can not be exposed to the upper surface of the first protective layer 150.

[0149] For example, in the second comparative example, when the first protective layer is stacked in a state in which the bump portion is provided, the first protective layer completely covers the bump portion, and thus, a process of thinning the thickness of the first protective layer is additionally performed. Accordingly, in the second comparative example, the manufacturing process is complex because the process of thinning the thickness of the first protective layer must be performed, thereby increasing the delivery time, and in addition, the product yield can be reduced. Further, in the second comparative example, in the process of thinning the thickness of the first protective layer, the filler provided in the first protective layer can be exposed to the upper surface of the first protective layer. In addition, the exposed filler can remain on the upper surface of the bump portion 140, which can deteriorate the electrical characteristics of the bump portion 140.

[0150] In contrast, in the embodiment, the first protective layer 150 is stacked by applying a vacuum lamination method. Accordingly, in the lamination process according to the vacuum lamination method, the first protective layer 150 can be provided with a through-hole corresponding to the bump portion 140. Accordingly, the embodiment can omit the process of thinning the thickness of the first protective layer 150, and thus, the manufacturing process can be simplified, the delivery time can be shortened, and the product yield can be further improved.

[0151] Further, the embodiments can prevent the filler from being exposed to the upper surface of the first protective layer 150 by omitting the process of thinning the thickness of the first protective layer 150. Accordingly, the embodiments can prevent the electrical characteristics of the circuit board from being deteriorated due to the filler, and thus can further improve the product reliability of the circuit board and the semiconductor package.

[0152] Figure 4 is a cross-sectional view illustrating a circuit board according to a second embodiment. In the circuit board of the second embodiment, the shape of the first electrode pattern 121a can be different from that of the circuit board of the first embodiment, and thus the shape of the lower surface of the first protective layer 150, which contacts the first electrode pattern 121a, can be different from that of the circuit board of the first embodiment.

[0153] Referring to Figure 4 , the first electrode pattern 121a can include a tapered inclined side surface which varies in width. The side surface of the first electrode pattern 121a can include a portion in which the inclination varies. Here, the portion in which the inclination varies means not only a change in the direction of the inclination but also a change in the size of the inclination.

[0154] For example, the side surface of the first electrode pattern 121a can include a first inclination 121s1 which is adjacent to the upper surface 121at of the first electrode pattern 121a and gradually increases the width toward the lower surface of the first electrode pattern 121a. Further, the side surface of the first electrode pattern 121a can include a second inclination 121s2 which is adjacent to the lower surface of the first electrode pattern 121a and is different from the first inclination 121s1. The second inclination 121s2 can be perpendicular to the upper surface 121at and / or the lower surface of the first electrode pattern 121a, but is not limited thereto. An internal angle between the upper surface 121at of the first electrode pattern 121a and the first inclination 121s1 of the first electrode pattern 121a can be an obtuse angle. The internal angle between the upper surface 121at of the first electrode pattern 121a and the first inclination 121s1 can be in the range of 95 degrees to 160 degrees. Preferably, the internal angle between the upper surface 121at of the first electrode pattern 121a and the first inclination 121s1 can be in the range of 100 degrees to 150 degrees. More preferably, the internal angle between the upper surface 121at of the first electrode pattern 121a and the first inclination 121s1 can be in the range of 105 degrees to 140 degrees.

[0155] When the internal angle between the upper surface 121at of the first electrode pattern 121a and the first slope 121s1 is less than 95 degrees, the effect of increasing the contact area between the first protective layer 150 and the first electrode pattern 121a can be insufficient. Accordingly, a problem in which the first protective layer 150 is separated from the first electrode pattern 121a and / or the insulating layer 110 can occur. In addition, when the internal angle between the upper surface 121at of the first electrode pattern 121a and the first slope 121s1 exceeds 160 degrees, the difference in the width of the upper surface 121at and the lower surface of the first electrode pattern 121a in the horizontal direction can increase. As the width difference increases, the transmission loss of a signal transmitted through the first electrode pattern 121a increases, and thus the signal transmission characteristics can deteriorate. Furthermore, when the width of the upper surface 121at becomes too small due to the increase in the width difference, the bump portion 140 can not be stably disposed on the first electrode pattern 121a, and furthermore, the semiconductor device can not be stably coupled to the bump portion 140. In addition, when the width of the lower surface of the first electrode pattern 121a becomes too large due to the increase in the width difference, it can be difficult to miniaturize the line width and the pitch of the first electrode pattern 121a. For this reason, it can be difficult to make the circuit board slim, and the volume of the semiconductor package and the electronic product or server including the same can increase.

[0156] The second slope 121s2 of the first electrode pattern 121a can connect the lower end of the first slope 121s1 and the lower surface of the first electrode pattern 121a. The second slope 121s2 can be more inclined than the first slope 121s1 with respect to the upper surface 121at of the first electrode pattern 121a. Furthermore, the second slope 121s2 can be less inclined than the first slope 121s1 with respect to the lower surface of the first electrode pattern 121a.

[0157] Preferably, the internal angle between the upper surface 121at of the first electrode pattern 121a and the second slope 121s2 can be less than the internal angle between the upper surface 121at and the first slope 121s1. Preferably, the internal angle between the upper surface 121at of the first electrode pattern 121a and the second slope 121s2 can be close to 90 degrees.

[0158] An inner angle between the upper surface 121at of the first electrode pattern 121a and the second slope 121s2 can be in a range of 80 degrees to 100 degrees. Preferably, the inner angle between the upper surface 121at of the first electrode pattern 121a and the second slope 121s2 can be in a range of 82 degrees to 98 degrees. More preferably, the inner angle between the upper surface 121at of the first electrode pattern 121a and the second slope 121s2 can be in a range of 85 degrees to 95 degrees. When the inner angle between the upper surface 121at of the first electrode pattern 121a and the second slope 121s2 exceeds the range of 80 degrees to 100 degrees, a difference between the width of the upper surface 121at and the lower surface of the first electrode pattern 121a can increase, and thus, a signal transmission characteristic can be degraded as a signal transmission loss increases.

[0159] The first slope 121s1 and the second slope 121s2 of the first electrode pattern 121a can be provided in a process of plating the bump portion 140 on the first electrode pattern 121a and removing the seed layer of the first electrode pattern 121a and the bump portion 140.

[0160] The first protective layer 150 can be in contact with the first slope 121s1 of the first electrode pattern 121a. For example, the first protective layer 150 can include a first portion 150a disposed on the insulating layer 110. In addition, the first protective layer 150 can include a second portion 150b extending downward from the first portion 150a and in contact with the first slope 121s1 of the first electrode pattern 121a. The second portion 150b is in contact with the first slope 121s1 of the first electrode pattern 121a, and thus, adhesion between the first protective layer 150 and the first electrode pattern 121a can be further improved.

[0161] Figure 5 is a cross-sectional view illustrating a circuit board according to a third embodiment. In the circuit board of the third embodiment, a height of an upper surface of the insulating layer 110 can be different from that of the circuit board of the second embodiment.

[0162] Referring to Figure 5 , the upper surface 110T of the insulating layer 110 can have a step difference with an upper surface of the wiring layer 121. For example, the upper surface 110T of the insulating layer 110 can have a step difference with an upper surface of the first electrode pattern 121a of the wiring layer 121. For example, the upper surface of the insulating layer 110 can have a step difference with an upper surface of the second electrode pattern 121b of the wiring layer 121.

[0163] For example, the upper surface 110T of the insulating layer 110 can be lower than the upper surface of the wiring layer 121 by a predetermined height T. This can be achieved by performing a process of thinning the thickness of the insulating layer 110 after a process of forming the bump portion 140. That is, the embodiments can perform a process of thinning the thickness of the upper surface 110T of the insulating layer 110. Accordingly, the embodiments can prevent the seed layer of the wiring layer 121 and / or the bump portion 140 from remaining on the upper surface 110T of the insulating layer 110 and solve an electrical reliability problem that can occur due to the remaining of the seed layer.

[0164] Figure 6 A semiconductor package including the circuit board of FIG. 1 is illustrated.

[0165] Reference Figure 6 The semiconductor package includes the circuit board of FIG. 1.

[0166] In addition, the semiconductor package includes a connection portion 310 disposed on the bump portion 140 of the circuit board. The connection portion 310 electrically connects the terminal 325 of the semiconductor device 320 and the bump portion 140.

[0167] The connection portion 310 can use at least one of a wire bonding, a solder bonding, and an intermetallic direct bonding.

[0168] The wire bonding method denotes electrically connecting the bump portion 140 and the terminal 325 of the semiconductor device 320 using a wire such as gold (Au).

[0169] The solder bonding method electrically connects the electrode portion of the substrate 100 and the terminal 325 of the semiconductor device 320 using a material including at least one of Sn, Ag, and Cu.

[0170] The intermetallic direct bonding method denotes directly coupling the bump portion 140 and the terminal 325 of the semiconductor device 320 by applying heat and pressure between the bump portion 140 and the terminal 325 of the semiconductor device 320 without a member such as solder, a wire, or a conductive adhesive. In this case, the connection portion 310 can refer to a metal layer between the bump portion 140 and the terminal 325 of the semiconductor device 320 provided by recrystallization.

[0171] For example, the connection portion 310 can electrically connect the bump portion 140 to the terminal 325 of the semiconductor device 320 by a thermal compression bonding method. The thermal compression bonding method can reduce the volume of the connection portion 310 and prevent short circuits between a plurality of adjacent connection portions. Accordingly, the thermal compression bonding method can be advantageous when the terminal 325 of the semiconductor device 320 and / or the bump portion 140 have a fine pitch.

[0172] In addition, the semiconductor package can include a semiconductor device 320 disposed on the connection part 310. The type of the semiconductor device 320 has been described previously, and thus a detailed description thereof will be omitted.

[0173] The semiconductor package can further include a molding member 330 molding the semiconductor device 320. The molding member 330 can mold the semiconductor device 320 and the connection part 310. In this case, a lower surface of the molding member 330 includes a convex surface. For example, the lower surface of the molding member 330 includes a convex surface in contact with an upper surface of the first protective layer 150. Accordingly, a contact area between the molding member 330 and the first protective layer 150 can be increased, and thus a coupling strength between the molding member 330 and the first protective layer 150 can be improved.

[0174] Figure 7 A semiconductor package according to a second embodiment is illustrated.

[0175] Reference Figure 7 In the semiconductor package, the connection member 200 can be embedded in a circuit board, a plurality of semiconductor devices can be disposed on the circuit board and spaced apart from each other in a horizontal direction, compared to the semiconductor package of Figure 6

[0176] The semiconductor package includes the connection member 200 embedded in a circuit board. The connection member 200 can be a die.

[0177] The connection member 200 according to the embodiment can be a bridge die. For example, the connection member 200 partially overlaps the semiconductor devices 320a and 320b in a vertical direction. The connection member 200 electrically connects a portion of the terminal 325a of the first semiconductor device 320a to a portion of the terminal 325b of the second semiconductor device 320b.

[0178] Small chip (Chiplet) units of semiconductor devices divided according to functions and / or pitches or a plurality of semiconductor devices 320a and 320b having different functions, such as a CPU and a GPU, a GPU and an HBM, can be mounted on a circuit board, and the connection member 200 can be used to horizontally connect and electrically connect them.

[0179] ​In an embodiment, the connection member 200 can be an inorganic bridge. For example, the connection member 200 can be a silicon bridge. The connection member 200 can include a silicon substrate and a redistribution layer. For example, the connection member 200 can include the same material as the semiconductor devices 320a and 320b. When the connection member 200 is an inorganic bridge, the pads respectively disposed on the upper and lower surfaces of the connection member 200 can be electrically connected by a TSV (Through Silicon Via). However, embodiments are not limited thereto, and when the connection member 200 is an inorganic bridge, the connection member 200 can not include a TSV, and the pads of the connection member 200 can be disposed only on the upper surface of the connection member 200.

[0180] In another embodiment, the connection member 200 is an organic bridge. For example, the connection member 200 can include an organic material. The connection member 200 can include an organic substrate in which a silicon substrate of an inorganic bridge is replaced with an organic material. In this case, the organic material can include a photocurable resin or a thermosetting resin. When the connection member 200 is an organic bridge, the pads respectively disposed on the upper and lower surfaces of the connection member 200 can be electrically connected to each other by a through electrode passing through the connection member 200. However, embodiments are not limited thereto, and the pads of the connection member 200 can be disposed only on the upper surface of the connection member 200.

[0181] The connection member 200 includes a pad portion 210. The pad portion 210 of the connection member 200 is connected to the lower surface of the first electrode pattern 121a of the wiring layer 121. To this end, an adhesive member 220 can also be disposed between the pad portion 210 and the first electrode pattern 121a.

[0182] In this case, the bump portions 140 disposed on the circuit board can include a first group of bumps that do not overlap the connection member 200 in the vertical direction and a second group of bumps that overlap the connection member 200 in the vertical direction.

[0183] In this case, the first group of bumps can not depend on the width and / or pitch of the pad portion 210 disposed in the connection member 200, and thus can be spaced apart from each other at a greater horizontal distance than the second group of bumps. In addition, the second group of bumps can depend on the width and / or pitch of the pad portion 210 disposed in the connection member 200, and thus the second group of bumps can be spaced apart from each other at a smaller horizontal distance than the first group of bumps.

[0184] Accordingly, a first portion 150T1 of the concave surface provided in the first protective layer 150 can not be vertically overlapped with the connection member 200, and a second portion 150T2 of the concave surface can be vertically overlapped with the connection member 200. Accordingly, in an embodiment, the second portion 150T2 of the concave surface is provided in an area vertically overlapped with the connection member 200, thereby reducing a horizontal distance between the plurality of bumps and effectively preventing electrical short-circuit of the connection portions provided on each of the plurality of bumps.

[0185] Figures 8 to 17 is a cross-sectional view illustrating a method of manufacturing the circuit board of FIG. 1 in a process order.

[0186] Referring to Figure 8 , in an embodiment, an insulating member, which is a basis for manufacturing a circuit board, can be prepared. The insulating member can be a carrier board. For example, the insulating member can include a carrier insulating layer CB1 and a carrier metal layer CB2. The insulating member can be a copper clad laminate (CCL).

[0187] Referring to Figure 9 , an embodiment can perform a process of forming a wiring electrode under the carrier metal layer CB2 of the insulating member. For example, an embodiment can perform a process of forming a first electrode pattern 121a and a second electrode pattern 121b of a wiring layer 121 under the carrier metal layer CB2. The wiring layer 121 can be formed by electroplating the carrier metal layer CB2 as a seed layer.

[0188] Referring to Figure 10 , an embodiment can perform a process of forming an insulating layer 110 under the carrier metal layer CB2. For example, an embodiment can perform a process of forming the insulating layer 110 to cover the wiring layer 121 under the carrier metal layer CB2.

[0189] Referring to Figure 11 , an embodiment can perform a process of forming a via hole TH by processing the insulating layer 110.

[0190] Referring to Figure 12 , an embodiment can perform a process of forming a via electrode 130 filling the via hole TH and a wiring electrode 120 under the via electrode 130. Next, an embodiment can perform a process of manufacturing a circuit board having a multilayer structure by repeating the processes of Figures 10 to 12 .

[0191] Referring to Figure 13 , an embodiment can perform a process of separating and removing the carrier insulating layer CB1 from the insulating member.

[0192] Referring to Figure 14When the formation of the bump portion 140 is completed, the embodiments can perform a process of removing the carrier metal layer CB2.

[0193] Referring to Figure 15 When the formation of the bump portion 140 is completed, the embodiments can perform a process of removing the carrier metal layer CB2.

[0194] Referring to Figure 16 In the embodiments, a vacuum lamination process can be performed after the first protective layer 150 is placed on the insulating layer 110 and the bump portion 140.

[0195] Referring to Figure 17 Through the vacuum lamination process, the embodiments can form the first protective layer 150 including the first portion 150T1 of the concave surface and the second portion 150T2 of the concave surface, and the first protective layer 150 can have a through hole through which the bump portion 140 passes. In addition, the embodiments can perform a process of forming the second protective layer 160 on the lower surface of the insulating layer 110.

[0196] On the other hand, when the circuit board having the above-described characteristics of the present application is used for an IT device or a home appliance such as a smart phone, a server computer, a TV, etc., a function such as signal transmission or power supply can be stably performed. For example, when the circuit board having the characteristics of the present application performs a semiconductor packaging function, it can be used to safely protect a semiconductor chip from external moisture or contaminants, or alternatively, can solve the problems of leakage current, electrical short between terminals, and electrical disconnection of terminals provided to the semiconductor chip. In addition, when responsible for a signal transmission function, a noise problem can be solved. Thereby, the circuit board having the above-described characteristics of the present application can maintain a stable function of the IT device or the home appliance, so that the entire product and the circuit board to which the present application is applied can achieve functional consistency or technical interlocking with each other.

[0197] When the circuit board having the above-described characteristics of the present application is used for a transport device such as a vehicle, a problem of signal distortion transmitted to the transport device can be solved, or alternatively, the safety of the transport device can be further improved by safely protecting a semiconductor chip that controls the transport device from external influences and solving the problems of leakage current or electrical short between terminals or electrical disconnection of terminals provided to the semiconductor chip. Therefore, the transport device and the circuit board to which the present application is applied can achieve functional integrity or technical interlocking with each other.

[0198] The features, structures, effects, etc. described in the above-described embodiments include those in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. shown in each embodiment can be combined or modified by those of ordinary skill in the art to which the embodiments belong, for other embodiments. Therefore, what is related to such combinations and changes should be interpreted as included in the scope of the embodiments.

[0199] In the above, the embodiments have been mainly described, but this is only an example and does not limit the embodiments, and those of ordinary skill in the art to which the embodiments belong will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be implemented by modification, and the differences related to these modifications and applications should be interpreted as included in the scope of the embodiments set forth in the appended claims.

Claims

1. A circuit board, comprising: Insulating layer; A protective layer disposed on the insulating layer; and The protrusion portion passing through the protective layer, The upper surface of the protective layer has a concave surface that is recessed toward the lower surface of the protective layer. The thickness of the protective layer at the lowest point of the concave surface is half or less than the thickness of the protruding portion.

2. The circuit board according to claim 1, wherein, The bump portion includes multiple bumps. The concave surface is disposed between the plurality of protrusions.

3. The circuit board according to claim 2, wherein, The concave surface includes a first portion disposed between a plurality of protrusions spaced apart by a first horizontal distance, and a second portion disposed between a plurality of protrusions spaced apart by a second horizontal distance different from the first horizontal distance. The first part and the second part have different curvatures.

4. The circuit board according to claim 3, wherein, The first portion includes a curved surface recessed from the upper surface of the protective layer toward the lower surface of the protective layer and a plane extending from the curved surface. Wherein, the thickness of the protective layer at the lowest end of the concave surface is the thickness of the protective layer at the plane of the first portion.

5. The circuit board according to claim 4, wherein, The first horizontal distance is greater than the second horizontal distance. The second part includes a curved surface recessed from the upper surface of the protective layer toward the lower surface of the protective layer and does not include a flat surface. The thickness of the protective layer at the lowest point of the concave surface is the same as the thickness of the protective layer at the lowest point of the curved surface in the second part.

6. The circuit board according to claim 1, wherein, The height of the uppermost part of the protective layer is less than or equal to the height of the upper surface of the protrusion portion.

7. The circuit board according to claim 3, further comprising: Wiring electrodes disposed in the recesses on the upper surface of the insulating layer. The wiring electrode includes a first electrode pattern that overlaps with the bump portion in the vertical direction and a second electrode pattern that does not overlap with the bump portion in the vertical direction.

8. The circuit board according to claim 7, wherein, The first portion of the concave surface overlaps with the second electrode pattern in the vertical direction.

9. The circuit board according to claim 7, wherein, Each of the first and second portions of the concave surface overlaps with the second electrode pattern in the vertical direction. The number of second electrode patterns that overlap with the first portion in the vertical direction is greater than the number of second electrode patterns that overlap with the second portion in the vertical direction.

10. The circuit board according to claim 7, wherein, At least a portion of the curved surface of each of the first and second portions overlaps with the first electrode pattern in the vertical direction.

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