Planar multistage semiconductor refrigeration device and preparation method thereof

Abstract

The invention discloses a planar multistage semiconductor refrigeration device and a preparation method, the device comprises a substrate, the upper part of the substrate is provided with a layer of supporting film, the upper part of the supporting film is provided with an electrode pressure welding block, one end of the electrode pressure welding block is electrically connected with a device refrigeration unit, and two ends of a thermocouple pair are a cold end and a hot end of the device refrigeration unit. An isolation cavity is formed in the device refrigeration unit, an isothermal structure is arranged on the supporting film in the cold end of the device refrigeration unit and is in insulated connection with the cold end of the device refrigeration unit, and protective films are arranged on the upper surface of the whole planar multistage semiconductor refrigeration device except the electrode pressure welding block and the isothermal structure. And the substrate corresponding to the lower part of the supporting film of the device refrigeration unit is provided with a back cavity structure. Under the room temperature condition and the ideal condition of the cold end temperature, the low-temperature cooling device can reach-60 DEG C, and the low-temperature cooling requirement of chip-level small electronic equipment is met.

Description

Technical Field

[0001] This invention relates to a micro-semiconductor cooling device and its fabrication method, and more particularly to a planar multi-stage semiconductor cooling device and its fabrication method, belonging to the field of semiconductor devices. Background Technology

[0002] As the performance of electronic products continues to improve, heat dissipation in chip packaging has gradually become a key factor restricting their performance. This problem not only reduces the performance of electronic devices but also shortens their lifespan, seriously affecting the reliability and user experience of electronic products. To solve this problem, thin-film semiconductor cooling devices based on the Peltier effect are considered a promising solution due to their advantages such as miniaturization, high reliability, vibration-free or noiseless operation, and fast response speed, and can meet the heat dissipation requirements of high-performance chips.

[0003] Currently, there are two main types of thermoelectric coolers: vertical thermoelectric coolers and planar thermoelectric coolers. Vertical thermoelectric coolers can directly pump heat from hot spots to heat sinks across a plane, offering the advantage of high cooling density. However, due to their high power consumption and poor heat dissipation, the high cooling density of vertical thermoelectric coolers is often offset by reverse heat flow, resulting in limited practical effect on hot spot cooling. In contrast, planar thermoelectric coolers can spread heat from localized hot spots to a wider planar area. Although their cooling density is not as high as that of vertical thermoelectric coolers, the planar configuration can suppress instantaneous peak temperatures of hot spots and increase the area of ​​the heat sink, providing greater flexibility for integrated thermal management solutions. Furthermore, planar thermoelectric coolers can be mass-produced using traditional MEMS microfabrication processes, thus playing an important role in small electronic devices and chip temperature control.

[0004] Despite this, the cooling efficiency of existing planar thermocouple cooling devices is limited by the thermal conductivity of the thermocouple support materials. Support materials such as silicon, silicon oxide, and silicon nitride, due to their high thermal conductivity, increase the heat transfer efficiency of the planar design and suppress the formation of large temperature differences across the thermocouple. The SiGe-based planar cooling chip developed by the Hong Kong University of Science and Technology achieves a maximum cooling temperature difference of 11.2℃ across its two stages. Furthermore, the poor thermal conductivity of the conductive components in planar thermocouple cooling chips makes it difficult to effectively transfer heat from the hot end to the cold end, limiting the increase in cooling temperature difference and affecting the application range of planar thermocouple cooling devices. Materials such as polyimide, polyester, and polydimethylsiloxane exhibit this problem in practical applications. To address this issue, Wuhan University of Technology simulated a multi-stage planar cooling chip using silicone grease as a conductive component, but the maximum temperature difference between the hot and cold ends was only 8.2℃.

[0005] In summary, existing planar semiconductor cooling devices have significant shortcomings in cooling performance and cannot meet the cooling requirements of chips and small electronic devices. The complexity of the conductive components and the low heat transfer efficiency make it difficult to dissipate heat at the hot end, making it difficult to achieve ideal cold end temperature and temperature difference between the hot and cold ends.

[0006] Therefore, it is necessary to design a planar multi-stage semiconductor cooling device to solve the above-mentioned technical problems. Summary of the Invention

[0007] Purpose of the invention: The purpose of this invention is to provide a planar multi-level semiconductor cooling device and its fabrication method. By synergistically designing to reduce the thermal conductivity of the support film and improve the thermal conductivity of the conductive components, the device's cooling performance is enhanced, meeting the cooling requirements of chips and small electronic devices.

[0008] Technical Solution: The planar multi-level semiconductor cooling device of the present invention includes a substrate, a support film on the upper part of the substrate, an electrode bonding block on the upper part of the support film, one end of the electrode bonding block being electrically connected to a device cooling unit, the device cooling unit forming a cold end and a hot end through a thermocouple pair, an isolation cavity inside the device cooling unit, an isothermal structure on the support film inside the cold end of the device cooling unit, the isothermal structure being insulated from the cold end of the device cooling unit, and a protective film on the upper surface of the entire planar multi-level semiconductor cooling device except for the electrode bonding block and the isothermal structure, and a back cavity structure corresponding to the lower part of the support film of the device cooling unit.

[0009] Furthermore, the number of cooling units in the device is two or more. When the device has multiple cooling units, each stage is connected in series, parallel, or with independent power supplies, with series connection being preferred. An isolation chamber is located between the cold and hot ends of each cooling unit. In a multi-stage device cooling unit, the hot end of the preceding cooling unit and the cold end of the following cooling unit are thermally connected via conductive components. Each cooling unit in the device cooling unit forms a cold and hot end at both ends of a thermocouple pair. The conductive components are made of a material with an electrical conductivity greater than 1×10⁻⁶. 7 The thermal conductivity is greater than 90 W / (mK), and the thickness of the conductive component is 100 nm - 2 μm. The conductive component is preferably made of a metallic material, which can be selected from any one or more combinations of copper, gold, silver, aluminum, chromium, and nickel, with a copper-nickel alloy being preferred. The thickness of the conductive component is 1 μm.

[0010] Furthermore, the thermocouple pair is made of thermoelectric material, such as bismuth telluride-based, lead telluride-based, and silicon-germanium alloy thermoelectric materials; bismuth telluride-based thermoelectric materials are preferred. There are multiple thermocouple pairs, each consisting of a pair of N-type thermoelectric arms and a pair of P-type thermoelectric arms. The N-type and P-type thermoelectric arms are arranged alternately to form multiple thermocouple pairs. The thermoelectric arms are electrically connected by wires to form a π-type thermocouple. The material of the N-type thermoelectric arm is Bi₂Te. 2.7 Se 0.3 The material of the P-type thermoelectric arm is Bi. 0.5 Sb 1.5 Te3. The thermocouple thickness is 1 μm.

[0011] The substrate includes a Si substrate with a SiO2 barrier layer on top. The Si substrate and the SiO2 barrier layer together constitute the substrate. The support film and the protective film are made of polyimide (PI), with the support film having a thickness of 4 μm and the protective film having a thickness of 2 μm.

[0012] A method for fabricating a planar multi-stage semiconductor cooling device according to the present invention includes the following steps:

[0013] (1) A PI film is formed on the front side of the substrate as a support film by spin coating and thermal curing process, and the support film is patterned by photolithography and reactive ion etching process;

[0014] (2) The cold end and hot end of the device cooling unit, as well as the conductive components, isothermal structure and electrode bonding block, are prepared on the surface of the patterned support film by photolithography, sputtering and lift-off processes. Similarly, the N-type thermoelectric arm and the P-type thermoelectric arm are prepared by photolithography, sputtering and lift-off processes.

[0015] (3) A PI film is prepared on the surface of the device by spin coating and thermal curing process, and a protective film 7 is formed by photolithography and reactive ion etching process;

[0016] (4) The back cavity structure is prepared on the back side of the substrate by photolithography, deep reactive ion etching and wet etching processes.

[0017] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0018] (1) The planar semiconductor cooling device of the present invention uses PI material with poor thermal conductivity as the support film and protective film, which reduces most of the heat loss compared with other materials with better thermal conductivity. An isolation cavity is set between the cold end and the hot end of the device cooling unit, which effectively increases the temperature difference between the cold and hot ends and reduces the temperature of the cold end. At the same time, PI material has good toughness, which makes the cooling device have strong vibration resistance and is not easily damaged.

[0019] (2) This invention uses a highly thermally conductive metal as the conductive component of the cooling unit, effectively solving the limitation of poor heat transfer performance between cooling units in planar multi-stage semiconductor cooling devices. The highly thermally conductive component can transfer heat between multi-stage cooling units, significantly improving the cooling effect of semiconductor devices. Under ideal conditions, the cold end temperature can reach -60 ℃ at room temperature, meeting the low-temperature cooling requirements of chip-level small electronic devices.

[0020] (3) In terms of design, the cold and hot ends of the conductive components and multi-stage refrigeration units also function as metal leads, connecting thermocouples to form an electrical circuit and realizing heat transfer between refrigeration units. In addition, the implementation of the cold and hot ends of the conductive components and multi-stage refrigeration units does not require additional process steps, but only requires appropriately increasing the lead area during the design, which simplifies the process flow. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the planar multi-stage semiconductor cooling device structure in Example 1 (the protective film is not shown here for ease of understanding).

[0022] Figure 2 This is a cross-sectional view of the planar multi-stage semiconductor cooling device in Example 1 (the protective film is not shown here for ease of understanding).

[0023] Figure 3 This is a schematic diagram of the three-dimensional structure of the planar multi-stage semiconductor cooling device in Example 1;

[0024] In the diagram: 1. Substrate; 11. Si substrate; 12. SiO2 barrier layer; 2. Support film; 3. Conductive component; 4. Isothermal structure; 5. Three-stage device cooling unit; 51. First-stage cooling unit; 511. Cold end of first-stage cooling unit / device cold end; 512. Hot end of first-stage cooling unit; 52. Second-stage cooling unit; 521. Cold end of second-stage cooling unit; 522. Hot end of second-stage cooling unit; 53. Third-stage cooling unit; 531. Cold end of third-stage cooling unit; 532. Hot end of third-stage cooling unit / device hot end; 54. Thermocouple pair; 541. N-type thermocouple arm; 542. P-type thermocouple arm; 55. Quaternary cooling unit; 551. Cold end of fourth-stage cooling unit; 552. Hot end of fourth-stage cooling unit; 6. Electrode bonding block; 7. Protective film; 8. Isolation cavity; 9. Back cavity;

[0025] Figure 4 This is a cross-sectional view of the structure in the first step of the preparation method in Example 1;

[0026] Figure 5 This is a cross-sectional view of the structure in the second step of the preparation method in Example 1;

[0027] Figure 6 This is a cross-sectional view of the structure in the third step of the preparation method in Example 1;

[0028] Figure 7 This is a cross-sectional view of the structure in the fourth step of the preparation method in Example 1;

[0029] Figure 8 This is a cross-sectional view of the structure in the fifth step of the preparation method in Example 1;

[0030] Figure 9 This is a cross-sectional view of the structure in step six of the preparation method in Example 1;

[0031] Figure 10 This is a cross-sectional view of the structure in step seven of the preparation method in Example 1;

[0032] Figure 11 This is a temperature isosurface plot of the cooling effect of the device in Example 2;

[0033] Figure 12 This is a simulation diagram of the cooling effect of the device in Example 2;

[0034] Figure 13 This is a magnified simulation diagram of the cold-end cooling effect in Example 2;

[0035] Figure 14 This is a temperature curve of the cold junction under different currents in Example 2;

[0036] Figure 15 This is a schematic diagram of the planar primary semiconductor cooling device structure in Example 3 (the protective film is not shown here for ease of understanding).

[0037] Figure 16 This is a temperature curve of the cold end of the planar primary semiconductor refrigeration device under different currents in Example 3;

[0038] Figure 17 This is a schematic diagram of the planar secondary semiconductor cooling device structure in Example 4 (the protective film is not shown here for ease of understanding).

[0039] Figure 18 This is a temperature curve of the cold end of the planar secondary semiconductor refrigeration device under different currents in Example 4;

[0040] Figure 19 This is a schematic diagram of the planar four-stage semiconductor cooling device structure in Example 5 (the protective film is not shown here for ease of understanding).

[0041] Figure 20 This is a temperature curve of the cold end of the planar four-stage semiconductor refrigeration device under different currents in Example 5. Detailed Implementation

[0042] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0043] Example 1

[0044] like Figure 1-3 As shown, the planar multi-stage semiconductor cooling device of the present invention includes a substrate 1. A support film 2 and an electrode bonding block 6 are sequentially disposed on the upper part of the substrate 1. The electrode bonding block 6 is used to connect an external power supply to the planar multi-stage semiconductor cooling device to provide operating voltage / current. One end of the electrode bonding block 6 is electrically connected to a three-stage device cooling unit 5, wherein the three-stage device cooling unit 5 consists of a first-stage cooling unit 51, a second-stage cooling unit 52, and a third-stage cooling unit 53 (e.g., from the inside out). Figure 1 As shown, the three-stage cooling unit 53 is identified by two blue boxes in the figure (located within the two blue boxes). Each cooling unit has an isolation cavity 8 inside, and adjacent cooling units are thermally coupled through conductive components 3. An isothermal structure 4 is provided on the support film 2 inside the cold end of the first-stage cooling unit 51, and the isothermal structure 4 is electrically insulated from the cold end of the first-stage cooling unit 51. Except for the electrode bonding block 6 and the isothermal structure 4, the upper surface of the entire planar semiconductor cooling device is covered with a protective film 7. A window is opened on the back side of the substrate 1 and etched to form a back cavity structure 9 (e.g., Figure 1 As shown, the back cavity structure 9 (identified by a red frame in the figure) is arranged in the cold ends and thermocouple pairs of the primary cooling unit 51, secondary cooling unit 52, and tertiary cooling unit 53, as well as the hot end regions of the primary cooling unit 51 and secondary cooling unit 52, within the corresponding device cooling unit 5. This arrangement positions the devices in these regions above the support film 2, while the substrate 1 is retained in the region corresponding to the hot end of the tertiary cooling unit 53 to provide mechanical support and a heat diffusion channel. Thus, the device cooling unit 5 is positioned above the support film 2, and the back cavity structure 9 is a partially substrate-removed structure formed through a process. The support film 2 and the protective film 7 are preferably PI films.

[0045] The substrate 1 consists of a Si substrate 11 and an SiO2 barrier layer 12 above it. The primary refrigeration unit 51, the secondary refrigeration unit 52, and the tertiary refrigeration unit 53 are each composed of several thermocouple pairs 54. Each thermocouple pair 54 consists of an N-type thermocouple arm 541 and a P-type thermocouple arm 542, connected by a large-area metal junction region at both ends. When current is applied, based on the Peltier effect, this metal junction region acts as the cold end (511, 521, 531) and the hot end (512, 522, 532) of that stage. Therefore, the cold or hot end is a functional region generated on the junction region after the thermocouple is energized, and is not an independent heating or cooling element. Within the same refrigeration unit, adjacent thermocouple arms are electrically connected in series through the metal junction region, forming a π-type thermocouple pair 54. These metal junction regions, while acting as electrical connecting wires, also constitute the interface for thermal exchange between the various stages of the refrigeration unit. Dielectric isolation structures (such as insulating gaps, dielectric layers, etc.) are provided between the hot end 512 of the primary cooling unit 51 and the cold end 521 of the secondary cooling unit 52, as well as between the hot end 522 of the secondary cooling unit 52 and the cold end 531 of the tertiary cooling unit 53, to prevent electrical short circuits while maintaining the electrical circuit and thermal conductivity provided by the aforementioned conductive component 3. For the sake of terminology consistency, the cold end of the entire device is defined as the cold end 511 of the primary cooling unit 51, and the hot end of the entire device is defined as the hot end 532 of the tertiary cooling unit 53.

[0046] In this embodiment, the primary refrigeration unit 51, the secondary refrigeration unit 52, and the tertiary refrigeration unit 53 are all provided with an isolation cavity 8. The isolation cavity 8 is located inside the primary refrigeration unit 51, the secondary refrigeration unit 52, and the tertiary refrigeration unit 53, specifically in the area between the cold end and the hot end of that stage, excluding the thermocouple pair 54. It is formed by removing the support film 2 and its protective film 7 material from this area. The isolation cavity 8 is used to block non-primary heat transfer paths between the cold end and the hot end, except for the thermocouple pair 54, thereby effectively suppressing parasitic heat flow and heat loss caused by structures such as the support film. This structure constrains heat transfer and mainly proceeds along the preset direction of the thermocouple pair 54, which helps to increase the temperature difference between the cold and hot ends of each refrigeration unit and improve the thermoelectric conversion efficiency. At the same time, the back cavity structure 9 further reduces heat loss generated by heat transfer, such as... Figure 2 As shown.

[0047] In this embodiment, the thermocouple pair 54 can be made of thermoelectric materials such as bismuth telluride-based, lead telluride-based, or silicon-germanium alloy. Since bismuth telluride-based thermoelectric materials are suitable for low-temperature regions (200-300 K), lead telluride-based thermoelectric materials are suitable for medium-temperature regions (300-500 K), and silicon-germanium alloys are suitable for high-temperature regions (500-900 K), and the application scenario of the semiconductor refrigeration device of this invention is room temperature, bismuth telluride-based thermoelectric materials are used as the thermocouple material. The conductive component 3 is made of a material with high electrical conductivity (greater than 1×10⁻⁶). 7Made of metal materials with high thermal conductivity (greater than 90 W / (mK)) and S / m, which can be selected from any one or more combinations of copper, gold, silver, aluminum, chromium and nickel.

[0048] Because the supporting film 2 has low thermal conductivity, it will create significant thermal resistance between the hot end 512 of the first-stage refrigeration unit 51 and the cold end 521 of the second-stage refrigeration unit 52, and between the hot end 522 of the second-stage refrigeration unit 52 and the cold end 531 of the third-stage refrigeration unit 53, hindering the effective transfer of heat between stages. To solve this problem, this embodiment uses a conductive component 3 to connect the hot end 512 of the first-stage refrigeration unit 51 and the cold end 521 of the second-stage refrigeration unit 52, and between the hot end 522 of the second-stage refrigeration unit 52 and the cold end 531 of the third-stage refrigeration unit 53. This conductive component 3 utilizes its excellent thermal conductivity to establish an efficient heat flow channel between stages, ensuring smooth heat transfer and thus significantly improving the cooling effect of the device. Meanwhile, to prevent electrical short circuits between adjacent stages of the primary cooling unit 51, secondary cooling unit 52, and tertiary cooling unit 53, dielectric isolation structures (such as gaps) are provided at the corresponding interfaces of the hot end 512 of the primary cooling unit 51 and the cold end 521 of the secondary cooling unit 52, and the hot end 522 of the secondary cooling unit 52 and the cold end 531 of the tertiary cooling unit 53, forming electrical insulation. Furthermore, to address the problem of localized temperature unevenness caused by the poor thermal conductivity of the support film 2, an isothermal structure 4 is provided on the surface of the cold end 511 of the primary cooling unit 51. This isothermal structure 4 has good thermal conductivity, which can promote the homogenization of the cold end temperature field, thereby improving the overall cooling performance and stability of the device. The isothermal structure 4 and the cold end 511 of the primary cooling unit 51 are insulated from each other to avoid forming electrical short circuits. In terms of structural design, the first-stage refrigeration unit 51, the second-stage refrigeration unit 52 and the third-stage refrigeration unit 53 all use large-area metal layers as their cold ends (511, 521, 531) and hot ends (512, 522, 532) respectively, and keep a small distance between the cold ends and hot ends inside each stage. This design helps to concentrate the heat flow path and improve the heat pumping rate of the thermocouple to 54.

[0049] The planar multi-stage semiconductor cooling device of the present invention uses a PI film as the support film 2 and the protective film 7. The support film 2, located below the thermocouple pair 54, utilizes its low thermal conductivity to significantly reduce parasitic heat flow and longitudinal heat leakage from the cold end to the hot end within the cooling unit, thereby effectively increasing the temperature difference between the cold and hot ends and ultimately achieving a further reduction in the temperature of the cold end 511 of the first-stage cooling unit 51. Furthermore, the use of a PI film aligns with the requirements of MEMS microfabrication processes, facilitating mass production of the device. Additionally, the PI film material itself possesses good mechanical toughness, endowing the cooling device with excellent vibration and impact resistance.

[0050] The thickness of the support film 2 can be 0.5-15 μm, preferably 2-8 μm, and more preferably 3-5 μm. This is a balance between film uniformity, structural mechanical strength, and minimizing parasitic heat leakage in MEMS microfabrication processes. The thickness of the protective film 7 is also not limited and can be 0.1-5 μm. It is mainly used for surface passivation, anti-oxidation, and mechanical protection, and does not bear mechanical support. Therefore, a smaller thickness can be adopted under the premise of meeting the requirements of film formation and insulation.

[0051] The fabrication method of the above-mentioned planar multi-stage semiconductor cooling device includes the following steps:

[0052] Step 1: As Figure 4 As shown, a SiO2 barrier layer 12 is prepared on the upper surface of the Si substrate 11 by vapor deposition or thermal oxidation process;

[0053] The second step, as Figure 5 As shown, a PI film is prepared on the SiO2 barrier layer 12 as a support film 2 by spin coating and thermosetting process;

[0054] Step 3: As Figure 6 As shown, the support film 2 is patterned on the PI film using photolithography and reactive ion etching processes;

[0055] Step 4: As Figure 7 As shown, conductive components 3, isothermal structures 4, electrode bonding blocks 6, and cold ends (511, 521, 531) and hot ends (512, 522, 532) of primary cooling units 51, secondary cooling units 52, and tertiary cooling units 53 are simultaneously fabricated on the surface of patterned support film 2 using photolithography, sputtering, and lift-off processes.

[0056] Step 5: As Figure 8 As shown, N-type thermoelectric arms 541 and P-type thermoelectric arms 542 of primary cooling unit 51, secondary cooling unit 52 and tertiary cooling unit 53 are successively prepared on the support film 2 using photolithography, sputtering and lift-off processes, wherein N-type thermoelectric arms 541 and P-type thermoelectric arms 542 are arranged alternately.

[0057] Step 6: As Figure 9 As shown, a PI film is prepared on the device surface using spin coating and thermal curing processes, and the protective film 7 is patterned using photolithography and reactive ion etching processes;

[0058] Step 7: As Figure 10 As shown, a back cavity structure 9 is fabricated on the lower surface of the Si substrate 11 using photolithography, deep reactive ion etching, and wet etching processes to release the thermocouple pair 54 and the support film 2, thus completing the fabrication of the device.

[0059] The specific usage method of the above-mentioned planar multi-stage semiconductor cooling device is as follows: First, the electrode bonding block 6 is connected to the external test circuit using pressure bonding technology. Next, voltage or current is applied to the device. At this time, the thermocouple pair 54 simultaneously pumps the heat from the cold ends (511, 521, 531) of the first-stage cooling unit 51, the second-stage cooling unit 52, and the third-stage cooling unit 53 to the hot ends (512, 522, 532) of the first-stage cooling unit 51, the second-stage cooling unit 52, and the third-stage cooling unit 53, respectively. A temperature difference is generated on both sides of the thermocouple pair 54, such as... Figure 11 As shown, heat is transferred sequentially between each cooling unit of the planar multi-stage semiconductor refrigeration device, level by level, to the hot end 532 of the highest-level cooler, i.e., the hot end of the refrigeration device. Since the hot end 532 is connected to the substrate 1, the heat pumped in the device can be effectively transferred to the substrate and then to the environment, thus creating a temperature difference within the planar multi-stage semiconductor refrigeration device. During use, the temperature distribution at various points on the device can be monitored in real time using a microscopic thermal imaging temperature measurement system. Furthermore, samples requiring experiments at low temperatures can be placed at the cold end of the device to observe the performance changes of the sample under the set low-temperature environment in real time, thereby enabling the study of the material's performance and behavior under low-temperature conditions.

[0060] Example 2

[0061] A planar multi-stage semiconductor cooling device was fabricated using the method described in Example 1. In this example, the thickness of the support film 2 is 4 μm, and the thickness of the protective film 7 is 2 μm. Since the application scenario of the semiconductor cooling device in this example is room temperature, bismuth telluride-based thermoelectric material is used as the material for thermocouple pair 54. The film thickness of N-type thermoelectric arm 541 and P-type thermoelectric arm 542 is 1 μm, which is the result of optimization between the cooling effect of the planar semiconductor cooling device and the MEMS process: if the thickness of this layer is less than 1 μm, the internal resistance of the device increases significantly, causing Joule heat to exceed the lateral heat dissipation capacity of the device, and the cooling efficiency decreases; if the thickness is greater than 1 μm, the magnetron sputtering deposition time increases linearly, and the brittle bismuth telluride-based ceramic target is prone to cracking under continuous high-energy bombardment, resulting in a sharp drop in target utilization and an increase in film defect density.

[0062] Since metals have high electrical and thermal conductivity, they can effectively reduce Joule losses and increase cooling output. They are also widely applicable to MEMS processes. Therefore, the conductive components are made of any one or more combinations of copper, gold, silver, aluminum, chromium, and nickel. In view of the fact that copper achieves the best compromise between thermal conductivity, process stability, and cost, copper is used as the material for the cold end (511, 521, 531) and hot end (512, 522, 532) of the first-stage cooling unit 51, the second-stage cooling unit 52, and the third-stage cooling unit 53. Since the cold ends (511, 521, 531) and hot ends (512, 522, 532) of the first-stage refrigeration unit 51, the second-stage refrigeration unit 52, and the third-stage refrigeration unit 53 are in direct contact with the thermocouple pair 54, and copper and bismuth telluride-based thermoelectric materials are prone to element diffusion leading to interface alloying, which may form a Cu-Te brittle phase, resulting in a surge in contact resistance, this embodiment sets a nickel metal as a barrier layer between the thermocouple pair 54 and the metallic copper. Since the cold ends (511, 521, 531) and hot ends (512, 522, 532) of the first-stage cooling unit 51, the second-stage cooling unit 52, and the third-stage cooling unit 53 are supported by a support film 2, a nickel metal layer is placed between the support film 2 and the copper metal as an adhesion layer to improve the adhesion between the support film 2 and the cold ends (511, 521, 531) and hot ends (512, 522, 532) of the first-stage cooling unit 51, the second-stage cooling unit 52, and the third-stage cooling unit 53. Therefore, the metal structure is Ni / Cu / Ni, and according to mature MEMS technology, the metal thickness is set to 50 nm / 1 μm / 50 nm.

[0063] Given that Ni / Cu / Ni material is selected to prepare the cold ends (511, 521, 531) and hot ends (512, 522, 532) of the first-stage refrigeration unit 51, the second-stage refrigeration unit 52, and the third-stage refrigeration unit 53, in order to simplify the process and avoid adding extra steps, this embodiment selects the same metal material Ni / Cu / Ni as the conductive component 3, the isothermal structure 4, and the electrode pressure welding block 6.

[0064] To verify the thermoelectric performance of the planar multi-stage semiconductor cooling device described in this embodiment, multi-physics coupled simulation was performed on the device using multi-physics finite element analysis software. The simulation geometric model was constructed based on the actual structure of the planar multi-stage semiconductor cooling device described in this embodiment, as follows: Figure 12 As shown, the model includes a Si substrate 11, a SiO2 barrier layer 12, a support film 2, a conductive component 3, an isothermal structure 4, a cold end 511 of a primary refrigeration unit 51, a hot end 512 of a primary refrigeration unit 51, a cold end 521 of a secondary refrigeration unit 52, a hot end 522 of a secondary refrigeration unit 52, a cold end 531 of a tertiary refrigeration unit 53, a hot end 532 of a tertiary refrigeration unit 53, and a thermocouple pair 54 structure.

[0065] Among them, the material of the support film 2 is set to PI film, and the materials of the conductive component 3, the isothermal structure 4, and the cold end 511, hot end 512, cold end 521, hot end 522, cold end 531, and hot end 532 of the first-stage refrigeration unit 51 are uniformly set to Ni / Cu / Ni metal multilayer structure; the material of the N-type thermocouple arm 541 in the thermocouple pair 54 is set to Bi2Te. 2.7 Se 0.3 The material of the P-type thermoelectric arm 542 is set to Bi. 0.5 Sb 1.5 Te3.

[0066] The current physical field module includes thermocouple pairs 54, conductive components 3, and the cold junction 511, hot junction 512, cold junction 521, hot junction 522, cold junction 531, and hot junction 532 of the first-stage refrigeration unit 51, forming a complete current loop. The hot junction 532 of the third-stage refrigeration unit 53, connected to the P-type thermocouple arm 541, is grounded; the hot junction 532 of the third-stage refrigeration unit 53, connected to the N-type thermocouple arm 542, is set as the input terminal (i.e., the end) of the current loop, achieving stable current input and output, thereby driving the thermocouple pairs 54 at each stage within the device to operate and form an effective refrigeration cycle.

[0067] In the solid heat transfer physics field of the multiphysics finite element simulation software, all solid structures are considered, and the initial temperature is uniformly set to room temperature (20 ℃). Except for the bottom surface of the Si substrate 11, the boundary conditions of the other surfaces in contact with the outside are set to adiabatic to simulate an ideal thermal insulation state. The bottom surface of the Si substrate 11 is set as a constant temperature boundary with a fixed temperature of 20 ℃ to simulate good heat dissipation conditions.

[0068] During the simulation, multiphysics coupling simulation was implemented, incorporating thermoelectric and electromagnetic thermal effects. Specifically, thermoelectric coupling was considered for thermocouple pair 54; Joule heating was considered for thermocouple pair 54, conductive component 3, and the cold and hot ends 511 and 512 of the first-stage refrigeration unit 51, the cold and hot ends 521 and 522 of the second-stage refrigeration unit 52, and the cold and hot ends 531 and 532 of the third-stage refrigeration unit 53. The multiphysics fields were solved by coupling the current physical field with the solid heat transfer physical field.

[0069] To optimize device performance while considering the feasibility of MEMS micro / nano fabrication processes, a parametric scan was performed on the length, width, height, and applied current of the thermocouple-54 structure. By comparing the cold junction temperature under different parameter combinations, the influence of different structural dimensions and driving conditions on the device's cooling capacity was analyzed. Based on this, the key geometric parameters and operating current range of the semiconductor cooling device in this embodiment were determined to achieve an optimized balance between structural performance and fabrication process. Simulation comparisons show that, under ideal conditions at room temperature, the cold junction temperature of this invention can reach -60°C. Figure 11-14 This meets the low-temperature cooling requirements of small chip-level electronic devices.

[0070] Example 3

[0071] like Figure 15 As shown, the preparation process is the same as in Example 2, except that the three-stage device cooling unit 5 is modified into a single-stage device cooling unit. Compared with the three-stage semiconductor cooling device in Example 2, the single-stage semiconductor cooling unit in this example simplifies the number of cooling units in its structure, retaining only a single-stage cooling unit. Therefore, the thermocouples of the semiconductor cooling device in this example consist of only a single-stage thermocouple pair. Compared with the three-stage semiconductor cooling device in Example 2, the single-stage semiconductor cooling device in this example does not have intermediate-stage thermocouple pairs, thus reducing the number of conductive components. The heat transfer between the cold and hot ends of the single-stage semiconductor cooling device is relatively simple, therefore its support film and protective film structure is more concise.

[0072] The simulation process is the same as in Example 2, and the simulation results are as follows: Figure 16 As shown in the figure. Simulation results indicate that, under the same environmental conditions, the lowest cold junction temperature of the primary semiconductor refrigeration device is -24°C. Compared to -60°C in the tertiary refrigeration device in Example 2, the temperature difference of the primary semiconductor refrigeration device is smaller. This is because the lack of additional refrigeration units results in a limited reduction in cold junction temperature, thus limiting the overall temperature regulation effect of the device.

[0073] Example 4

[0074] like Figure 17 As shown, the preparation process is the same as in Example 2, except that the tertiary device cooling unit 5 is modified to a secondary device cooling unit. Compared with the tertiary semiconductor refrigeration device in Example 2, the secondary semiconductor refrigeration device in this example includes a primary cooling unit and a secondary cooling unit, while omitting the tertiary cooling unit. Specifically, the secondary semiconductor refrigeration device adds a secondary thermocouple pair to the primary semiconductor refrigeration device. The hot end of the primary cooling unit is connected to the cold end of the secondary cooling unit through a conductive component, and the cold end of the primary cooling unit serves as the cold end of the device. Compared with the tertiary semiconductor refrigeration device, the secondary semiconductor refrigeration device reduces the tertiary cooling unit and its related connection structures, thus resulting in lower overall structural complexity.

[0075] The simulation process is the same as in Example 2, and the results are as follows: Figure 18 As shown in the figure. Simulation results show that, under the same environmental conditions, the lowest cold junction temperature of the secondary semiconductor refrigeration device in this embodiment is -52℃. Compared to -24℃ of the primary semiconductor refrigeration device, the secondary semiconductor refrigeration device exhibits better cooling performance in reducing the cold junction temperature, mainly due to the introduction of the secondary refrigeration unit. The temperature difference of the secondary semiconductor refrigeration device is increased, and its cooling effect is better than that of the primary semiconductor refrigeration device.

[0076] Example 5

[0077] like Figure 19 As shown, the preparation process is the same as in Example 2, except that the three-stage device cooling unit 5 is modified to a four-stage device cooling unit. Compared with the three-stage semiconductor refrigeration device in Example 2, the four-stage semiconductor refrigeration device in this example includes a first-stage cooling unit, a second-stage cooling unit, a third-stage cooling unit, and a fourth-stage cooling unit. Based on the three-stage semiconductor refrigeration device in Example 2, a fourth-stage cooling unit 55 is added (the cold end 551 and the hot end 552 of the fourth-stage cooling unit 55). Specifically, the hot end of the third-stage cooling unit of the four-stage semiconductor refrigeration device is connected to the hot end of the fourth-stage cooling unit through an additional conductive component. Compared with the three-stage semiconductor refrigeration device, the four-stage semiconductor refrigeration device adds four thermocouple pairs and corresponding cold and hot ends, making the connection more complex.

[0078] The simulation process is the same as in Example 2, and the results are as follows: Figure 20 As shown. Simulation results: The lowest cold junction temperature of the four-stage semiconductor refrigeration device in this embodiment is -53℃. Compared with the three-stage semiconductor refrigeration device in Embodiment 2, the cold junction temperature of the four-stage semiconductor refrigeration device in this embodiment is actually higher. This may be due to the increased internal resistance caused by the increase in the number of stages. This indicates that more stages are not necessarily better, and optimization is needed according to application requirements.

Claims

1. A planar multistage semiconductor refrigeration device, characterized by comprising: The substrate is provided with a support film on the upper part, and the support film is provided with an electrode pressure welding block on the upper part, and the electrode pressure welding block is electrically connected with a multi-stage device refrigeration unit at one end, and the device refrigeration unit forms a cold end and a hot end through a thermocouple pair, and the device refrigeration unit is provided with an isolation cavity inside, and the support film on the cold end of the device refrigeration unit is provided with an isothermal structure, and the isothermal structure is insulatedly connected with the cold end of the device refrigeration unit, and the upper surface of the whole planar multi-stage semiconductor refrigeration device is provided with a protective film except the electrode pressure welding block and the isothermal structure, and the lower part of the support film corresponding to the device refrigeration unit is a back cavity structure.

2. The planar multistage semiconductor refrigeration device according to claim 1, characterized by The hot end of the front stage refrigeration unit in the multi-stage device refrigeration unit is connected with the cold end of the rear stage refrigeration unit through a conduction component, and the cold end and the hot end in each stage refrigeration unit are connected in heat.

3. The planar multistage semiconductor refrigeration device according to claim 2, wherein The material used for the conduction part has an electrical conductivity greater than 1 x 10 7 S / m, a thermal conductivity greater than 90 W / (mK), and a thickness of the conduction part of 100 nm - 2 μm.

4. The planar multistage semiconductor refrigeration device according to claim 2, wherein The conduction component is made of metal, and the metal is any one or a combination of copper, gold, silver, aluminum, chromium and nickel.

5. The planar multistage semiconductor refrigeration device according to claim 1, wherein The stages of the multi-stage device refrigeration unit are connected in series, in parallel or independently, and the isolation cavity is located between the cold end and the hot end of each stage refrigeration unit.

6. The planar multistage semiconductor refrigeration device according to claim 1, wherein The material of the thermocouple pair is a thermoelectric material, which can be a bismuth telluride-based, lead telluride-based and silicon-germanium alloy thermoelectric material.

7. The planar multistage semiconductor refrigeration device according to claim 1, wherein The thermocouple pair is more than one, each thermocouple pair is composed of a pair of N-type thermoelectric arms and P-type thermoelectric arms, the N-type thermoelectric arms and the P-type thermoelectric arms are alternately arranged to form multiple thermocouple pairs, the thermoelectric arms are electrically connected through wires, and a π-type thermocouple is formed.

8. The planar multistage semiconductor refrigeration device according to claim 1, wherein The substrate includes a Si substrate, and the upper part of the Si substrate is a SiO2 blocking layer, and the Si substrate and the SiO2 blocking layer together constitute the substrate.

9. The planar multistage semiconductor refrigeration device according to claim 1, wherein The multi-stage device refrigeration unit is more than two stages.

10. A method of manufacturing the planar multistage semiconductor refrigeration device according to any one of claims 1 to 9, characterized by, The method comprises the following steps: (1) PI film is formed on the front surface of the substrate as a support film by spin coating and heat curing process, and the support film is patterned by photolithography and reactive ion etching process; (2) the cold end and the hot end of the device refrigeration unit, the conduction component, the isothermal structure and the electrode pressure welding block are prepared on the patterned support film surface by photolithography, sputtering and stripping process, and the N-type thermoelectric arm and the P-type thermoelectric arm are patterned by photolithography, sputtering and stripping process in turn; (3) PI film is prepared on the surface of the device by spin coating and heat curing process, and the protective film 7 is patterned by photolithography and reactive ion etching process; (4) the back cavity structure is prepared on the back surface of the substrate by photolithography, deep reactive ion etching and wet etching process.

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