Differential series underwater acoustic chip array structure and chip

Abstract

The invention discloses a differential serial underwater acoustic chip array structure and a chip, and belongs to the technical field of micro electro mechanical systems. The chip array structure sequentially comprises an upper electrode positive end, an upper electrode negative end, a piezoelectric layer, an upper electrode positive end and lower electrode negative end interconnection line embedded into and penetrating through the piezoelectric layer, an insulating layer and a lower electrode positive end and lower electrode negative end penetrating through the insulating layer from top to bottom. The structure is deposited on an SOI layer, and the SOI layer sequentially comprises a device silicon layer, a buried oxide layer and a back substrate from top to bottom; the cavities are arranged on the back substrate, the cavities penetrate through the back substrate from bottom to top, and each cavity defines a chip unit. And the upper and lower electrodes are electrically conducted with the adjacent chip units through the upper and lower electrode positive and negative end interconnection lines to form a chip-level differential series structure. Through reasonable differential positive and negative electrode series array arrangement, the array output voltage is improved, and the chip sensitivity is further improved.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) technology, and particularly relates to a differential series underwater acoustic chip array structure and chip. Background Technology

[0002] Piezoacoustic chips are primarily used in hydrophones, but are not limited to them. Hydrophones are key components of underwater acoustic monitoring systems. In hydrophones, the main device for electroacoustic conversion is the acoustic sensor chip, and its electroacoustic conversion efficiency determines the hydrophone's performance. The primary quantification standard for electroacoustic conversion efficiency is chip sensitivity. Higher sensitivity indicates better electroacoustic conversion efficiency. Piezoacoustic chips primarily improve chip sensitivity by modifying the chip structure.

[0003] Currently, improvements in chip structure mainly focus on improving unit structure, with chip arrays generally using parallel arrangements. For example, a MEMS piezoelectric thin-film acoustic chip array consists of a bottom SOI substrate, upper and lower electrodes, and a piezoelectric thin film located between the upper and lower electrodes. The upper electrode consists of an electrode disc located in the central region of the piezoelectric thin film and an outer conductive wire; both are electrically connected and in direct contact with the piezoelectric thin film. When the piezoelectric thin-film acoustic chip array is deformed by a force, a positive charge is generated in the central 70% region of the piezoelectric thin film, and a different charge is generated in the outer 20% region. The conductive wire passes through the 20% region of the different charge and interconnects with the electrode disc. This chip array structure improves reliability but does not increase the output voltage, resulting in limited improvement in sensitivity.

[0004] For example, Chinese invention patent CN114034377B discloses a double-layer AlN piezoelectric thin-film hydrophone chip unit, a chip, and a hydrophone. The chip unit includes, from bottom to top, an SOI substrate, a first AlN piezoelectric layer, a first electrode layer, an isolation layer, a second AlN piezoelectric layer, and a second electrode layer. While the chip uses a parallel arrangement and the unit employs a piezoelectric stacking structure, which improves the output voltage and sensitivity, the increased number of layers due to process limitations leads to greater polarization difficulty and more severe interlayer stress accumulation, thus limiting the overall effectiveness. Summary of the Invention

[0005] Based on the above-mentioned technical problems, this invention proposes a differential series underwater acoustic chip array structure and chip.

[0006] The technical solution adopted in this invention is as follows: A differential series underwater acoustic chip array structure includes an SOI layer, an insulating layer and a sensitive structure layer arranged sequentially from bottom to top. The sensitive structure layer includes an upper electrode positive terminal, an upper electrode negative terminal, a piezoelectric layer, a lower electrode positive terminal, a lower electrode negative terminal, an interconnection line between the upper and lower electrode positive terminals and an interconnection line between the upper and lower electrode negative terminals. The upper electrode positive end and the upper electrode negative end are disposed on the upper side of the piezoelectric layer, the lower electrode positive end and the lower electrode negative end are disposed on the lower side of the piezoelectric layer, the upper electrode negative end is disposed on the outer edge of the upper electrode positive end, the lower electrode negative end is disposed on the outer edge of the lower electrode positive end, and the upper electrode positive end is directly above the lower electrode positive end, and the upper electrode negative end is directly above the lower electrode negative end. The SOI layer has cavities, and the positive end of the upper electrode, the negative end of the upper electrode, the positive end of the lower electrode, and the negative end of the lower electrode are all located directly above the cavities. Each cavity defines a chip unit. The positive end of the lower electrode is connected to the positive end of the upper electrode of the adjacent chip unit through the interconnection line between the positive ends of the upper and lower electrodes, and the negative end of the lower electrode is connected to the negative end of the upper electrode of the adjacent chip unit through the interconnection line between the negative ends of the upper and lower electrodes, so that the adjacent chip units are arranged in series. The chip units are arranged in multiple arrays, and the multiple chip units constitute a chip array structure.

[0007] Preferably, both the positive end of the upper electrode and the positive end of the lower electrode are circular, and both the negative end of the upper electrode and the negative end of the lower electrode include two arc-shaped segments, which are symmetrically arranged on both sides of the edge of the positive end of the upper electrode or the positive end of the lower electrode.

[0008] Preferably, the positive end of the upper electrode is located in the central region directly opposite the cavity, occupying 70% of the chip unit area; the negative end of the upper electrode occupies 20% of the outer edge area of ​​the chip unit.

[0009] Preferably, the positive end of the upper electrode is connected to the first connecting line, and the positive end of the lower electrode is connected to the second connecting line. The first and second connecting lines are arranged facing each other and are connected by an interconnecting line between the positive ends of the upper and lower electrodes. The two arc-shaped segments of the negative end of the upper electrode are respectively connected to the third and fourth connecting lines, and the two arc-shaped segments of the negative end of the lower electrode are respectively connected to the fifth and sixth connecting lines. The third and fifth connecting lines, and the fourth and sixth connecting lines, are connected by an interconnecting line between the negative ends of the upper and lower electrodes. Through holes adapted to the interconnecting lines between the positive and negative ends of the upper and lower electrodes are respectively provided at corresponding positions in the piezoelectric layer.

[0010] Preferably, in the chip array structure, the positive terminal of the upper electrode of one chip unit is connected to the positive terminal output line of the upper electrode, and the negative terminal of the upper electrode is connected to the negative terminal output line of the upper electrode; the positive terminal of the lower electrode of one chip unit is connected to the positive terminal output line of the lower electrode, and the negative terminal of the lower electrode is connected to the negative terminal output line of the lower electrode, and a through hole adapted to the negative terminal output line of the upper electrode and the negative terminal output line of the lower electrode is provided at the corresponding position on the piezoelectric layer.

[0011] Preferably, the insulating layer is provided with an insertion port that is adapted to the positive end of the lower electrode, the negative end of the lower electrode, the second connection line, the fifth connection line, and the sixth connection line, and the insulating layer has the same thickness as the positive end of the lower electrode, the negative end of the lower electrode, the second connection line, the fifth connection line, and the sixth connection line.

[0012] Preferably, the SOI layer includes a back substrate, a buried oxide layer and a device silicon layer arranged sequentially from bottom to top, and the cavity is disposed on the back substrate and passes through the back substrate from bottom to top.

[0013] Preferably, the upper electrode positive terminal, upper electrode negative terminal, lower electrode positive terminal, and lower electrode negative terminal are all Mo electrodes; the interconnecting lines of the upper and lower electrode positive terminals, the upper and lower electrode negative terminals, the first connecting line, the second connecting line, the third connecting line, the fourth connecting line, the fifth connecting line, and the sixth connecting line are all made of Mo material.

[0014] Preferably, the insulating layer is made of silicon dioxide or silicon nitride; the piezoelectric layer is made of AlN, ZnO2 or PZT.

[0015] The present invention also provides a differential series underwater acoustic chip, which employs several differential series underwater acoustic chip array structures as described above, all of which are connected in series.

[0016] The beneficial technical effects of the present invention are as follows: The piezoelectric underwater acoustic chip array structure constructed in this invention employs an array of chip units, with the positive terminals of the upper and lower electrodes, as well as the negative terminals of the upper and lower electrodes, connected in series between adjacent chip units. This invention improves the array output voltage and thus enhances chip sensitivity through a rational differential series-connected array arrangement of positive and negative electrodes. Furthermore, the chip array structure used in this invention, while increasing the output voltage, allows for an unlimited increase in the number of chip units, overcoming the processing drawbacks of stacked structures. Simultaneously, the chip-level series connection significantly reduces circuit losses. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of one embodiment of the differential series underwater acoustic chip array structure of the present invention; Figure 2 An exploded view of one embodiment of the differential series underwater acoustic chip array structure of the present invention; Figure 3 This is a schematic diagram of the insulating layer and sensitive structure layer in the differential series underwater acoustic chip array structure of the present invention; Figure 4 The diagram shows the electrical schematic of a differential array structure; (a) is the schematic of the four-array series array of the present invention, and (b) is the schematic of the traditional four-layer series array.

[0018] In the diagram: 101-Insulating layer, 102-Positive terminal of upper electrode, 103-Negative terminal of upper electrode, 104-Piezoelectric layer, 105-Positive terminal of lower electrode, 106-Negative terminal of lower electrode, 107-Interconnection line between positive terminals of upper and lower electrodes, 108-Interconnection line between negative terminals of upper and lower electrodes, 109-Device silicon layer, 110-Cavity, 111-Back substrate, 112-Buried oxide layer, 113-First connection, 114-Second connection, 115-Third connection, 116-Fourth connection, 117-Fifth connection, 118-Sixth connection, 119-Through hole, 120-Output line of positive terminal of upper electrode, 121-Output line of negative terminal of upper electrode, 122-Output line of positive terminal of lower electrode, 123-Output line of negative terminal of lower electrode, 124-Through hole, 125-Embedded port. Detailed Implementation

[0019] Existing series-connected underwater acoustic chip array structures, such as multi-layer stacked structures, have the following shortcomings: (1) Stress accumulation: The core of multilayer stacked structures is to enhance the piezoelectric effect (such as displacement output or charge collection) through series connection. However, each layer of piezoelectric material will generate internal stress under the action of an electric field (such as the expansion and contraction deformation caused by the inverse piezoelectric effect of piezoelectric ceramics). The more layers there are, the more serious the interlayer stress accumulation will be. When the stress exceeds the bending strength of the material or the interfacial bonding strength, it will lead to interlayer cracking and delamination, destroy the integrity of the structure, and thus lose the piezoelectric properties.

[0020] (2) Difficulty in polarization: Piezoelectric materials require polarization processes to ensure their piezoelectric performance. After traditional stacked electrodes are stacked in multiple layers, the internal electric field distribution becomes more complex. It is necessary to optimize the polarization electric field (such as electric field strength and direction) to ensure the polarization consistency of each layer. The more layers there are, the greater the difficulty in polarization. Therefore, they cannot be stacked indefinitely.

[0021] Based on this, the present invention proposes a differential series underwater acoustic chip array structure and chip. Its core working mechanism is to construct an inner and outer differential series array, which can obtain twice the number of series electrodes of the traditional circular electrode array, significantly improving the output voltage and thus improving the sensitivity.

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0023] Referring to the accompanying drawings, a differential series underwater acoustic chip array structure includes an SOI layer, an insulating layer 101, and a sensitive structure layer arranged sequentially from bottom to top. The sensitive structure layer includes an upper positive electrode 102, an upper negative electrode 103, a piezoelectric layer 104, a lower positive electrode 105, a lower negative electrode 106, an interconnection line 107 between the upper and lower positive electrodes, and an interconnection line 108 between the upper and lower negative electrodes. The upper positive electrode 102 and the upper negative electrode 103 are disposed on the upper side of the piezoelectric layer 104, and the lower positive electrode 105 and the lower negative electrode 106 are disposed on the lower side of the piezoelectric layer 104. The upper negative electrode 103 is disposed on the outer edge of the upper positive electrode 102, and the lower negative electrode 106 is disposed on the outer edge of the lower positive electrode 105. The upper positive electrode 102 is directly above the lower positive electrode 105, and the upper negative electrode 103 is directly above the lower negative electrode 106.

[0024] like Figure 1 , Figure 2 As shown, both the upper electrode positive end 102 and the lower electrode positive end 105 are circular, i.e., circular electrode plates. Both the upper electrode negative end 103 and the lower electrode negative end 106 include two arc-shaped segments, which are symmetrically arranged on both sides of the edge of the upper electrode positive end 102 or the lower electrode positive end 105.

[0025] The SOI layer comprises, from bottom to top, a back substrate 111, a buried oxide layer 112, and a device silicon layer 109, with cavities 110 formed on the back substrate 111. The cavities 110 extend from bottom to top through the back substrate 111. The upper positive electrode 102, upper negative electrode 103, lower positive electrode 105, and lower negative electrode 106 are all located directly above the cavities 110, and each cavity 110 defines a chip unit. That is, each cavity 110 and its corresponding upper positive electrode 102, upper negative electrode 103, lower positive electrode 105, and lower negative electrode 106 can be considered a chip unit.

[0026] The positive end 102 of the upper electrode is located in the central region directly opposite the cavity 110, occupying 70% of the chip unit area. The negative end 103 of the upper electrode occupies 20% of the outer edge area of ​​the chip unit. The positive end 105 of the lower electrode is directly opposite the positive end 102 of the upper electrode, and the negative end 106 of the lower electrode is directly opposite the negative end 103 of the upper electrode. Therefore, the positive end 105 and the negative end 106 of the lower electrode also occupy 70% of the chip unit area and 20% of the outer edge area of ​​the chip unit, respectively.

[0027] like Figure 2 As shown, the lower electrode positive terminal 105 is connected to the upper electrode positive terminal of the adjacent chip unit through the upper and lower electrode positive terminal interconnection line 107, and the lower electrode negative terminal 106 is connected to the upper electrode negative terminal of the adjacent chip unit through the upper and lower electrode negative terminal interconnection line 108, so that the adjacent chip units are arranged in series.

[0028] The chip units are multiple and arranged in an array, forming a chip array structure. For example... Figure 1 , Figure 2 The diagram shows a layout of four chip units arranged in a row. Of course, this connection method can be used to expand horizontally and vertically to form a matrix array structure.

[0029] As a further design of the present invention, such as Figure 2 As shown, the upper electrode's positive end is connected to the first connecting line 113, and the lower electrode's positive end is connected to the second connecting line 114. The first connecting line 113 and the second connecting line 114 are staggered vertically and arranged facing each other, within the same vertical plane. The first connecting line 113 and the second connecting line 114 are connected by an interconnecting line 107 between the upper and lower electrode positive ends, which is arranged vertically. That is, the top surface of the interconnecting line 107 directly contacts the bottom surface of the end of the first connecting line 113, and the bottom surface of the interconnecting line 107 directly contacts the top surface of the end of the second connecting line 114, thus forming an electrical connection. The two arc-shaped segments at the negative end of the upper electrode are respectively connected to the third connecting line 115 and the fourth connecting line 116, and the two arc-shaped segments at the negative end of the lower electrode are respectively connected to the fifth connecting line 117 and the sixth connecting line 118. Similar to the arrangement of the first and second connecting lines, the third connecting line 115 and the fifth connecting line 117 are staggered vertically and facing each other in the same vertical plane, and the fourth connecting line 116 and the sixth connecting line 118 are staggered vertically and facing each other in the same vertical plane. The third and fifth connecting lines, and the fourth and sixth connecting lines, are connected by the upper and lower electrode negative end interconnecting lines 108, that is, two upper and lower electrode negative end interconnecting lines 108 are provided and arranged vertically. If the top surface of one of the upper and lower electrode negative end interconnecting lines is in direct contact with the bottom surface of the end of the third connecting line, and the bottom surface of the upper and lower electrode negative end interconnecting line is in direct contact with the top surface of the end of the fourth connecting line, electrical conductivity is formed. Through holes 119 are provided at corresponding positions in the piezoelectric layer 104 to match the interconnection lines of the positive and negative ends of the upper and lower electrodes, respectively.

[0030] As can be seen, the positive terminal of the upper electrode is connected to the positive terminal of the lower electrode of the adjacent chip unit through the interconnection line between the positive terminals of the upper and lower electrodes, thus forming an electrical connection. The negative terminal of the upper electrode is connected to the negative terminal of the lower electrode of the adjacent chip unit through the interconnection line between the negative terminals of the upper and lower electrodes, thus forming an electrical connection.

[0031] One of the chip units in the chip array structure (such as...) Figure 1 , Figure 2 The positive terminal of the upper electrode of the leftmost chip unit is connected to the positive terminal output line 120, and the negative terminal of the upper electrode is connected to the negative terminal output line 121. One of the chip units (e.g....) Figure 1 , Figure 2The rightmost chip unit (or the chip unit at the end of the array) has its lower electrode positive terminal connected to the lower electrode positive terminal output line 122, and its lower electrode negative terminal connected to the lower electrode negative terminal output line 123. A through-hole 124, adapted to the upper electrode negative terminal output line and the lower electrode negative terminal output line, is provided at the corresponding position on the piezoelectric layer. That is, the piezoelectric layer is of equal thickness and perfectly fits the upper and lower electrode positive terminal interconnects, the upper and lower electrode negative terminal interconnects, the lower electrode positive terminal output line 122, and the lower electrode negative terminal output line 123.

[0032] The above-mentioned upper electrode positive terminal output line 120, upper electrode negative terminal output line 121, lower electrode positive terminal output line 122 and lower electrode negative terminal output line 123 can be connected to the edge chip units of another row, or they can be used as the total output line of the chip array structure.

[0033] Furthermore, the insulating layer 101 is provided with an insertion port 125 adapted to the positive terminal of the lower electrode, the negative terminal of the lower electrode, the second connection line, the fifth connection line, and the sixth connection line, such as... Figure 2 As shown, the insert 125 matches the shape and size of the positive end of the lower electrode, the negative end of the lower electrode, and all connecting wires. The insulating layer 101 has the same thickness as the positive end of the lower electrode, the negative end of the lower electrode, the second connecting wire, the fifth connecting wire, and the sixth connecting wire. That is, the insulating layer has the same thickness as the positive end of the lower electrode, the negative end of the lower electrode, the second connecting wire, the fifth connecting wire, and the sixth connecting wire, and fits perfectly.

[0034] The upper electrode positive terminal 102, upper electrode negative terminal 103, lower electrode positive terminal 105, and lower electrode negative terminal 106 are all Mo electrodes. The interconnecting lines 107, 108, 113, 114, 115, 116, 117, and 118 of the upper and lower electrode positive terminals, as well as the first connecting line 113, the second connecting line 114, the third connecting line 115, the fourth connecting line 116, the fifth connecting line 117, and the sixth connecting line 118, are all made of Mo material.

[0035] The insulating layer 101 is made of silicon dioxide or silicon nitride, but other insulating materials may also be used. The piezoelectric layer 104 is made of AlN, ZnO2, or PZT, but other piezoelectric materials may also be used.

[0036] The present invention also provides a differential series underwater acoustic chip, which employs several differential series underwater acoustic chip array structures as described above, all of which are connected in series.

[0037] In summary, this invention discloses a differential series underwater acoustic chip array structure, taking a four-chip unit arrangement as an example. From top to bottom, the structure consists of a top electrode (positive and negative terminals), a piezoelectric layer with interconnecting lines between the top and bottom electrodes (embedded and penetrating the piezoelectric layer), and an insulating layer with interconnecting lines between the bottom electrode (positive and negative terminals). This structure is deposited on an SOI layer, which, from top to bottom, consists of a top silicon layer (device silicon layer), a buried oxide layer, and a substrate layer (back substrate). The substrate layer has a cavity and defines a chip unit. The top and bottom electrodes are electrically connected to adjacent chip units through interconnecting lines between their positive and negative terminals, forming a chip-level differential series structure. This invention, through a rational differential series array arrangement of positive and negative electrodes, improves the array output voltage, thereby enhancing chip sensitivity.

[0038] The principle underlying the differential series underwater acoustic chip array structure of this invention is roughly as follows: The piezoelectric equivalent capacitance is the capacitance value that equates the electrical behavior of a piezoelectric material under an electric field to that of a capacitor. It reflects the ability of a piezoelectric material to store electrical energy and is a core parameter in the electrical model of piezoelectric devices. The upper electrode, central piezoelectric layer, and lower electrode of each chip unit form the piezoelectric equivalent capacitance.

[0039] The formula for calculating the piezoelectric equivalent capacitance is:

[0040] in: Piezoelectric equivalent capacitance (unit: farad, F); Dielectric constant of piezoelectric materials (unit: farads per meter, F / m); Electrode area (unit: square meters, m²); Thickness of piezoelectric material (unit: meter, m).

[0041] In the array, the total piezoelectric equivalent capacitance After array is connected in series When connected in series, the total piezoelectric equivalent capacitance is less than the piezoelectric equivalent capacitance of any single element. The charge after series connection... The output voltage increases significantly while remaining constant. .

[0042] In traditional parallel electrodes, the piezoelectric equivalent capacitances are arranged in parallel. The total capacitance is the sum of the capacitances of each individual unit, the total output voltage is equal to the voltages of each individual unit, and the total charge is the sum of the capacitances of each individual unit.

[0043] Figure 4The diagrams show the electrical schematics of a differential array structure; (a) is the schematic of the four-array series configuration of this invention, and (b) is the schematic of a traditional four-layer series configuration. By comparison, it can be seen that the chip array structure of this invention is a two-dimensional planarization of the traditional multi-layer stacked structure, avoiding the polarization difficulties and stress accumulation problems caused by excessive stacking layers in traditional multi-layer stacked electrodes. In the case of series connection, all capacitors have equal charge, the reciprocal of the total capacitance is equal to the sum of the reciprocals of each individual capacitor, and the total voltage is the sum of the voltages of each individual capacitor.

[0044] The core mechanism of the high-sensitivity differential series underwater acoustic chip array structure of this invention lies in constructing a chip-level series array, which reduces the total piezoelectric equivalent capacitance of the array while maintaining a constant output charge; in addition, the chip-level series method also significantly reduces circuit losses.

[0045] Therefore, the differential series underwater acoustic chip array structure of the present invention can significantly improve the output voltage, thereby improving the array sensitivity.

[0046] For any parts not mentioned above, existing technologies can be adopted or referenced.

[0047] Of course, the above description is only a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. It should be noted that any equivalent substitutions or obvious modifications made by those skilled in the art under the guidance of this specification fall within the scope of this specification and should be protected by the present invention.

Claims

1. A differential series hydrophone chip array structure, characterized in that: The sensitive structure layer comprises an upper electrode positive terminal, an upper electrode negative terminal, a piezoelectric layer, a lower electrode positive terminal, a lower electrode negative terminal, an upper-lower electrode positive terminal interconnection line and an upper-lower electrode negative terminal interconnection line. The upper electrode positive terminal and the upper electrode negative terminal are arranged on the upper side of the piezoelectric layer, the lower electrode positive terminal and the lower electrode negative terminal are arranged on the lower side of the piezoelectric layer, the upper electrode negative terminal is arranged outside the edge of the upper electrode positive terminal, the lower electrode negative terminal is arranged outside the edge of the lower electrode positive terminal, and the upper electrode positive terminal is directly above the lower electrode positive terminal, and the upper electrode negative terminal is directly above the lower electrode negative terminal. The SOI layer is provided with cavities, and the upper electrode positive terminal, the upper electrode negative terminal, the lower electrode positive terminal and the lower electrode negative terminal are all directly above the cavities, and each cavity defines a chip unit. The lower electrode positive terminal is connected with the upper electrode positive terminal of the adjacent chip unit through the upper-lower electrode positive terminal interconnection line, and the lower electrode negative terminal is connected with the upper electrode negative terminal of the adjacent chip unit through the upper-lower electrode negative terminal interconnection line, so that the adjacent chip units are arranged in series. The chip units are arranged in an array.

2. The array structure of differential series hydrophone chip according to claim 1, characterized in that: The upper electrode positive terminal and the lower electrode positive terminal are both in the shape of a circular sheet, and the upper electrode negative terminal and the lower electrode negative terminal each comprise two arc-shaped segments symmetrically arranged on both sides of the edge of the upper electrode positive terminal or the lower electrode positive terminal.

3. The array structure of differential type hydroacoustic chip in series according to claim 2, characterized in that: The upper electrode positive terminal is directly above the central region of the cavity, and occupies an area of 70% of the chip unit area; and the upper electrode negative terminal occupies an area of 20% of the outer edge of the chip unit.

4. The array structure of differential type hydroacoustic chip in series according to claim 2, characterized in that: The upper electrode positive terminal is connected with a first connecting line, the lower electrode positive terminal is connected with a second connecting line, the first connecting line and the second connecting line are arranged in opposite directions, the first connecting line and the second connecting line are connected through the upper-lower electrode positive terminal interconnection line, the two arc-shaped segments of the upper electrode negative terminal are connected with a third connecting line and a fourth connecting line respectively, the two arc-shaped segments of the lower electrode negative terminal are connected with a fifth connecting line and a sixth connecting line respectively, the third connecting line and the fifth connecting line are connected through the upper-lower electrode negative terminal interconnection line, and the fourth connecting line and the sixth connecting line are connected through the upper-lower electrode negative terminal interconnection line; and through holes corresponding to the upper-lower electrode positive terminal interconnection line and the upper-lower electrode negative terminal interconnection line are arranged at corresponding positions of the piezoelectric layer.

5. The array structure of differential type hydroacoustic chip in series according to claim 4, characterized in that: The upper electrode positive terminal of one of the chip units in the chip array structure is connected with an upper electrode positive terminal output line, and the upper electrode negative terminal is connected with an upper electrode negative terminal output line; the lower electrode positive terminal of one of the chip units is connected with a lower electrode positive terminal output line, and the lower electrode negative terminal is connected with a lower electrode negative terminal output line; and through holes corresponding to the upper electrode negative terminal output line and the lower electrode negative terminal output line are arranged at corresponding positions of the piezoelectric layer.

6. The array structure of differential series hydrophone chip according to claim 4, characterized in that: The insulating layer is provided with embedding entrances corresponding to the lower electrode positive terminal, the lower electrode negative terminal, the second connecting line, the fifth connecting line and the sixth connecting line, and the insulating layer has the same thickness as the lower electrode positive terminal, the lower electrode negative terminal, the second connecting line, the fifth connecting line and the sixth connecting line.

7. The array structure of differential hydrophone chip in series according to claim 1, characterized in that: The SOI layer comprises a back substrate, a buried oxygen layer and a device silicon layer arranged in sequence from bottom to top, and the cavities are arranged on the back substrate and pass through the back substrate from bottom to top.

8. The array structure of differential type hydroacoustic chip in series according to claim 5, characterized in that: The upper electrode positive terminal, the upper electrode negative terminal, the lower electrode positive terminal and the lower electrode negative terminal are Mo electrodes; the upper and lower electrode positive terminal interconnection lines, the upper and lower electrode negative terminal interconnection lines, the first connecting line, the second connecting line, the third connecting line, the fourth connecting line, the fifth connecting line and the sixth connecting line are all made of Mo material.

9. The array structure of differential hydrophone chip in series according to claim 1, characterized in that: The insulating layer is made of silicon dioxide or silicon nitride material; the piezoelectric layer is made of AlN, ZnO2 or PZT material.

10. A differential, serial hydrophone chip, characterized by: A plurality of the differential series underwater acoustic chip array structures as claimed in any one of claims 1-9 are connected in series.

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