Testing method, device and equipment based on voltage analog quantity fault injection and medium

Abstract

The invention discloses a test method, device and equipment based on voltage analog quantity fault injection and a medium. The method comprises the following steps: sending a simulated standard fault signal to the equipment to be tested; wherein the standard fault signal is generated by the voltage analog quantity fault injection equipment through attenuation, isolation amplification and differential-to-single-ended conditioning of an external standard signal according to a preset test requirement; monitoring the operation state of the to-be-tested equipment under the action of the standard fault signal, and collecting the output voltage, the output current and the function response data of the to-be-tested equipment; and based on the output voltage, the output current and the function response number, determining a tolerance index and an exception handling index of the to-be-tested device to a voltage analog quantity fault. The beneficial effect of improving the fault test efficiency and accuracy is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data acquisition and testing, and particularly relates to a test method and device based on voltage analog quantity fault injection, equipment and a medium. BACKGROUND

[0002] Voltage analog quantity fault injection is a technology for testing and verifying the behavior of an electronic system under abnormal conditions. This technology is widely used in the simulation of typical voltage faults that occur during normal operation in industrial automation production sites, thereby verifying whether the system functions normally.

[0003] Common voltage faults in industrial automation sites include voltage sag, voltage interruption, overvoltage, and undervoltage, and voltage faults in industrial sites have the characteristics of suddenness, diversity, and chain reaction.

[0004] During the research and development design phase of a device, there are numerous signals involved on the mainboard. According to different development requirements, fault injection testing needs to be performed on signals at different positions. Testing according to test cases results in a long testing period, low testing quality, and easy occurrence of problems. In particular, during system-level testing, it is inconvenient to perform fault injection operations on signals, which affects testing efficiency. SUMMARY

[0005] The present application provides a test method and device based on voltage analog quantity fault injection, and equipment and a medium, to realize precise testing of voltage analog quantity faults of a device to be tested in an industrial automation scenario.

[0006] According to an aspect of the present application, a test method based on voltage analog quantity fault injection is provided, which is applied to a voltage analog quantity fault injection device. The method comprises the following steps:

[0007] sending a simulated standard fault signal to a device to be tested; wherein the standard fault signal is generated by the voltage analog quantity fault injection device according to a preset testing requirement, after attenuating, isolating, amplifying, and differentiating and converting a single-end processing of an external standard signal;

[0008] monitoring the running state of the device to be tested under the action of the standard fault signal, and collecting output voltage, output current, and functional response data of the device to be tested;

[0009] determining the tolerance index and abnormal processing index of the device to be tested to voltage analog quantity faults based on the output voltage, the output current, and the functional response data.

[0010] According to another aspect of the present application, a test device based on voltage analog quantity fault injection is provided, which comprises the following steps:

[0011] The signal receiving module is configured to send an analog standard fault signal to the device under test; wherein the standard fault signal is generated by the voltage analog quantity fault injection device according to a preset test requirement, and is generated by attenuating, isolating, amplifying, and differentially converting and single-ended processing an external standard signal.

[0012] The device detection module is configured to monitor the running state of the device under test under the action of the standard fault signal, and collect output voltage, output current, and functional response data of the device under test.

[0013] The test index determination module is configured to determine the tolerance index and the abnormal processing index of the device under test to the voltage analog quantity fault based on the output voltage, the output current, and the functional response data.

[0014] According to another aspect of the present application, an electronic device is provided, which comprises:

[0015] at least one processor;

[0016] and a memory in communication connection with the at least one processor;

[0017] wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the test method based on voltage analog quantity fault injection of any embodiment of the present application.

[0018] According to another aspect of the present application, a computer readable storage medium is provided, which stores computer instructions for enabling a processor to implement the test method based on voltage analog quantity fault injection of any embodiment of the present application when executed by the processor.

[0019] The technical scheme of the embodiments of the present application realizes the accurate test of the voltage analog quantity fault of the device under test in the industrial automation scene by the voltage analog quantity fault injection device generating a standard fault signal according to a preset test requirement, attenuating, isolating, amplifying, and differentially converting and single-ended processing an external standard signal, and sending the standard fault signal to the device under test, synchronously monitoring the running state of the device under test, collecting the output voltage / current and functional response data, and then determining the device fault tolerance index and the abnormal processing index, solves the technical problems of being unable to efficiently simulate a typical voltage fault, long test period, and low quality in the prior art, and achieves the technical effects of improving the fault test efficiency and accuracy.

[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0022] Figure 1 A flow chart of a test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0023] Figure 2a A disturbance signal conditioning circuit diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0024] Figure 2b A disturbance voltage signal detection circuit diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0025] Figure 2c An operational amplifier output circuit diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0026] Figure 2d A common mode fault injection circuit principle diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0027] Figure 2e A differential mode fault injection circuit principle diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0028] Figure 2f A positive and negative signal line parallel impedance fault injection circuit principle diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0029] Figure 2g A positive voltage signal line and cabinet parallel impedance fault injection circuit principle diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0030] Figure 2h A negative voltage signal line and cabinet parallel impedance fault injection circuit principle diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0031] Figure 2i A positive voltage signal line series resistance fault injection circuit principle diagram of another test method based on voltage analog quantity fault injection provided by the embodiment of the present application is shown in the figure.

[0032] Figure 2jA negative voltage signal line series resistance fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0033] Figure 2k A chassis signal line series resistance fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0034] Figure 2l A positive voltage signal line open circuit fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0035] Figure 2m A negative voltage signal line open circuit fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0036] Figure 2n A positive and negative signal line short circuit fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0037] Figure 2o A positive signal line chassis short circuit short circuit fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0038] Figure 2p A negative signal line chassis short circuit short circuit fault injection circuit principle diagram of another voltage analog quantity fault injection based test method provided by the embodiment of the present application;

[0039] Figure 3 A structure schematic diagram of a voltage analog quantity fault injection based test device provided by the embodiment of the present application;

[0040] Figure 4 A structure schematic diagram of an electronic device of a voltage analog quantity fault injection based test method for realizing the embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and in the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Figure 1 A flowchart of a test method based on voltage analog quantity fault injection provided for an embodiment of the present application. The embodiment can be applicable to the test case based on voltage analog quantity fault injection. The method can be executed by a test device based on voltage analog quantity fault injection. The device can be realized in the form of hardware and / or software. The device can be configured in an electronic device. As shown in the figure, the method specifically includes the following steps: Figure 1

[0044] S110, send an analog standard fault signal to the device to be tested; wherein the standard fault signal is generated by the voltage analog quantity fault injection device according to the preset test requirement after the external standard signal is attenuated, isolated, amplified and converted from differential to single-ended.

[0045] Wherein, the voltage analog quantity fault injection device can be understood as a special device for generating and injecting voltage fault signals to test the fault tolerance of other devices.

[0046] ​It is worth mentioning that the voltage analog quantity fault injection device adopts a portable box integrated design, the overall structure integrates five core function modules and is compactly arranged, the upper front surface of the box is provided with a human-computer interaction area, is equipped with a touch display screen for parameter setting, real-time display of fault waveforms and test state, and physical keys such as a power key, a fault injection start-stop key, an emergency reset key, and the like, and a state indicator light group is distributed on the side edge to intuitively feed back the working state of the device; the core circuit modules are arranged in layers in the box, the upper layer is a signal processing unit, which integrates a voltage divider composed of a first top resistor, a second top resistor and a bottom resistor, an industrial-grade isolation amplifier, a high common-mode rejection ratio operational amplifier and a series relay switching matrix, realizes attenuation, isolation amplification, differential to single-ended conditioning and fault mode switching of external standard signals / field interference signals, wherein a fault influence adjustment circuit is arranged beside the relay switching matrix, and a multi-turn wire-wound potentiometer (supporting manual and automatic double adjustment) is carried; the middle layer is a control unit, which takes a main control chip as the core, is matched with a relay drive circuit and a signal detection circuit, can collect fault signal parameters in real time and control the cooperative work of each module; the lower layer is a power supply and interface unit, which is internally provided with a rechargeable lithium battery and an external power supply interface (supporting dual power supply mode switching), the power management circuit has overvoltage and overcurrent protection functions, is provided with a signal input interface (connecting external standard signals), a terminal row / aviation plug type signal output interface (connecting a test device), a PE protection grounding terminal and a data export interface, the modules are connected through shielded cables, the box shell is provided with a heat dissipation grid and a portable handle, which not only guarantees the signal anti-interference capability and equipment heat dissipation efficiency in the complex industrial field environment, but also meets the mobile test requirements in multiple scenes.

[0047] The to-be-tested device can be understood as an electronic device that needs to accept voltage fault testing. The standard fault signal can be understood as an electrical signal generated after signal conditioning, which is used to simulate typical voltage faults in an industrial field. The preset test requirement can be understood as a condition set in advance according to the test target of the to-be-tested device, including the fault type to be simulated and the fault signal parameter. The external standard signal can be understood as a basic signal input from the outside of the device for generating a fault signal. The attenuation can be understood as reducing the amplitude of the external standard signal through resistors and other elements. The isolation amplification can be understood as amplifying the attenuated signal through an isolation amplifier. The differential to single-ended conditioning can be understood as converting the double-ended differential signal output by the isolation amplifier into a single-ended signal through an operational amplifier circuit.

[0048] Specifically, the voltage analog quantity fault injection device first attenuates the external standard signal according to the preset test requirement to match the input range of the isolation amplifier, to enhance the signal and resist interference through isolation amplification, and to adapt to the signal interface of the to-be-tested device through differential to single-ended conditioning. After generating a standard fault signal, it is sent to the to-be-tested device.

[0049] Optionally, before sending the simulated standard fault signal to the device under test, further comprising:

[0050] The signal output end of the voltage analog quantity fault injection device is physically connected to the voltage analog quantity signal receiving end of the device under test.

[0051] The signal output end can be understood as an interface on the voltage analog quantity fault injection device for sending standard fault signals externally. The voltage analog quantity signal receiving end can be understood as an interface on the device under test for receiving external voltage analog quantity signals. The physical connection can be understood as directly connecting the signal output end of the fault injection device to the signal receiving end of the device under test through physical components.

[0052] Specifically, before sending the standard fault signal, the hardware connection between the fault injection device and the device under test is completed first, and an adapter is selected according to the interface types of both parties to firmly connect the signal output end of the fault injection device to the voltage analog quantity signal receiving end of the device under test.

[0053] Optionally, before sending the simulated standard fault signal to the device under test, further comprising:

[0054] According to the preset test requirements, the external standard signal is attenuated by a voltage divider composed of a first top resistor, a second top resistor, and a bottom resistor of the voltage analog quantity fault injection device; the attenuated signal is isolated and amplified by an isolation amplifier, the differential signal output by the isolation amplifier is converted into a single-ended signal by an operational amplifier circuit, and the standard fault signal is determined based on the transfer function of the operational amplifier circuit, the positive output end signal of the isolation amplifier, and the negative output end signal of the isolation amplifier.

[0055] The first top resistor and the second top resistor can be understood as two resistors that make up the top part of the voltage divider, which are connected in series to form the upper half of the voltage divider and are used in conjunction with the bottom resistor to achieve signal attenuation. The bottom resistor can be understood as a single resistor that makes up the bottom part of the voltage divider and is connected in series with the top resistors. The voltage divider can be understood as a circuit structure composed of the first top resistor, the second top resistor, and the bottom resistor. The transfer function of the operational amplifier circuit can be understood as a mathematical formula that describes the relationship between the input signal and the output signal of the operational amplifier circuit. The positive output end signal of the isolation amplifier and the negative output end signal of the isolation amplifier can be understood as two differential signals output by the isolation amplifier. The positive output end signal is a positive signal output by the forward end, and the negative output end signal is a negative signal output by the reverse end. The difference between the two is amplified by the operational amplifier circuit to form a single-ended signal.

[0056] Specifically, before sending the standard fault signal, the external standard signal is first processed according to the preset test requirement, the external standard signal is attenuated by a voltage divider composed of the first top resistor, the second top resistor and the bottom resistor, then the attenuated signal is amplified by an isolation amplifier, and at the same time, electrical isolation is realized, and positive and negative two-way differential signals are output; then the differential signal is converted into a single-ended signal by an operational amplifier circuit, the signal amplitude is calculated through a transfer function, and finally a standard fault signal meeting the preset requirement is generated.

[0057] Optionally, the preset test requirement includes selecting a target fault mode, and the target fault mode includes at least one of a common-mode fault, a differential-mode fault, a series impedance fault, a parallel impedance fault, a short-circuit fault and an open-circuit fault.

[0058] Among them, the target fault mode can be understood as a specific voltage fault type selected according to the preset test requirement. The common-mode fault can be understood as superimposing the fault signal on the positive voltage signal line and the negative voltage signal line of the device under test at the same time, simulating the fault type that the two signal lines are disturbed at the same time in the industrial field. The differential-mode fault can be understood as superimposing the fault signal on the positive voltage signal line of the device under test, and connecting the ground end of the fault signal to the negative voltage signal line, simulating the fault type that there is a potential difference between the two signal lines. The series impedance fault can be understood as connecting a variable resistor in series on the signal line (such as the positive voltage signal line) of the device under test, simulating the fault type that the signal is attenuated due to the increase of line impedance in long line transmission. The parallel impedance fault can be understood as connecting a variable resistor in parallel between the signal line and the chassis, or between the positive and negative voltage signal lines of the device under test, simulating the fault type that the impedance is abnormal due to the decrease of line insulation. The short-circuit fault can be understood as directly short-circuiting the signal line (such as the positive voltage signal line and the chassis, or the positive and negative voltage signal lines) of the device under test through a relay, simulating the fault type that the line is accidentally short-circuited. The open-circuit fault can be understood as cutting off the signal line (such as the positive voltage signal line and the negative voltage signal line) of the device under test through a relay, simulating the fault type that the line is broken.

[0059] Specifically, the fault type to be simulated needs to be specified in the preset test requirement, and at least one of the typical industrial voltage faults such as common-mode, differential-mode, series impedance, parallel impedance, short-circuit and open-circuit is selected as the target fault mode, for example: to test the line breaking resistance of the device, the open-circuit fault is selected. When the target fault mode is series impedance fault or parallel impedance fault, the voltage analog fault injection device adjusts the resistance value of the potentiometer to a target value in the range of 0~100K through the fault influence adjustment circuit, and then generates a standard fault signal corresponding to the impedance parameter

[0060] S120, monitoring the running state of the device under test under the action of the standard fault signal, collecting the output voltage, output current and functional response data of the device under test.

[0061] Functional response data can be understood as data showing changes in the function of the device under test (DUT) under fault signal conditions, such as function interruption time and alarm trigger status. The DUT's status is tracked in real time using sensors, indicator lights, and other methods. For example, a voltage sensor is used to collect data on whether the output voltage exceeds the normal range, and a current sensor is used to collect data on whether the output current is abnormal. Simultaneously, it records whether the device's function is interrupted and whether an alarm is triggered.

[0062] Optionally, monitoring the operating status of the device under test under the action of a standard fault signal includes:

[0063] Monitor the status of the operating indicator lights and the output of alarm signals of the device under test;

[0064] Collect the output voltage and output current data of the device under test, and record the time data of the device under test when its function is interrupted or restored.

[0065] Based on the status of the operation indicator light, the output of the alarm signal, the output voltage data, the output current data, and the time data, the operation status monitoring data corresponding to the device under test is determined.

[0066] The status of the operating indicator lights can be understood as the on / off status and flashing of the indicator lights on the device under test (DUT) used to indicate its working status. The alarm signal output status can be understood as the alarm information output by the DUT in a fault state. The output voltage data can be understood as the real-time value and fluctuation range of the output voltage of the DUT under the influence of a fault signal. The output current data can be understood as the real-time value and peak value of the output current of the DUT under the influence of a fault signal. The time data for function interruption or recovery can be understood as the data formed by the time when the function of the DUT stops due to a fault signal and the time when the function returns to normal.

[0067] Operational status monitoring data can be understood as a comprehensive data set that integrates indicator light status, alarm status, voltage and current data, and time data, forming a complete reflection of the fault status of the device under test.

[0068] Specifically, first observe whether the equipment indicator lights are on and listen for alarm sounds, and record the alarm signal output status; then, use voltage sensors and / or current sensors to collect the equipment output voltage and current data in real time, and use a timer to record the time of function interruption and recovery; finally, integrate all the data to form complete operating status monitoring data.

[0069] S130. Based on the output voltage, the output current, and the functional response data, determine the tolerance index and anomaly handling index of the device under test to voltage analog quantity faults.

[0070] Among them, tolerance indicators can be understood as indicators that measure the extreme conditions that the device under test can withstand under voltage faults, such as the maximum tolerable voltage fluctuation range and peak current. Anomaly handling indicators can be understood as indicators that measure whether the device under test can respond and restore normal operation in a timely manner when encountering a voltage fault, such as alarm trigger speed and fault recovery time.

[0071] Specifically, the collected output voltage and current data are compared with the rated voltage and current range of the device under test. For example, if the rated voltage of the device is 220V±10%, and it can still work when the voltage drops to 180V under a fault signal, then 180V can be used as the voltage tolerance threshold, i.e., tolerance index. Based on the alarm trigger time in the functional response data, such as 0.5 seconds after the fault occurs, and the fault recovery time, such as 3 seconds after the alarm, the abnormal response speed and fault recovery capability are determined, i.e., abnormal handling index.

[0072] Optionally, determining the tolerance index and anomaly handling index of the device under test to analog voltage faults includes:

[0073] The collected output voltage and output current data are compared with the rated voltage range and rated current range of the device under test to determine the voltage tolerance threshold and current tolerance threshold of the device under test under standard fault signals.

[0074] Determine the abnormal response speed data and fault recovery data of the device based on the device alarm trigger time and fault recovery time in the functional response data;

[0075] The tolerance index is determined based on the voltage tolerance threshold and the current tolerance threshold, and the anomaly handling index is determined based on the abnormal response speed data and the fault recovery data.

[0076] The rated voltage range can be understood as the standard range of input or output voltage of the device under test (DUT) when it is operating normally. The rated current range can be understood as the standard range of input or output current of the DUT when it is operating normally. The voltage withstand threshold can be understood as the maximum / minimum voltage value that the DUT can maintain its basic functions under a fault signal. The current withstand threshold can be understood as the maximum / minimum current value that the DUT can maintain its basic functions under a fault signal. The device alarm trigger time can be understood as the time interval from when the fault signal begins to act on the DUT to when the device outputs an alarm signal. The fault recovery time can be understood as the time interval from when the fault signal stops being injected to when the DUT's functions return to normal. The abnormal response speed data can be understood as data based on the alarm trigger time. The fault recovery data can be understood as data based on the fault recovery time.

[0077] Specifically, by comparing the collected voltage / current data with the equipment's rated range, the voltage and current limits at which the equipment can still operate are identified and used as voltage / current tolerance thresholds. Alarm trigger time and fault recovery time are extracted from the functional response data and converted into abnormal response speed data and fault recovery data. The voltage / current tolerance thresholds are then integrated into tolerance indicators, and the abnormal response speed data and fault recovery data are integrated into abnormal handling indicators.

[0078] Optionally, the method further includes:

[0079] After stopping the standard fault signal injection, the test result data of the device under test is exported, wherein the test result data includes fault mode, fault parameters, injection duration and monitoring data of the device under test;

[0080] A fault injection test report is generated based on the test results data.

[0081] The "stop standard fault signal injection" can be understood as the operation whereby the voltage analog fault injection device stops sending standard fault signals to the device under test (DUT) after a certain round of fault testing. For example, this can be stopped via device buttons or host computer commands. Test result data can be understood as a collection of data integrating key information from the entire fault testing process. The fault injection test report can be understood as a document generated based on the test result data, used to present the test process and conclusions. The fault injection test report may include test objectives, fault types, data charts, and indicator conclusions (such as device withstand voltage of 18V and abnormal response speed of 0.3 seconds).

[0082] Specifically, the relays of the control voltage analog fault injection device are reset and the potentiometer is de-energized, disconnecting the signal and power connections between the device and the device under test. After the fault injection stops, the test result data is first exported from the voltage analog fault injection device. The data must include the fault mode, fault parameters, injection duration, and monitoring data of the device under test. Then, a fault injection test report is compiled based on the test result data. The report also includes whether the device meets the design requirements, so as to facilitate subsequent R&D improvements or acceptance.

[0083] The technical solution of this invention uses a voltage analog fault injection device to generate a standard fault signal from an external standard signal through attenuation, isolation amplification, and differential-to-single-ended conditioning according to preset test requirements, and sends it to the device under test. Simultaneously, it monitors the operating status of the device under test, collects output voltage / current and functional response data, and then determines the fault tolerance index and anomaly handling index of the device. This achieves accurate testing of voltage analog faults in the device under test in industrial automation scenarios, solves the technical problems of existing technologies that cannot efficiently simulate typical voltage faults, have long test cycles, and low quality, and achieves the technical effect of improving the efficiency and accuracy of fault testing.

[0084] As an optional embodiment of the present invention, the test method based on voltage analog quantity fault injection in this embodiment specifically includes the following steps:

[0085] The fault injection circuit includes fault signal generation and fault injection. The input fault signal consists of external signals and on-site interference signals. The signals are processed by an interference conditioning circuit to generate a fault signal VOUT. VOUT enters a fault adjustment matrix to achieve different fault injections. Specifically, the main control chip controls the relay switches to switch the matrix, and controls the potentiometer to adjust the fault impact. The interference voltage signal detection circuit is used for interference voltage detection by the isolation chip. The operational amplifier circuit provides high input impedance and low output impedance for the interference voltage signal. The relay switching matrix controls the on / off state of the circuit to inject different fault modes. The fault impact adjustment circuit allows for adjustable input of resistance values ​​in the circuit. The analog voltage fault injection methods include: common-mode fault injection, differential-mode fault injection, series impedance fault injection, parallel impedance fault injection, short-circuit fault injection, and open-circuit fault injection.

[0086] The common-mode fault injection can be achieved by introducing a common-mode interference voltage signal into the circuit using the fault injection method of the present invention. The differential-mode fault injection can be achieved by introducing a differential-mode interference voltage signal into the circuit using the fault injection method of the present invention. The series impedance fault injection can be achieved by changing the series impedance value in the circuit using the fault injection method of the present invention; the parallel impedance fault injection can be achieved by changing the parallel impedance value in the circuit using the fault injection method of the present invention; the short-circuit fault injection can be achieved by creating a short circuit in the circuit using the fault injection method of the present invention; and the open-circuit fault injection can be achieved by creating an open circuit in the circuit using the fault injection method of the present invention.

[0087] The device based on voltage analog quantity fault injection includes the generation of fault interference signals and the injection of interference signals. The fault interference signals include field interference signals and common interference signals, including sinusoidal voltage signals, square wave voltage signals and triangular wave voltage signals. The fault signals can be generated by interference signal detection, operational amplification circuit and differential to single-ended output to form injectable fault signals. The main control chip realizes the state of relays and potentiometers under different fault injection modes, thereby realizing the fault injection of voltage signals.

[0088] In one embodiment, the electrical layer fault simulation circuit mainly includes fault injection of common-mode, differential-mode, series impedance, parallel impedance, short circuit, and open circuit into the voltage analog signal using fault interference signals.

[0089] The input signals of the entire fault simulation device are obtained by conditioning standard signals and field interference signals. Therefore, the signals are divided into external signals, such as sine waves, triangular waves, and other voltage signals; and field interference signals.

[0090] Figure 2a A circuit diagram for conditioning interference signals in another test method based on voltage analog quantity fault injection provided in an embodiment of the present invention; as shown. Figure 2a As shown, it includes an interference signal detection circuit, an isolation amplifier circuit, and an operational amplifier output circuit.

[0091] For example, the interference signal detection circuit consists of a resistor at the top of a voltage divider. The bottom resistor of the voltage divider Composition. The isolation amplifier is differential input, with its full-scale input voltage set to ±250mV, AC voltage. The voltage is 5V. The voltage divider attenuation factor Gain is calculated to be 2 using the following formula.

[0092] ;

[0093] Figure 2b An interference voltage signal detection circuit diagram for another test method based on analog voltage fault injection provided in this embodiment of the invention; as shown. Figure 2b As shown, the top resistor of the voltage divider is... , The composition and top resistance of the voltage divider can be calculated using the following formula. 20KΩ:

[0094] ;

[0095] The selected isolation amplifier is a low input impedance device, and its input impedance is... The impedance is 35kΩ. Considering that the interaction between the input impedance of the isolation amplifier and the input voltage divider will cause gain error, and that the bias current of the isolation amplifier will flow through the voltage sensing resistor and cause offset error, it is necessary to adjust the impedance according to... Design Perform additional error compensation.

[0096] The bottom resistance of the voltage divider is calculated using the following formula. 1120Ω:

[0097] ;

[0098] Calculated according to the following formula It is 1060.6Ω:

[0099] ;

[0100] Figure 2c An operational amplifier output circuit diagram for another test method based on voltage analog quantity fault injection provided in an embodiment of the present invention; as shown. Figure 2c As shown, an operational amplifier is added to the output of the isolation amplifier to achieve differential to single-ended conversion. The OUTP and OUTN ports are connected to the operational amplifier to achieve differential to single-ended conversion.

[0101] From the differential-to-single-ended output circuit diagram, the transfer function of the output stage is:

[0102] ;

[0103] in, , Take 2430Ω, , Taking 1000Ω, we get:

[0104] ;

[0105] Therefore, the amplification factor of this operational amplifier is 2.43, that is, when and The differential output voltage is ±2.05V. It is ±5V.

[0106] In one possible embodiment, Figure 2d A schematic diagram of a common-mode fault injection circuit for another voltage analog fault injection testing method provided in this embodiment of the invention; as shown. Figure 2d As shown, after interference signal detection, operational amplifier circuit and differential to single-ended output to form a fault signal, according to the principle of common-mode fault injection, the generated fault interference signal VOUT is superimposed on the positive voltage signal line and the negative voltage signal line respectively. The interference signal GND is connected to the chassis ground. The main control chip controls the closing of relay 1, relay 2 and relay 3 to realize the common-mode fault injection of the fault interference signal.

[0107] In one possible embodiment, Figure 2e A schematic diagram of a differential-mode fault injection circuit for another voltage analog fault injection testing method provided in this embodiment of the invention; as shown. Figure 2e As shown, after interference signal detection, operational amplifier circuit and differential to single-ended output to form a fault interference signal, according to the principle of differential mode fault injection, the generated fault interference signal VOUT is superimposed on the positive voltage signal line, the interference signal GND is connected to the negative voltage signal line, and the main control chip controls the closing of relay 1 and relay 2 to realize the differential mode fault injection of the fault interference signal.

[0108] In one possible embodiment, Figure 2fA schematic diagram of a parallel impedance fault injection circuit for positive and negative signal lines, provided in an embodiment of the present invention, for another test method based on analog voltage fault injection; as shown. Figure 2f As shown, the generated fault interference signal VOUT is selected as the fault injection signal source of the parallel impedance. An adjustable potentiometer is connected in parallel between the positive and negative signal lines. The resistance value can be adjusted from 0 to 100K. The impedance is simulated by manually adjusting the potentiometer value. The main control chip controls the closing of the potentiometer to realize the parallel impedance fault injection of the positive and negative signal lines.

[0109] In one possible embodiment, Figure 2g A schematic diagram of a positive voltage signal line and a chassis parallel impedance fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2g As shown, the generated fault interference signal VOUT is selected as the fault injection signal source of the parallel impedance. An adjustable potentiometer is connected in parallel between the positive signal line and the chassis. The resistance value can be adjusted from 0 to 100K. The impedance is simulated by manually adjusting the potentiometer value. The main control chip controls the closing of the potentiometer to realize the parallel impedance fault injection between the positive voltage signal line and the chassis.

[0110] In one possible embodiment, Figure 2h A schematic diagram of a negative voltage signal line and a chassis parallel impedance fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2h As shown, the generated fault interference signal VOUT is selected as the fault injection signal source of the parallel impedance. An adjustable potentiometer is connected in parallel between the negative signal line and the chassis. The resistance value can be adjusted from 0 to 100K. The impedance is simulated by manually adjusting the potentiometer value. The main control chip controls the closing of the potentiometer to realize the parallel impedance fault injection between the negative voltage signal line and the chassis.

[0111] In one possible embodiment, Figure 2i A schematic diagram of a positive voltage signal line series resistor fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2i As shown, the generated fault interference signal VOUT is selected as the fault injection signal source of the series impedance. A potentiometer with an adjustable resistance value is connected in series on the positive signal line. The main control chip controls the closing of the potentiometer to realize the fault injection of the series resistance on the positive voltage signal line.

[0112] In one possible embodiment, Figure 2j A schematic diagram of a negative voltage signal line series resistor fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2jAs shown, the generated fault interference signal VOUT is selected as the fault injection signal source of the series impedance. A potentiometer with an adjustable resistance value is connected in series on the negative signal line. The main control chip controls the closing of the potentiometer to realize the series resistance fault injection of the negative voltage signal line.

[0113] In one possible embodiment, Figure 2k A schematic diagram of a chassis signal line series resistance fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2k As shown, the generated fault interference signal VOUT is selected as the fault injection signal source of the series impedance. A potentiometer with an adjustable resistance value is connected in series on the chassis signal line. The main control chip controls the closing of the potentiometer to realize the series resistance fault injection of the chassis signal line.

[0114] In one possible embodiment, Figure 2l A schematic diagram of a positive voltage signal line open circuit fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2l As shown, a relay is connected in series on the positive pressure signal line, and the main control chip controls the closing of the potentiometer to realize the injection of fault for open circuit in the positive pressure signal line.

[0115] In one possible embodiment, Figure 2m A schematic diagram of a negative voltage signal line open circuit fault injection circuit for another voltage analog quantity fault injection test method provided in this embodiment of the invention; as shown. Figure 2m As shown, a relay is connected in series on the negative pressure signal line, and the main control chip controls the closing of the potentiometer to realize the injection of fault for open circuit in the negative pressure signal line.

[0116] In one possible embodiment, Figure 2n A schematic diagram of a short-circuit fault injection circuit for positive and negative signal lines, provided by an embodiment of the present invention, for another test method based on voltage analog quantity fault injection; as shown. Figure 2n As shown, relays are connected in parallel on the positive and negative voltage signal lines, and the main control chip controls the closing of the potentiometer to realize the injection of short-circuit faults on the positive and negative voltage signal lines.

[0117] In one possible embodiment, Figure 2o A schematic diagram of a short-circuit fault injection circuit for a positive signal line chassis, provided as an embodiment of the present invention, for another test method based on voltage analog quantity fault injection; as shown. Figure 2o As shown, a relay is connected in parallel between the positive pressure signal line and the chassis. The main control chip controls the closing of the potentiometer to realize the injection of short-circuit faults into the positive pressure signal line and chassis.

[0118] In one possible embodiment, Figure 2p A schematic diagram of a short-circuit fault injection circuit for a negative signal line chassis, provided as an embodiment of the present invention, for another test method based on analog voltage fault injection; as shown.Figure 2p As shown, a relay is connected in parallel between the negative pressure signal line and the chassis. The main control chip controls the closing of the potentiometer to realize the injection of short-circuit faults into the negative pressure signal line and chassis.

[0119] The technical solution of this invention, through real-time control of the relay matrix and the fault impact adjustment circuit, can not only inject conventional electrical signals such as sine waves, square waves, and triangular waves, as well as interference signals collected on-site, meeting the requirements for multi-signal comprehensive communication fault injection, and reproducing various communication anomaly scenarios, providing a comprehensive and efficient test platform for the certification of compatibility, coordination, and anti-interference capabilities of various analog signals; it can also accurately simulate typical communication faults in industrial sites, such as short circuits, open circuits, series or parallel impedances, and reproduce signal attenuation in long-distance transmission through series resistance, etc., with rapid fault injection response and reliable switching, meeting the stringent requirements of the industrial communication environment. It provides a fault verification method that conforms to actual working conditions for the research and development testing, on-site debugging, and operation and maintenance of industrial communication equipment, helping to improve the reliability of industrial communication networks and enhance the real-time security of the system.

[0120] Figure 3 This is a schematic diagram of a test device based on voltage analog quantity fault injection, provided as an embodiment of the present invention. Figure 3 As shown, the device includes: a signal receiving module 310, an equipment detection module 320, and a test index determination module 330.

[0121] The signal receiving module 310 is used to send a simulated standard fault signal to the device under test (DUT). The standard fault signal is generated by the voltage analog fault injection device according to preset test requirements, after attenuation, isolation amplification, and differential-to-single-ended conditioning of an external standard signal. The device detection module 320 is used to monitor the operating status of the DUT under the action of the standard fault signal and collect the output voltage, output current, and functional response data of the DUT. The test index determination module 330 is used to determine the tolerance index and anomaly handling index of the DUT to voltage analog faults based on the output voltage, the output current, and the functional response data.

[0122] The technical solution of this invention uses a voltage analog fault injection device to generate a standard fault signal from an external standard signal through attenuation, isolation amplification, and differential-to-single-ended conditioning according to preset test requirements, and sends it to the device under test. Simultaneously, it monitors the operating status of the device under test, collects output voltage / current and functional response data, and then determines the fault tolerance index and anomaly handling index of the device. This achieves accurate testing of voltage analog faults in the device under test in industrial automation scenarios, solves the technical problems of existing technologies that cannot efficiently simulate typical voltage faults, have long test cycles, and low quality, and achieves the technical effect of improving the efficiency and accuracy of fault testing.

[0123] Optionally, the device further includes:

[0124] The connection module is used to physically connect the signal output terminal of the voltage analog fault injection device to the voltage analog signal receiving terminal of the device under test before sending a simulated standard fault signal to the device under test.

[0125] Optionally, the preset test requirements include selecting a target fault mode, which includes at least one of common-mode fault, differential-mode fault, series impedance fault, parallel impedance fault, short-circuit fault, and open-circuit fault.

[0126] Optionally, the device detection module includes:

[0127] The detection unit is used to monitor the status of the operating indicator lights and the output of alarm signals of the device under test;

[0128] The acquisition and recording unit is used to acquire the output voltage data and output current data of the device under test, and record the time data of the device under test when its function is interrupted or restored.

[0129] The data determination unit is used to determine the operating status monitoring data corresponding to the device under test based on the status of the operation indicator light, the alarm signal output, the output voltage data, the output current data, and the time data.

[0130] Optionally, the test index determination module includes:

[0131] The data comparison unit is used to compare the collected output voltage and output current data with the rated voltage range and rated current range of the device under test, and to determine the voltage tolerance threshold and current tolerance threshold of the device under test under standard fault signals.

[0132] An abnormal response data determination unit is used to determine the abnormal response speed data and fault recovery data of the device based on the device alarm trigger time and fault recovery time in the functional response data.

[0133] The indicator determination unit is used to determine the tolerance indicator based on the voltage tolerance threshold and the current tolerance threshold, and to determine the abnormal handling indicator based on the abnormal response speed data and the fault recovery data.

[0134] Optionally, the device further includes:

[0135] The test result export module is used to export the test result data of the device under test after stopping the injection of standard fault signals. The test result data includes fault mode, fault parameters, injection duration and monitoring data of the device under test.

[0136] The test report generation module is used to generate a fault injection test report based on the test result data.

[0137] Optionally, the device further includes:

[0138] The external signal processing module is used to attenuate the external standard signal by a voltage divider composed of a first top resistor, a second top resistor, and a bottom resistor, according to preset test requirements, before sending the simulated standard fault signal to the device under test.

[0139] The fault signal determination module is used to isolate and amplify the attenuated signal through an isolation amplifier, convert the differential signal output by the isolation amplifier into a single-ended signal through an operational amplifier circuit, and determine a standard fault signal based on the transfer function of the operational amplifier circuit, the positive output signal of the isolation amplifier, and the negative output signal of the isolation amplifier.

[0140] The voltage analog quantity fault injection-based test device provided in the embodiments of the present invention can execute the voltage analog quantity fault injection-based test method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0141] Figure 4 This is a schematic diagram of an electronic device for implementing the voltage analog quantity fault injection test method according to embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0142] like Figure 4As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0143] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0144] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the method of voltage analog fault injection testing.

[0145] In some embodiments, the method for testing based on voltage analog fault injection can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the method for testing based on voltage analog fault injection described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the method for testing based on voltage analog fault injection by any other suitable means (e.g., by means of firmware).

[0146] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0147] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0148] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0149] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0150] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0151] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0152] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0153] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A test method based on voltage analog quantity fault injection, characterized in that, Applications include voltage analog signal fault injection devices, including: A simulated standard fault signal is sent to the device under test; wherein the standard fault signal is generated by the voltage analog quantity fault injection device according to preset test requirements, after attenuation, isolation amplification and differential to single-ended conditioning of an external standard signal; Monitor the operating status of the device under test under the action of a standard fault signal, and collect the output voltage, output current and functional response data of the device under test; Based on the output voltage, the output current, and the functional response data, the tolerance index and anomaly handling index of the device under test to voltage analog quantity faults are determined.

2. The method according to claim 1, characterized in that, Before sending a simulated standard fault signal to the device under test, the following steps are also included: The signal output terminal of the voltage analog fault injection device is physically connected to the voltage analog signal receiving terminal of the device under test.

3. The method according to claim 2, characterized in that, The preset test requirements include selecting a target fault mode, which includes at least one of common-mode fault, differential-mode fault, series impedance fault, parallel impedance fault, short-circuit fault, and open-circuit fault.

4. The method according to claim 1, characterized in that, The monitoring of the operating status of the device under test under the action of a standard fault signal includes: Monitor the status of the operating indicator lights and the output of alarm signals of the device under test; Collect the output voltage and output current data of the device under test, and record the time data of the device under test when its function is interrupted or restored. Based on the status of the operation indicator light, the output of the alarm signal, the output voltage data, the output current data, and the time data, the operation status monitoring data corresponding to the device under test is determined.

5. The method according to claim 1, characterized in that, The determination of the tolerance index and anomaly handling index of the device under test to analog voltage faults includes: The collected output voltage and output current data are compared with the rated voltage range and rated current range of the device under test to determine the voltage tolerance threshold and current tolerance threshold of the device under test under standard fault signals. Determine the abnormal response speed data and fault recovery data of the device based on the device alarm trigger time and fault recovery time in the functional response data; The tolerance index is determined based on the voltage tolerance threshold and the current tolerance threshold, and the anomaly handling index is determined based on the abnormal response speed data and the fault recovery data.

6. The method according to claim 1, characterized in that, Also includes: After stopping the standard fault signal injection, the test result data of the device under test is exported, wherein the test result data includes fault mode, fault parameters, injection duration and monitoring data of the device under test; A fault injection test report is generated based on the test results data.

7. The method according to claim 1, characterized in that, Before sending a simulated standard fault signal to the device under test, the following steps are also included: According to the preset test requirements, the external standard signal is attenuated by a voltage divider composed of the first top resistor, the second top resistor, and the bottom resistor of the voltage analog quantity fault injection device. The attenuated signal is isolated and amplified by an isolation amplifier. The differential signal output by the isolation amplifier is converted into a single-ended signal by an operational amplifier circuit. A standard fault signal is determined based on the transfer function of the operational amplifier circuit, the positive output signal of the isolation amplifier, and the negative output signal of the isolation amplifier.

8. A test device based on voltage analog quantity fault injection, characterized in that, include: The signal receiving module is used to send a simulated standard fault signal to the device under test; wherein the standard fault signal is generated by the voltage analog quantity fault injection device according to preset test requirements, after attenuation, isolation amplification and differential to single-ended conditioning of the external standard signal; The device detection module is used to monitor the operating status of the device under test under the action of a standard fault signal, and to collect the output voltage, output current and functional response data of the device under test. The test index determination module is used to determine the tolerance index and anomaly handling index of the device under test to voltage analog quantity faults based on the output voltage, the output current and the functional response number.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the test method based on voltage analog quantity fault injection as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the test method based on voltage analog quantity fault injection as described in any one of claims 1-7.

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