Method and device for detecting parasitic loop of ultrahigh-voltage primary and secondary equipment

Abstract

The invention provides a method and a device for detecting a parasitic loop of ultrahigh-voltage primary and secondary equipment. The method comprises the following steps: acquiring an electric signal by adopting an external detection head in contact with a node of a parasitic loop to be detected; when a level jump signal of opening and closing of the ultrahigh-voltage primary equipment is received, hardware interruption is generated; responding to the hardware interruption, switching the ADC to a highest sampling rate mode, starting high-speed parallel sampling of a parasitic loop special detection circuit, and generating multiple paths of parallel data based on the electric signal; according to the multi-path parallel data, a parasitic loop diagnosis algorithm model is operated to carry out fusion analysis, and a diagnosis result and a confidence coefficient corresponding to the diagnosis result are generated; and according to the diagnosis result, the confidence coefficient and the multi-path parallel data, generating a risk assessment result and a disposal strategy according to a preset risk assessment matrix and a disposal strategy library. According to the method and the device, dual high integration is realized on hardware and software levels, and the detection efficiency and accuracy are improved.

Description

Technical Field

[0001] This invention relates to the field of power system safety operation and maintenance technology, and more specifically, to a method and apparatus for detecting parasitic circuits in ultra-high voltage primary and secondary equipment. Background Technology

[0002] Parasitic loop faults in power systems are caused by a variety of factors, including but not limited to AC intrusion, where high-voltage side enters the secondary system through stray capacitance, electromagnetic coupling, insulation damage, or poor grounding, creating parasitic AC current; DC grounding, where multiple points in the DC control system are accidentally grounded, leading to point drift and loop short circuits; DC interconnection, where different DC systems are unintentionally connected through incorrect wiring, stray paths, capacitive coupling, etc.; and other factors, including electrical, magnetic field, structural, and grounding-related factors between different systems and multiple loops. The hazards of parasitic loop faults are characterized by three main features: concealment, chain reaction, and destructiveness. They can cause performance degradation, malfunctions, equipment damage, and even safety accidents. Existing technologies for detecting parasitic loops lack the ability to physically integrate and logically unify multiple detection functions. Different instruments and wiring methods are required for different parasitic loop faults, failing to achieve timely conversion between various fault detection methods, resulting in isolated tools and fragmented processes. The entire detection process, from opening and closing circuit breakers at various levels, connecting test leads, reading instrument data, to recording results, relies entirely on manual operation. This is not only inefficient, but also introduces a large risk of human error and lacks the ability to intelligently analyze and detect data. Summary of the Invention

[0003] To address the technical problems of fragmented and inefficient fault detection processes caused by the lack of integration and intelligence in existing parasitic circuit detection technologies, this invention provides a method and apparatus for detecting parasitic circuits in ultra-high voltage primary and secondary equipment.

[0004] According to one aspect of the present invention, the present invention provides a method for detecting parasitic circuits in ultra-high voltage primary and secondary equipment, the method comprising:

[0005] An external detection head is used to collect electrical signals by contacting the nodes of the parasitic circuit to be detected in the ultra-high voltage primary and secondary equipment. The external detection head is electrically connected to the ADC, voltage / current sensor and signal conditioning circuit of the dedicated detection circuit for the parasitic circuit.

[0006] When a level transition signal for the opening and closing of the ultra-high voltage primary equipment is received from the GPIO interface, it generates a hardware interrupt as a trigger event.

[0007] In response to the hardware interrupt, the ADC is switched to the highest sampling rate mode, and the high-speed parallel sampling of the parasitic loop detection circuit is started to generate multiple parallel data based on the electrical signal.

[0008] Based on the multi-path parallel data, the parasitic loop diagnosis algorithm model is run to perform fusion analysis, generate diagnosis results, and the confidence level corresponding to the diagnosis results;

[0009] Based on the diagnostic results, the confidence level, and the multi-path parallel data, risk assessment results and treatment strategies are generated according to a pre-set risk assessment matrix and treatment strategy library.

[0010] According to another aspect of the present invention, the present invention provides a parasitic circuit detection device for ultra-high voltage primary and secondary equipment, which is a circuit-integrated box structure, including a main unit and an external detection head, wherein:

[0011] The external detection head is connected to the node of the parasitic circuit to be detected in the ultra-high voltage primary and secondary equipment for acquiring raw electrical signals. The external detection head is also electrically connected to the ADC, voltage / current sensor and signal conditioning circuit of the parasitic circuit dedicated detection circuit inside the host.

[0012] The host is also equipped with a GPIO interface on its side for transmitting level switching signals of the opening and closing of the ultra-high voltage primary equipment;

[0013] The host also includes an embedded CPU with a built-in main control program. When the level transition signal is received, the CPU generates a hardware interrupt as a trigger event. In response to the hardware interrupt, the ADC switches to the highest sampling rate mode and starts high-speed parallel sampling of the dedicated parasitic loop detection circuit, generating multiple parallel data streams based on the electrical signal. Based on the multiple parallel data streams, the host runs a parasitic loop diagnostic algorithm model for fusion analysis, generating diagnostic results and corresponding confidence levels. Based on the diagnostic results, the confidence levels, and the multiple parallel data streams, the host generates risk assessment results and treatment strategies according to a preset risk assessment matrix and treatment strategy library.

[0014] According to another aspect of the present invention, a computer-readable storage medium is provided, the storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in any of the above aspects of the present invention.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the executable instructions to implement the steps of the method described in any of the preceding aspects of the present invention.

[0016] The present invention discloses a method and apparatus for detecting parasitic loops in ultra-high voltage primary and secondary equipment. The method includes: acquiring electrical signals using an external detection head that contacts the node of the parasitic loop to be detected in the ultra-high voltage primary and secondary equipment; generating a hardware interrupt as a trigger event when a level transition signal of the opening and closing of the ultra-high voltage primary equipment is received via a GPIO interface; responding to the hardware interrupt, switching the ADC to the highest sampling rate mode and starting high-speed parallel sampling of the dedicated parasitic loop detection circuit to generate multiple parallel data based on the electrical signals; performing fusion analysis on the parasitic loop diagnostic algorithm model based on the multiple parallel data to generate diagnostic results and the corresponding confidence levels; and generating risk assessment results and disposal strategies based on the diagnostic results, the confidence levels, and the multiple parallel data, according to a preset risk assessment matrix and disposal strategy library. The method and apparatus achieve a high degree of integration at both the hardware and software levels. The hardware layer establishes a unified platform with three independent dedicated detection circuits, corresponding to DC grounding, AC interference, and DC interconnection detection, respectively. Parallel sampling technology allows the three circuits to operate synchronously, simultaneously acquiring necessary physical quantities such as ground voltage and insulation resistance without time-division multiplexing. The acquired signals are externally connected to a single multi-functional detection head, and internally coordinated and triggered via a GPIO interface, avoiding frequent changes to test leads and sensors. This allows multiple systems to sense in parallel with a single probe connection, physically eliminating the need for multiple instruments. The software layer encodes the diagnostic methods and judgment logic for different parasitic loops into algorithms, integrating them into the main control program. Human-computer interaction is achieved through a touchscreen, encapsulating complex professional knowledge, reducing manual operation, and improving detection accuracy and efficiency. Attached Figure Description

[0017] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures:

[0018] Figure 1 This is a flowchart of a parasitic circuit detection method for ultra-high voltage primary and secondary equipment according to a preferred embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of the parasitic circuit detection device for ultra-high voltage primary and secondary equipment according to a preferred embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of an electronic device according to a preferred embodiment of the present invention. Detailed Implementation

[0021] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0022] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0023] Example 1

[0024] Figure 1 This is a flowchart of a parasitic circuit detection method for ultra-high voltage primary and secondary equipment according to a preferred embodiment of the present invention. Figure 1 As shown, the parasitic circuit detection method for ultra-high voltage primary and secondary equipment described in this preferred embodiment starts from step 101.

[0025] In step 101, an external detection head is used to collect electrical signals by contacting the node of the parasitic circuit to be detected in the ultra-high voltage primary and secondary equipment. The external detection head is electrically connected to the ADC, voltage / current sensor and signal conditioning circuit of the dedicated detection circuit for the parasitic circuit.

[0026] In this preferred embodiment, the electrical signals of the parasitic circuit are uniformly connected through a multi-functional detection head, avoiding frequent replacement of test leads and sensors, and enabling multiple systems to sense in parallel with a single probe connection, thus eliminating the need for multiple instruments physically.

[0027] In step 102, when a level transition signal for the opening and closing of the ultra-high voltage primary equipment is received from the GPIO interface, it is used as a trigger event to generate a hardware interrupt.

[0028] Preferably, the method further includes communicating with a remote control platform via an Ethernet interface, receiving remote commands as trigger events to initiate high-speed parallel sampling of the dedicated parasitic loop detection circuit, and generating multiple parallel data streams based on the electrical signals.

[0029] In this preferred embodiment, the triggering event is used as a "switch" to realize the dynamic detection of parasitic loops, so that the method can be instantly woken up from the low power monitoring state to the high speed capture state, so as to ensure that millisecond-level instantaneous faults have nowhere to hide.

[0030] Preferably, before generating a hardware interrupt, the method further includes: When a level transition signal indicating the opening or closing of the ultra-high voltage primary equipment is received via the GPIO interface.

[0031] The adaptive initialization process is executed, and the self-test and calibration algorithms are invoked to perform zero-drift calibration and accuracy verification on the voltage / current sensor.

[0032] Based on the real-time ambient temperature and power grid operating status, the system loads detection parameters and parasitic loop diagnosis algorithm models suitable for the current operating conditions from the preset strategy library.

[0033] In this preferred embodiment, before the intelligent diagnosis of parasitic loops is initiated by the trigger event, the built-in voltage / current sensor is first calibrated for zero drift and its accuracy is verified. Environmental perception and strategy loading are also performed to ensure that the data for intelligent diagnosis is "clean", "accurate" and "adapted to the field environment", thus providing a reliable data foundation for the entire detection process.

[0034] In step 103, in response to the hardware interrupt, the ADC is switched to the highest sampling rate mode, and the high-speed parallel sampling of the parasitic loop dedicated detection circuit is started to generate multiple parallel data based on the electrical signal.

[0035] In this preferred embodiment, the core physical quantities that need to be collected when performing parasitic loop detection include, but are not limited to, the positive / negative bus voltage to ground (V+_gnd, V-_gnd), the total insulation resistance to ground (R_insulation), and the leakage current of each branch (I_leakage) involved in DC grounding detection; the AC voltage component on the DC bus (V_ac_on_dc), the frequency of the AC component (Freq_ac), the AC component in the leakage current to ground (I_leakage_ac) involved in AC intrusion detection; and the voltage difference between different DC buses / systems (ΔV_between_systems), the impedance / resistance between buses (R_between_buses), and the voltage fluctuation correlation of the buses involved in DC interconnection detection.

[0036] In step 104, based on the multi-path parallel data, the parasitic loop diagnostic algorithm model is run to perform fusion analysis, generate diagnostic results, and the confidence level corresponding to the diagnostic results.

[0037] Preferably, based on the multi-path parallel data, a parasitic loop diagnostic algorithm model is run for fusion analysis to generate diagnostic results and the confidence levels corresponding to the diagnostic results, including:

[0038] Extract the feature signals from the multi-channel parallel data;

[0039] Based on the characteristic signals, a parasitic loop diagnosis algorithm model is run, integrating waveform analysis, spectrum analysis, time series analysis, and time series correlation analysis to generate diagnostic results. These results include whether a fault exists or not. When the diagnostic result indicates a fault exists, the result further includes the fault type and fault location. The fault type includes direct grounding faults, AC interference faults, DC interconnection faults, and composite faults of at least two of the above three types. When the fault type is a branch-level fault, the fault location is determined to be the specific branch where the fault occurred. When the fault type is a system-level fault, the fault location is determined to be the two or more DC systems where the fault occurred.

[0040] Based on the intensity of the feature signal, the degree of consistency between the feature signals, and the time synchronization accuracy between the feature signal and the triggering event, the confidence level corresponding to the diagnostic result is generated according to the pre-set confidence level assignment rules.

[0041] In this preferred embodiment, when the GPIO interface captures the trigger signal of dynamic processes such as opening and closing, it immediately starts the high-speed sampling mode. Through a unified external detection head and three sets of internally integrated parasitic loop dedicated detection circuits, the above-mentioned core physical quantities are collected synchronously and in parallel, and the parasitic loop diagnostic algorithm model is run for fusion analysis. The specific analysis process is shown in Table 1.

[0042] Table 1

[0043]

[0044]

[0045] It should be noted that the three diagnostic algorithms in Table 1 are not isolated judgments, but rather undergo cross-validation and fusion analysis, for example:

[0046] During the dynamic process, a step drop in the DC bus-to-ground voltage (V+_gnd) was detected (DC grounding characteristic), while a strong 50Hz AC component was simultaneously captured on the DC bus (AC intrusion characteristic). Conventional techniques might misdiagnose this as two independent faults, or only detect one due to slow instrument switching. However, this preferred embodiment… The algorithm immediately correlates these two highly synchronized temporal features, performs a fusion diagnosis, and ultimately concludes that this is highly likely a composite fault caused by insulation breakdown or strong electromagnetic induction during equipment operation, resulting in "AC current intrusion accompanied by DC system grounding." The accuracy and depth of this diagnosis are unmatched by traditional single-dimensional detection.

[0047] After performing fusion analysis, this preferred embodiment generates a structured diagnostic report, which includes the diagnostic results and the corresponding confidence levels. The diagnostic report clearly outputs whether a fault exists, and the fault type (DC grounding, AC interference, DC interconnection, or a combination of these), as well as the fault location. For branch-level faults (such as DC grounding), the specific branch can be located by analyzing the magnitude and direction of I_leakage in each branch and combining it with topological relationships. For system-level faults (such as DC interconnection), correlation analysis directly identifies which two or more DC systems are interconnected. Regarding the confidence level of the diagnostic results, a pre-set confidence level assignment rule is used. The strength of the feature signals extracted from the collected parallel data, the consistency between the feature signals, and the time synchronization accuracy between the feature signals and the triggering event are substituted into the confidence level assignment rule to determine the confidence level of the diagnostic results. For example, if only a single feature triggers weakly while other features do not respond, the confidence level will be low (e.g., 60%), prompting maintenance personnel to pay further attention. When the strength of the feature signal, the degree of agreement between multiple features, and the time synchronization accuracy with the triggering event all reach a threshold, the confidence level of the diagnostic result is 95%.

[0048] In step 105, based on the diagnostic results, the confidence level, and the multi-path parallel data, a risk assessment result and a treatment strategy are generated according to a preset risk assessment matrix and treatment strategy library.

[0049] Preferably, based on the diagnostic results, the confidence level, and the multi-path parallel data, a risk assessment result and a treatment strategy are generated according to a pre-set risk assessment matrix and treatment strategy library, including:

[0050] The diagnostic results, the confidence level, and the multi-path parallel data are compared with the corresponding items in the risk assessment matrix to determine the risk level.

[0051] Based on the handling strategies in the handling strategy library corresponding to the risk level, generate a diagnostic report, local alarm information, and remote alarm information.

[0052] Preferably, the method further includes establishing a connection with the cloud via an Ethernet interface or a Wi-Fi module, uploading the stored detection data and generated diagnostic cases to the cloud, and downloading new algorithm models, optimization strategies, or software upgrade packages from the cloud to update the main control program.

[0053] In this preferred embodiment, risk assessment is performed based on a preset risk assessment matrix, for example:

[0054] ●High risk: "DC grounding" and insulation resistance is lower than the specified value, or "AC intrusion" voltage is higher than the safety threshold.

[0055] ●Medium risk: "DC interconnection" but with relatively high impedance, which has not yet affected operation.

[0056] ●Low risk: Warning with low confidence level.

[0057] After determining the risk level, this preferred implementation method executes the corresponding processing strategy based on a pre-set handling strategy library. For example, for a local high-level warning, the alarm indicator light flashes rapidly, and a red alarm window pops up on the IPS touchscreen, displaying a detailed diagnostic report; a diagnostic report is generated, automatically producing a complete report including waveform screenshots, data analysis, fault location, and handling suggestions, which is stored in the built-in memory or exported to an SD card; cloud reporting and remote alarms are also implemented, immediately uploading alarm information and diagnostic reports to a remote monitoring center or cloud platform via Ethernet / Wi-Fi to notify remote maintenance personnel.

[0058] In summary, the parasitic circuit detection method for ultra-high voltage primary and secondary equipment described in this preferred embodiment overcomes the passive limitations of existing technologies that rely on manual serial switching of instruments, changes in wiring, and parameter settings. By integrating three dedicated detection circuits for DC grounding, AC interference, and DC interconnection onto a unified hardware platform and employing parallel sampling technology to simultaneously detect multiple parasitic circuits, it solves the limitation of traditional technologies that can only diagnose one type of fault at a time. This achieves a leap from "manual switching" to "automatic / trigger-based conversion" and enables comprehensive diagnosis of primary and secondary parasitic circuits in power equipment, improving detection efficiency and accuracy.

[0059] Example 2

[0060] Figure 2 This is a schematic diagram of the structure of a parasitic circuit detection device for ultra-high voltage primary and secondary equipment according to a preferred embodiment of the present invention. Figure 2 As shown, the ultra-high voltage primary and secondary equipment parasitic circuit detection device 200 of this preferred embodiment is a circuit-integrated box structure, including a main unit 201 and an external detection head 202, wherein:

[0061] The external detection head 202 is connected to the node of the parasitic circuit to be detected in the primary and secondary equipment of the ultra-high voltage power supply, and is used to collect the original electrical signal. The external detection head 202 is also electrically connected to the ADC, voltage / current sensor and signal conditioning circuit of the dedicated parasitic circuit detection circuit inside the host (all of which are internal hardware structures of the host and are not shown in the attached drawings). The side of the host is also equipped with a GPIO interface 203 for transmitting the level transition signal of the opening and closing of the ultra-high voltage primary equipment.

[0062] The host also includes an embedded CPU (internal hardware structure, not shown in the attached figures), which has a built-in main control program. When the level transition signal is received, the CPU generates a hardware interrupt as a trigger event. In response to the hardware interrupt, the ADC switches to the highest sampling rate mode and starts high-speed parallel sampling of the dedicated parasitic loop detection circuit, generating multiple parallel data streams based on the electrical signal. Based on the multiple parallel data streams, the parasitic loop diagnostic algorithm model is run for fusion analysis to generate diagnostic results and the corresponding confidence levels. Based on the diagnostic results, the confidence levels, and the multiple parallel data streams, a risk assessment result and a treatment strategy are generated according to a preset risk assessment matrix and treatment strategy library.

[0063] Preferably, the host 201 has an IPS capacitive touchscreen 210 mounted on its top for providing human-computer interaction services based on the main control program; the host has a built-in Wi-Fi module (an internal hardware structure of the host, not shown in the accompanying drawings) for communicating with the cloud or a remote platform; the host 201 also has a USB interface 204, an Ethernet interface 205, a Micro SD card interface 206, an HDMI interface 207, a power interface 208, and an alarm indicator light 209 mounted on its side. The USB interface 204, Ethernet interface 205, and Micro SD card interface 206 are used for bidirectional data transmission; the HDMI interface 207 is used to project the device's visualization capabilities onto other display devices; the power interface 208 supplies power to the device; and the alarm indicator light 209 is electrically connected to the dedicated parasitic loop detection circuit, which triggers an alarm based on the diagnostic results.

[0064] In this preferred embodiment, by setting up a rich variety of expansion interfaces and adopting the concept of software-defined functions, the core detection algorithm supports remote upgrades, breaking the problem of the single function of traditional equipment that is "fixed at the factory". In the future, when facing new parasitic loops or detection needs, there is no need to replace the host; the detection capability can be expanded by connecting new sensors or remotely upgrading the software algorithm, ensuring the long-term investment value and technological foresight of the equipment.

[0065] The parasitic circuit detection device for ultra-high voltage primary and secondary equipment described in this preferred embodiment has the same steps for parasitic circuit detection as the parasitic circuit detection method for ultra-high voltage primary and secondary equipment, and achieves the same technical effect, so it will not be described again here.

[0066] Example 3

[0067] Figure 3 This is a schematic diagram of the structure of an electronic device according to a preferred embodiment of the present invention. Figure 3 As shown, the electronic device includes one or more processors 301 and memory 302.

[0068] The processor 301 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0069] The memory 302 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 301 may execute the program instructions to implement the ultra-high voltage primary and secondary equipment parasitic loop detection methods and / or other desired functions described in the various embodiments disclosed above. In one example, the electronic device may also include an input device 303 and an output device 304, these components being interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0070] In addition, the input device 303 may also include, for example, a keyboard, a mouse, etc.

[0071] The output device 304 can output various information to the outside. The output device 304 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0072] Of course, for the sake of simplicity, Figure 3 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0073] Example 4

[0074] In addition to the methods and devices described above, embodiments of this disclosure may also be computer program products, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for detecting parasitic circuits in ultra-high voltage primary and secondary equipment according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0075] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0076] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for detecting parasitic circuits in ultra-high voltage primary and secondary equipment according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0077] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0078] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0079] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0080] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0081] The apparatus and methods of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0082] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps are decomposable and / or recombinable. Such decomposition and / or recombination should be considered equivalent to the present disclosure. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0083] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for detecting a parasitic loop of an ultra-high voltage primary and secondary device, characterized in that, The method comprises: An external detection head is used to collect electrical signals by contacting nodes of the parasitic loop of the ultra-high voltage primary and secondary equipment, wherein the external detection head is electrically connected with an ADC, a voltage / current sensor and a signal conditioning circuit of the parasitic loop special detection circuit; When receiving a level jump signal of the opening and closing of the ultra-high voltage primary equipment transmitted by the GPIO interface, a hardware interrupt is generated as a trigger event; In response to the hardware interrupt, the ADC is switched to the highest sampling rate mode, and high-speed parallel sampling of the parasitic loop special detection circuit is started, and multiple parallel data are generated based on the electrical signals; According to the multiple parallel data, a parasitic loop diagnostic algorithm model is run for fusion analysis to generate a diagnostic result and a confidence level corresponding to the diagnostic result; According to the diagnostic result, the confidence level and the multiple parallel data, a risk assessment result and a treatment strategy are generated according to a pre-set risk assessment matrix and a treatment strategy library.

2. The method of claim 1, wherein, Before generating the hardware interrupt when receiving the level jump signal of the opening and closing of the ultra-high voltage primary equipment transmitted by the GPIO interface, it further comprises: An adaptive initialization process is performed, a self-checking and calibration algorithm is called, and zero drift calibration and accuracy verification are performed on the voltage / current sensor; According to the real-time environmental temperature and power grid operation state read, detection parameters and parasitic loop diagnostic algorithm models suitable for the current working condition are loaded from the pre-set strategy library.

3. The algorithm of claim 2, wherein, According to the multiple parallel data, a parasitic loop diagnostic algorithm model is run for fusion analysis to generate a diagnostic result and a confidence level corresponding to the diagnostic result, comprising: Feature signals of the multiple parallel data are extracted; According to the feature signals, a parasitic loop diagnostic algorithm model is run for fusion waveform analysis, frequency spectrum analysis, time sequence analysis and time sequence correlation analysis to generate a diagnostic result, wherein the diagnostic result includes existence of a fault and non-existence of a fault; when the diagnostic result is existence of a fault, the diagnostic result further includes a fault type and a fault location, the fault type includes a direct grounding fault, an alternating current intrusion fault, a direct current interconnection fault, and a composite fault of at least two of the above three faults; when the fault type is a branch-level fault, the fault location is determined as a specific branch where the fault occurs, and when the fault type is a system-level fault, the fault location is determined as two or more sets of direct current systems where the fault occurs; According to the intensity of the feature signals, the degree of coincidence between the feature signals, and the time synchronization accuracy of the feature signals and the trigger event, a confidence level corresponding to the diagnostic result is generated based on a pre-set confidence level assignment rule.

4. The method of claim 1, wherein, According to the diagnostic result, the confidence level and the multiple parallel data, a risk assessment result and a treatment strategy are generated according to a pre-set risk assessment matrix and a treatment strategy library, comprising: The diagnostic result, the confidence level and the multiple parallel data are compared with corresponding items in the risk assessment matrix to determine a risk level; According to the treatment strategy in the treatment strategy library corresponding to the risk level, a diagnostic report, local alarm information and remote alarm information are generated.

5. The method of claim 1, wherein, The method further comprises establishing a connection with the cloud through an Ethernet interface or a wifi module, uploading the stored detection data and the generated diagnostic cases to the cloud, and downloading a new algorithm model, an optimization strategy or a software upgrade package to update the host program.

6. The method of claim 1, wherein, The method further comprises communicating with a remote control platform through an Ethernet interface, receiving a remote instruction as a trigger event to start the high-speed parallel sampling of the parasitic loop dedicated detection circuit, and generating multiple parallel data based on the electrical signal.

7. A device for detecting a parasitic loop of an ultra-high voltage primary and secondary equipment, characterized in that, The device is a circuit integrated box structure, including a host and an external detection head, wherein: The external detection head is connected to the node of the parasitic loop to be detected of the ultra-high voltage primary and secondary equipment for collecting original electrical signals, and the external detection head is electrically connected to the ADC, voltage / current sensor and signal conditioning circuit of the parasitic loop dedicated detection circuit inside the host; The side of the host is also provided with a GPIO interface for transmitting the level jump signal of the opening and closing of the ultra-high voltage primary equipment; The host further includes an embedded CPU with a built-in host program, which generates a hardware interrupt as a trigger event when the level jump signal is received; in response to the hardware interrupt, the ADC is switched to the highest sampling rate mode, and the high-speed parallel sampling of the parasitic loop dedicated detection circuit is started to generate multiple parallel data based on the electrical signal; according to the multiple parallel data, the parasitic loop diagnostic algorithm model is run for fusion analysis to generate a diagnostic result and a confidence degree corresponding to the diagnostic result; according to the diagnostic result, the confidence degree and the multiple parallel data, a risk assessment result and a disposal strategy are generated according to a pre-set risk assessment matrix and disposal strategy library.

8. The apparatus of claim 7, wherein, An IPS touch capacitive screen is installed on the top of the host for providing human-computer interaction services based on the host program; The host is provided with a wifi module for communication with the cloud or a remote platform; The side of the host is also provided with a USB interface, an Ethernet interface, a Micro SD card interface, an HDMI interface, a power supply interface and an alarm signal lamp, wherein the USB interface, the Ethernet interface and the Micro SD card interface are used for bidirectional data transmission, the HDMI interface is used for projecting the visualization capability of the device to other display devices, the power supply interface is used for powering the device, and the alarm signal lamp is electrically connected to the parasitic loop dedicated detection circuit and driven to alarm according to the diagnostic result.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by a processor to implement the steps of the method of any one of claims 1-6.

10. An electronic device, comprising: It comprises: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the executable instructions to implement the steps of the method of any one of claims 1-6.

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