Multi-channel synchronous double-pulse test system and test equipment

Abstract

The invention relates to the technical field of electronics, and discloses a multichannel synchronous double-pulse test system and test equipment, and the system comprises a test host unit, a synchronous trigger main line unit, a six-channel test channel unit, a centralized collection unit, and a cloud unit. After the test host unit generates a double-pulse signal, the signal is synchronously transmitted to the six-path test channel unit by the synchronous trigger main line unit, so that the parallel test of six paths of tested devices is realized; the six test channel units apply driving signals to the six tested devices at the same time to complete testing and cooperate with the centralized acquisition unit to synchronously acquire six test data, and the cloud unit generates a test result based on the synchronous data acquired in a centralized manner; according to the multi-channel synchronous double-pulse test system, through cooperation of all the units, the dynamic test efficiency of the power module is effectively improved, and the test requirement of a large-scale production line is met.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a multi-channel synchronous dual-pulse test system and test equipment. Background Technology

[0002] Currently, the dynamic testing of power modules commonly uses a single-channel dual-pulse instrument combined with manual wiring for testing. This testing method can only test one IGBT or FRD device at a time. When the test object is six devices in a three-phase full-bridge structure, manual wiring is required at least five times. This is not only cumbersome to operate, but also makes the single test cycle longer. Furthermore, due to the lack of a unified synchronous transmission and centralized acquisition mechanism, it is impossible to achieve parallel testing of multiple devices and synchronous data analysis, which seriously restricts the efficiency and large-scale application requirements of dynamic testing of power modules. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to solve at least one of the technical problems mentioned above.

[0004] The solution to the technical problem of this invention is: A first aspect of the present invention provides a multi-channel synchronous dual-pulse test system, comprising: The system comprises a test host unit, a synchronous triggering mainline unit, a six-channel test unit, a centralized acquisition unit, and a cloud unit. The test host unit is electrically connected to the synchronous triggering mainline unit, which is electrically connected to the six-channel test unit. The six-channel test unit is electrically connected to the centralized acquisition unit, and the centralized acquisition unit is electrically connected to the cloud unit. The test host unit generates a dual-pulse signal. The synchronous triggering mainline unit synchronously transmits the dual-pulse signal to the six-channel test unit. The six-channel test unit applies a drive signal to the device under test (DUT) to complete the test. The centralized acquisition unit acquires the test data from the six-channel test unit. The cloud unit generates test results based on the test data.

[0005] The beneficial effects of the first aspect of the present invention are as follows: In the multi-channel synchronous dual-pulse test system of the present invention, after the test host unit generates a dual-pulse signal, the synchronous triggering main line unit synchronously transmits the signal to the six test channel units, avoiding the limitation of traditional single-channel architecture requiring testing one channel at a time, and realizing parallel testing of six devices under test; secondly, the six test channel units can simultaneously apply drive signals to the six devices under test to complete the test, and with the synchronous acquisition of six test data by the centralized acquisition unit, the overall test cycle of the three-phase full bridge is significantly shortened; finally, the cloud unit generates test results based on the synchronously acquired data; the multi-channel synchronous dual-pulse test system of the present invention effectively improves the dynamic testing efficiency of power modules through the cooperation of each unit, meeting the testing needs of large-scale production lines.

[0006] As some sub-solutions of the above technical solution, the test host unit includes a pulse generator and a synchronization distributor; the pulse generator is electrically connected to the synchronization distributor; the synchronization distributor is electrically connected to the synchronization trigger main unit; the pulse generator is used to generate a dual-pulse signal; the synchronization distributor is used to copy the dual-pulse signal into six initial pulse signals with consistent characteristics.

[0007] As some sub-solutions of the above technical solution, the pulse generator includes a DSP chip; the synchronization distributor includes an FPGA chip; the DSP chip is electrically connected to the FPGA chip, and the FPGA chip is electrically connected to the synchronization triggering main unit; the DSP chip is used to generate a dual-pulse signal according to the test parameters sent by the cloud unit, and transmit the dual-pulse signal to the FPGA chip; the FPGA chip includes a six-channel DDS counter and a system clock, the six-channel DDS counter is used to copy the dual-pulse signal into six initial pulse signals, and the system clock is used to perform timing calibration on the six initial pulse signals.

[0008] As some sub-solutions of the above technical solution, the synchronous triggering mainline unit includes a fan-out buffer and a delay-locked loop; the FPGA chip is electrically connected to the fan-out buffer, the fan-out buffer is electrically connected to the delay-locked loop, and the delay-locked loop is electrically connected to the six-channel test channel unit; the fan-out buffer is used to convert the six initial pulse signals output by the FPGA chip into six low-skew differential signals, and the delay-locked loop is used to perform delay compensation on the six low-skew differential signals.

[0009] As some sub-solutions of the above technical solution, the six-channel test unit includes an LVDS receiver and six parallel test circuits; the LVDS receiver is electrically connected to each of the six test circuits, and the six test circuits are electrically connected to the centralized acquisition unit; all the test circuits include a relay matrix switch, a driver IC, and a current sensor connected in sequence; the LVDS receiver is used to convert the low-skew differential signal output by the synchronous triggering main unit into a single-ended signal; the relay matrix switch is used to switch the electrode connection state of the device under test according to the single-ended signal to realize different test modes; the driver IC is used to convert the switched signal into a drive signal adapted to the device under test; and the current sensor is used to acquire the current signal generated by the device under test during the test.

[0010] As some sub-solutions of the above technical solution, the centralized acquisition unit includes an ADC module and a delay line; the current sensors of the six test circuits are electrically connected to the ADC module, the ADC module is electrically connected to the delay line, and the delay line is electrically connected to the cloud unit; the ADC module is used to synchronously acquire the electrical signals output by the six test circuits and convert them into digital signals; the delay line is used to perform timing alignment processing on the digital signals.

[0011] As some sub-solutions of the above technical solution, the cloud unit includes: a communication interface module and a host computer; the delay line is electrically connected to the host computer through the communication interface module; the communication interface module is used to realize bidirectional data transmission between the centralized acquisition unit and the host computer; the host computer is used to configure the test parameters required for the test process and generate test results based on the data received from the centralized acquisition unit.

[0012] A second aspect of the present invention provides a testing device, the testing device comprising the multi-channel synchronous dual-pulse testing system as described above.

[0013] The testing equipment according to the second aspect of the present invention, since it includes the multi-channel synchronous dual-pulse testing system of the above-described technical solution, also has corresponding beneficial effects. Attached Figure Description

[0014] Figure 1 This is a system block diagram of the multi-channel synchronous dual-pulse test system provided by the present invention; Figure 2 This is a schematic diagram of the structure of a multi-channel synchronous dual-pulse test system; Figure 3 This is a schematic diagram of a matrix switch. Figure 4 This is a representation of the address function of the matrix switch; Figure 5 This is a relay truth table logic diagram.

[0015] The reference numerals in the attached figures are as follows: 100-Test host unit, 110-Pulse generator, 120-Synchronizer distributor, 200-Synchronizer trigger main line unit, 210-Fan-out buffer, 220-Delay lock loop, 300-Six-channel test unit, 310-LVDS receiver, 320-Test circuit, 321-Matrix switch, 322-Driver IC, 323-Current sensor, 400-Central acquisition unit, 410-ADC module, 420-Delay line, 500-Cloud unit, 510-Communication interface module, 520-Host computer. Detailed Implementation

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments have been briefly explained above. Obviously, the described drawings are only a part of the embodiments of the present invention, and not all of them. Those skilled in the art can obtain other design schemes and drawings based on these drawings without creative effort.

[0017] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages mentioned herein do not simply refer to direct connection of components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0018] Reference Figures 1 to 5 The first aspect of the present invention will be described; A first aspect of the present invention provides a multi-channel synchronous dual-pulse test system, comprising: The system comprises a test host unit 100, a synchronous triggering main line unit 200, a six-channel test unit 300, a centralized acquisition unit 400, and a cloud unit 500. The test host unit 100 is electrically connected to the synchronous triggering main line unit 200, which is electrically connected to the six-channel test unit 300. The six-channel test unit 300 is electrically connected to the centralized acquisition unit 400, and the centralized acquisition unit 400 is electrically connected to the cloud unit 500. The test host unit 100 generates a dual-pulse signal. The synchronous triggering main line unit 200 synchronously transmits the dual-pulse signal to the six-channel test unit 300. The six-channel test unit 300 applies a drive signal to the device under test (DUT) to complete the test. The centralized acquisition unit 400 acquires the test data from the six-channel test unit 300. The cloud unit 500 generates test results based on the test data.

[0019] In the multi-channel synchronous dual-pulse test system of the present invention, after the test host unit 100 generates a dual-pulse signal, the synchronous triggering main line unit 200 synchronously transmits the signal to the six-channel test unit 300, avoiding the limitation of traditional single-channel architecture requiring test one channel at a time, and realizing parallel testing of six devices under test; secondly, the six-channel test unit 300 can simultaneously apply drive signals to the six devices under test to complete the test, and with the synchronous acquisition of the six test data by the centralized acquisition unit 400, the overall test cycle of the three-phase full bridge is significantly shortened; finally, the cloud unit 500 generates test results based on the synchronously acquired data; the multi-channel synchronous dual-pulse test system of the present invention effectively improves the dynamic testing efficiency of power modules through the cooperation of each unit, meeting the testing needs of large-scale production lines.

[0020] Specifically, the test host unit 100 includes a pulse generator 110 and a synchronization distributor 120; the pulse generator 110 is electrically connected to the synchronization distributor 120; the synchronization distributor 120 is electrically connected to the synchronization trigger main unit 200; the pulse generator 110 is used to generate a dual-pulse signal; the synchronization distributor 120 is used to copy the dual-pulse signal into six initial pulse signals with consistent characteristics.

[0021] Specifically, the pulse generator 110 includes a DSP chip; the synchronization distributor 120 includes an FPGA chip; the DSP chip is electrically connected to the FPGA chip, and the FPGA chip is electrically connected to the synchronization triggering main unit 200; the DSP chip is used to generate a dual-pulse signal according to the test parameters sent by the cloud unit 500, and transmit the dual-pulse signal to the FPGA chip; the FPGA chip includes a six-channel DDS counter and a system clock, the six-channel DDS counter is used to copy the dual-pulse signal into six initial pulse signals, and the system clock is used to perform timing calibration on the six initial pulse signals.

[0022] Specifically, the synchronous triggering main unit 200 includes a fan-out buffer 210 and a delay-locked loop 220; the FPGA chip is electrically connected to the fan-out buffer 210, the fan-out buffer 210 is electrically connected to the delay-locked loop 220, and the delay-locked loop 220 is electrically connected to the six-channel test channel unit 300; the fan-out buffer 210 is used to convert the six initial pulse signals output by the FPGA chip into six low-skew differential signals, and the delay-locked loop 220 is used to perform delay compensation on the six low-skew differential signals.

[0023] Specifically, the six-channel test unit 300 includes an LVDS receiver 310 and six parallel test circuits 320; the LVDS receiver 310 is electrically connected to each of the six test circuits 320, and the six test circuits 320 are electrically connected to the centralized acquisition unit 400; all the test circuits 320 include a relay matrix switch 321, a driver IC 322, and a current sensor 323 connected in sequence; the LVDS receiver 310 is used to convert the low-skew differential signal output by the synchronous triggering main unit 200 into a single-ended signal; the relay matrix switch 321 is used to switch the electrode connection state of the device under test according to the single-ended signal to realize different test modes; the driver IC 322 is used to convert the switched signal into a drive signal adapted to the device under test; and the current sensor 323 is used to collect the current signal generated by the device under test during the test.

[0024] Specifically, the centralized acquisition unit 400 includes an ADC module 410 and a delay line 420; the current sensors 323 of the six test circuits 320 are electrically connected to the ADC module 410, the ADC module 410 is electrically connected to the delay line 420, and the delay line 420 is electrically connected to the cloud unit 500; the ADC module 410 is used to synchronously acquire the electrical signals output by the six test circuits 320 and convert them into digital signals; the delay line 420 is used to perform timing alignment processing on the digital signals.

[0025] Specifically, the cloud unit 500 includes a communication interface module 510 and a host computer 520; the delay line 420 is electrically connected to the host computer 520 through the communication interface module 510; the communication interface module 510 is used to realize bidirectional data transmission between the centralized acquisition unit 400 and the host computer 520; the host computer 520 is used to configure the test parameters required for the test process and generate test results based on the data received from the centralized acquisition unit 400.

[0026] The following examples are described in three parts: system structure, signal flow, and specific testing principles.

[0027] See Figure 1 and Figure 2 In this embodiment, the structure of each unit in the multi-channel synchronous double-pulse test system is as follows: The test host unit 100 serves as the signal generation core of the system, responsible for generating dual-pulse signals. Specifically, the test host unit 100 includes a pulse generator 110 and a synchronization distributor 120, which are electrically connected via high-speed signal lines on the PCB board to jointly generate and initially synchronize the dual-pulse signals. Pulse Generator 110: Employs a TMS320F28388D DSP chip, which integrates an ePWM (enhanced pulse width modulation) module. Based on test parameters (such as pulse frequency 100kHz-1MHz, pulse width 100ns-1μs, amplitude 5V-12V) sent from the cloud unit 500, it generates a high-precision, high-stability standard dual-pulse signal. To ensure signal quality, Pulse Generator 110 also integrates a front-end filter circuit (composed of a 0.1μF ceramic capacitor and a 10Ω current-limiting resistor), which filters out high-frequency noise in the signal, ensuring that the rise time and fall time of the output pulse are ≤10ns and the timing accuracy is controlled within ±1ns, providing a reliable trigger reference for the entire system. Synchronizer 120: Employs an XC7K325T FPGA chip, which is electrically connected to the DSP chip of pulse generator 110 via an SPI interface. The FPGA chip internally deploys six independent DDS (Direct Digital Synthesis) counters and a 100MHz high-precision system clock (using a temperature-compensated crystal oscillator with a frequency stability of ±5ppm). The DDS counters can accurately replicate the single-channel dual-pulse signal output by the DSP chip into six initial pulse signals. The system clock then provides a synchronous clock reference for the six DDS counters. Through the timing calibration logic inside the FPGA, the phase deviation of the six initial pulse signals is controlled within 50ps, ensuring that the frequency, amplitude, and pulse width of each signal are completely consistent, laying the foundation for further calibration of the subsequent synchronous triggering main unit 200.

[0028] The synchronous triggering main line unit 200 serves as a signal transmission bridge connecting the test host unit 100 and the six-channel test unit 300, and is used to synchronously transmit dual pulse signals. The synchronous triggering main line unit 200 includes a fan-out buffer 210 and a delay lock ring 220, which are electrically connected through equal-length wiring on the PCB board. Fan-out buffer 210: A low-voltage differential signal buffer of model CDCVF2310 is selected. Its input terminal is electrically connected to the output terminal of the FPGA chip of the synchronization distributor 120. It can convert the six initial pulse signals output by the FPGA chip into LVDS (low-voltage differential signal) format. The fan-out buffer 210 supports a maximum signal transmission frequency of 200MHz, output skew <50ps, and has 8kV ESD protection capability. It can effectively enhance the signal driving capability, avoid signal attenuation or distortion during long-distance transmission, and ensure that key parameters such as amplitude, rise / fall time and other parameters of each signal remain stable. Delay Locking Loop 220: It uses six independent DLL chips of model IDT8T49N104, which are electrically connected to the six output terminals of the fan-out buffer 210 respectively. The output terminals are directly connected to the six test channel unit 300. Each DLL chip supports a delay adjustment in 25ps steps. Through the calibration command issued by the FPGA chip via the bus, the transmission delay caused by the difference in PCB wiring length and the discreteness of device parameters can be compensated in real time.

[0029] The six-channel test unit 300 is used to apply drive signals to the device under test to complete the test. It contains six test channels with the same structure and independent from each other. Each channel integrates an LVDS receiver 310, a matrix switch 321, a driver IC 322 and a current sensor 323. The components in the unit are electrically connected through dedicated signal links on the PCB board. LVDS Receiver 310: An isolated LVDS receiver 310 of model ISO5852S is adopted. Its input terminal is electrically connected to the output terminal of the delay-locked loop 220 of the synchronous trigger main line unit 200. It can convert the received LVDS differential signal into a 3.3V single-ended signal and achieve 2.5kVrms electrical isolation at the same time. This avoids interference from the high-voltage test environment (maximum test voltage 1200V) of the six-channel test unit 300 on the synchronous trigger signal and ensures the integrity of the trigger signal. Matrix switch 321: Composed of nine G6K-2F-Y miniature relays forming a 3×3 matrix structure, its input is electrically connected to the output of LVDS receiver 310, and its output is connected to driver IC 322. Under the control of the FPGA chip (control signal conversion is achieved through a 74HC138 decoder and a ULN2803 driver chip), matrix switch 321 can flexibly switch the on / off states of the relays to achieve precise connection of the collector, gate, and emitter of the device under test (IGBT / SiC / GaN / FRD). For example, in the upper bridge test mode, relays K11, K22, and K33 are closed, routing the drive signal to the collector, gate, and emitter of the device under test; in the lower bridge test mode, relays K12, K23, and K31 are closed, completing the electrode connection switching to meet the testing requirements of different types of devices. Driver IC322: Electrically connected to the output of matrix switch 321, using the same ISO5852S chip as the LVDS receiver 310 (with high-side / low-side drive function), it converts the single-ended signal output by matrix switch 321 into a drive signal adapted to the device under test. For IGBT devices, the high-side drive (HO) signal output by driver IC322 has an amplitude of 15V, and the low-side drive (LO) signal has an amplitude of 0V, with a rise time ≤50ns and a fall time ≤50ns. For SiC / GaN devices, the pre-charge / pre-discharge current of the drive signal (maximum ±2A) can be configured via FPGA to ensure reliable device turn-on and turn-off, while avoiding damage to the device under test due to overvoltage or overcurrent. Current sensor 323: The current sensor 323 is a coreless current sensor based on Rogowski coil with a bandwidth of 50MHz. The input is connected in series in the collector circuit of the device under test, and the output is connected to the analog acquisition module. The current sensor 323 can acquire the collector current (Ic) signal of the device under test in real time during dynamic testing and convert it into a voltage signal of 0-5V, providing accurate current information for subsequent data acquisition.

[0030] The centralized acquisition unit 400 is used to acquire test data from the six-channel test unit 300; the centralized acquisition unit 400 includes an analog signal acquisition module (ADC) and a delay line 420; Analog Input / Output Module (ADC): Each channel is equipped with one ADS8688 16-bit 10MS / s high-speed ADC. The input terminals are electrically connected to the output terminal of the current sensor 323, the collector-emitter (Vce) and gate-emitter (Vge) pins of the device under test (the signal amplitude is matched by the front-end conditioning circuit, which divides the Vce signal to 0-5V and clamps the Vge signal (-10V-20V) to 0-5V). The ADC is electrically connected to the centralized acquisition unit 400 in a daisy-chain configuration via the SPI interface. It can simultaneously acquire three analog signals (Ic, Vce, and Vge) and convert them into digital signals. The sampling rate is 10MS / s and the resolution is 16-bit, ensuring accurate capture of rapid signal changes during the switching process of power devices. On the other hand, an FPGA chip of model XC7K325T is used, which is electrically connected to the ADC module 410 through the SPI daisy-chain port. It can simultaneously receive digital signals uploaded by six ADCs (each signal contains three digital signals: Ic, Vce, and Vge). The FPGA chip integrates a data buffer to perform real-time buffering and preliminary processing of the received digital signals to ensure data integrity and consistency and avoid data loss due to mismatch in data transmission rates. Delay line 420: Based on the 256-tap delay line 420 built into the FPGA chip and the cross-correlation algorithm, it can perform precise timing calibration of six digital signals. First, the characteristic points of each signal (such as the voltage drop time of the Vce signal and the current rise time of the Ic signal) are extracted, the timing deviation between each channel is automatically calculated, and the signal is compensated and adjusted through the delay line 420. In practical applications, the deviation of the six waveform data on the time axis after timing alignment can be controlled within 100ps, ensuring the comparability of test data of different channels and providing a synchronous basis for subsequent data analysis of the cloud unit 500.

[0031] The cloud unit 500 is the control and data processing center of the system. It consists of two parts: a communication interface module 510 and a host computer 520, which are electrically connected via USB 3.0 or Gigabit Ethernet cable. High-speed communication interface: It adopts a USB 3.0 interface chip (model CYUSB3014) or a gigabit Ethernet chip (model W5500) to be electrically connected to the high-speed data port of the FPGA chip, and the output end is connected to the host computer 520 / cloud; the high-speed communication interface can efficiently and reliably transmit six timing-aligned digital signals to the host computer 520 / cloud. The Host Computer 520, built on an industrial-grade computer, is used for real-time processing and in-depth analysis of large amounts of collected test data. Through comprehensive analysis of multi-dimensional data such as Vce, Vge, and Ic, it calculates key performance parameters of power devices, such as turn-on time (Ton), turn-off time (Toff), turn-on loss (Eon), turn-off loss (Eoff), and reverse recovery charge (Qrr), helping users quickly understand the dynamic performance and operating status of power devices. After testing, the Host Computer 520 automatically generates detailed test results based on preset templates. The test results include basic test information (such as test time, test personnel, test equipment, etc.), test parameter settings, test result data, and key waveform screenshots, facilitating user traceability and comparative analysis of test results and providing strong data support for product quality assessment and R&D improvement.

[0032] In this embodiment, the signal flow between the units within the multi-channel synchronous dual-pulse test system is as follows: The DSP chip inside the test host unit 100 receives the test parameters sent by the cloud unit 500 and generates a single-ended standard double pulse signal through the internal timer and comparator logic. The FPGA chip of the synchronous distributor 120 receives the single-channel dual-pulse signal output by the DSP chip; the FPGA chip deploys 6 independent DDS counters, which are based on the 100MHz system clock, synchronously capture the rising and falling edges of the input pulse, and accurately copy the single pulse into six initial pulse signals through phase-locked logic. The fan-out buffer 210 of the synchronous trigger main unit 200 receives six initial pulse signals output by the FPGA chip and converts them into LVDS (Low Voltage Differential Signal) format; Six LVDS signals are output from the fan-out buffer 210 and then connected to six independent delay-locked loops 220 respectively. The FPGA chip sends delay compensation parameters (based on PCB trace length differences) to each delay-locked loop 220 via the bus. The delay-locked loop 220 performs delay calibration on each signal in 25ps increments. The calibrated six LVDS signals are respectively distributed to the LVDS receivers 310 of the six test channel units 300, with each receiver corresponding to one test channel; the LVDS receivers 310 convert the differential signals into single-ended trigger signals. Each test channel's 3×3 relay matrix switch 321 receives a single-ended trigger signal from the LVDS receiver 310, and simultaneously receives a three-bit binary address control signal from the FPGA chip (converted into relay drive current via a 74HC138 decoder and a ULN2803 driver chip) to complete the electrode connection of the test circuit 320. Taking the three-phase full-bridge IGBT test as an example: when the address signal is "001", the 74HC138 decoder outputs a low-level signal, and the ULN2803 amplifies the signal into a 500mA drive current, activating the closing of relays K11, K22, and K33. K11 closing enables the high-side voltage (HO_H=15V) to connect to the collector of the device under test, K22 closing enables the gate voltage (HO_G=15V) to connect to the gate of the device under test, and K33 closing enables the low-side voltage (LO_L=0V) to connect to the emitter of the device under test, completing the electrode connection configuration for the bridge test. After the matrix switch 321 completes the electrode connection, its output signal is connected to the isolation driver IC 322. The driver IC 322 converts the signal output by the matrix switch 321 into an appropriate drive signal according to the type of the device under test (IGBT / SiC / GaN). The drive signal is transmitted to the gate and emitter of the device under test through a dedicated power link on the PCB board, so as to realize precise control of the device's turn-on / turn-off. The ADC module 410 of the six-channel test unit 300 acquires three key electrical signals of the device under test: collector-emitter voltage Vce, gate-emitter voltage Vge, and collector current Ic. The ADC module 410 samples the three signals synchronously and uploads them to the FPGA chip in the centralized acquisition unit 400 in a daisy chain via the SPI interface. After the FPGA chip of the centralized acquisition unit 400 receives the digital data uploaded by the six-channel ADC module 410, it performs timing calibration on each channel of data through the built-in 256-tap delay line 420; it uses a cross-correlation algorithm to extract the voltage drop feature points of each Vce signal (corresponding to the device turn-on time), and uses this as a reference to calculate the timing deviation of each channel's data. If the data of a certain channel has a delay compared with the reference channel, the corresponding delay is added to the data of that channel through the delay line 420 to align the feature points of the six channels of data. The FPGA chip of the centralized acquisition unit 400 packages the timing-aligned six channels of digital data into Ethernet data packets, which are then uploaded to the host computer 520 or the cloud via the communication interface module 510. The host computer 520 or the cloud then generates test results based on the six channels of digital data.

[0033] See Figures 3 to 5 In this embodiment, the specific testing principle of the multi-channel synchronous dual-pulse test system is as follows: Matrix switches 321 (K1 to K6) are the core execution components of the six-channel test unit 300. Each matrix switch 321 includes drive terminal row lines, DUT terminal column lines, and cross relays, as follows: The three horizontally arranged rows (driving ends) serve as driving signal inputs for the matrix switch 321, corresponding to... Figure 3 The functions of each row line from "R1-R3" are as follows: R1 VOUT_H (row 1) corresponds to the high-side drive voltage output terminal (HO_H), which provides a high-potential drive signal to the DUT; R2VOUT_G (row 2) corresponds to the gate-dedicated drive voltage output terminal (HO_G), which controls the DUT gate to turn on / off; R3 VOUT_L (row 3) corresponds to the low-side drive voltage output terminal (LO_L), which serves as the ground terminal of the drive loop to form current return; Three vertically arranged column lines (DUT electrode terminals) are used to connect to the electrodes of the device under test (IGBT / SiC / GaN / FRD), corresponding to... Figure 3 The “C1-C3” columns correspond to fixed electrodes: C1 (column 1) corresponds to the collector (C) connection terminal of the DUT and is connected to the main current loop; C2 (column 2) corresponds to the gate (G) connection terminal of the DUT and only receives the gate control signal; C3 (column 3) corresponds to the emitter (E) connection terminal of the DUT and serves as the current return terminal. A cross relay consists of nine relays Kxy (model G6K-2F-Y) located at the intersection of a row and a column line. Kxy represents the relay at the intersection of the x-th row and the y-th column. For example: K11: A relay that intersects row 1 (R1 VOUT_H) and column 1 (C1, collector). When closed, it connects the high-side drive signal to the collector of the DUT. K22: A relay that intersects row 2 (R2 VOUT_G) and column 2 (C2, gate). When closed, it connects the gate drive signal to the DUT gate. K33: A relay that intersects row 3 (R3 VOUT_L) and column 3 (C3, emitter). When closed, it connects the low-side drive signal to the emitter of the DUT. See Figure 4 and 5 The matrix switch 321 achieves adaptation to different power devices and different test scenarios through the closed combination of the row-column relays described above. The correspondence between the matrix switch 321 and the three-bit address code output by the FPGA is as follows: Address code 000 corresponds to the function mode of full disconnect (idle), all relays are disconnected, and there is no connection between row and column lines to avoid DUT being mistakenly connected to drive signals; Address code 001 corresponds to the IGBT test of the upper bridge function mode. Close the three relays K11, K22 and K33. K11 (R1→C1) supplies power to the collector, K22 (R2→C2) supplies power to the gate, and K33 (R3→C3) grounds the emitter, forming the IGBT turn-on circuit. Address code 010 corresponds to the bridge IGBT test in the functional mode. Close the three relays K12, K23 and K31. K12 (R1→C2) supplies power to the gate, K23 (R2→C3) supplies power to the emitter, and K31 (R3→C1) grounds the collector to adapt to the lower bridge layout. Address code 011 corresponds to the FRD forward test function mode. When the three relays K13, K21 and K32 are closed, K13 (R1→C3) supplies power to the emitter, K21 (R2→C1) supplies power to the collector, and K32 (R3→C2) grounds the gate, forming the FRD forward conduction circuit. Address code 100 corresponds to the FRD reverse test function mode. Close three relays K13, K31 and K22. K13 (R1→C3) supplies power to the emitter, K31 (R3→C1) grounds the collector, and K22 (R2→C2) supplies power to the gate, thus constructing the FRD reverse blocking circuit. Address code 101 corresponds to the GE short-circuit protection mode, which closes relay K32; K32 (R3→C2) grounds the gate, shorts the gate-emitter junction of the DUT, quickly discharges the gate charge, and prevents overcurrent damage.

[0034] The above describes the specific structure of the matrix switch 321. The following section explains the control logic of the matrix switch 321 from the FPGA chip instructions to the relay action. The specific flow is as follows: The FPGA chip generates a three-bit binary address control signal in its internal logic circuit according to the test mode instructions issued by the cloud unit 500. The 74HC138 decoder receives a three-bit binary address control signal. When the enable pin is active, it is decoded into eight low-level active strobe signals. The 3×3 relay matrix switch 321 only requires six operating modes (full open, upper bridge test, lower bridge test, FRD forward test, FRD reverse test, GE short circuit protection). Therefore, of the eight outputs of the 74HC138, only six are used to drive the relay combination of the corresponding mode, and the remaining two are in standby mode. The ULN2803 eight-channel Darlington driver chip converts the decoded low-level signal into a high drive current of 500mA / 12V; The relay is tested under the drive of the drive current.

[0035] The following section uses the IGBT test and GE short-circuit protection test as examples to illustrate the specific implementation process of testing the matrix switch 321: Example of IGBT test on bridge: The user selects "IGBT test" through the host computer 520. The host computer 520 sends instructions to the FPGA chip, and the FPGA chip generates a three-bit address code "001". After the address code "001" is decoded by the 74HC138 decoder, the first drive channel of the ULN2803 eight-channel Darlington driver chip is activated, and a 500mA / 12V current is output to drive relays K11, K22, and K33 to close (the other relays remain open). K11 (row 1-column 1) closed: row line R1 (high-side drive output HO_H) and column line C1 (DUT collector) are connected, providing a high-potential drive voltage for the collector of the upper bridge IGBT; K22 (row 2 - column 2) closed: row line R2 (gate drive output HO_G) and column line C2 (DUT gate) are connected, and an on signal is input to the IGBT gate; K33 (row 3-column 3) closed: row line R3 (low-side drive output LO_L) and column line C3 (DUT emitter) are connected, grounding the IGBT emitter and forming a current return path; The drive current flows from R1→K11→C1 (collector)→IGBT interior→C3 (emitter)→K33→R3 (ground). The IGBT completes the turn-on / turn-off operation under the control of the gate signal. At the same time, the ADC module 410 synchronously acquires the collector-emitter voltage (Vce) between C1 and C3 and the gate-emitter voltage (Vge) between C2 and C3. The collector current (Ic) acquired by the current sensor 323 realizes the dynamic characteristic test of the IGBT.

[0036] GE short-circuit protection implementation example: When the current sensor 323 detects an overcurrent, or the ADC module 410 experiences an overvoltage, the centralized acquisition unit 400 uploads the abnormal data to the host computer. The host computer determines that protection needs to be activated and issues a "GE short circuit protection" command. After receiving the instruction, the FPGA chip generates the address code "101". After being decoded by the 74HC138 decoder, the K32 relay (row 3-column 2) closes; the row line R3 (LO_L) and the column line C2 (DUT gate) are connected, directly connecting the IGBT gate to the low potential ground; The gate charge of the IGBT is rapidly discharged through K32, and the gate-emitter voltage (Vge) drops quickly to below 0V. The IGBT is immediately turned off to avoid overcurrent / overvoltage causing the device to burn out.

[0037] In summary, the 3×3 relay matrix switch 321, as the core component of the multi-channel synchronous dual-pulse test system, achieves closed-loop test control logic based on a 3×3 row-column architecture, FPGA driver chip, and host computer. Nine relays cover six test modes, replacing the traditional forty-two relays, simplifying the circuit and improving integration. The test process requires no manual wiring changes; it is independently controlled by the FPGA chip, and the coordination of delay lines and the system clock ensures a time deviation of <100ps for all six channels, addressing the poor synchronization issue of traditional solutions. The host computer provides timely feedback based on the received test data, implementing short-circuit protection to ensure a safe and controllable test process.

[0038] A second aspect of the present invention provides a testing device, the testing device comprising the multi-channel synchronous dual-pulse testing system as described above.

[0039] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A multi-channel synchronous dual-pulse test system, characterized in that, include: The test host unit, synchronous trigger main line unit, six-channel test channel unit, centralized acquisition unit, and cloud unit are all included. The test host unit is electrically connected to the synchronous triggering main line unit, which is electrically connected to the six-channel test unit, which is electrically connected to the centralized acquisition unit, and the centralized acquisition unit is electrically connected to the cloud unit. The test host unit generates a dual-pulse signal. The synchronous triggering main line unit synchronously transmits the dual-pulse signal to the six-channel test unit. The six-channel test unit applies a drive signal to the device under test to complete the test. The centralized acquisition unit acquires the test data from the six-channel test unit. The cloud unit generates test results based on the test data.

2. The multi-channel synchronous dual-pulse test system according to claim 1, characterized in that: The test host unit includes a pulse generator and a synchronization distributor; the pulse generator is electrically connected to the synchronization distributor; the synchronization distributor is electrically connected to the synchronization trigger main unit; the pulse generator is used to generate a dual-pulse signal; the synchronization distributor is used to copy the dual-pulse signal into six initial pulse signals with consistent characteristics.

3. The multi-channel synchronous dual-pulse test system according to claim 2, characterized in that: The pulse generator includes a DSP chip; the synchronization distributor includes an FPGA chip; the DSP chip is electrically connected to the FPGA chip, and the FPGA chip is electrically connected to the synchronization triggering main unit; the DSP chip is used to generate a dual-pulse signal according to the test parameters sent by the cloud unit, and transmit the dual-pulse signal to the FPGA chip; the FPGA chip includes a six-channel DDS counter and a system clock, the six-channel DDS counter is used to copy the dual-pulse signal into six initial pulse signals, and the system clock is used to perform timing calibration on the six initial pulse signals.

4. The multi-channel synchronous dual-pulse test system according to claim 3, characterized in that: The synchronous triggering main unit includes a fan-out buffer and a delay-locked loop; the FPGA chip is electrically connected to the fan-out buffer, the fan-out buffer is electrically connected to the delay-locked loop, and the delay-locked loop is electrically connected to the six-channel test channel unit; the fan-out buffer is used to convert the six initial pulse signals output by the FPGA chip into six low-skew differential signals, and the delay-locked loop is used to perform delay compensation on the six low-skew differential signals.

5. The multi-channel synchronous dual-pulse test system according to claim 4, characterized in that: The six-channel test unit includes an LVDS receiver and six parallel test circuits. The LVDS receiver is electrically connected to each of the six test circuits, and the six test circuits are electrically connected to the centralized acquisition unit. All test circuits include a relay matrix switch, a driver IC, and a current sensor connected in sequence. The LVDS receiver converts the low-skew differential signal output by the synchronous triggering main unit into a single-ended signal. The relay matrix switch switches the electrode connection state of the device under test (DUT) according to the single-ended signal to achieve different test modes. The driver IC converts the switched signal into a drive signal adapted to the DUT. The current sensor acquires the current signal generated during the DUT's testing process.

6. The multi-channel synchronous dual-pulse test system according to claim 5, characterized in that: The centralized acquisition unit includes an ADC module and a delay line; the current sensors of the six test circuits are electrically connected to the ADC module, the ADC module is electrically connected to the delay line, and the delay line is electrically connected to the cloud unit; the ADC module is used to synchronously acquire the electrical signals output by the six test circuits and convert them into digital signals; the delay line is used to perform timing alignment processing on the digital signals.

7. The multi-channel synchronous dual-pulse test system according to claim 6, characterized in that: The cloud unit includes a communication interface module and a host computer; the delay line is electrically connected to the host computer through the communication interface module; the communication interface module is used to realize bidirectional data transmission between the centralized acquisition unit and the host computer; the host computer is used to configure the test parameters required for the test process and generate test results based on the data received from the centralized acquisition unit.

8. A testing device, characterized in that, The testing equipment includes the multi-channel synchronous double-pulse testing system as described in any one of claims 1-7.

Images