Chip failure analysis method and device

Abstract

The present disclosure provides a chip failure analysis method and device, which can solve the technical problem that related technologies cannot perform failure analysis on advanced processes. The method comprises: in the case of chip delayering to the contact layer, obtaining electrical measurement results by testing the combination of body diodes of a plurality of metal oxide semiconductor (MOS) tubes and testing the combination of MOS tubes and body diodes; and obtaining a chip failure analysis result according to the electrical measurement results. In the case of chip delayering to the contact layer (i.e. Via 0), the body diode effect of the MOS tube is utilized to directly determine whether Via 0 is abnormal through electrical measurement. The body diode of the MOS tube, the combination of the body diode and the MOS tube are utilized to quickly locate Via 0, and the chip failure analysis result is obtained. At most three pins are required for abnormal electrical testing, and the testing time is shortened by 50%. Furthermore, the carbon deposition on the surface of the sample is reduced, and the introduction of analysis noise is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of chip failure analysis technology, and in particular to a chip failure analysis method and apparatus. Background Technology

[0002] Failure analysis of chips is a crucial tool in the field of integrated circuits. It allows for the identification of the root causes of chip failures, helping to improve process yield and optimize chip design. As integrated circuit process nodes evolve, failure analysis methods also advance, with nanoprobes becoming an important tool for characterizing the electrical properties of metal-oxide-semiconductor (MOS) transistors and chips at abnormal points in advanced processes.

[0003] Currently, there are three main methods for failure analysis in mature manufacturing processes. The first is to directly remove the layer down to the metal 0 layer and test the electrical properties of a single metal-oxide-semiconductor (MOS) transistor at the metal 0 layer to help determine if the contact layer (Via 0) is functioning correctly. The second is to remove the layer down to the contact layer (Via 0) and use two combined tests, PG+PU and PG+PD, to identify abnormal circuits. The third is, if the Design for Testability (DFT) data is sufficiently clear, to directly perform destructive analysis such as transmission electron microscopy (TEM) on the target area.

[0004] However, in advanced processes, after the static random access memory (SRAM) is stripped down to the contact layer (Via 0), the metal-oxide-semiconductor (MOS) transistors are not independent of each other, making it impossible to measure their electrical properties individually. Abnormalities in the contact layer (Via 0) itself remain a core issue in failure analysis. Summary of the Invention

[0005] This disclosure provides a chip failure analysis method and apparatus, which can solve the technical problem that related technologies cannot perform failure analysis on advanced manufacturing processes.

[0006] In a first aspect, this disclosure provides a chip failure analysis method, which includes: obtaining electrical measurement results by combining and testing the body diodes of multiple metal-oxide-semiconductor (MOS) transistors and combining and testing the MOS transistors and body diodes when the chip is stripped down to the contact layer; and obtaining chip failure analysis results based on the electrical measurement results.

[0007] Based on the above description of the chip failure analysis method provided in the embodiments of this application, it can be seen that when the chip is delaminated to the contact layer (i.e., Via 0), the body diode effect of the MOSFET is utilized to directly determine whether Via 0 is abnormal through electrical measurements. By using the body diode of the MOSFET, or a combination of body diode and MOSFET, the chip failure analysis result is quickly located at the Via 0 terminal, thus completing the failure analysis operation for advanced processes.

[0008] Furthermore, a maximum of three pins are required for abnormal electrical tests, reducing testing time by 50%. This effectively reduces carbon buildup on the sample surface and minimizes the introduction of analytical noise.

[0009] In one possible implementation of the first aspect, the chip includes a memory structure comprising a plurality of bit cells, and the method further includes: determining the electrical measurement result of each bit cell one by one; if the electrical measurement result of any bit cell is a failure, marking the contact layer of the bit cell as an abnormal contact layer; and obtaining a failure analysis result based on the abnormal contact layer and destructive analysis.

[0010] Determine the status of VIA0 in each BIT CELL. If the failure occurs in Via 0, the abnormal Via 0 can be directly identified for further destructive analysis, saving analysis resources and time.

[0011] In one possible implementation of the first aspect, when performing the steps of obtaining electrical measurement results by combining the body diodes of multiple metal-oxide-semiconductor (MOS) transistors and combining the MOS transistors and body diodes after chip delamination to the contact layer, the multiple MOS transistors include a first MOS transistor, a second MOS transistor, and a third MOS transistor; the method includes: performing electrical tests on the contact layer to obtain electrical measurement results of the contact layer; applying a voltage between the substrate and source of the first MOS transistor; and determining the electrical measurement results of the source of the first MOS transistor based on the electrical curve of the body diode of the first MOS transistor.

[0012] In one possible implementation of the first aspect, the method includes: fixing the gate of the first MOS transistor at a high voltage, grounding the substrate of the third MOS transistor, and scanning the source of the first MOS transistor with a stepped voltage, and determining the electrical measurement result of the gate of the first MOS transistor by testing the electrical curves of the second body diodes of the first MOS transistor and the third MOS transistor.

[0013] In one possible implementation of the first aspect, the method includes: applying a voltage between the substrate and source of the second MOS transistor, and determining an electrical measurement result of the source of the second MOS transistor based on the electrical characteristics of the body diode of the second MOS transistor; the first MOS transistor and the second MOS transistor share the same substrate.

[0014] In one possible implementation of the first aspect, the method includes: applying a voltage between the substrate and source of the third MOS transistor, and determining an electrical measurement result of the source of the third MOS transistor based on the electrical characteristics of the first body diode of the third MOS transistor.

[0015] In one possible implementation of the first aspect, the storage structure is a static random access memory, and each bit cell includes six MOS transistors.

[0016] In one possible implementation of the first aspect, the contact layer is the layer where Via0 is located.

[0017] In one possible implementation of the first aspect, the method includes: if the current and voltage are linearly correlated in the electrical curve, the electrical measurement result is normal; if a high-resistivity anomaly exists in the electrical curve, the electrical measurement result is abnormal.

[0018] In a second aspect, this disclosure provides a chip failure analysis apparatus for performing the chip failure analysis method of the first aspect described above.

[0019] The chip failure analysis device of the second aspect mentioned above can refer to the beneficial effects of the first aspect and any of its possible design methods, which will not be elaborated here. Attached Figure Description

[0020] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0021] Figure 1 A schematic flowchart illustrating a chip failure analysis method provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the chip structure in a chip failure analysis method provided in an embodiment of this application;

[0023] Figure 3 This is a top view of the chip after delamination down to the contact layer in a chip failure analysis method provided in this application embodiment;

[0024] Figure 4 for Figure 3 A front view of the provided chip;

[0025] Figure 5 A schematic diagram of the body diode in a chip failure analysis method provided in this application embodiment;

[0026] Figure 6 This is a schematic diagram of the electrical curve in a chip failure analysis method provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can represent A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0028] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0029] As a highly integrated and complex system, a chip contains multiple functional structures, such as storage structures, arithmetic logic units (ALUs), controllers, and / or registers. Storage structures, including caches or registers, are used to store data or instructions for computation. The ALU performs operations such as addition, subtraction, multiplication, division, and logical judgments. The controller parses instructions and coordinates the work of various components. These multiple functional structures work together to achieve core functions such as computation, storage, and communication.

[0030] The chip integrates various types of memory cells as a storage structure, depending on the requirements. These include Dynamic Random Access Memory (DRAM), Read-Only Memory (ROM), Flash Memory, and Static Random Access Memory (SRAM).

[0031] SRAM, which uses transistor flip-flops to store data without requiring refresh, is fast but has low integration density. It is often used as a high-speed cache or register within a chip and is a functional module inside the chip die. Its unique structural characteristics, key application scenarios, mature testing system, and deep correlation with process design make it a "benchmark object" for reliability research, process optimization, and fault location, and a core focus in failure analysis.

[0032] From its structural perspective, SRAM uses a 6T structure composed of six MOS transistors as its basic memory cell. Compared to DRAM (single transistor and capacitor) or ordinary logic circuits, its cell structure is more complex and its transistor interconnection density is higher. This structural characteristic makes it extremely sensitive to manufacturing defects and environmental stress. During the manufacturing process, minute process defects such as photolithography deviations, uneven doping concentrations, metal line bridging, or open circuits are more easily exposed in SRAM and can lead to cell failure. For example, a deviation of only 0.1μm in the gate spacing between adjacent transistors can cause a short circuit in an SRAM cell, while such defects are often difficult to detect in devices with simpler structures. In the operating environment, factors such as temperature, voltage, and radiation can cause problems such as transistor threshold voltage drift and increased leakage current, which directly affect SRAM and its read / write stability, such as "hold failure" where stored data is lost when there is no refresh. By analyzing these parameter failure phenomena in SRAM, the inherent laws of transistor characteristic degradation can be accurately deduced.

[0033] In application scenarios, SRAM's core role gives high weight to its failure consequences, further reinforcing its necessity as the subject of failure analysis. As a core component of L1 / L2 cache in core computing units such as CPUs and GPUs, the stable operation of SRAM directly determines the accuracy of computing power output. Once it fails, it will directly lead to calculation errors and program crashes, such as instruction execution anomalies caused by cached data errors. In embedded systems in extreme environments such as aerospace and military, SRAM must withstand complex stresses such as radiation, vibration, and wide temperature ranges. Radiation failure modes such as single-event upsets (SEU) and single-event lockouts (SEL) directly affect the reliability of device tasks. Therefore, failure analysis of SRAM becomes a key link in ensuring the stability of such systems.

[0034] Furthermore, the deep integration of SRAM with semiconductor processes and design makes it a "barometer" of the industry's technological level, giving SRAM failure analysis broader industry value. At the process level, an abnormally high leakage rate in SRAM cells may reflect dosage deviations in the ion implantation process, while inconsistent read / write speeds of memory cells may point to resistance differences in the metal interconnects. By analyzing the failure mechanisms of SRAM, key process steps such as photolithography, deposition, and etching can be optimized in reverse. At the design level, the minimum cell size of SRAM (such as a 6T cell area in FinFET technology) is a core indicator of chip manufacturing capability. Analyzing SRAM failures can verify the rationality of design rules such as transistor spacing and oxide layer thickness, providing crucial support for the implementation of more advanced processes.

[0035] In mature manufacturing processes, SRAM bit lines, word lines, power supplies, and grounds are interconnected via CT / METAL1. When a CT anomaly or a single MOSFET anomaly occurs, after delamination down to the CT, the six MOSFETs are independent of each other, allowing the location of the anomaly to be determined by testing individual MOSFETs. For example, when an SRAM experiences a bit cell failure, the failure area can generally be narrowed down to its standard 6T cell structure. The MOSFETs that make up the basic structure are planar, with their gates, drains, sources, and substrates connected to the upper METAL1 layer via CT contact holes. Therefore, when a bit cell failure occurs, the conventional analysis method is to delaminate the chip layer by layer from top to bottom. When delamination reaches the CT contact holes, the interconnections between the MOSFETs are broken, and the six MOSFETs become independent of each other, allowing for individual MOSFET electrical testing.

[0036] With the continuous evolution of integrated circuit manufacturing process nodes, in advanced processes, the MOSFET structure has evolved from the traditional planar structure into a more complex FinFET structure. Interconnection methods such as GATE METAL / METAL0 / VIA0 have also been introduced in the back-end interconnection process. The complex process flow and MOSFET structure make chip failure analysis more difficult. For example, due to the introduction of interconnection methods such as GATE METAL / METAL0 / VIA0 in advanced processes, the six MOSFETs in the VIA0 layer are not independent of each other, making it impossible to perform electrical testing on individual MOSFETs. Anomalies in the VIA0 layer itself become a major challenge in failure analysis.

[0037] To address this issue, this disclosure provides a chip failure analysis method that utilizes the body diode of a MOSFET, or a combination of a body diode and a MOSFET, to quickly locate the chip at the Via 0 terminal and obtain the chip failure analysis results, thereby completing the failure analysis operation for advanced processes.

[0038] Figure 1This is a flowchart illustrating a chip failure analysis method provided in an embodiment of this application. Figure 1 As shown, in some embodiments, the method includes the following steps:

[0039] S101, when the chip is stripped down to the contact layer, electrical measurement results are obtained by combining the body diodes of multiple metal oxide semiconductor MOSFETs and by combining the MOSFETs and body diodes.

[0040] In some embodiments, the chip includes a memory structure. The memory structure includes multiple bit cells. A bit cell is a basic circuit unit in memory used to store one bit of binary information; it is the smallest core unit that constitutes various types of memory (such as SRAM, DRAM, etc.). For example, the basic memory cell of SRAM has a 6-transistor (6T) structure and is responsible for storing one bit of binary data (0 or 1).

[0041] In some embodiments, each bit unit may be as follows: Figure 2 The 6T structure shown is a MOSFET structure consisting of six transistors. The first MOSFET (i.e., ...) is... Figure 2 The PG1 shown is an N-channel metal-oxide-semiconductor (NMOS) transistor, and the second MOS transistor (i.e., Figure 2 The PD1 and NMOS transistors shown are shown, as well as the third MOS transistor (i.e., PD1, NMOS). Figure 2 The PU1 shown is a P-channel metal-oxide-semiconductor PMOS transistor, and the fourth MOS transistor (i.e., Figure 2 The PU2 and PMOS transistors shown are the fifth MOS transistor (i.e., PMOS). Figure 2 The PD2, NMOS and the sixth MOS transistor (i.e. Figure 2 As shown in the diagram, PG2 is an NMOS transistor. Four NMOS transistors (PG1, PG2, PD1, PD2) and two PMOS transistors (PU1, PU2) are connected in a specific way to form a bistable storage circuit to store data as "0" and "1".

[0042] In this configuration, PU1 and PU2 act as pull-up transistors, with their sources connected to the power supply (VDD). Their drains are connected to the drains of the NMOS pull-down transistors (PD1 and PD2) and the NMOS transmission transistors (PG1 and PG2), respectively, forming a cross-coupled bistable structure. For example, the drain of PU1 is connected to the drains of PD1 and PG1, and the drain of PU2 is connected to the drains of PD2 and PG2.

[0043] PD1 and PD2 act as pull-down transistors, with their sources grounded (VSS). Their drains are connected to the drains of the pull-up transistors (PU1, PU2) and the drains of the transmission transistors (PG1, PG2), forming a bistable circuit (the core for storing "0" and "1") through cross-coupling with PU1 / PU2. The drain of PD1 is connected to the drains of PU1 and PG1; the drain of PD2 is connected to the drains of PU2 and PG2. When PD1 is on and PU1 is off, it stores "0". When PD2 is on and PU2 is off, it stores "1".

[0044] PG1 and PG2 act as transmission transistors (access transistors), with their gates connected to the word line, their sources connected to the bit line, and their drains connected to the connection node of a pull-up or pull-down transistor. When the word line is high, PG1 and PG2 are turned on, connecting the bit cell to the bit line, allowing for read and write operations. When the word line is low, PG1 and PG2 are turned off, isolating the bit cell from the bit line and preserving the stored data.

[0045] The left branch (PU1, PD1, PG1) and the right branch (PU2, PD2, PG2) are cross-coupled to form a bistable circuit for storing data.

[0046] The following detailed description of the interlayer structure from the chip delamination layer to the contact layer, with reference to the accompanying drawings, is provided in detail.

[0047] Combined Figure 3 and Figure 4 In some embodiments, the chip includes a substrate, an active area (AA), a gate oxide (GT), a gate metal layer, a metal zero layer (METAL0), and a contact layer (VIA0) stacked sequentially.

[0048] The substrate includes N-wells (NW) and P-wells (PW), which serve as the substrate regions of semiconductor devices, providing the operating environment for N-type and P-type devices respectively, and forming regions with different conductivity types through doping.

[0049] like Figure 3 As shown, after the chip is stripped down to the contact layer, the exposed structures include the substrate BULK terminals of PG1 and PD1 (e.g., Figure 3 Position 1 shown in the middle label 1), the source of PG1 (as shown in the middle label 1) Figure 3 Position 2 shown in the middle label 2), the source of PD1 (as shown in the middle label 2) Figure 3 Position 3 as indicated by reference numeral 3), gate of PG1 (as shown in Figure 3) Figure 3 Position 4 as indicated by the number 4), the BUIK end of PU1 (such as...) Figure 3 Position 5 as indicated by the Chinese reference numeral 5), the source of PU1 (as shown in Figure 5). Figure 3 Position 6 is indicated by the number 6 in the middle.

[0050] Combined Figure 3 and Figure 5 The PN junction formed between the BULK terminal and the source of PG1 (such as...) Figure 5 Position 7 (as indicated by reference numeral 7). The PN junction formed between the BUIK terminal and the source of PD1 (as shown in Figure 7). Figure 5 Position 8 (as indicated by reference numeral 8). The PN junction formed between the source and BUIK terminals of PU1 (as shown by reference numeral 8). Figure 5 Position 9 (as indicated by reference numeral 9). The PN junction formed between the drain and BUIK terminal of PU1 (as shown by reference numeral 9). Figure 5 Position 10 is indicated by the number 10.

[0051] A body diode (also known as a parasitic diode) is a diode formed by a naturally occurring PN junction within the structure of a semiconductor device. Essentially, it's a PN junction "hidden" within the device's inherent structure. Taking an NMOS transistor as an example, both its source and drain are N-type doped regions, and the substrate is a P-type semiconductor. In this case, a PN junction is formed between the N-type region of the source (or drain) and the P-type region of the substrate. When the device is operating, this PN junction, unavoidable due to the device structure, naturally possesses the unidirectional conductivity characteristic of a diode, thus becoming the body diode of the NMOS transistor.

[0052] To detect the exposed structure, electrical measurement results were obtained by combining the body diodes of multiple metal-oxide-semiconductor (MOS) transistors and combining the MOS transistors and body diodes after the chip was delaminated to the contact layer.

[0053] In some embodiments, when performing the steps of obtaining electrical measurement results by combining the body diodes of multiple metal-oxide-semiconductor (MOS) transistors and combining the MOS transistors and body diodes after chip delamination to the contact layer, the multiple MOS transistors include a first MOS transistor, a second MOS transistor, and a third MOS transistor; the method includes:

[0054] S201, Perform electrical tests on the contact layer to obtain the electrical measurement results of the contact layer.

[0055] S301, apply a voltage between the substrate and source of the first MOS transistor, and determine the electrical measurement result of the source of the first MOS transistor based on the electrical curve of the body diode of the first MOS transistor.

[0056] In some embodiments, the method includes:

[0057] S401, fix the gate of the first MOSFET at a high voltage, ground the substrate of the third MOSFET, and scan the source of the first MOSFET with a stepped voltage. By testing the electrical curves of the second body diodes of the first and third MOSFETs, determine the electrical measurement results of the gate of the first MOSFET.

[0058] The second body diode, the PN junction formed between the drain of PU1 and the BUIK terminal (such as...) Figure 5 Position 10 is indicated by the number 10.

[0059] In some embodiments, the method includes:

[0060] S501: Apply a voltage between the substrate and source of the second MOSFET, and determine the electrical measurement results of the source of the second MOSFET based on the electrical curve of the body diode of the second MOSFET.

[0061] The first MOSFET and the second MOSFET share the same substrate.

[0062] In some embodiments, the method includes:

[0063] S601: Apply a voltage between the substrate and source of the third MOS transistor, and determine the electrical measurement results of the source of the third MOS transistor based on the electrical curve of the first body diode of the third MOS transistor.

[0064] The first body diode, namely the PN junction formed between the source of PU1 and the BUIK terminal (such as... Figure 5 Position 9 is indicated by the number 9 in the middle.

[0065] By executing steps S201, S301, S401, S501, and S601, the characteristics of the body diode of the MOSFET are utilized to perform combined testing of the body diodes of multiple metal-oxide-semiconductor MOSFETs, as well as combined testing of the MOSFETs and body diodes, thus completing the detection of VIA0 and the drain terminals of the left branch (PU1, PD1, PG1). The right branch (PU2, PD2, PG2) adopts the same detection logic and process as the left branch, which will not be described in detail here.

[0066] In some embodiments, the method includes:

[0067] S701, if the current and voltage are linearly correlated in the electrical curve, then the electrical measurement result is normal.

[0068] like Figure 6 As shown, the electrical curve is presented in a logarithmic coordinate system (LN(Current)-Voltage). Its shape change is directly related to the resistance state of VIA0 (via 0 layer), clearly reflecting whether there is a high resistance anomaly in the via.

[0069] For example, the electrical curve of the test appears as follows: Figure 6 If curve 1 is in the middle, then the electrical measurement result is normal.

[0070] Understandably, when VIA0 is normal, the test result is curve 1. At this time, the via contact resistance is extremely low and the performance is stable. The logarithmic relationship between current and voltage shows a gentle slope and excellent linearity. This is because, without high resistance, the change of current with voltage conforms to the ideal conduction law. The logarithmic current response to voltage is uniform, which intuitively reflects that the circuit conduction path is smooth, the resistance is stable, and the signal transmission is not hindered in any way.

[0071] S702, if there is a high resistance anomaly in the electrical curve, the electrical measurement result is abnormal.

[0072] For example, if a high-resistivity anomaly exists in VIA0, the test curve will be as follows: Figure 6 As shown in curves 2, 3, and 4, the electrical measurement results are abnormal.

[0073] Understandably, when VIA0 exhibits a high-resistivity anomaly, the test curve will appear as curve 2, curve 3, or curve 4. The core difference lies in the fact that high resistance significantly increases the resistance to current flow, resulting in a much smaller current value at the same voltage compared to the case without anomalies, or requiring a higher voltage to achieve the same current. Reflected on a logarithmic scale, this resistance amplifies the "voltage boosting effect on current," causing LN (Current) to change more drastically with voltage, ultimately manifesting as a significantly steeper curve slope.

[0074] The three curves exhibit varying degrees of steepness. Curve 4 has the steepest slope, indicating the most severe VIA0 high-resistivity anomaly. Curve 3 has the second steepest slope, indicating a moderate degree of high resistance. Curve 2 has a relatively gentle slope, suggesting a milder high-resistivity anomaly. In summary, by observing the differences in curve shape (gentle vs. steep) and the degree of steepness, it is possible to directly determine whether a high-resistivity defect exists in VIA0, and simultaneously quantify the severity of the anomaly.

[0075] S102, based on the electrical measurement results, obtain the chip failure analysis results.

[0076] In some embodiments, based on electrical measurement results, the failure mode of the chip can be accurately located, and the failure analysis results of the chip can be obtained.

[0077] For example, if the on-resistance of VIA0 in electrical measurements is significantly higher than the process specifications, and the LN (Current)-Voltage curve exhibits a steep characteristic similar to curves 2, 3, and 4, it indicates that VIA0 has a high-resistance anomaly. This type of failure will cause a sharp increase in signal transmission resistance at vias, slowing down the charging and discharging speed of the bistable circuit, causing the toggle time of the memory cell to exceed the design threshold, or even making it impossible to stably maintain the data level, manifesting as erroneous toggle of stored data or failure of the ability to retain data.

[0078] For example, threshold voltage (Vth) measurements are performed on PU1 (PMOS transistor) and PD1 / PG1 (NMOS transistor). If the threshold voltage of PU1 is greater than the design threshold, it will increase the difficulty of its conduction, resulting in insufficient drive capability of the pull-up branch of the bistable circuit, and the stored high level cannot be effectively maintained. If the threshold voltage of PD1 / PG1 is less than the design threshold, it will cause an increase in device leakage current, "pulling out" the stored low level, and ultimately leading to data loss.

[0079] For example, if electrical measurements show that the resistance of a certain branch is close to infinity, it indicates an open-circuit defect in the METAL0 wiring or VIA0. For instance, a broken metal wire in the left branch (PU1, PD1, PG1) will disrupt the symmetry of the bistable circuit, preventing it from switching or maintaining between the two stable states and directly causing it to lose its data storage function. If an abnormally low resistance (close to 0) is observed, it indicates a short-circuit defect. For example, a short circuit between the source of PU1 and VSS (ground) will cause the power supply and ground to be directly connected, leading to device burnout. At the same time, the storage logic of the bistable circuit will be completely destroyed, and the data will be completely lost.

[0080] In this way, by analyzing the correspondence between electrical measurement results and the aforementioned failure modes, the root cause of chip failure can be identified, providing a direct basis for subsequent process optimization or fault repair, and ensuring the functional reliability of the bistable memory circuit.

[0081] In this embodiment of the application, by executing steps S101 to S102, after delamination to VIA0, electrical testing is performed to determine whether VIA0 has failed. Then, proceeding to the next step, electrical testing after delamination, ensures that no failure phenomena are missed.

[0082] In some embodiments, the chip includes a memory structure comprising a plurality of bit cells, and the method further includes:

[0083] S801 determines the electrical measurement results of each bit cell one by one.

[0084] S802, if the electrical measurement result of any bit cell is a failure, mark the contact layer of the bit cell as an abnormal contact layer.

[0085] S803, based on the abnormal contact layer, failure analysis results are obtained through destructive analysis.

[0086] This application also provides a chip failure analysis apparatus, which is used to execute the chip failure analysis method provided in the foregoing embodiments.

[0087] In some embodiments, the chip failure analysis apparatus includes a nanoprobe. A nanoprobe is an advanced tool that integrates an ultra-fine probe, a precision positioning system, and a highly sensitive electrical measurement module, providing nanometer-level spatial resolution and accurate electrical testing capabilities.

[0088] In some embodiments, the nanoprobe includes an ultrafine probe unit, a nanopositioning unit, a microscope-aided positioning module, and a precision electrical measurement module.

[0089] The probe tip diameter in the ultrafine probe unit can be as low as 10-100 nanometers. It is made of highly conductive materials (such as tungsten and platinum-iridium alloys) to ensure stable ohmic contact with the structure under test, while avoiding mechanical damage to the microstructure.

[0090] The nanometer positioning unit, combining piezoelectric drive technology and laser interferometric positioning feedback, achieves sub-nanometer displacement accuracy in three dimensions, ensuring that the probe can be accurately aligned with the area being measured (such as the gate edge of a MOSFET, the center of a via, etc.).

[0091] The microscope-assisted positioning module allows for real-time observation of the relative position of the probe and the structure under test using an optical microscope (OM) or a scanning electron microscope (SEM), improving the positioning accuracy to the micrometer or even nanometer level.

[0092] The precision electrical measurement module integrates devices such as a source meter and a semiconductor parameter analyzer. It can apply precise voltage / current signals (ranging from pA to mA and mV to V) and simultaneously acquire current / voltage responses to achieve quantitative measurement of parameters such as resistance, threshold voltage, and leakage current.

[0093] In some embodiments, the nanoprobe is configured to obtain electrical measurement results by combining tests of the body diodes of multiple metal-oxide-semiconductor MOSFETs and combining tests of MOSFETs and body diodes when the chip is stripped down to the contact layer; and to obtain chip failure analysis results based on the electrical measurement results.

[0094] In this way, a maximum of three pins are needed for abnormal electrical tests, reducing testing time by 50%. Furthermore, this effectively reduces carbon buildup on the sample surface and minimizes the introduction of analytical noise.

[0095] In some embodiments, the nanoprobe is further configured to determine the electrical measurement results of each bit cell individually; if the electrical measurement result of any bit cell is a failure, the contact layer of the bit cell is marked as an abnormal contact layer; based on the abnormal contact layer, a failure analysis result is obtained based on destructive analysis. In this way, by determining the VIA 0 condition in each bit cell individually, if the failure occurs at Via 0, the abnormal Via 0 can be directly identified for further destructive analysis, saving analysis resources and time.

[0096] In some embodiments, the nanoprobe is further configured to perform electrical tests on the contact layer to obtain electrical measurement results of the contact layer; apply a voltage between the substrate and source of the first MOS transistor, and determine the electrical measurement results of the source of the first MOS transistor based on the electrical curve of the body diode of the first MOS transistor.

[0097] In some embodiments, the nanoprobe is further configured to fix the gate of the first MOS transistor at a high voltage, ground the substrate of the third MOS transistor, and scan the source of the first MOS transistor with a stepped voltage to determine the electrical measurement result of the gate of the first MOS transistor by testing the electrical curves of the second body diodes of the first and third MOS transistors.

[0098] In some embodiments, the nanoprobe is further configured to apply a voltage between the substrate and source of the second MOS transistor, and to determine the electrical measurement result of the source of the second MOS transistor based on the electrical characteristics of the body diode of the second MOS transistor; the first MOS transistor and the second MOS transistor share the same substrate.

[0099] In some embodiments, the nanoprobe is further configured to apply a voltage between the substrate and source of the third MOS transistor, and to determine the electrical measurement results of the source of the third MOS transistor based on the electrical characteristics of the first body diode of the third MOS transistor.

[0100] In some solutions, multiple embodiments of this application can be combined, and the combined solution can be implemented. Optionally, some operations in the processes of each method embodiment may be combined, and / or the order of some operations may be changed. Furthermore, the execution order between the steps of each process is merely exemplary and does not constitute a limitation on the execution order between steps; other execution orders are also possible. It is not intended to indicate that the execution order is the only possible order in which these operations can be performed. Those skilled in the art will conceive of various ways to reorder the operations described herein. In addition, it should be noted that the process details involved in one embodiment of this document are similarly applicable to other embodiments, or different embodiments may be combined.

[0101] Furthermore, some steps in the method embodiments can be equivalently replaced with other possible steps. Alternatively, some steps in the method embodiments may be optional and can be deleted in certain use cases. Or, other possible steps may be added to the method embodiments. Moreover, the various method embodiments can be implemented individually or in combination.

[0102] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus (such as device nodes and first target network nodes) of the embodiments of this disclosure, and the principle is the same, so it is not limited in the embodiments of this disclosure.

[0103] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0104] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip failure analysis method, characterized in that, The method includes: When the chip is stripped down to the contact layer, electrical measurement results are obtained by combining the body diodes of multiple MOS transistors and by combining the MOS transistors and the body diodes. Based on the electrical measurement results, the failure analysis results of the chip are obtained; When performing the steps of obtaining electrical measurement results by combining the body diodes of multiple MOS transistors and combining the MOS transistors and the body diodes after chip delamination to the contact layer, the multiple MOS transistors include a first MOS transistor, a second MOS transistor, and a third MOS transistor; The method includes: An electrical test was performed on the contact layer to obtain the electrical measurement results of the contact layer; A voltage is applied between the substrate and the source of the first MOS transistor, and the electrical measurement results of the source of the first MOS transistor are determined based on the electrical curve of the body diode of the first MOS transistor. The gate of the first MOS transistor is fixed at a high voltage, the substrate of the third MOS transistor is grounded, and the source of the first MOS transistor is scanned with a stepped voltage. By testing the electrical curves of the second body diode of the first MOS transistor and the third MOS transistor, the electrical measurement result of the gate of the first MOS transistor is determined. The second body diode is a PN junction formed between the drain of PU1 and the BUIK terminal.

2. The chip failure analysis method according to claim 1, characterized in that, The chip includes a memory structure, the memory structure includes multiple bit cells, and the method further includes: The electrical measurement results for each of the bit cells are determined one by one; If the electrical measurement result of any of the bit cells is a failure, the contact layer of the bit cell is marked as an abnormal contact layer; Based on the abnormal contact layer, the failure analysis results are obtained through destructive analysis.

3. The chip failure analysis method according to claim 1, characterized in that, The method includes: A voltage is applied between the substrate and source of the second MOS transistor, and the electrical measurement result of the source of the second MOS transistor is determined based on the electrical curve of the body diode of the second MOS transistor; the first MOS transistor and the second MOS transistor share the same substrate.

4. The chip failure analysis method according to claim 1, characterized in that, The method includes: A voltage is applied between the substrate and source of the third MOS transistor. Based on the electrical characteristics of the first body diode of the third MOS transistor, the electrical measurement results of the source of the third MOS transistor are determined. The first body diode is a PN junction formed between the source of PU1 and the BUIK terminal.

5. The chip failure analysis method according to claim 2, characterized in that, The storage structure is a static random access memory, and each bit cell includes six MOS transistors.

6. The chip failure analysis method according to claim 2, characterized in that, The contact layer is the layer where Via0 is located.

7. The chip failure analysis method according to claim 1, characterized in that, The method includes: If the current and voltage are linearly correlated in the electrical curve, then the electrical measurement result is normal. If a high-resistivity anomaly is present in the electrical curve, then the electrical measurement result is abnormal.

8. A chip failure analysis device, characterized in that, The chip failure analysis device is used to perform the method according to any one of claims 1 to 7.

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