Preparation method of patch strip, optical waveguide network chip and light quantum computer

Abstract

The invention provides a patch strip preparation method, an optical waveguide network chip and an optical quantum computer, and relates to the technical field of optical communication, and the method comprises the steps: sequentially forming a buried oxide layer and a waveguide layer on a first substrate, and enabling the waveguide layer to form a plurality of nano teeth which are arranged in an array; the buried oxide layer is etched to form a plurality of first open grooves in the buried oxide layer, an oxidation column is formed between every two adjacent first open grooves, and the nanometer teeth are located on the oxidation columns; bonding a second substrate on the waveguide layer through an adhesive, wherein the adhesive far away from the second substrate extends into the first open slot to form a first adhesive layer; the adhesive which does not extend into the first open groove and is close to the second substrate forms a second adhesive layer; removing the first substrate and the buried oxide layer; the first glue layer is removed, a plurality of second open grooves are formed in the second glue layer, second glue columns are formed between the adjacent second open grooves, and the nanometer teeth are located in the second glue columns; and splitting the second substrate along the second slots to obtain a plurality of patch strips. And the nanometer teeth are completely transferred to the second substrate, so that reliable surface mounting is realized.

Description

Technical Field

[0001] This application relates to the field of optical communication technology, specifically to a method for preparing a patch strip, an optical waveguide network chip, and an optical quantum computer. Background Technology

[0002] With the rapid development of applications such as optical quantum computing, the demand for large-size optical waveguide network chips is increasing, especially in achieving a higher number of optical qubits, necessitating the development of ultra-large-size optical waveguide network technology. However, existing electron beam lithography (EBL) and deep ultraviolet lithography (DUV) technologies have certain limitations in directly manufacturing ultra-large-size optical waveguide networks. These traditional lithography technologies face challenges in terms of precision and scale expansion, making it difficult to meet the manufacturing requirements of large-scale optical waveguide networks.

[0003] To address this issue, one possible solution is to design the optical waveguide network in blocks. This involves using DUV lithography to fabricate multiple copies of the optical waveguide network on a single wafer. Then, a second DUV lithography process is performed on another wafer to create another set of optical waveguide network copies. After these copies are fabricated, the corresponding optical waveguide network copies can be extracted from each wafer and precisely stitched together to form a large-scale optical waveguide network. This stitching method allows for the design of larger-scale optical waveguide networks within a limited lithography area. To connect these optical waveguide network copies, connectors (such as Nanoteeth structures) can be used to connect the block-designed optical waveguide network copies with low loss, ultimately forming a large-scale optical waveguide network. However, using conventional methods to fabricate Nanoteeth structures presents some challenges: In existing conventional silicon-on-insulator (SOI) fabrication and thinning processes, curling and shedding are prone to occur, affecting the stability of Nanoteeth patches. When the silicon substrate is removed, leaving only the buried oxide layer, wavy undulations are easily generated, which may lead to crack formation. The direction and length of cracks are uncontrollable, and when cracks cross the Nanoteeth region, they may cause silicon waveguide breakage, failing to meet the requirements for low transmission loss. Furthermore, in existing conventional dicing processes, composite structures cannot be directly mechanically cut, making it difficult to divide multiple Nanoteeth layers fabricated simultaneously on an SOI wafer into Nanoteeth patches for actual connection, thus affecting production efficiency and fabrication accuracy. Summary of the Invention

[0004] The purpose of this application is to provide a method for preparing a patch strip, an optical waveguide network chip, and an optical quantum computer, which can solve the problems existing in the prior art, ensure high stability and high reliability in the bonding transfer process, achieve low-loss connection of optical waveguide network replicas, and at the same time ensure production efficiency and preparation accuracy.

[0005] One aspect of this application provides a method for preparing a patch strip, comprising: A buried oxide layer and a waveguide layer are sequentially formed on a first substrate, and the waveguide layer is arranged in an array of multiple nanotooth-shaped structures. The buried oxide layer is etched to form multiple first slots within the buried oxide layer, and oxide pillars are formed between adjacent first slots, with nanotooth-shaped structures located on the oxide pillars. A second substrate is bonded to the waveguide layer with an adhesive, with the adhesive extending away from the second substrate into the first groove to form a first adhesive layer; the adhesive that does not extend into the first groove but is close to the second substrate forms a second adhesive layer. Remove the first substrate and the buried oxide layer; Remove the first adhesive layer and make the second adhesive layer form multiple second grooves, and form second adhesive pillars between adjacent second grooves, with nano-tooth located inside the second adhesive pillars; Multiple patch strips are obtained along the second substrate of the second slotted slit.

[0006] Optionally, a buried oxide layer and a waveguide layer are sequentially formed on a first substrate, and the waveguide layer is arranged in an array of multiple nanotooth-shaped structures, including: A buried oxide layer and a waveguide layer are sequentially formed on the first substrate; Photolithography is used to form multiple nanotooth-shaped structures in the waveguide layer.

[0007] Optionally, the buried oxide layer is etched to form a plurality of first trenches within the buried oxide layer, and oxide pillars are formed between adjacent first trenches, with nanotooth-like structures located on the oxide pillars, including: The depth of the first groove along the first direction is at least greater than 1.5 μm, the width of the first groove along the second direction is at least greater than 10 μm, the etching cycle of the multiple first grooves along the second direction is less than 1000 μm, and the etching cycle along the third direction is less than 400 μm; the first direction, the second direction and the third direction are perpendicular to each other.

[0008] Optionally, removing the first substrate and the buried oxide layer includes: Thinning of the first substrate; The remaining first substrate after thinning is removed by deep silicon etching process; Dry etching is used to bury the oxide layer, forming multiple arrays of first adhesive pillars in the first adhesive layer. The nanotooth is located in the second adhesive layer and between adjacent first adhesive pillars. The remaining buried oxide layer is wet-etched to expose the nanotooth structure.

[0009] Optionally, removing the first substrate and the buried oxide layer includes: Thinning of the first substrate; The remaining first substrate after thinning is removed by deep silicon etching process; The second substrate is attached to the third substrate, and the third substrate completely covers the second substrate. Etching to cover the oxide layer; The remaining buried oxide layer is wet-etched to expose the nanotooth structure.

[0010] Optionally, wet etching of the remaining buried oxide layer to expose the nanotooth structure includes: The remaining buried oxide layer was etched using ammonium fluoride solution.

[0011] Optionally, the first substrate is a silicon substrate, the buried oxide layer is a silicon dioxide layer, the waveguide layer is a silicon waveguide, and the second substrate is glass.

[0012] Optionally, along the thickness direction, the first substrate is 350um to 450um, the buried oxide layer is 2um to 4um, the waveguide layer is 210nm to 230nm, the second adhesive layer is 130um to 150um, and the second substrate is 500um to 600um.

[0013] In another aspect of this application, an optical waveguide network chip is provided, comprising: a plurality of photonic chips, wherein the plurality of photonic chips are connected by a patch strip obtained by the above-described patch strip preparation method.

[0014] In another aspect of this application, an optical quantum computer is provided, comprising: a quantum light source, a detector, and a photonic chip of the aforementioned optical waveguide network chip.

[0015] The patch strip fabrication method, optical waveguide network chip, and optical quantum computer provided in this application embodiment transfer the nanotooth array structure fabricated on the waveguide layer completely onto a second substrate using an adhesive. Using an adhesive with suitable bonding strength ensures that the nanotooths are firmly bonded to the second substrate, preventing curling and adhesive detachment, thus guaranteeing reliable connection of the nanotooths. Furthermore, the nanotooth array structure and the second adhesive pillar form an interlocking state, creating a physical mechanical interlock that effectively resists shear and peel forces and prevents interface delamination and curling. The tooth-shaped structure of the nanotooth array also disperses concentrated stress during the bonding process over a larger area, preventing excessive local stress from causing material deformation, wrinkling, or breakage. Additionally, the second slot further disperses the nanotooth array, avoiding cracking caused by concentrated nanotooth placement and ensuring the structural integrity of the nanotooths. Therefore, the nanotooth array and the second slot in this application, through mechanical interlocking and stress dispersion, work synergistically at the physical and material levels to achieve high stability and high reliability in the bonding transfer process; when splitting along the second slot, it can also avoid the problem of cutting difficulties caused by direct cutting of the adhesive, and can successfully separate the patch strip for actual patching from the nanotooth array group, thereby realizing a convenient and reliable patching process, and then connecting discrete optical waveguides with low loss. The patch strips prepared above are connected to the photonic chip to form an ultra-large-sized optical waveguide network, thus completing the inter-waveguide interconnection of the photonic chip.

[0016] When applied to optical quantum computers, quantum light sources generate photons, which are then transmitted through photonic chips in an optical waveguide network chip. Detectors convert the optical signals from the photonic chips into electrical signals to achieve functions such as transmission or display. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the schematic diagrams of the preparation method of the patch strip provided in this embodiment; Figure 2 This is the second schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 3 This is the third schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 4This is the fourth schematic diagram of the preparation method of the patch strip provided in this embodiment; Figure 5 This is the fifth schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 6 This is the sixth schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 7 This is the seventh schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 8 This is the eighth schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 9 This is the ninth schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 10 This is the tenth schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 11 This is 11 of the schematic diagrams illustrating the preparation process of the patch strip provided in this embodiment; Figure 12 This is the twelfth schematic diagram of the preparation process of the patch strip provided in this embodiment; Figure 13 This is 13th schematic diagram of the preparation method of the patch strip provided in this embodiment; Figure 14 This is the fourteenth schematic diagram of the preparation method of the patch strip provided in this embodiment; Figure 15 This is a sample image of the PDMS adhesive that curled and detached after SOI thinning; Figure 16 This is an image of a wrinkled and fragmented nanotooth array prepared without grooves; Figure 17 This is a diagram of the nanotooth array transferred after grooving treatment in the preparation method of the patch strip provided in this embodiment; Figure 18 This is a photograph of the nanotooth array used for waveguide connection after the patch strip provided in this embodiment is applied; Figure 19 This is a schematic diagram of the optical waveguide network chip structure provided in this embodiment.

[0019] Icons: 100 - Patch strip; 10 - First substrate; 11 - Buried oxide layer; 12 - Waveguide layer; 120 - Nanotooth; 110 - First slot; 111 - Oxide pillar; 13 - Second substrate; 14 - Adhesive; 141 - First adhesive layer; 1410 - First adhesive pillar; 142 - Second adhesive layer; 1420 - Second slot; 1421 - Second adhesive pillar; 15 - Third substrate; F1 - First orientation; F2 - Second orientation. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0021] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] This application provides a method for preparing a patch strip, the method comprising: Step 200: A buried oxide layer 11 and a waveguide layer 12 are sequentially formed on the first substrate 10, and the waveguide layer 12 is arranged in an array of multiple nanotooths 120.

[0024] like Figure 1 As shown, a buried oxide layer 11 and a waveguide layer 12 are sequentially formed on the first substrate 10.

[0025] like Figure 2 As shown, waveguide layer 12 is photolithographically patterned to form multiple nanotooth 120s on waveguide layer 12. For example, the first substrate 10 is an SOI (silicon-on-insulator) wafer, the buried oxide layer 11 is a silicon dioxide layer, and the waveguide layer 12 is a silicon (Si) layer. Nanoteeth (nanotooth 120) array Si waveguides are fabricated on the SOI wafer using positive photoresist EBL (electron beam lithography).

[0026] Combination Figure 19 As shown, the top view of the nanotooth 120 is a rhomboid structure that is wide in the middle and pointed at both ends. Of course, other similar shapes can also be used, as long as the two ends of the nanotooth 120 are pointed structures. When using this pointed structure to connect different photonic chips, the interlocking between the nanotooth 120 and the photonic chip is more reliable, which is beneficial to the reliability of the connection, so as to realize low-loss interconnection between different waveguides.

[0027] It should be noted that, in addition to SOI wafers, the first substrate 10 can also be other suitable optical waveguide materials such as LNOI (lithium niobate on insulator) and Si3N4 (silicon nitride).

[0028] In addition to EBL, other photolithography methods such as laser direct writing, contact exposure, and DUV (deep ultraviolet lithography) can also be used to fabricate nano-tooth 120. Furthermore, positive EBL photoresist can be replaced with various other photoresists such as negative photoresist to fabricate nano-tooth 120.

[0029] like Figure 3 As shown, positive adhesive contact exposure removes the large-area outer waveguide layer 12, leaving an array of nanotooth-shaped structures 120 on the top waveguide layer 12. The purpose of this step is to directly expose the soft adhesive of the subsequently formed Nanoteeth patch strip 100 on the surface to complete the bonding with the photonic chip.

[0030] The contact exposure in this step can also be replaced by other lithography methods such as laser direct writing or EBL.

[0031] Furthermore, without considering cost, the etching of waveguide layer 12 and the removal of the large-area top waveguide layer 12 can be performed in the same round of EBL, laser direct writing, contact exposure and other photolithography methods.

[0032] Step 201: Etch the buried oxide layer 11 to form a plurality of first slots 110 in the buried oxide layer 11, and form oxide pillars 111 between adjacent first slots 110, with nanotooth 120 located on the oxide pillars 111.

[0033] like Figure 4 As shown, a negative photoresist contact etching process is used to etch a SiO2 buried oxide layer 11 with a thickness of approximately 3 micrometers (along the first direction F1). Multiple first slots 110 are formed within the buried oxide layer 11, and oxide pillars 111 capable of supporting nanotooth 120 are formed between adjacent first slots 110. The purpose of this step is to prevent the nanotooth 120 structure from breaking when the first substrate 10 is removed.

[0034] The depth of the first groove 110 along the first direction F1 should be at least greater than 1.5 micrometers, as deeper etching provides better protection for the nanotooth 120; the width of the first groove 110 along the second direction F2 should be at least greater than 10 micrometers, as wider etching also provides better protection for the nanotooth 120; the longitudinal (third direction) etching cycle of the first groove 110 should be less than 400 micrometers, and the transverse (second direction F2) etching cycle can be 100 micrometers to 1000 micrometers, as denser grooves provide better protection; the first direction F1, the second direction F2, and the third direction are perpendicular to each other; in specific fabrication, due to process error, the perpendicularity between the first direction F1, the second direction F2, and the third direction can be within a reasonable process error range.

[0035] In addition to the aforementioned negative photoresist contact exposure overlay, other similar photolithography methods can also be used to achieve the above-mentioned grooving effect, which will not be elaborated here.

[0036] For example, the etch depth of the buried oxide layer 11 is 3.3 micrometers, the etch width is 10 micrometers, the lateral etch cycle is 1000 micrometers, the longitudinal etch cycle is 100 micrometers, and the vertical etch method is adopted.

[0037] The oxide pillar 111 can have different shapes, such as trapezoidal, rectangular, etc. For example, the oxide pillar 111 is in... Figure 4 In the side view, it has a rectangular column shape. Rectangle has a significant advantage in resisting bending and torsional forces. Therefore, the rectangular oxide column 111 can better support the nanotooth 120, ensure the structural stability of the nanotooth 120 during the preparation process, and avoid phenomena such as breakage.

[0038] Correspondingly, a first groove 110 is formed between adjacent oxide pillars 111, and the shape of the first groove 110 corresponds to and matches the shape of the oxide pillar 111. The first groove 110 includes a horizontal and vertical grid structure. Different structures can be adopted for waveguides of different shapes (such as irregular, spiral, etc.), including irregular, spiral, and etching of all buried oxide layers 11 except for necessary areas.

[0039] Step 202: Bond the second substrate 13 to the waveguide layer 12 with adhesive 14. The adhesive 14 away from the second substrate 13 extends into the first groove 110 to form the first adhesive layer 141; the adhesive 14 that does not extend into the first groove 110 and is close to the second substrate 13 forms the second adhesive layer 142.

[0040] like Figure 5As shown, for example, adhesive 14 may be a UV-curable adhesive; in some embodiments, NTT AT6001 is a UV-curable optical adhesive that can be used as adhesive 14 to bond the first substrate 10 to a second substrate 13 of appropriate thickness. The purpose of this step is to fix the waveguide layer 12 to the second substrate 13 together.

[0041] For example, the second substrate 13 is a glass substrate or other material, which is used to provide support for the waveguide layer 12 that is wrapped by NTT AT6001 after transfer. Transparent materials are easy to judge the bonding effect and easy to align, while opaque substrate materials can also be used.

[0042] During bonding, since the buried oxide layer 11 has a first groove 110, a portion of the adhesive 14 can extend into the first groove 110. The adhesive 14 extending into the first groove 110 is defined as the first adhesive layer 141, while the adhesive 14 not extending into the first groove 110 is defined as the second adhesive layer 142. The second adhesive layer 142 is close to the second substrate 13.

[0043] It should be noted that the adhesive 14 used here is generally a soft adhesive. Soft adhesives are soft polymer materials used in bonding processes to achieve flexible connections or functionalization between materials. They are flexible plastic materials that are soft at room temperature and do not require vulcanization. The NTT AT6001 in this application can also be replaced with other organic soft adhesives as adhesive 14. Adhesives with suitable adhesion and low shrinkage should be selected to reduce the chances of curling, wrinkling, and cracking, and to avoid the problem of difficulty in cutting the fragments later.

[0044] For example, an adhesive 14 with a viscosity of approximately 80 mPa·s to 300 mPa·s and a shrinkage rate of approximately 0.4% to 1.2% can be selected. An adhesive 14 with suitable viscosity has good flowability, which can reduce local accumulation and also provides strong adhesion, preventing curling. An adhesive 14 with low shrinkage can reduce internal stress after curing, thereby reducing the risk of wrinkling and breakage. In addition to the aforementioned UV soft adhesive and NTT AT6001, the adhesive 14 of this application can also be made of materials such as PU (polyurethane), TPE (thermoplastic elastomer), and TPU (thermoplastic polyurethane elastomer).

[0045] Step 203: Remove the first substrate 10 and the buried oxide layer 11.

[0046] like Figure 6 As shown, the first substrate 10 is thinned to approximately 100 micrometers by mechanical polishing or other thinning processes. The purpose of this step is to rapidly thin the first substrate 10, saving time for deep silicon etching.

[0047] like Figure 7As shown, the remaining first substrate 10 is removed using deep silicon etching technology. The purpose of this step is to precisely remove the first substrate 10.

[0048] Without considering cost, deep silicon etching can be used to directly remove the first substrate 10, which is more than 100 micrometers in diameter, without the need for a thinning step.

[0049] like Figure 8 As shown, TMAH (tetramethylammonium hydroxide, a key chemical used in the developing process of photolithography, specifically as an alkaline aqueous developer) is used to remove any unetched silicon particles. The purpose of this step is to prevent the fabricated nanotooth 120 from being contaminated in subsequent processes, which would lead to increased losses.

[0050] like Figure 9 As shown, the remaining 3-micrometer-thick buried oxide layer 11 is dry-etched to remove approximately 2-micrometer-thick buried oxide layer 11, so that the first adhesive layer 141 forms multiple arrays of first adhesive pillars 1410, and the nanotooth 120 is located within the second adhesive layer 142 and between adjacent first adhesive pillars 1410.

[0051] The purpose of this step is to accelerate the removal of the buried oxide layer 11. The subsequent BOE (ammonium fluoride solution) has low corrosion efficiency for the transition state layer between silicon and silicon oxide. Prolonged immersion will cause the glass substrate used as the transfer substrate to also be corroded.

[0052] like Figure 10 As shown, the remaining buried oxide layer 11 is wet-etched to expose the nanotooth 120.

[0053] Specifically, BOE etching is used to remove the remaining buried oxide layer 11. The purpose of this step is to expose the surface of the soft adhesive, nano-tooth 120, for patch application. The nano-tooth 120 is exposed through the gap region between adjacent first adhesive pillars 1410.

[0054] In other embodiments, Figure 9 , Figure 10 The steps can also be replaced with Figure 13 , Figure 14 The second substrate 13 is attached to the third substrate 15, and the third substrate 15 completely covers the second substrate 13; then the buried oxide layer 11 is etched; the remaining buried oxide layer 11 is wet-etched to expose the nanotooth 120.

[0055] PDMS (polydimethylsiloxane, mainly used as the core material in soft lithography) can be used to attach the buried oxide layer 11, waveguide layer 12, adhesive 14, and glass surface of the glass substrate to the third substrate 15. Note that the glass substrate is completely encapsulated and protected by PDMS, which can prevent the glass substrate in the composite from being etched by BOE. After a sufficiently long soaking time, the buried oxide layer 11 can be completely removed.

[0056] It should be noted that PDMS can be replaced with other protective materials. Its purpose is to protect the glass substrate from contact with BOE, while the buried oxide layer 11 is exposed to contact with BOE.

[0057] Step 204: Remove the first adhesive layer 141 and form a plurality of second grooves 1420 in the second adhesive layer 142. Second adhesive pillars 1421 are formed between adjacent second grooves 1420, and nanotooth 120 is located in the second adhesive pillars 1421.

[0058] like Figure 11 As shown, laser processing removes the adhesive 14 material between the nanotooth 120, forming a second groove 1420 that extends to the surface of the second substrate 13. The purpose of this step is to directly expose the glass substrate to air for cutting. Compared to conventional removal methods, laser removal of the adhesive 14 material offers higher removal efficiency and precision.

[0059] Step 205: Split the second substrate 13 along the second slot 1420 to obtain multiple patch strips 100.

[0060] like Figure 12 As shown, the second substrate 13 is cut and cleaved to obtain patch strips 100. Laser cutting is used to obtain small patch strips 100 for patching. The patch strips 100 have nanotooth 120 and are supported by the second substrate 13.

[0061] For example, along the thickness direction (first direction F1), the first substrate 10 is 350um to 450um, the buried oxide layer 11 is 2um to 4um, the waveguide layer 12 is 210nm to 230nm, the second adhesive layer 142 is 130um to 150um, and the second substrate 13 is 500um to 600um.

[0062] In existing conventional silicon-on-insulator (SOI) fabrication and thinning processes, when using adhesives with low adhesion (such as PDMS) to fabricate Nanoteeth patches, if the silicon substrate is thinned to a certain thickness on the silicon dioxide buried oxide layer in SOI, curling can easily occur due to internal stress, causing the adhesive layer to detach and affecting the stability of the Nanoteeth patch. Figure 15 As shown.

[0063] Furthermore, in existing conventional SOI fabrication and thinning processes, when using adhesives with excessively strong bonding strength to fabricate Nanoteeth patches, wavy undulations can easily occur after the silicon substrate is removed, leaving only the buried oxide layer, potentially leading to crack formation. The direction and length of these cracks are uncontrollable, and when cracks traverse the Nanoteeth region, they can cause silicon waveguide breakage, failing to meet the requirements for low transmission loss. Figure 16 As shown.

[0064] On the other hand, UV adhesives shrink during the curing process, exhibiting a tendency to shrink after curing. When the silicon substrate is thick enough, its material strength is sufficient to effectively suppress this shrinkage. However, when the silicon substrate is thinned to a certain extent, its material strength is insufficient to resist the shrinkage of the UV adhesive, leading to wavy undulations on the adhesive surface and potentially causing cracks in the buried oxide layer 11, resulting in the breakage of the silicon waveguide. This phenomenon significantly affects quality control during the manufacturing process and the performance of the final product.

[0065] Using flexible soft adhesive materials for patching can also make them difficult to cut mechanically. Current cutting processes struggle to precisely cut them without damaging the structure, making it difficult to divide multiple Nanoteeth connectors fabricated simultaneously on an SOI wafer into usable Nanoteeth patch strips, thus impacting process efficiency and accuracy.

[0066] The above-mentioned problems can be solved by using the patch strip preparation method provided in this application embodiment. The patch strip preparation method provided in this application embodiment transfers the nanotooth 120 array structure prepared on the waveguide layer 12 completely onto the glass substrate using soft adhesive. Using an adhesive 14 with suitable adhesion, the nanotooth 120 can be firmly bonded to the glass substrate, avoiding curling and causing the adhesive 14 to fall off, thus ensuring the reliable connection of the nanotooth 120. Furthermore, the nanotooth 120 array structure and the second adhesive pillar 1421 form an interlocking state, forming a physical mechanical interlock, which can effectively resist shear force and peeling force, and also prevent interface delamination and curling. The tooth-shaped structure of the nanotooth 120 array can also disperse the concentrated stress during the bonding process to a larger area, avoiding excessive local stress that could cause material deformation, wrinkling, or breakage. In addition, the setting of the second slot 1420 also distributes the nanotooth 120 array, avoiding cracking caused by concentrated setting, and ensuring the structural integrity of the nanotooth 120. Therefore, the arrangement of the nanotooth 120 array in this application works synergistically from the physical and material levels through mechanical interlocking and stress dispersion, and the distribution of the nanotooth 120 through the second slot 1420 achieves high stability and high reliability in the bonding transfer process, thereby realizing a convenient and reliable patching process, and then connecting discrete optical waveguides with low loss.

[0067] Furthermore, the adhesive 14 with suitable adhesion can also avoid the problem of difficult cutting. In the final step of this application, when cutting the slit, the second substrate 13 is slit along the second groove 1420. The setting of the second groove 1420 avoids cutting the second adhesive layer 142 formed by NTT AT6001 material. At the same time, the laser cutting method can cut the second substrate 13 with precision without damaging the structure and with high cutting efficiency.

[0068] The aforementioned patch strip 100 connects the photonic chips, ultimately forming a large-scale optical waveguide network, completing the inter-waveguide interconnection of the photonic chips. For example, the photonic chip can be an LNOI photonic chip, or other photonic chips; this application does not specifically limit this. The patch strip fabrication method provided in this application embodiment can effectively avoid curling, wrinkling, and breakage. Figure 17 As shown, patch strips 100 for actual patching can be successfully separated from the nano-tooth 120 array group, and the cutting accuracy and cutting efficiency are both high.

[0069] Using the patch strip 100 and the alignment marks on the photonic chip, the patch strip 100 is attached to the interface of the adjacent chip of the photonic chip. A photograph of the completed patch installation is shown below. Figure 18 As shown, the seamless fit between the NTT AT6001 and the photonic chip can be seen through the transparent backplate glass, indicating a good bonding effect.

[0070] Reference Figure 19 As shown in the embodiments of this application, an optical waveguide network chip is also disclosed, including multiple photonic chips, which are connected by a patch strip 100 obtained by any of the patch strip preparation methods described above.

[0071] On the other hand, this application also provides an optical quantum computer, including a quantum light source, a detector, and a photonic chip of the aforementioned optical waveguide network chip.

[0072] In this system, quantum light sources generate photons, which are then transmitted through photonic chips in an optical waveguide network chip. A detector converts the optical signals from the photonic chips into electrical signals to achieve functions such as transmission or display.

[0073] The optical waveguide network chip and optical quantum computer have the same structure and beneficial effects as the patch strip fabrication method in the foregoing embodiments. The structure and beneficial effects of the patch strip fabrication method have been described in detail in the foregoing embodiments and will not be repeated here.

[0074] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method of preparing a patch strip, characterized by, The method comprises the following steps: forming a buried oxide layer and a waveguide layer on a first substrate in sequence, and forming a plurality of nanotines arranged in an array on the waveguide layer; etching the buried oxide layer to form a plurality of first grooves in the buried oxide layer, and forming oxide columns between adjacent first grooves, wherein the nanotines are located on the oxide columns; bonding a second substrate to the waveguide layer by an adhesive, and the adhesive away from the second substrate extends into the first grooves to form a first adhesive layer; the adhesive close to the second substrate and not extending into the first grooves forms a second adhesive layer; removing the first substrate and the buried oxide layer; removing the first adhesive layer, and forming a plurality of second grooves in the second adhesive layer, and forming second adhesive columns between adjacent second grooves, wherein the nanotines are located in the second adhesive columns; breaking the second substrate along the second grooves to obtain a plurality of patch strips.

2. The method of claim 1, wherein, The method of forming a buried oxide layer and a waveguide layer on a first substrate in sequence, and forming a plurality of nanotines arranged in an array on the waveguide layer comprises: forming the buried oxide layer and the waveguide layer on the first substrate in sequence; photolithographing the waveguide layer to form a plurality of nanotines on the waveguide layer.

3. The method of claim 1 or 2, wherein The method of etching the buried oxide layer to form a plurality of first grooves in the buried oxide layer, and forming oxide columns between adjacent first grooves, wherein the nanotines are located on the oxide columns, comprises: the depth of the first grooves in a first direction is at least greater than 1.5 um, the width of the first grooves in a second direction is at least greater than 10 um, the etching period of a plurality of first grooves in the second direction is less than 1000 um, and the etching period of a plurality of first grooves in a third direction is less than 400 um; the first direction, the second direction and the third direction are perpendicular to each other.

4. The method of claim 3, wherein the patch strip is prepared by The method of removing the first substrate and the buried oxide layer comprises: thinning the first substrate; removing the remaining first substrate after thinning by a deep silicon etching process; dry etching the buried oxide layer to form a plurality of arrays of first adhesive columns in the first adhesive layer, wherein the nanotines are located in the second adhesive layer and between adjacent first adhesive columns; wet etching the remaining buried oxide layer to expose the nanotines.

5. The method of claim 3, wherein the patch strip is prepared by the steps of: The method of removing the first substrate and the buried oxide layer comprises: thinning the first substrate; removing the remaining first substrate after thinning by a deep silicon etching process; adhering the second substrate to a third substrate, and wrapping the second substrate with the third substrate; etching the buried oxide layer; wet etching the remaining buried oxide layer to expose the nanotines.

6. The method of claim 4 or 5, wherein the patch strip is prepared by The method of wet etching the remaining buried oxide layer to expose the nanotines comprises: adopting an ammonium fluoride solution to etch the remaining buried oxide layer.

7. The method of claim 1, wherein The first substrate is a silicon substrate, the buried oxide layer is a silicon dioxide layer, the waveguide layer is a silicon waveguide, and the second substrate is glass.

8. The method of claim 1 or 7, wherein, Along the thickness direction, the first substrate is 350um to 450um, the buried oxide layer is 2um to 4um, the waveguide layer is 210nm to 230nm, the second adhesive layer is 130um to 150um, and the second substrate is 500um to 600um.

9. An optical waveguide network chip, characterized by It includes multiple photonic chips, and the multiple photonic chips are connected by the patch strip obtained by the patch strip preparation method according to any one of claims 1 to 8.

10. A photonic quantum computer, characterized by It includes a quantum light source, a detector, and a photonic chip as described in claim 9, which is a waveguide network chip.

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