Memory configuration method and device, electronic equipment, storage medium and program product

Abstract

The application relates to the technical field of integrated circuits and discloses a memory configuration method and device, electronic equipment, a storage medium and a program product. The method is applied to a configuration engine connected to a starting end of a cascade chain formed by connecting a plurality of memories in series through cascade signals; the method comprises the following steps: receiving a configuration instruction, determining a target memory to be configured, and acquiring a position identifier of the target memory in the cascade chain; broadcasting the position identifier to the cascade chain, so that the target memory enters an active state and feeds back a ready signal, and the remaining memories enter a bypass state to transparently transmit passing data; after detecting the ready signal, outputting configuration data, so that the configuration data is sequentially transmitted along the cascade chain and directly reaches the target memory through the intermediate memories in the bypass state, so that the target memory receives the configuration data and completes a configuration operation. The above scheme can improve the configuration efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to memory configuration methods, apparatus, electronic devices, storage media, and program products. Background Technology

[0002] An FPGA (Field-Programmable Gate Array) is a programmable integrated circuit that can be configured by the user to implement specific digital logic functions. During the initial power-up phase of an FPGA, the system configures its internal logic and memory resources by loading a bitstream file to complete the device's functional initialization.

[0003] In related technologies, the on-chip memory of FPGA is configured using a bus method. However, as the size of FPGA increases, the size of the bus circuit specially designed for memory also increases, increasing the hardware implementation cost. Furthermore, the increased size of the bus circuit limits the operating frequency of hardware loading and readback, reducing configuration efficiency. Summary of the Invention

[0004] This invention provides a memory configuration method, apparatus, electronic device, storage medium, and program product to at least solve the problem of low efficiency in memory configuration schemes in related technologies.

[0005] In a first aspect, the present invention provides a memory configuration method applied to a configuration engine; the configuration engine is connected to the starting end of a cascade chain formed by multiple memories connected in series via cascade signals; the method includes:

[0006] Receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain;

[0007] The location identifier is broadcast to the cascaded chain, causing the target memory to enter an active state and feed back a ready signal, while the other memories enter a bypass state to pass through the data.

[0008] Upon detecting the ready signal, configuration data is output, which is transmitted sequentially along the cascade chain and directly reaches the target memory through an intermediate memory in a bypass state, so that the target memory can receive the configuration data and complete the configuration operation.

[0009] In one optional implementation, a timing adjustment register is provided in the end memory of the cascaded chain; the timing adjustment register is used to register and schedule configuration data passing through the end memory.

[0010] In one alternative implementation, when the length of the cascade chain is detected to exceed a preset threshold, a register enable signal is sent, causing the register enable signal to be transmitted sequentially along the cascade chain to the end memory, so that the end memory receives the register enable signal and enables the timing adjustment register.

[0011] In an optional implementation, the method further includes:

[0012] Send a readback request to the cascaded chain, so that the readback request is transmitted sequentially along the cascaded chain to the target memory to be verified;

[0013] The system receives the configured data fed back by the target memory according to the readback request; the configured data is then transmitted back to the configuration engine along the cascade chain.

[0014] The configured data is compared and verified based on the original configuration data to determine the correctness of the configuration result.

[0015] In one alternative implementation, the location identifier includes at least one of the following:

[0016] Address number, used to indicate the sequential number of the target memory on the cascade chain;

[0017] The index number is used to indicate the logical identifier corresponding to the target memory.

[0018] Physical location information, used to indicate the coordinates of the target memory.

[0019] In one optional implementation, the configuration engine is connected to the starting ends of multiple parallel cascaded chains; the method further includes:

[0020] Receive configuration instructions and parse the chain index information and the target memory location identifier in the configuration instructions;

[0021] The target cascaded chain to be operated on is determined based on the chain index information, and the target cascaded chain is set to an active state, while the other cascaded chains remain inactive.

[0022] The location identifier is broadcast to the target cascade chain, causing the target memory to enter an active state and feed back a ready signal. The remaining memories on the target cascade chain enter a bypass state to pass through the data.

[0023] Secondly, the present invention provides a memory configuration apparatus for use in a configuration engine; the configuration engine is connected to the starting end of a cascade chain formed by multiple memories connected in series via cascaded signals; the apparatus includes:

[0024] The instruction receiving module is used to receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain;

[0025] The broadcast module is used to broadcast the location identifier to the cascaded chain, so that the target memory enters the active state and feeds back a ready signal, while the other memories enter the bypass state to pass through the data.

[0026] The configuration data output module is used to output configuration data after detecting the ready signal, so that the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memory in the bypass state, so that the target memory can receive the configuration data and complete the configuration operation.

[0027] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory configuration method of the first aspect or any corresponding embodiment described above.

[0028] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the memory configuration method of the first aspect or any corresponding embodiment thereof.

[0029] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the memory configuration method of the first aspect or any corresponding embodiment thereof.

[0030] The technical solution provided by this invention may include the following beneficial effects:

[0031] The memory configuration method provided by this invention achieves precise addressing of the target memory by receiving configuration instructions, determining the target memory to be configured, and obtaining the position identifier of the target memory in the cascade chain, thus avoiding the resource waste caused by full broadcast. By broadcasting the position identifier to the cascade chain, each memory in the cascade chain can autonomously compare addresses and dynamically enter active or bypass states, completing distributed control without complex decoding circuits and significantly reducing logic overhead. By setting a ready signal for the target memory to feed back, the timing synchronization and reliability of data transmission are ensured, eliminating the risk of accidental writes. By setting the other memories to enter bypass states to pass through the data, an efficient serial path is constructed, simplifying the data path structure. By setting the output of configuration data after detecting the ready signal, the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through intermediate memories in bypass states, making full use of a single wire control mechanism to complete long-distance writing, saving wiring resources and supporting high-frequency operation. Finally, the target memory receives the configuration data and completes the configuration operation, forming a closed-loop process. Therefore, the above solution enables precise addressing and data loading of the target memory without the need for a traditional bus, significantly reducing hardware resource overhead and wiring complexity, simplifying control logic, improving configuration efficiency and scalability, and achieving rapid initialization and flexible management. Attached Figure Description

[0032] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a schematic flowchart of a first method for configuring a memory according to an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of a second process for a memory configuration method according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the cascaded chain partitioning according to an embodiment of the present invention;

[0036] Figure 4 This is a structural block diagram of a memory configuration apparatus according to an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0040] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] An FPGA (Field Programmable Gate Array) is a programmable integrated circuit that can be configured by the user to implement specific digital logic functions. During the initial power-up phase of an FPGA, the system loads a bitstream file to configure the internal logic and memory resources, thus completing the device's functional initialization.

[0042] In related technologies, dedicated address decoding and bus circuits are designed for a large number of memories, and bitstream files are loaded through the CFGengine (Configuration Engine) bus to configure all memories on the FPGA chip, including address decoding, chip selection, loading configuration data, and reading back initialization data. However, as the scale of FPGAs increases, the size of the bus circuits specially designed for the memories also increases, leading to increased hardware configuration overhead and higher hardware implementation costs. Furthermore, the increased bus circuit size results in longer bus paths, heavier loads, and limitations on the operating frequency of hardware loading and reading back due to bus performance, thus reducing overall configuration efficiency.

[0043] According to an embodiment of the present invention, a memory configuration method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0044] This embodiment provides a memory configuration method, applied to a configuration engine; Figure 1 This is a flowchart of a memory configuration method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0045] Step S101: Receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain.

[0046] The configuration engine connects to the beginning of a cascade chain formed by multiple memories connected in series via cascading signals. In other words, the configuration engine is connected to the memory at the beginning of the cascade chain. The memories in this cascade chain are connected end-to-end, forming a series structure. The cascade chain can be deployed on the FPGA chip in any topology, dynamically adjusted according to the FPGA chip's physical layout and routing resources, and is not limited by a fixed bus architecture. The specific number of memories is set according to the actual application scenario. For example, if there are N memories in the cascade chain, and these N memories are sequentially labeled 1 to N, then the memories are connected sequentially according to their indexes, i.e., 1-2-3-…-N. Adjacent memories communicate via cascading signals. If data needs to be sent to the k-th memory, it needs to pass through the memories preceding the k-th memory sequentially. That is, the data output by the configuration engine passes through the first to (k-1) memories before being transmitted to the k-th memory.

[0047] For example, the cascaded signal includes control signals and data signals. The control signals are used to control the read and write operations, including read and write commands, address broadcasts, ready signals, etc.; the data signals are the actual data stream transmitted.

[0048] For example, the memory is a block random access memory (BRAM) in an FPGA chip, and the various BRAMs in the FPGA chip are connected into a cascade chain through cascading signals.

[0049] During the power-on initialization phase of the FPGA chip, an external configuration master device (such as a configuration chip, processor, downloader, etc.) loads bitstream data containing configuration instructions into the FPGA chip. Then, the configuration instructions are sent to the configuration engine through the corresponding interface or configuration bus. The configuration engine receives the configuration instructions and parses the relevant information of the target memory (such as number, location, etc.) contained in the configuration instructions to determine the target memory to be configured and the location identifier of the target memory on the cascade chain. The location identifier is used to uniquely identify the address of the target memory.

[0050] In step S102, the location identifier is broadcast to the cascade chain, causing the target memory to enter the active state and feed back a ready signal, while the remaining memories enter the bypass state to pass through the data.

[0051] The location identifier is broadcast to the cascade chain, and this identifier is transmitted sequentially along the chain, passing through each memory in turn. Each memory determines whether it is the target memory based on the location identifier, until a target memory is identified. Specifically, if a memory determines that it is not the target memory, it enters a bypass state. In the bypass state, the memory transparently transmits the data it has passed through (such as the location identifier and a ready signal). Transparent transmission is a technique that does not parse or process the data content during data transmission, and does not change the data content or format; it only transmits the data from the input end to the output end to improve transmission speed and reduce communication latency. If a memory determines that it is the target memory, it is identified as the target memory, the location identifier stops being transmitted, the target memory enters an active state, and feeds back a ready signal. This ready signal indicates that the target memory is ready to perform configuration operations, and this ready signal is transmitted back to the configuration engine along the cascade chain.

[0052] Step S103: After detecting the ready signal, configuration data is output, so that the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memory in the bypass state, so that the target memory can receive the configuration data and complete the configuration operation.

[0053] After detecting the ready signal from the target memory, the configuration engine determines that the target memory is ready for configuration operations. It then outputs the configuration data corresponding to the target memory to the cascade chain. The configuration data is transmitted sequentially along the cascade chain. The intermediate memories between the configuration engine and the target memory are all in a bypass state, and the configuration data is transmitted transparently until the configuration data is transmitted to the target memory. The target memory receives the configuration data and completes the configuration operation based on the configuration data.

[0054] By connecting the various memories in the FPGA chip end-to-end with cascading signals to form a cascade chain, the configuration engine only needs to connect to the first memory in the cascade chain (the starting memory). This allows configuration of all memories in the cascade chain via cascading signals, eliminating the need for a configuration bus, saving hardware overhead, effectively reducing the size of the configuration bus, and improving configuration efficiency.

[0055] The memory configuration method provided in this embodiment achieves precise addressing of the target memory by receiving configuration instructions, determining the target memory to be configured, and obtaining the location identifier of the target memory in the cascade chain, thus avoiding the resource waste caused by full broadcast. By broadcasting the location identifier to the cascade chain, each memory in the cascade chain can autonomously compare addresses and dynamically enter active or bypass states, completing distributed control without complex decoding circuits and significantly reducing logic overhead. By setting the target memory to feed back a ready signal, the timing synchronization and reliability of data transmission are ensured, eliminating the risk of accidental writes. By setting the other memories to enter bypass states to pass through the data, an efficient serial path is constructed, simplifying the data path structure. By setting the configuration data to output after detecting the ready signal, the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memories in bypass states, making full use of a single wire control mechanism to complete long-distance writing, saving wiring resources and supporting high-frequency operation. Finally, the target memory receives the configuration data and completes the configuration operation, forming a closed-loop process. Therefore, the above solution enables precise addressing and data loading of the target memory without the need for a traditional bus, significantly reducing hardware resource overhead and wiring complexity, simplifying control logic, improving configuration efficiency and scalability, and achieving rapid initialization and flexible management.

[0056] This embodiment provides a memory configuration method applied to a configuration engine; the configuration engine is connected to the starting end of a cascade chain formed by multiple memories connected in series via cascade signals; Figure 2 This is a flowchart of a memory configuration method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0057] Step S201: Receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain.

[0058] This location identifier uniquely identifies the target memory on the cascade chain. The location identifier is encoded in a configuration instruction and propagated along the cascade chain to trigger a response operation from the corresponding memory (target memory). Optionally, the location identifier includes at least one of the following:

[0059] The address number is used to indicate the sequential number of the target memory in the cascade chain. For example, k is used to indicate the kth memory in the cascade chain.

[0060] The index number is used to indicate the logical identifier corresponding to the target memory. This index number is obtained by the configuration engine mapping the target memory.

[0061] Physical location information, used to indicate the coordinates of the target memory, such as the layout coordinates of the target memory in the FPGA chip or the identifier of the functional area to which it belongs.

[0062] Furthermore, the address number is a continuous integer sequence, starting at the beginning of the cascade chain and increasing sequentially along the cascade chain.

[0063] Furthermore, the index number supports non-linear mapping relationships, allowing for skipped numbering or multi-segment grouping structures.

[0064] Furthermore, the physical location information includes two-dimensional planar coordinates (X,Y) to locate the specific position of the memory in the layout array of the FPGA chip.

[0065] Furthermore, during the broadcast process, the location identifier is compared sequentially by each memory. If a match is found, the system enters the active state; otherwise, it enters the bypass state.

[0066] Since the maximum operating frequency of a circuit is determined by the combinational logic delay between registers, the larger the combinational logic delay, the lower the maximum frequency. However, the combinational logic delay of a single memory is generally fixed. Therefore, to overcome the timing bottleneck caused by excessively long combinational logic paths due to excessively long cascade chains, registers can be configured in the terminal memory (the last memory, the cascade boundary) of the cascade chain to selectively schedule data in the terminal memory, ensuring data is registered for one clock cycle. If the maximum frequency for a single memory is f, and there are N memories in the cascade chain, the maximum frequency decreases to f / N when registers are not enabled. When registers are enabled, the longest combinational logic path is the same as the combinational logic path of a single register, meaning the maximum frequency of the entire circuit is also f. This divides the long combinational logic path spanning multiple memories into independent pipeline stages, improving the maximum operating frequency and stability of the circuit, maintaining a high operating frequency during long-chain configurations, and significantly improving configuration efficiency and scalability. Specifically, a timing adjustment register is set in the terminal memory of the cascade chain; this timing adjustment register is used to schedule the configuration data passing through the terminal memory.

[0067] Optionally, a threshold (preset threshold) can be pre-set based on the actual working state of the FPGA chip (e.g., functional area allocation, cascade chain length, system timing requirements, etc.) and the configuration / readback limit performance of a single memory. This threshold serves as the basis for judging whether the cascade chain is too long, thereby setting the enable condition of the timing adjustment register. When the cascade chain is too long and causes excessive path delay, the register is enabled to meet the high-frequency working requirements. Specifically, when the length of the cascaded chain exceeds a preset threshold, a register enable signal is sent. This signal is then transmitted sequentially along the cascaded chain to the end memory, where it receives and activates the timing adjustment register. The timing adjustment register then enters its working state, pausing the data in the end memory and locking it in the timing adjustment register before outputting it in the next pause. This cuts off the long combinational logic path that originally spanned multiple memories, confining it to a single memory. The maximum delay of signal propagation depends only on the internal logic of that single memory, preventing a decrease in system operating frequency due to link growth, avoiding accumulated delay, and increasing the overall operating frequency limit of the cascaded chain. Otherwise, the timing adjustment register is not activated, and data is passed directly through the cascaded chain to reduce latency.

[0068] Optionally, the memories in the FPGA chip are divided into multiple parallel cascaded chains. Each cascaded chain consists of several memories connected in series end-to-end via cascading signals, and they are electrically isolated from each other. Different cascaded chains communicate with each other through a shared control bus, but their data paths are isolated from each other. The configuration engine is connected to the starting end of each of the multiple parallel cascaded chains. When configuring the memory, the configuration engine first receives a configuration command, parses the chain index information and the location identifier of the target memory in the configuration command. The chain index information is used to uniquely identify the cascaded chain to be operated. Then, the engine determines the target cascaded chain to be operated based on the chain index information and sets the target cascaded chain to an active state, while the other cascaded chains connected to the configuration engine remain inactive. Then, the engine broadcasts the location identifier to the target cascaded chain, causing the target memory to enter an active state and feed back a ready signal. The other memories on the target cascaded chain enter a bypass state to pass through the data.

[0069] Optionally, the configuration engine controls the sending and receiving process of configuration data through an internal state machine to ensure that only one data transmission operation is executed at any given time, thus avoiding communication conflicts.

[0070] Optionally, each cascade chain's end memory is equipped with a timing adjustment register to selectively enable data register functionality based on the length and operating frequency requirements of the cascade chain, in order to maintain a high operating frequency.

[0071] Optionally, these multiple cascaded chains can be divided according to the functional areas of the chip, including but not limited to memory sets within the logic computation area, data cache area, or high-speed interface area. The grouping structure and chain index mapping relationship of this cascaded chain can be redefined by the bitstream file during the initialization phase of the FPGA chip, enabling flexible resource configuration.

[0072] For example, Figure 3 This is a schematic diagram of cascaded chain partitioning according to an embodiment of the present invention. The configuration engine is connected in series with each level of cascaded chain via a configuration engine bus (cfg bus). The configuration engine manages different cascaded chains through different chain index information. Data transmission is not prioritized, and there is no situation where data is transmitted or received simultaneously. The configuration engine controls data transmission and reception to avoid conflicts through an internal state machine. The optional D flip-flop (DFF, or Data Flip-Flop) can be used as a timing adjustment register.

[0073] Therefore, the memory configuration method provided in this embodiment has strong scalability, and the cascade chain can be propagated in any way on the FPGA chip. As the size of the FPGA chip increases, the grouping and propagation methods of the cascade chain can be modified to adapt to different FPGA chip architecture requirements. When the cascade length is long, the circuit configuration, readback timing, and extreme performance can be flexibly adjusted by opening the timing adjustment register at the cascade boundary.

[0074] Furthermore, this memory configuration method is also applicable to applications in high-capacity FPGA chips, AI accelerators, high-speed communication devices, or high-reliability embedded systems, in order to reduce memory configuration hardware overhead and improve configuration efficiency and system startup speed.

[0075] In step S202, the location identifier is broadcast to the cascade chain, causing the target memory to enter the active state and feed back a ready signal, while the remaining memories enter the bypass state to pass through the data.

[0076] Please see details Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0077] Step S203: After detecting the ready signal, configuration data is output so that the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memory in the bypass state, so that the target memory can receive the configuration data and complete the configuration operation.

[0078] Please see details Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0079] Step S204: Send a readback request to the cascade chain, so that the readback request is transmitted sequentially along the cascade chain to the target memory to be verified.

[0080] In FPGA chip power-on initialization configuration integrity verification, production testing yield assessment, or field operation fault diagnosis, data readback verification is performed on the target memory to be verified to improve configuration yield and testability. Specifically, the configuration engine sends a readback request to the cascade chain, which is transmitted sequentially along the cascade chain until it reaches the target memory to be verified. The target memory then feeds back its configured data based on the readback request.

[0081] Step S205: Receive the configured data fed back by the target memory according to the readback request.

[0082] The configured data is transmitted back to the configuration engine along the cascade chain. The reverse transmission path reuses the cascade signal path used in the forward configuration, only changing the direction of data flow. During the readback process, each level of memory is still in bypass mode, only responsible for transparently forwarding the back data. The configuration engine receives the configured data.

[0083] Optionally, in a multi-parallel cascaded chain architecture, readback operations are executed in time-sharing on a chain-by-chain basis to avoid data conflicts.

[0084] Step S206: The configured data is compared and verified based on the original configuration data to determine the correctness of the configuration result.

[0085] The original configuration data is the configuration data transmitted when performing forward configuration of the target memory. After receiving the configured data, the configuration engine compares and verifies the configured data with the original configuration data. If the configured data is consistent with the original configuration data, the configuration result is determined to be correct; otherwise, the configuration result is determined to be incorrect, and an error is reported or the configuration operation is re-executed.

[0086] The memory configuration method provided in this embodiment sets a timing adjustment register in the end memory of the cascade chain and sets the activation conditions for the timing adjustment register. When the length of the cascade chain is detected to exceed a preset threshold, the timing adjustment register is activated, causing the timing adjustment register to puncture the data in the end memory. This cuts off the long combinational logic path that originally spanned multiple memories and restricts the combinational logic path to a single memory, thereby preventing the system operating frequency from decreasing due to link growth and improving the operating limit frequency of the entire cascade chain. By setting chain index information, the configuration engine can configure multiple parallel cascade chains, improving configuration flexibility and scalability. By performing data readback verification on the target memory to be verified, the configuration yield and testability are improved.

[0087] This embodiment also provides a memory configuration device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0088] This embodiment provides a memory configuration device applied to a configuration engine; the configuration engine is connected to the starting end of a cascade chain formed by multiple memories connected in series via cascaded signals; such as Figure 4 As shown, the device includes:

[0089] The instruction receiving module 401 is used to receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain.

[0090] Broadcast module 402 is used to broadcast the location identifier to the cascade chain, so that the target memory enters the active state and feeds back a ready signal, while the other memories enter the bypass state to pass through the data.

[0091] The configuration data output module 403 is used to output configuration data after detecting the ready signal, so that the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memory in the bypass state, so that the target memory can receive the configuration data and complete the configuration operation.

[0092] In one alternative implementation, a timing adjustment register is provided in the end memory of the cascade chain; the timing adjustment register is used to register and stamp configuration data passing through the end memory.

[0093] In an alternative implementation, the device further includes a register management module for:

[0094] When the length of the cascade chain exceeds a preset threshold, a register enable signal is sent, which is then transmitted sequentially along the cascade chain to the end memory, so that the end memory can receive the register enable signal and enable the timing adjustment register.

[0095] In an optional implementation, the device further includes a readback verification module for:

[0096] Send a readback request to the cascade chain, so that the readback request is transmitted sequentially along the cascade chain to the target memory to be verified;

[0097] The system receives the configured data fed back by the target memory according to the readback request; the configured data is then transmitted back to the configuration engine along the cascade chain.

[0098] The configured data is compared and verified based on the original configuration data to determine the correctness of the configuration result.

[0099] In one alternative implementation, the location identifier includes at least one of the following:

[0100] Address number, used to indicate the sequential number of the target memory in the cascade chain;

[0101] The index number is used to indicate the logical identifier corresponding to the target memory.

[0102] Physical location information, used to indicate the coordinates of the target memory.

[0103] In one alternative implementation, the configuration engine is connected to the starting ends of multiple parallel cascaded chains; the instruction receiving module is further configured to:

[0104] Receive configuration instructions and parse the chain index information and the target memory location identifier in the configuration instructions;

[0105] The target cascade chain to be operated on is determined based on the chain index information, and the target cascade chain is set to the active state, while the other cascade chains remain inactive.

[0106] This broadcast module is also used for:

[0107] The location identifier is broadcast to the target cascade chain, causing the target memory to enter an active state and feed back a ready signal. The remaining memories on the target cascade chain enter a bypass state to pass through the data.

[0108] The memory configuration apparatus provided in this embodiment of the invention can execute the memory configuration method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the various modules and units described above are the same as in the corresponding embodiments described above, and will not be repeated here.

[0109] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0110] The following is a detailed reference. Figure 5This diagram illustrates a suitable structural schematic for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from memory 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the electronic device. The processor 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0111] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509. Communication device 509 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0112] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a memory 508, or installed from a ROM 502. When the computer program is executed by the processor 501, it performs the functions defined in the memory configuration method of the embodiments of the present invention.

[0113] Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0114] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the memory configuration method shown in the above embodiments is implemented.

[0115] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0116] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the invention.

Claims

1. A memory configuration method, characterized in that, Applied to a configuration engine; the configuration engine is connected to the start of a cascade chain formed by multiple memories connected in series via cascaded signals; the method includes: Receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain; The location identifier is broadcast to the cascaded chain, causing the target memory to enter an active state and feed back a ready signal, while the other memories enter a bypass state to pass through the data. After detecting the ready signal, configuration data is output, so that the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memory in the bypass state, so that the target memory can receive the configuration data and complete the configuration operation; The cascaded chain's end memory is provided with a timing adjustment register; the timing adjustment register is used to register and schedule configuration data passing through the end memory, so as to limit the combinational logic path to a single memory range; When the length of the cascade chain exceeds a preset threshold, a register enable signal is sent, which is then transmitted sequentially along the cascade chain to the end memory, so that the end memory can receive the register enable signal and enable the timing adjustment register.

2. The method according to claim 1, characterized in that, The method further includes: Send a readback request to the cascaded chain, so that the readback request is transmitted sequentially along the cascaded chain to the target memory to be verified; The system receives the configured data fed back by the target memory according to the readback request; the configured data is then transmitted back to the configuration engine along the cascade chain. The configured data is compared and verified based on the original configuration data to determine the correctness of the configuration result.

3. The method according to claim 1, characterized in that, The location identifier includes at least one of the following: Address number, used to indicate the sequential number of the target memory on the cascade chain; The index number is used to indicate the logical identifier corresponding to the target memory. Physical location information, used to indicate the coordinates of the target memory.

4. The method according to claim 1, characterized in that, The configuration engines are respectively connected to the starting ends of multiple parallel cascaded chains; the method further includes: Receive configuration instructions and parse the chain index information and the target memory location identifier in the configuration instructions; The target cascaded chain to be operated on is determined based on the chain index information, and the target cascaded chain is set to an active state, while the other cascaded chains remain inactive. The location identifier is broadcast to the target cascade chain, causing the target memory to enter an active state and feed back a ready signal. The remaining memories on the target cascade chain enter a bypass state to pass through the data.

5. A memory configuration device, characterized in that, Applied to the configuration engine; The configuration engine is connected to the beginning of a cascade chain formed by multiple memories connected in series via cascade signals; The device includes: The instruction receiving module is used to receive configuration instructions, determine the target memory to be configured, and obtain the position identifier of the target memory in the cascade chain; The broadcast module is used to broadcast the location identifier to the cascaded chain, so that the target memory enters the active state and feeds back a ready signal, while the other memories enter the bypass state to pass through the data. The configuration data output module is used to output configuration data after detecting the ready signal, so that the configuration data is transmitted sequentially along the cascade chain and directly to the target memory through the intermediate memory in the bypass state, so that the target memory can receive the configuration data and complete the configuration operation; The cascaded chain's end memory is provided with a timing adjustment register; the timing adjustment register is used to register and schedule configuration data passing through the end memory, so as to limit the combinational logic path to a single memory range; The device further includes a detection module for: When the length of the cascade chain exceeds a preset threshold, a register enable signal is sent, which is then transmitted sequentially along the cascade chain to the end memory, so that the end memory can receive the register enable signal and enable the timing adjustment register.

6. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory configuration method of any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the memory configuration method according to any one of claims 1 to 4.

8. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the memory configuration method according to any one of claims 1 to 4.

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