Metadata register for memory device

Abstract

This disclosure provides systems, methods, and devices for a memory system supporting metadata. In a first aspect, a method of processing data and metadata at a memory device includes receiving data from a host into a first plurality of registers via at least one data connection; receiving metadata from the host into a second plurality of registers via at least one non-data connection; storing data in a first portion of the memory array; and storing the metadata in a second portion of the memory array. Other aspects and features are also claimed and described.

Description

[0001] This application is a continuation of patent application No. 202380071787.8, with the title “METADATA REGISTERS FOR A MEMORY DEVICE”, filed on September 14, 2023, having the same filing date and priority date, and claiming the benefit of priority to U.S. Patent Application No. 18 / 047,493, filed on October 18, 2022, entitled “METADATA REGISTERS FOR A MEMORY DEVICE”, the entire contents of which are expressly incorporated herein by reference. Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 047,493, filed on October 18, 2022, entitled “METADATA REGISTERS FOR A MEMORY DEVICE”, the entire contents of which are expressly incorporated herein by reference. TECHNICAL FIELD

[0003] Aspects of the disclosure relate generally to computer information systems, and more particularly, to memory systems for storing data. Some features can enable and provide improved memory capabilities for storing metadata, such as error-correcting codes (ECCs) for data stored in memory. BACKGROUND

[0004] Computing devices (e.g., laptops, mobile phones, etc.) can include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions, among others. Memory is an important component of a computing device. The processor(s) can be coupled to the memory to perform the computing functions described above, to fetch instructions from the memory to perform the computing functions and / or to store temporary data within the memory for processing these computing functions, among others. SUMMARY

[0005] The following summarizes some aspects of the disclosure to provide a basic understanding of the discussed technology. This summary is not a comprehensive overview of all the contemplated features of the disclosure, and is neither intended to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a generalized form as a prelude to the more detailed description to be given later.

[0006] An apparatus according to at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing a compute function. In some aspects, registers of the memory device can be configured to store data and metadata separately in different sets of registers. Metadata registers can temporarily store information during a transfer between a host device and the memory device for retrieval from the memory array of the memory device in response to a read command or storage in the memory array of the memory device in response to a write command.

[0007] In one aspect of the disclosure, a memory device includes a memory array including a first portion and a second portion; and a memory input / output (I / O) module. The memory I / O module can be coupled to the memory array, configured to communicate with a host over a channel including a plurality of connections including at least one data connection and at least one non-data connection, and including at least one first register and at least one second register. The memory I / O module can be configured to perform operations including receiving data from the host into the at least one first register via the at least one data connection; receiving metadata from the host into the at least one second register via the at least one non-data connection; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. The memory I / O module can also be configured to perform operations including retrieving data from the first portion of the memory array into the at least one first register; retrieving metadata from the second portion of the memory array into the at least one second register; sending the data from the at least one first register to the host via the at least one data connection; and sending the metadata from the at least one second register to the host via the at least one non-data connection.

[0008] In an additional aspect of the disclosure, an apparatus, such as a wireless device, includes at least one processor and memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory through a memory controller coupled to a channel that couples the processor to the memory. The processor can be a processor, controller, or other logic circuitry in a host.

[0009] In an additional aspect of the disclosure, a non-transitory computer- readable medium stores instructions that, when executed by a processor, cause the processor to perform operations described herein with respect to aspects of the disclosure.

[0010] The term one or more error-correcting codes (ECCs) in this disclosure can refer to error detection, error correction, or error detection and correction codes. ECCs are not limited to a particular type of decoding. In some examples, ECCs can include Hamming codes and / or parity check codes.

[0011] Memory in this disclosure can be embedded within a processor on a semiconductor die or be part of a different semiconductor die. Memory can be a variety of types. For example, memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.

[0012] Methods and apparatus are presented in this disclosure by the non-limiting example of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, LPDDR memory operates according to LPDDR specifications promulgated by the Joint Electron Device Engineering Council (JEDEC). One such LPDDR specification can be LPDDR5. Another such LPDDR specification can be LPDDR6.

[0013] Other aspects, features, and implementations will become apparent to those of ordinary skill in the art, upon reviewing the following description in conjunction with the accompanying figures. While features can be discussed relative to certain example aspects and figures below, one or more of such features can be utilized in accordance with various aspects. In other words, while one or more aspects can be discussed as having certain advantageous features, one or more of such features can also be used in accordance with the various aspects. In a similar manner, different example aspects can be discussed hereinafter with reference to a device, system, or method aspect. As such, a claim can come in a device, system, or method aspect.

[0014] The method can be embedded in a computer-readable medium as computer program code comprising instructions that cause a processor to perform the steps of the method. In some embodiments, the processor can be part of a mobile device that includes a first network adapter configured to transmit data, such as images or video in a recording, or as streaming data, over a first network connection of a plurality of network connections. The processor can be coupled to the first network adapter and to a memory for storing data that supports processing and communication operations performed by the processor. The network adapter can support communication over a wireless communication network, such as a 5G NR communication network. The processor can cause transmission of data stored in the memory over the wireless communication network.

[0015] The foregoing has outlined rather broadly the features and technical advantages of examples according to the disclosure in order that the detailed description that follows can be better understood. Additional features and advantages will be described hereinafter. The disclosed concepts and specific examples can be readily utilized as bases or premises for the design of other structures for performing the same purposes thereof. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein, both their organization and method of operation, together with related advantages will be better understood from the following description when considered in connection with the accompanying drawings. Each of the figures is provided for the purpose of illustration and description, and is not intended as a definition of the limits of the claims.

[0016] While aspects and implementations are described in this application by illustration to some examples, those skilled in the art will understand that additional implementations and use cases can come about in many other arrangements and scenarios. Innovations described herein can be implemented across many differing platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects and / or uses can come about in integrated chip implementations and other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, artificial intelligence (Al)-enabled devices, etc.). While some examples can or can not be specifically directed to use cases or applications, a wide assortment of applicability of the innovations described can occur. Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregate, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some physical settings, devices incorporating described aspects and features can necessarily include additional components and features to enable and practice claimed and described aspects. For example, transmission and reception of wireless signals necessarily includes a number of components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.). Innovations described herein are intended to be applicable in a wide array of devices, chip-level components, systems, distributed arrangements, end-user devices, etc. of varying sizes, shapes, and constitution. BRIEF DESCRIPTION OF DRAWINGS

[0017] Further understanding of the nature and advantages of the disclosure can be realized by reference to the drawings. In the drawings, like components or features can have the same reference label. Furthermore, various components of the same type can be distinguished by following the designation of the first component with a dash and a second designation that distinguishes among the group of similar components. If only the first designation is used in the specification, the description is applicable to any member of the similar components bearing the same first designation independent of the second designation.

[0018] Figure 1 A block diagram of an example computing system that includes a host, a memory, and a channel coupling the host and the memory is shown, in accordance with one or more aspects of the disclosure.

[0019] Figure 2A A block diagram of an example computing system that includes a host, a memory, and a channel coupling the host and the memory is shown, in accordance with one or more aspects of the disclosure.

[0020] Figure 2B A block diagram of an example computing system that includes a host, a memory, and a channel coupling the host and the memory is shown, in accordance with one or more aspects of the disclosure.

[0021] Figure 2C A block diagram of an example computing system that includes a host, a memory, and a channel coupling the host and the memory is shown, in accordance with one or more aspects of the disclosure.

[0022] Figure 3A A flow diagram depicting an example method for a memory usage metadata register to execute a write command is shown, in accordance with one or more aspects of the disclosure.

[0023] Figure 3B A flow diagram depicting an example method for a memory usage metadata register to execute a read command is shown, in accordance with one or more aspects of the disclosure.

[0024] Figure 4A A block diagram depicting an example configuration for a metadata register is shown, in accordance with one or more aspects of the disclosure.

[0025] Figure 4B A block diagram depicting an example configuration for a metadata register is shown, in accordance with one or more aspects of the disclosure.

[0026] Figures 5A-5BA timing diagram depicting a write operation transferring metadata over a non-data connection is shown in accordance with one or more aspects of the present disclosure.

[0027] Figures 6A-6B A timing diagram depicting a read operation transferring metadata over a non-data connection is shown in accordance with one or more aspects of the present disclosure.

[0028] Figure 7 A block diagram depicting a configuration of a memory array for storing metadata in a memory device is shown in accordance with one or more aspects of the present disclosure.

[0029] Figure 8 A block diagram depicting another configuration of a memory array for storing metadata in a memory device is shown in accordance with one or more aspects of the present disclosure.

[0030] Figure 9 A block diagram depicting storing data and metadata in a memory array is shown in accordance with one or more aspects of the present disclosure.

[0031] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0032] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to limit the scope of the disclosure. Rather, the detailed description includes specific details for the purpose of providing a thorough understanding of the inventive subject matter. It will be apparent to those skilled in the art, from this detailed description, that the

[0033] The present disclosure provides systems, apparatuses, methods, and computer readable media that support data processing, including techniques for supporting transfer of data between a host and a memory device. A host can send data and accompanying metadata for storage in a memory array of a memory device. The memory device can include registers for receiving and accumulating data and metadata for writing to the memory array. The metadata registers of the memory device can be organized to associate metadata with data without using two separate addresses for the data and the metadata. Examples of metadata for storage with data include error correction code (ECC) to protect the data from errors and / or a signature to protect the data from tampering. However, metadata can be used for more than protecting data.

[0034] Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides techniques for storing metadata with data in a manner that fits current memory array architectures by coordinating the storage of data and metadata in pages of a memory array. Moreover, in some aspects, metadata can be sent between a host and a memory device without requiring a dedicated connection in a channel between the host and the memory device for carrying the metadata.

[0035] As the demand for computing devices to perform more functions at faster and faster speeds grows, errors in data stored in memory can also increase. Errors can grow as the amount of data stored in memory and transferred between blocks increases. One example of preventing such errors is to use error-correcting codes (ECCs) associated with data. Schemes that improve error detection / correction when accessing memory without overburdening the host or memory are beneficial to improve system performance. ECCs can be attached during transmission over a channel, such as in the case of link ECCs. ECCs can also be attached for storage into a memory array, such as in the case of system ECCs. In some examples, end-to-end system ECCs can be implemented in a host by adding a large density on-chip SRAM to store online ECC parity bits for certain data to enhance overall data reliability. However, such high density on-chip SRAM is very expensive in terms of overall system cost, and the high density SRAM is susceptible to soft errors associated with SRAM cells.

[0036] In the present disclosure, system ECC data or other metadata is generated internally in the host and transmitted over a non-data channel (e.g., RDQS_t in a write operation and DM in a read operation) between the host and the memory device. The ECC bits can be stored into a memory array (e.g., an array of DRAM cells) with the corresponding data, such that the ECC protection provides a unified and consistent way to reduce overall system cost by allowing the removal of on-chip SRAM and enables better performance without the need for separate memory link ECCs. Thus, the present disclosure provides a simplified and efficient ECC scheme to implement system ECC by sharing certain resources with non-data connections. In this way, overall system cost can be reduced and performance can be improved.

[0037] Figure 1An apparatus 100 including a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150 is shown. For example, the apparatus 100 can be a device among a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop computer, a cell phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital camcorder, a wireless communication device handset (e.g., a mobile telephone, cellular or satellite radio telephone) equipped with a camera, a personal digital assistant (PDA), a panel or tablet computer, a gaming device, a computing device (e.g., a webcam, a video surveillance camera), or other device having digital imaging or video capability), and / or a multimedia system (e.g., a television, a compact disc player, a streaming device).

[0038] The host 110 can include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). The host 110 can be configured to be coupled to and communicate with the memory 150 (e.g., memories 150-1 to 150-4) via the channel 190 (e.g., channels 190-1 to 190-4) to perform a computing function, such as one of data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc. For example, the memories 150-1 to 150-4 can store instructions or data for the host to perform the computing function.

[0039] The host 110 can include a memory controller 130, which can include controller PHY modules 134-1 through 134-4. Each of the controller PHY modules 134-1 through 134-4 can be coupled to a respective one of the memories 150-1 through 150-4 via a respective channel 190-1 through 190-4. For ease of reference, reads and writes are referenced from the perspective of the host 110. For example, in a read operation, the host 110 can receive data stored in one or more of the memories 150-1 through 150-4 via one or more of the channels 190-1 — 190-4. In a write operation, the host 110 can provide data to be stored in one or more of the memories 150-1 — 150-4 via one or more of the channels 190-1 — 190-4. The memory controller 130 can be configured to control aspects of the communication to and from the memories 150-1 — 150-4, such as a logical layer. The controller PHY modules 134-1 — 134-4 can be configured to control electrical characteristics (e.g., voltage levels, phase, delay, frequency, etc.) of signals provided or received on the channels 190-1 — 190-4, respectively.

[0040] In some examples, the memories 150-1 — 150-4 can be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, the memories 150-1 — 150-4 can be different kinds of memories, such as one LPDDR5, one LPDDR6, one flash, and one SRAM, respectively. The host 110, the memories 150-1 — 150-4, and / or the channels 190-1 — 190-4 can operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of the channels 190-1 — 190-4 can include 16 bits of data (e.g., 16 DQs). In some examples, each of the channels 190-1 — 190-4 can operate on 32 bits of data (e.g., 32 DQs). In some examples, each of the channels 190-1 — 190-4 can operate on 64 bits of data (e.g., 64 DQs). Figure 1 In some examples, the host 110 can include more or fewer channels, such as 8 or 16 channels.

[0041] Figure 2A A configuration of the host 110, the memories 150, and the channels 190 according to some aspects of the disclosure is shown in more detail. Figure 2A A configuration of the host 110, the memories 150, and the channels 190 according to some aspects of the disclosure is shown in more detail. Figure 1another representation of the apparatus 100 of the host 110, the memory 150, and the channel 190. The channel 190 between the host 110 and the memory 150 can include multiple connections, some of which carry data (e.g., user data or application data) and some of which carry non-data (e.g., addresses and other signaling information). For example, the non-data connections in the channel 190 can include a data clock (e.g., WCK) to provide data to the respective memory 150 and a read data strobe (e.g., RDQS) to receive data from the respective memory 150 on a byte-by-byte basis. The channel 190 can also include data mask (e.g., DM, sometimes referred to as data mask inversion DMI, to indicate multiple functions performed by the signal connection) signaling to mask certain portions of data in a write operation. The channel 190 can further include commands and addresses (e.g., CA[0:n]) and associated CA clock to provide commands (e.g., read or write commands) to the memory 150.

[0042] The host 110 can include at least one processor 120, which can include a CPU 122, a GPU 123, and / or a NPU 124. The host 110 can also include a memory controller 130 with a controller PHY module 134. The memory controller 130 can be coupled to the at least one processor 120 via a bus system 115 in performing various computing functions. The term “bus system” can provide that elements coupled to the “bus system” can exchange information directly or indirectly with one another. In different embodiments, the “bus system” can encompass a number of physical connections and intervening stages such as buffers, latches, registers, etc. Modules can be implemented in hardware, software, or a combination of hardware and software.

[0043] The memory controller 130 can send and / or receive data blocks to other modules, such as the at least one processor 120 and / or the memory 150. The memory 150 can include a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) to provide or receive signals on connections of the channel 190. For example, the memory I / O module 160 can be configured to capture (e.g., sample) data, commands, and addresses from the host 110 via the channel 190 and output data to the host 110 via the channel 190. In Figures 5A-5B and Figures 6A-6BExample techniques for communicating over a channel 190 between a memory I / O module 160 and a memory controller 130 are shown in the example of FIG. 1. The memory 150 can also include a memory array 175 that can include a plurality of memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, and flash memory cells) that store values. The host 110 can read data stored in the memory array 175 and write data into the memory array 175 via the channel 190 and the memory I / O module 160. The memory array 175 can be divided into a plurality of memory banks, each organized as a plurality of pages.

[0044] Application or user data can be processed by the processor 120 and the memory controller 130 is instructed to store and / or retrieve such data from the memory 150. For example, data can be generated during execution of an application, such as an electronic spreadsheet program that computes numerical values based on other data. As another example, data can be generated during execution of an application by receiving user input, such as to an electronic spreadsheet program. As another example, data can be generated during execution of a game application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0045] Data can be associated with metadata that provides information about the data that is stored. Metadata can include attributes or characteristics of data. In one example, the metadata is an error-correcting code (ECC) that can be used to verify the integrity of data after transmission and / or storage and to correct a limited number of errors in the data. The ECC is metadata because it describes a characteristic of the data with which the ECC is associated (e.g., a numerical value generated by an algorithm when the data is provided as input to the algorithm).

[0046] Information transmitted via channel 190 can be stored in registers in memory I / O module 160 of memory 150 as temporary or short-term storage locations prior to long-term storage in memory array 175. Memory I / O module 160 may include a first register and a second register for storing data (e.g., user data or application data) and metadata, respectively. A first plurality of registers 182A-K stores data; and a second plurality of registers 181A-N stores metadata. In different embodiments, K may be equal to N, or K may be different from N, where K is greater than N or K is less than N. In some embodiments, N and / or K may be 1. The contents of registers 181A-N and 182A-K can then be transferred to memory array 175. In some embodiments, the contents of registers 181A-N and 182A-K may be transferred serially shortly after receipt to complete individual write commands. In some embodiments, the contents of registers 181A-N and 182A-K may be accumulated based on multiple write commands received at memory 150, and metadata is transferred to memory array 175 when certain criteria are met. In some embodiments, a single register 182 and / or a single register 181 may exist. For example, to reduce hardware size, a single data register 182 with multiple metadata registers 181A-N may exist. Write commands may be coupled with serial data input from the host, such that the write data (e.g., 32 bytes) is temporarily stored in the 32-byte register 182. The data is then automatically written to the first portion of the memory array without any additional write commands from the host. Figures 4A-4B The document shows some example configurations for metadata registers 181A-N.

[0047] Apparatus 100 can be configured to support the processing of metadata accompanying data transmitted between host 110 and memory 150. In one example, the metadata may be error-correcting codes (ECCs) used to protect data from at least some errors in communication and / or storage. Separate link ECC codes may be transmitted on channel 190 to protect data and / or metadata during transmission on channel 190. Figure 2B The diagram illustrates the configuration of host 110, memory 150, and channel 190 according to some aspects of this disclosure to support link ECC. Figure 2B It shows having Figure 1 and / or Figure 2A Another representation of the device 100, which includes a host 110, a memory 150, and a channel 190.

[0048] Host 110 can be configured to perform multiple ECC functions. To support system ECC functions, host 110 may include system ECC memory 137. Memory controller 130 may be coupled to system ECC memory 137 via bus system 116. Memory controller 130 may further include system ECC decoder 131 and system ECC encoder 132. Controller PHY module 134 may include link ECC decoder 135 and link ECC encoder 136.

[0049] The device 100 may implement system ECC functionality to detect / correct errors occurring during the execution of computational functions (e.g., operation using at least one processor 120). System ECC functionality can be particularly useful for applications with low fault tolerance, such as automotive applications. In some examples, a system ECC encoder 132 may generate a system ECC for a data block and an ECC associated with that data block, for example, by appending ECC bits to the data block. A memory controller 130 may send the data block along with the system ECC to other modules, such as at least one processor 120 and / or memory 150. For example, the system ECC may be sent to memory 150, and memory 150 may store the system ECC in the same manner as the data. In some embodiments, memory 150 does not perform system ECC-based ECC functionality. In some examples, memory controller 130 may receive a data block and associated system ECC from, for example, processor 120 and / or memory 150. Memory controller 130 may then use the system ECC to detect / correct errors in the data block.

[0050] Host 110 is coupled to memory 150 via channel 190, shown for data bytes DQ[0:7]. Channel 190 and the signaling between host 110 and memory 150 can be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As shown, channel 190 includes signaling connections for DQ, read data strobe (RDQS), data mask (DM), data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). Host 110 can use read data strobe (RDQS) to gating (e.g., timing) data on DQ during read operations to receive data. Memory 150 can use data mask (DM) to mask certain portions of the data to prevent them from being written during write operations. Memory 150 can use data clock (WCK) to sample data on DQ for write operations. Memory 150 can use command and address clock (CK) to time CA (e.g., receive). Signal connections for each signaling may include pins at host 110, pins at memory 150, and one or more conductive traces for electrical connection pins. One or more conductive traces may be part of a single integrated circuit (IC) on a silicon chip containing processor 120 and memory 150, part of a stacked package (PoP) containing processor 120 and memory 150, or part of a printed circuit board (PCB) coupled to both processor 120 and memory 150.

[0051] Memory 150 may include memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190.

[0052] Memory 150 may also include memory array 175, which may include multiple memory cells (e.g., DRAM memory cells) for storing information. Host 110 may read data stored in memory array 175 and write data to memory array 175 via channel 190. Furthermore, memory array 175 may be configured to store metadata, such as ECCs (e.g., system or array ECCs) associated with the stored data. For example, a data block (e.g., a word) in a first portion 176A of memory array 175 may be associated with a system ECC stored in a second portion 176B via a shared address. For example, reading (or writing) a shared address at memory array 175 may read (or write) both the data block at that address and the system ECC associated with that data block.

[0053] Apparatus 100 may include link ECC functionality to detect / correct errors caused by data transmission in channel 190. Memory I / O module 160 may include a memory link ECC decoder 161 and a memory link ECC encoder 162. Link ECC information may be appended during transmission over channel 190, verified at host 110 or memory 150, and then discarded. For example, in a write operation, link ECC encoder 136 may generate link ECC associated with a block of data to be written to memory 150 (e.g., write data). Host 110 may provide write data to memory 150 via a DQ signaling connection (e.g., a data connection in channel 190) and provide link ECC to memory 150 via a signaling connection of read data strobe RDQS (e.g., a non-data connection in channel 190). At memory 150, memory link ECC decoder 161 may use link ECC to detect / correct errors in the write data. Link ECC may not be stored in memory array 175 because the link ECC function is resolved at memory I / O module 160. During a read operation, memory link ECC encoder 162 can receive data stored in memory array 175 (e.g., read data) (e.g., via node 174, array ECC decoder 171, and node 164) and generate link ECC associated with the read data. Memory I / O module 160 can provide the read data to host 110 via the DQ signaling connection and provide the link ECC to host 110 via the data mask DM signaling connection. At host 110, link ECC decoder 135 can use the link ECC to detect / correct errors in the read data.

[0054] Referring to metadata registers 181A-N, multiple metadata registers may reside in the memory I / O module 160 of memory 150 and be associated with memory spaces partitioned off from memory banks (e.g., in the second portion 176B) within memory array 175 (e.g., in the first portion 176A). For example, column addresses “0x3C” to “0x3F” on each page may be reserved for metadata such as ECC. For 32 bytes of data, a write operation is performed to the target page and column location (data stored in data registers 182A-K) in the first portion 176A of memory array 175, and for the associated 2 bytes of metadata, a write operation is performed to a predetermined area (metadata stored in metadata registers 181A-N) in the second portion 176B of memory array 175. In memory 150 configured to support such write operations, the internal memory data bus (e.g., read bus 163) may maintain the word size configured for data, regardless of the metadata. In some embodiments, when an earlier read command is executed to retrieve metadata from the memory array back into the metadata register based on a read command to the metadata memory space (e.g., “0x3C”–“0x3F”), a read command to the normal memory space (e.g., “0x00”–“0x3B”) is executed to simultaneously retrieve 32 bytes of normal read data from the first part 176A and 2 bytes of metadata from the second part 176B.

[0055] exist Figure 2C Another configuration of channel 190 for transmitting metadata is shown in the diagram. Figure 2C In the example, channel 190 includes a dedicated system metadata bus. A data bus (“data bus [0:k-1]”) transmits, for example, 32 bytes of data, while a system metadata bus (“system metadata [0:p-1]”) simultaneously transmits, for example, 2 bytes of metadata to accompany data used for write or read operations. The data bus is an example of a data connection within channel 190, while the system metadata bus is an example of a non-data connection within channel 190.

[0056] Data and metadata transmitted via channel 190 can be sent through a combination of data and non-data connections. For example, user data can be sent via data connection DQ[0:7], while metadata can be sent via non-data connections (e.g., data mask DM connection or read strobe RDQS connection). Figure 3A The document describes operations for executing write commands involving data and metadata by storage devices.

[0057] In method 300, a write command issued by the host to the storage device causes the storage device to perform an operation at block 302, receiving data from the host via at least one data connection into a first plurality of registers. For example, data can be stored in data registers 182A-K by processing signals received on the data DQ[0:7] channel. Furthermore, at block 304, the storage device receives metadata from the host via at least one non-data connection into a second plurality of registers. For example, metadata can be stored in metadata registers 181A-N by processing signals received on the non-data read strobe RDQS channel. The data channel can be any channel carrying user or application data for at least temporary storage in the memory array. The non-data channel can be any channel carrying data different from the user or application data.

[0058] After certain conditions are met, the write command can be completed by executing blocks 306 and 308. At block 306, data is stored from a first plurality of registers into a first portion of the memory array, corresponding to the write address specified in the write command received for the received data at block 302. For example, the contents of data registers 182A-K may be stored in a region of the first portion 176A of memory array 175 based on the write address. At block 308, metadata is stored from a second plurality of registers into a second portion of the memory array. For example, the contents of metadata registers 181A-N may be stored in a region of the second portion 176B of memory array 175 corresponding to the write address (e.g., a region reserved for metadata corresponding to the data at the write address). In some examples, the execution of blocks 306 and 308 may be triggered by certain criteria, such as the filling of registers 181A-N or 182A-K, which have a specific number of bytes of data for storage in a single page. In some examples, data can be accumulated in registers 181A-N and / or 182A-K from two or more write commands before the write command is completed by executing blocks 306 and 308. In some examples, data can be accumulated in registers 181A-N and / or 182A-K while receiving a sequence of write commands with addresses corresponding to the same page of memory. When a subsequent write command pointing to a different page of memory is received, registers 181A-N and / or 182A-K can be written to memory array 176. In some embodiments of a memory device having a single register 182A, the data portion (e.g., corresponding to columns 0x00-0x3B) can be written to the memory array without any delay, such that metadata is stored in the memory array using only additional write commands to the metadata portion of the memory array (e.g., corresponding to columns 0x3C-0x3F).

[0059] exist Figure 3BThe document describes operations for executing read commands involving data and metadata by a storage device. In method 300, a read command issued by the host to the storage device causes memory 150 to perform a read operation. At block 352, metadata corresponding to the read address is received from the memory array into a second plurality of registers. At block 354, data corresponding to the read address is received from the memory array into a first plurality of registers. In some embodiments, metadata is loaded into a second set of registers before accessing normal data (e.g., data located in columns 0x00~0x3B). In some embodiments, blocks 352 and 356 can be executed sequentially during a read operation to simultaneously retrieve data and metadata from the storage device to the host. When a certain amount of data has accumulated in a register, for example, when the register is full or the requested data is already stored in the register, the data can be sent from the register to the host via channel 190. At block 356, data from the first plurality of registers is sent to the host via at least one data connection. For example, the contents of data registers 182A-K can be modulated onto the data DQ[0:7] connection of channel 190 and received at the memory controller 130 of host 110. At block 358, data from a second plurality of registers is transmitted to the host via at least one non-data connection. For example, the contents of metadata registers 181A-N can be modulated onto the non-data read strobe RDQS connection of channel 190 and received at the memory controller 130 of host 110. The memory controller 130 of host 110 can process the electrical signals received on channel 190 and provided to processor 120 and / or ECC memory 137.

[0060] Depending on the technology used, metadata registers 181A-N can be associated with memory addresses in memory array 175. Figure 4A An example memory address mapping is shown. Certain addresses within a page can be assigned to metadata, for example, by partitioning column spaces corresponding to 0x3C–0x3F. Metadata registers 181A-N can include n metadata registers dedicated to each column location. That is, column space 0x3C has a first set 481A with n metadata registers, column space 0x3D has a second set 481B with n metadata registers, column space 0x3E has a third set 481C with n metadata registers, and column space 0x3F has a fourth set 481D with n metadata registers. In this example configuration, metadata registers 181A-N can have a total of 4n registers, where each memory bank's column address is fully associated with n metadata registers.

[0061] exist Figure 4BAnother example memory address mapping is shown. N metadata registers 181A-N can be coupled to all column locations across all memory banks. Any metadata from reserved metadata column locations 0x3C–0x3F can be stored or retrieved from any of the n metadata registers during a write or read operation. An example command protocol for selecting one of the n metadata registers is the “CAS” + “WRITE / READ” command set, which selects one of the n metadata registers by a target column address. The “CAS” command selects one of the n metadata registers, and the “WRITE / READ” command passes the target column address (“0x3C”, “0x3D”, “0x3E”, or “0x3F”) for storing metadata in a specific register among registers 181A-N.

[0062] Figure 5A and Figure 5B The diagram illustrates waveforms of data and metadata transmitted via an example channel during a write operation, according to certain aspects of this disclosure. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (rising edge of CK_c and falling edge of CK_t), host 110 can provide a CAS command for a write operation to memory 150. At T1, a write command can be provided by host 110 to memory 150.

[0063] After the time-period write delay (WL), host 110 can switch data clocks WCK0_t and WCK0_c to provide a clock for memory 150 to receive data for writing on the DQ signal connections. At Tc0-Tc2, memory 150 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, timed by data clocks WCK0_t and WCK0_c. Memory 150 can serially (e.g., based on data clocks WCK0_t and WCK0_c) receive 16 bits of a data mask DM0 to mask certain portions of the data received from the write operation. In some examples, memory 150 can receive 16 bytes of data and a 16-bit data mask DM0, where each bit of the data mask DM0 masks the corresponding byte of data received.

[0064] At Tc0-Tc2, memory 150 can receive, for example, 8 bits of ECC or other metadata on the RDQS_t signal connection based on data clocks WCK0_t and WCK0_c. During read operations, the RDQS_t signal connection can be configured to provide a read data strobe (RDQS) from memory 150 to host 110. In some examples, in addition to metadata containing system ECC, ECC link data may also be included on the RDQS connection. (See reference) Figure 2B The memory link ECC decoder 161 can use the received link ECC to detect and / or correct errors in the received 16-byte data.

[0065] Figure 6A and Figure 6B Waveforms for reading data and metadata from the apparatus 100 of FIG2 during a read operation, according to certain aspects of this disclosure, are shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (rising edge of CK_c and falling edge of CK_t), the host 110 can provide a CAS command for a read operation to the memory 150. At T1, a read command can be provided by the host 110 to the memory 150.

[0066] After the time-period read delay (RL), memory 150 can switch the read data strobe RDQS to provide a clock to host 110 to receive data for read operations on the DQ signal connections. At Tc0-Tc2, host 110 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, timed by the read data strobes RDQS_t and RDQS_c. Therefore, in this example, host 110 receives 16 bytes of data.

[0067] At Tc0-Tc2, host 110 can receive, for example, 8 bits of metadata, such as system ECC, on the data mask DM0 signaling connection based on read data strobes RDQS_t and RDQS_c (e.g., timed by them). During write operations, the DM signaling connection can be configured to provide a data mask from host 110 to memory 150. In some examples, link ECC can also be inserted into the DM signaling connection.

[0068] Figure 7A first address space 742 for accessing a first portion 176A of a memory array 175 and a second address space 744 for accessing a second portion 176B of the memory array 175 are shown, according to certain aspects of this disclosure. In some examples, each of the first address space 742 and the second address space 744 may include row and column addresses received from the CA of channel 190. For example, the first address space 742 may correspond to row addresses 0000h to FFFFh and column addresses 00h to 3Ah, and the second address space 744 may correspond to row addresses 0000h to FFFFh and column addresses 3Bh to 3Fh. Therefore, the total address space of the memory array 175 is in the range from row address 0000h and column address 00h to row address FFFFh and column address 3Fh.

[0069] The first part 176A can be addressed by a first address (e.g., an address in the first address space 742), and the second part 176B can be addressed by a second address (e.g., an address in the second address space 744). Therefore, the first address and the second address can differ in column addressing. While this disclosure utilizes examples of first address space 742 and second address space 744 varying in column spaces, other examples are possible, such as... Figure 8 A row-based example.

[0070] Figure 8 Examples of first address space 842 and second address space 844 that differ in row space according to certain aspects of this disclosure are shown. Figure 8 In this example, the first part 176A can be accessed through the first address space 842, which corresponds to row addresses 0000h up to FFFDh. The second part 176B can be accessed through the second address space 844, which corresponds to row addresses FFFEh up to FFFFh. In this example, the first address space 842 and the second address space 844 can differ in the row space; therefore, the first address used to access the first part 176A and the second address used to access the second part 176B can differ in row addressing.

[0071] Figure 9 Examples of data and address mappings based on certain aspects of this disclosure are shown. Figure 9For example, data (written to or read from Part 176A; marked as normal data) can be 32 bytes, and ECC (written to or read from Part 276B) can be 16 bits or less. Unused address space (marked as “empty”) is clustered within column address 3Fh, whereas in other examples, unused address space is distributed across column address spaces. During the execution of each read or write command, a total of 34 bytes (32 bytes of data and 2 bytes of system ECC or other metadata) can be transmitted between host 110 and memory 150 (e.g., via at least one data connection and at least one non-data connection). In such a configuration, 2 bytes of ECC can be implemented without memory bandwidth loss. Furthermore, an additional 2 bytes of ECC (“c”) can be implemented to further protect the 32 bytes of data (“n”) and the two bytes of system ECC (“s”).

[0072] The table below shows an example mapping for a portion of a memory array. The column address used for metadata is associated with the column address of the corresponding data. The column address used for metadata is associated with a portion of the memory array reserved for metadata, such as... Figures 2A-2B The second part 176B of the memory array 175 in the memory array.

[0073] Wireless communication devices may include a memory configured to receive and output data (such as at least) via a data register and a metadata register. Figures 2A-2C (as shown), and according to any aspect disclosed herein, the wireless communication device may be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radio units, satellite radio units, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0074] In one or more aspects, the technology for memory storage and retrieval may include additional aspects, such as any single aspect or any combination of aspects described below or in conjunction with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations may include means configured to store and retrieve data from and from a memory array of the storage device. The means may respond to commands from a host device, such as read and write commands, and in response, provide certain data from the memory array on a channel coupling the storage device to the host device. The means may include a memory array and a memory I / O module coupled to the memory array and configured to communicate with the host via a channel including at least one data connection and at least one non-data connection. In some implementations, the storage device is included in a wireless device such as a UE. In some implementations, the means includes a remote server, such as a cloud-based computing scheme, which includes the storage device.

[0075] In some implementations, the apparatus may include at least one processor and memory coupled to the processor. The processor may be configured to perform the operations described herein with reference to the apparatus. In some other implementations, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon, and the program code may be computer-executable to cause the computer to perform the operations described herein with reference to the apparatus. In some implementations, the apparatus may include one or more units configured to perform the operations described herein. In some implementations, a method of accessing (including writing or reading) data in a memory array may include one or more of the operations described herein with reference to the apparatus.

[0076] In a second aspect, in conjunction with the first aspect, the apparatus is further configured to: receive data from the host into at least one first register via at least one data connection; receive metadata from the host into at least one second register via at least one non-data connection; store data in a first portion of a memory array; and store metadata in a second portion of the memory array.

[0077] In the third aspect, one or more aspects of the first or second aspect are combined to receive data and metadata simultaneously during a single write command.

[0078] In the fourth aspect, in conjunction with one or more of the first to third aspects, the apparatus can be configured to receive a first address via at least one second non-data connection corresponding to data, wherein storing data in a first portion of a memory array is based on the first address; and storing metadata in a second portion of the memory array is directed to a second address corresponding to the first address.

[0079] In the fifth aspect, in conjunction with one or more of the first to fourth aspects, receiving metadata from the host into a second plurality of registers via at least one non-data connection includes: receiving a plurality of metadata, including first metadata corresponding to a first write operation and second metadata corresponding to a second write operation, into at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of pages of a memory array; and storing the metadata in a second portion of the memory array includes: writing the plurality of metadata from at least one second register into pages of the memory array to complete the first write operation and the second write operation.

[0080] In the sixth aspect, combining one or more aspects from the first to the fifth aspects, the metadata includes error correction codes (ECC).

[0081] In the seventh aspect, in conjunction with one or more of the first to sixth aspects, the metadata includes a signature used to authenticate the data corresponding to the metadata.

[0082] In the eighth aspect, in conjunction with one or more of the first to seventh aspects, at least one non-data connection includes a data mask inversion (DMI) portion of the channel, wherein the number of connections in the data mask inversion (DMI) portion is less than the number of connections in at least one data connection.

[0083] In the ninth aspect, in conjunction with one or more aspects from the first to the eighth aspects, at least one non-data connection includes a read data strobe (RDQS) portion of the channel, wherein the number of connections in the read data strobe (RDQS) portion is less than the number of connections in at least one data connection.

[0084] In the tenth aspect, in conjunction with one or more of the first to ninth aspects, at least one second register includes a first portion associated with a first column address and a second portion associated with a second column address, and receiving metadata includes receiving metadata into the first portion or the second portion based on a memory address for data associated with metadata specified by a write command corresponding to data received by the memory I / O module.

[0085] In the eleventh aspect, in conjunction with one or more aspects from the first to the tenth aspects, at least one second register includes a first portion and a second portion, and

[0086] Receiving metadata includes receiving metadata in either the first or second part based on an indicator specified by a write command received by the memory I / O module.

[0087] In the twelfth aspect, in conjunction with one or more of the first to eleventh aspects, the memory I / O module can be configured to: retrieve data from a first portion of the memory array back into at least one first register; retrieve metadata from a second portion of the memory array back into at least one second register; send data from at least one first register to a host via at least one data connection; and send metadata from at least one second register to a host via at least one non-data connection.

[0088] In the thirteenth aspect, one or more aspects from the first to the twelfth aspects are combined to retrieve data and metadata simultaneously during a single read command.

[0089] In the fourteenth aspect, in conjunction with one or more of the first to thirteenth aspects, the memory I / O module is further configured to perform operations including: receiving a first address via at least one second non-data connection corresponding to data, wherein retrieving data from a first portion of the memory array is based on the first address; and retrieving metadata from a second portion of the memory array from a second address corresponding to the first address.

[0090] In the fifteenth aspect, in conjunction with one or more of the first to fourteenth aspects, retrieving metadata from a second portion of the memory array back to at least one second register includes: retrieving multiple metadata during a single-page operation, the multiple metadata including first metadata corresponding to a first read operation and second metadata corresponding to a second read operation, the multiple metadata corresponding to multiple memory addresses of pages in the memory array; and sending metadata to the host from the second plurality of registers via at least one non-data connection includes: sending the multiple metadata.

[0091] In a sixteenth aspect, in conjunction with one or more of the first to fifteenth aspects, an apparatus includes a host device configured to communicate with a storage device via a channel, the host device including a memory controller coupled to the channel, the memory controller being configured to perform operations including: transmitting data between the memory controller and at least one first register of the storage device via at least one data connection of the channel; and transmitting metadata between the memory controller and at least one second register of the storage device via at least one non-data connection of the channel.

[0092] In the seventeenth aspect, in conjunction with one or more of the first to sixteenth aspects, the host device is configured to signal a read command on a channel, the read command specifying a read address for retrieving data and metadata from a storage device.

[0093] In the eighteenth aspect, in conjunction with one or more aspects from the first to the seventeenth aspects, the read address identifies a set of at least one second register used to store metadata.

[0094] In the nineteenth aspect, in conjunction with one or more of the first to eighteenth aspects, the read command includes an indicator specifying a set of at least one second register for storing metadata.

[0095] In the twentieth aspect, in conjunction with one or more of the first to nineteenth aspects, the host device is configured to: send a write command on a channel by signaling, the write command specifying a write address for storing data; and send data to a storage device.

[0096] In the twenty-first aspect, in conjunction with one or more aspects from the first to the twentieth, a set of at least one second registers for storing metadata is written to an address identifier.

[0097] In the twenty-second aspect, in conjunction with one or more of the first to twenty-first aspects, the write command includes an indicator specifying one of at least one of the second registers for storing metadata.

[0098] Throughout the description of the embodiments herein, numerous specific details (e.g., examples of specific components, circuits, and processes) are set forth to provide a thorough understanding of this disclosure. As used herein, the term "coupled" means a direct connection or a connection via one or more intermediate components or circuits. Additionally, specific terminology is set forth in the following description and for purposes of explanation to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that implementing the teachings disclosed herein may not require these specific details. In other instances, known circuits and devices are illustrated in block diagram form to avoid obscuring the teachings of this disclosure.

[0099] Some parts of the following detailed description are presented based on other symbolic representations of programs, logic blocks, processes, and operations on data bits within computer memory. In this disclosure, programs, logic blocks, processes, etc., are conceived as a self-consistent sequence of steps or instructions that lead to a desired result. These steps are steps that require physical operations on physical quantities. Although not strictly necessary, these quantities typically take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated within a computer system.

[0100] In the diagrams, a single block can be described as performing one or more functions. These functions can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are generally described below in relation to their functions. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure. Furthermore, the example device may include components other than those shown, including well-known components such as processors, memory, etc.

[0101] Unless otherwise specifically stated, it should be understood from the following discussion that throughout this application, the use of terms such as “access,” “receive,” “send,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” “set,” “generate,” etc., refers to the actions and processing of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system.

[0102] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (e.g., a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more parts that can implement at least some of the contents of this disclosure. Although the term "device" is used in the description and examples herein to describe various aspects of this disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or part of a device for performing the described operations.

[0103] Certain components in a device or apparatus are described as “units for access,” “units for receiving,” “units for transmitting,” “units for using,” “units for selecting,” “units for determining,” “units for normalizing,” “units for multiplying,” or other similar terms, referring to one or more operations on data (e.g., image data). This may refer to processing circuitry (e.g., application-specific integrated circuits (ASICs), digital signal processors (DSPs), graphics processing units (GPUs), central processing units (CPUs)) configured to perform the functions by means of hardware, software, or a combination of hardware configured by software.

[0104] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0105] This article is about Figures 1-2C The components, functional blocks, and modules described may include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, and other examples or any combination thereof. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable programs, threads of execution, procedures and / or functions, and other examples, whether referred to as software, firmware, middleware, microcode, hardware description languages, or others. Furthermore, the features discussed herein may be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0106] Those skilled in the art can refer to Figure 1 and Figures 2A-2C One or more boxes (or operations) described are combined with one or more boxes (or operations) described with reference to another drawing in the accompanying drawings. For example, Figures 3A-3B One or more boxes (or operations) can be associated with Figure 1 and Figures 2A-2C Combine one or more boxes (or operations). For another example, with... Figures 5A-5B and Figures 6A-6B One or more associated boxes can be linked with and Figure 1 and Figures 2A-2C Combine one or more related boxes (or operations).

[0107] Those skilled in the art will also understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with this disclosure can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein is merely illustrative, and components, methods, or interactions of various aspects of this disclosure can be combined or performed in ways different from those shown and described herein.

[0108] The various illustrative logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the implementation methods disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether this functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0109] Hardware and data processing apparatuses for implementing the various illustrative logics, logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a general-purpose single-chip or multi-chip processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some implementations, specific processes and methods may be executed by circuitry specific to a given function.

[0110] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware (including the structures disclosed in this specification and their structural equivalents), or any combination thereof. Implementations of the subject matter described in this specification may also be implemented as one or more computer programs (which are one or more modules of computer program instructions) encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0111] If implemented in software, the functionality can be stored on or transmitted via a computer-readable medium as one or more instructions or code. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module residing on a computer-readable medium. Computer-readable media include both computer storage media and communication media, wherein the communication medium includes any medium capable of being implemented to transfer a computer program from one place to another. Storage media can be any available medium accessible by a computer. By way of example, and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible by a computer. Furthermore, any connection can be appropriately referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser optical discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while optical discs utilize lasers to optically copy data. Combinations of the above should also be included within the scope of computer-readable media. In addition, the operation of a method or algorithm may reside as one or any combination or set of code and instructions on a machine-readable medium and a computer-readable medium, which may be incorporated into a computer program product.

[0112] Various modifications to the implementations described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but are given the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0113] Furthermore, those skilled in the art will readily understand that, for the convenience of describing the accompanying drawings, opposing terms such as “upper” and “lower,” or “front” and “back,” or “top” and “bottom,” or “forward” and “backward” are sometimes used to indicate relative positions corresponding to the orientation of the drawings on the correctly oriented page, and may not reflect the correct orientation of any implemented device.

[0114] As used herein, the term "coupled to" in various tenses of the verb "couple" can mean that element A is directly connected to element B, or that other elements can be connected between element A and B (i.e., element A is indirectly connected to element B) to perform certain intended functions. In the case of electrical elements, the term "coupled to" may also be used herein to mean the electrical connection of element A and B (and any elements electrically connected between them) using wires, traces, or other conductive materials. In some examples, the term "coupled to" means the transfer of electrical energy between element A and B to perform certain intended functions.

[0115] In some examples, the term "electrical connection" means having current or being configurable to have current flowing between components A and B. For example, in addition to wires, traces, or other conductive materials and components, components A and B can also be connected via resistors, transistors, or inductors. Furthermore, for radio frequency functions, components A and B can be "electrically connected" via capacitors.

[0116] The terms "first," "second," and "third," etc., are used for ease of reference and may not carry substantial meaning. Similarly, component / module names may be used for ease of reference and may not be limiting. For example, such non-limiting names could include "read ECC" signal connection and "write ECC" signal connection.

[0117] Some features described in this specification in the context of individual implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features are described above as working under certain combinations and even initially claimed in this way, in some cases one or more features in the claimed combination can be separated from the combination, and the claimed combination can be for sub-combinations or variations thereof.

[0118] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the shown specific order or sequential order, or requiring all shown operations to be performed to achieve the desired result. Furthermore, the drawings may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be incorporated into the schematically shown example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any shown operations. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of the various system components in the implementations described above should not be construed as requiring such separation in all implementations, but rather should be understood as meaning that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result.

[0119] As used herein (including in the claims), when used in a list of two or more items, the term "or" means that any one of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a composition is described as containing components A, B, or C, the composition may contain: only A; only B; only C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein (including in the claims), "or" as used in a list of items ending in "at least one of" indicates a separate list, such that, for example, a list of "at least one of A, B, or C" means, for example, A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination thereof.

[0120] As will be understood by those skilled in the art, the term “substantially” is defined as an object that is substantially but not necessarily fully specified (and includes specified objects; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any disclosed implementation, the term “substantially” may be replaced with “within a specified [percentage]”, where the percentage includes 0.1, 1, 5, or 10%.

[0121] The foregoing description of this disclosure is provided to enable those skilled in the art to implement or use it. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: The host computer, which has a memory controller; The memory I / O module of the memory is coupled to the memory controller; The memory array of the memory, coupled to the memory I / O module and configured to have a first portion for data and a second portion for metadata, wherein the first portion is associated with a first column address and the second portion is associated with a second column address; and The memory's metadata register is configured to be coupled to the second part, wherein the metadata is stored in the metadata register during a write operation or retrieved from the metadata register during a read operation.

2. The apparatus according to claim 1, wherein, The metadata register is configured to be used exclusively for column positions in the second part.

3. The apparatus according to claim 1, wherein, The first column address is 0x00-0x3B, and the second column address is 0x3C-0x3F.

4. The apparatus according to claim 3, wherein, The metadata in column 0x3C is mapped to the data in columns 0x00-0x0F, the metadata in column 0x3B is mapped to the data in columns 0x10-0x1F, the metadata in column 0x3C is mapped to the data in columns 0x20-0x2F, and the metadata in column 0x3D is mapped to the data in columns 0x30-0x3B.

5. The apparatus according to claim 4, wherein, In the page, each column of the second part is configured to store 16 2-byte metadata bytes, each of which is associated with 32 bytes of data in the column of the first part.

6. The apparatus according to claim 1, wherein, The metadata register is configured to store or retrieve the metadata in response to a "CAS" + "write / read" command from the host having a column address in the second column address.

7. The apparatus according to claim 6, wherein, The memory I / O module is configured to transmit 32 bytes of data and 2 bytes of metadata to the host in response to a read or write command.

8. The apparatus according to claim 7, wherein, The memory I / O module is configured to transfer the 32 bytes of data between the host and the memory array, and to transfer the 2 bytes of metadata between the host and the metadata register.

9. The apparatus according to claim 1, further comprising: It is coupled to the data register of the first part.

10. The apparatus according to claim 1, wherein, The metadata is the error correction code (ECC) used for the data.

11. A method comprising: The host's memory controller sends write commands to the memory I / O module of the memory. The memory controller sends write data associated with the write command to the memory I / O module, wherein the write data includes data and metadata associated with the data; and The memory stores the data into a first portion of the memory array and stores metadata into a metadata register of the memory, wherein the metadata register is coupled to a second portion of the memory array.

12. The method of claim 11, further comprising: The metadata from the metadata register is stored by the memory into the second part of the memory array.

13. The method according to claim 11, wherein, The first part is associated with the first column address, while the second part is associated with the second column address.

14. The method according to claim 13, wherein, The metadata register is configured to be used exclusively for column positions in the second part.

15. The method according to claim 13, wherein, The first column address is 0x00-0x3B, and the second column address is 0x3C-0x3F.

16. The method according to claim 15, wherein, The metadata in column 0x3C is mapped to the data in columns 0x00-0x0F, the metadata in column 0x3B is mapped to the data in columns 0x10-0x1F, the metadata in column 0x3C is mapped to the data in columns 0x20-0x2F, and the metadata in column 0x3D is mapped to the data in columns 0x30-0x3B.

17. The method of claim 13, further comprising: The memory controller sends a "CAS" + "write" command with the column address in the second column address to the memory; as well as The memory transfers the metadata data in the metadata register to the second part of the memory array having the column address.

18. The method according to claim 11, wherein, The data is 32 bytes, and the metadata is 2 bytes.

19. The method of claim 11, further comprising: Before the data is stored in the first part, the memory stores the data in a data register.

20. The method according to claim 11, wherein, The metadata is the error correction code (ECC) used for the data.

21. A method comprising: The host's memory controller sends a read command to the memory I / O module of the memory. Data is retrieved from a first portion of the memory array by the memory, and metadata associated with the data is retrieved from a metadata register, wherein the metadata register is coupled to a second portion of the memory array; as well as In response to the read command, the memory I / O module of the memory sends the data and the metadata to the host.

22. The method of claim 21, further comprising: The metadata is retrieved from the second part of the memory array back to the metadata register by the memory.

23. The method according to claim 21, wherein, The first part is associated with the first column address, while the second part is associated with the second column address.

24. The method according to claim 23, wherein, The metadata register is configured to be used exclusively for column positions in the second part.

25. The method according to claim 23, wherein, The first column address is 0x00-0x3B, and the second column address is 0x3C-0x3F.

26. The method of claim 25, wherein, The metadata in column 0x3C is mapped to the data in columns 0x00-0x0F, the metadata in column 0x3B is mapped to the data in columns 0x10-0x1F, the metadata in column 0x3C is mapped to the data in columns 0x20-0x2F, and the metadata in column 0x3D is mapped to the data in columns 0x30-0x3B.

27. The method of claim 23, further comprising: The memory controller sends a "CAS" + "read" command with the column address from the second column address to the memory I / O module; as well as The metadata is transferred from the second portion of the memory array having the column address to the metadata register by the memory.

28. The method according to claim 21, wherein, The data is 32 bytes, and the metadata is 2 bytes.

29. The method of claim 21, further comprising: Before the data is sent to the host, the memory stores the data from the first portion into the data register.

30. The method according to claim 21, wherein, The metadata is the error correction code (ECC) used for the data.

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