Capacitance detection circuit, fingerprint acquisition chip and electronic equipment

Abstract

The invention relates to a capacitance detection circuit, a fingerprint acquisition chip and electronic equipment. In the capacitance detection circuit, a pixel unit circuit is used for converting a signal of an equivalent capacitance value sampled by a pixel unit of a sensing array into a pixel output voltage when a target object approaches the sensing array; the sampling and processing module is used for carrying out first-time sampling on corresponding pixel output voltage when a driving signal of the pixel unit is a reset level, carrying out second-time sampling and third-time sampling on the pixel output voltage in sequence when the driving signal is a signal level, and outputting an amplified signal with (V3-2 * V2 + V1) absolute value as a capacitance detection signal, v1, V2 and V3 represent three-time sampling voltage values respectively, so that the influence of interference caused by superposition of driving signals can be avoided, and the accuracy of a detection result can be improved. The fingerprint acquisition chip and the electronic equipment comprise the capacitance detection circuit.

Description

Technical Field

[0001] This invention relates to the field of capacitance detection, and more particularly to a capacitance detection circuit, a fingerprint acquisition chip, and an electronic device. Background Technology

[0002] Fingerprint acquisition technology can be used in various occasions involving user information verification, such as consumer electronics, access control systems, and information collection. Currently, the mainstream technology is capacitive fingerprint acquisition, which identifies fingerprint information based on the capacitive sensing between human fingerprints and the pixel units of the sensor array.

[0003] Fingerprint acquisition chips are commonly found in electronic devices such as mobile phones and tablets. These chips consist of a sensor array and a capacitance detection circuit. The capacitance detection circuit converts the signal of the equivalent capacitance value sampled by the pixel units in the sensor array when a target object (such as a fingerprint) approaches the array into a capacitance detection signal. One problem with existing capacitance detection circuits is that if the target object and the capacitance detection circuit (or the electronic device that houses the circuit) are not grounded—for example, if a mobile phone with a fingerprint acquisition chip is encased in an insulating protective case, the person being detected is not grounded to the phone—this is equivalent to an interference signal at the input of the capacitance detection circuit. This can cause the output result to deviate from the actual value, affecting the accuracy of the detection. Summary of the Invention

[0004] To avoid interference at the input of the capacitance detection circuit affecting the detection results, this invention provides a capacitance detection circuit, a fingerprint acquisition chip, and an electronic device.

[0005] On one hand, the present invention provides a capacitance detection circuit, the capacitance detection circuit comprising:

[0006] Pixel unit circuitry is used to convert the signal of the equivalent capacitance value sampled by the pixel units of the sensing array when a target object approaches the sensing array into a pixel output voltage; and

[0007] The sampling and processing module is used to sample the corresponding pixel output voltage for the first time to obtain a first sampled voltage value when the driving signal of the pixel unit is at a reset level, and to sample the pixel output voltage for the second and third times successively when the driving signal is at a signal level to obtain a second sampled voltage value and a third sampled voltage value, respectively. The module processes the first sampled voltage value, the second sampled voltage value and the third sampled voltage value, and outputs an amplified signal with an absolute value of (V3-2*V2+V1) as a capacitance detection signal, where V1, V2 and V3 represent the first sampled voltage value, the second sampled voltage value and the third sampled voltage value, respectively.

[0008] Optionally, the pixel unit circuit includes:

[0009] A first operational amplifier, with its non-inverting input coupled to a comparison voltage and its inverting input coupled to a signal representing the equivalent capacitance; and

[0010] The first feedback capacitor is coupled between the inverting input terminal and the output terminal of the first operational amplifier.

[0011] Optionally, the sampling and processing module includes:

[0012] A first CDS circuit is used to perform the first sampling and the second sampling to obtain the first sampling voltage value and the second sampling voltage value respectively, and to perform differential amplification processing on the first sampling voltage value and the second sampling voltage value to output a first CDS voltage, wherein the first CDS voltage is an amplified signal of the absolute value of (V2-V1);

[0013] A second CDS circuit is used to perform the second and third samplings to obtain the second and third sampled voltage values, respectively, and to perform differential amplification on the second and third sampled voltage values ​​to output a second CDS voltage, which is an amplified signal of the absolute value of (V3-V2); and

[0014] The difference unit is used to calculate the difference between the first CDS voltage and the second CDS voltage and output the corresponding difference result.

[0015] Optionally, the difference unit is used to perform analog difference calculation on the first CDS voltage and the second CDS voltage, and then perform analog-to-digital conversion to obtain a digital code representing the absolute value of (V3-2*V2+V1) and output it.

[0016] Optionally, the difference unit is used to perform analog-to-digital conversion on the first CDS voltage and the second CDS voltage respectively to obtain digital codes representing the first CDS voltage and the second CDS voltage respectively, and then perform digital difference on the digital codes representing the first CDS voltage and the second CDS voltage to obtain a digital code representing the absolute value of (V3-2*V2+V1) and output it.

[0017] Optionally, the sampling and processing module includes a third CDS circuit, which is used to perform the first sampling, the second sampling, and the third sampling to obtain the first sampling voltage value, the second sampling voltage value, and the third sampling voltage value, respectively. The sum of the first sampling voltage value and the third sampling voltage value is differentially amplified by twice the second sampling voltage value to output a third CDS voltage representing the amplified signal of the absolute value of (V3-2*V2+V1).

[0018] Optionally, the third CDS circuit includes:

[0019] The first capacitor unit includes a first sampling capacitor and a third sampling capacitor connected in parallel. The first terminals of the first sampling capacitor and the third sampling capacitor are respectively coupled to the output terminal of the pixel unit circuit through a switching element, and are also coupled to a reference voltage through a switching element. When the first sampling is performed, the first sampling capacitor is charged to the first sampling voltage value, and the third sampling capacitor is charged to the third sampling voltage value.

[0020] The second capacitor unit includes two second sampling capacitors connected in parallel. The first terminal of each second sampling capacitor is coupled to the output terminal of the pixel unit circuit via a switching element, and is also coupled to the reference voltage via a switching element. During the second sampling, each second sampling capacitor is charged to the second sampling voltage value; and

[0021] The second operational amplifier has its non-inverting input coupled to the second terminals of the first and third sampling capacitors, and its inverting input coupled to the second terminals of the two second sampling capacitors.

[0022] Optionally, the third CDS circuit further includes two second feedback capacitors. The first end of one second feedback capacitor is coupled to the non-inverting input of the second operational amplifier, and the second end is coupled to the reference voltage and the positive output of the second operational amplifier via a switching device. The non-inverting input and positive output of the second operational amplifier are coupled via a switching element. The first end of the other second feedback capacitor is coupled to the inverting input of the second operational amplifier, and the second end is coupled to the reference voltage and the negative output of the second operational amplifier via a switching device. The second end of the other second feedback capacitor is coupled to the reference voltage and the negative output of the second operational amplifier via a switching element. The inverting input and negative output are coupled via a switching element.

[0023] On the other hand, the present invention provides a fingerprint acquisition chip, the fingerprint acquisition chip including the above-mentioned capacitance detection circuit, wherein the target object is a finger fingerprint.

[0024] In another aspect, the present invention provides an electronic device, which includes the fingerprint acquisition chip described above.

[0025] In the capacitance detection circuit provided by this invention, the pixel unit circuit can convert the signal of the equivalent capacitance value sampled by the pixel unit of the sensor array when the target object approaches the sensor array into a pixel output voltage. The sampling and processing module can perform the first to third sampling on the pixel output voltage, and process the first sampled voltage value, the second sampled voltage value and the third sampled voltage value to output an amplified signal with an absolute value of (V3-2*V2+V1) as a capacitance detection signal. In this way, even if the driving signal is superimposed with interference, the influence of the interference can be eliminated by using the amplified signal with an absolute value of (V3-2*V2+V1) as a capacitance detection signal, which helps to improve the accuracy of the detection result.

[0026] The fingerprint acquisition chip and electronic device provided by the present invention both include the above-mentioned capacitance detection circuit and have the same or similar advantages as the capacitance detection circuit. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the pixel units of the fingerprint sensor array that form an equivalent capacitance.

[0028] Figure 2 This is a schematic diagram of a capacitance detection circuit.

[0029] Figure 3 yes Figure 2 The diagram shows the timing sequence of the capacitance detection circuit.

[0030] Figure 4 This is a schematic diagram of the capacitance detection circuit according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of the capacitance detection circuit according to another embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of a capacitance detection circuit according to another embodiment of the present invention.

[0033] Figure 7 yes Figure 6 The diagram shows the timing sequence of the capacitance detection circuit. Detailed Implementation

[0034] The capacitance detection circuit, fingerprint acquisition chip, and electronic device of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] Reference Figure 1To detect information about a target object (e.g., a fingerprint), a sensor array can be configured such that each pixel unit has an electrode plate 10 that generates a charge change when the target object approaches within a certain distance. This effectively creates an equivalent capacitance between the target object and the corresponding pixel unit. By sampling the charge change generated by the electrode plate 10 of the pixel unit, the capacitance value (i.e., the equivalent capacitance) can be obtained. The signal, equivalent capacitance value The signal varies depending on whether it corresponds to a ridge or a valley on the skin surface. Electrode plate 10 is connected to a drive signal (TX). When the drive signal is at a set level, the corresponding electrode plate 10 is selected. Electrode plate 10 is also connected to the input of a capacitance detection circuit, which can detect the equivalent capacitance value sampled from one or more pixel units. The signal is converted into pixel output voltage and sampled and calculated to form a capacitance detection signal corresponding to the equivalent capacitance value signal sampled for each pixel unit.

[0036] It should be noted that when using the above-mentioned capacitance detection mechanism for detection, the target object usually does not directly contact the electrode plate 10 in the sensor array. The sensor array is usually provided with an insulating covering layer. The target object to be detected can achieve the purpose of the target object approaching the sensor array and causing a change in the charge of the electrode plate of the pixel unit by approaching or contacting the covering layer.

[0037] Figure 2 A capacitance detection circuit is shown. This capacitance detection circuit includes a pixel unit circuit 110 and a coherent dual sampling circuit 120. For example... Figure 2 As shown, the pixel unit circuit 110 is used to convert the above-mentioned equivalent capacitance value (Taking a fingerprint as an example, the equivalent tolerance is expressed as follows) This is converted into pixel output voltage. As an example, pixel unit circuit 110 includes a first operational amplifier OP1 and a first feedback capacitor. The non-inverting input of the first operational amplifier OP1 is coupled to a comparator voltage. The inverting input is coupled to the equivalent capacitance value. The signal, the first feedback capacitor Coupled between the inverting input and output of the first operational amplifier OP1, the output voltage of the first operational amplifier OP1 is the pixel output voltage. ).

[0038] The coherent dual-sampling circuit 120 is used to sample the pixel output voltage and perform differential amplification on the voltages sampled twice. For example... Figure 1 As shown, the coherent dual sampling circuit 120 includes two sampling capacitors. Second operational amplifier OP2, two second feedback capacitors and multiple switching elements ( ~ (This represents the control signal for the plurality of switching elements). Indicates the reference voltage. This represents the CDS voltage output by the coherent dual sampling circuit 120.

[0039] Figure 3 It shows Figure 2 The timing diagram of the capacitance detection circuit shown is provided. (Refer to...) Figure 2 and Figure 3 , The driving signal representing the pixel unit connection, the coherent dual sampling circuit 120 in the control signal When the signal is high, the first sampling is performed (corresponding to the first sampling phase), in the control signal. When the signal is high, a second sampling is performed (corresponding to the second sampling phase), in the control signal. When the signal is high, it is amplified (corresponding to the amplification phase). Theoretically, the CDS voltage output by the coherent dual sampling circuit 120 is... It can be expressed by equation (1):

[0040] (1)

[0041] In equation (1), and These are the pixel output voltages obtained by the coherent dual sampling circuit 120 during the first and second sampling, respectively. The driving signals for the first and second sampling. Voltage changes, Indicates sampling capacitance The capacitance value, Indicates the first feedback capacitor The capacitance value, Indicates the second feedback capacitor The capacitance value, This is the equivalent capacitance value.

[0042] When the target object and the capacitance detection circuit do not share a common ground (e.g., the human body whose fingerprint is being detected and the electronic device on which the capacitance detection circuit is located do not share a common ground), it is equivalent to a drive signal. An interference signal is superimposed on the signal, at which point the first CDS voltage output by the coherent dual sampling circuit 120 is... This can be expressed by equation (2):

[0043] (2)

[0044] In equation (2), This represents the voltage change of the interference signal during the time interval between the first and second sampling.

[0045] From equations (1) and (2), it can be seen that, using... Figure 2 When the timing sequence shown is in operation, if the target object and the capacitance detection circuit share a common ground, the input terminal of the capacitance detection circuit (specifically, the drive signal) will be... The interference signal generated will cause the output of the coherent dual sampling circuit 120 to deviate from the actual value.

[0046] The present invention includes a capacitance detection circuit, which can be used to detect target object information (such as fingerprint collection) and can avoid interference caused by the target object and the capacitance detection circuit (or the electronic device on which the capacitance detection circuit is set) not being in the same location.

[0047] Reference Figures 4 to 7 The capacitance detection circuit of this embodiment includes a pixel unit circuit 110 and a sampling and processing module 200.

[0048] Pixel unit circuit 110 is used to measure the equivalent capacitance value sampled by the pixel unit of the sensing array when a target object (taking a fingerprint as an example) approaches the sensing array. The signal is converted into pixel output voltage ( ).

[0049] The pixel unit circuit 110 can be adopted as follows: Figure 1 and Figure 6 The circuit structure shown is as follows: Figure 1 and Figure 6 As shown, the pixel unit circuit 110 includes a first operational amplifier OP1 and a first feedback capacitor. The non-inverting input of the first operational amplifier OP1 is coupled to a comparator voltage. The inverting input is coupled to the above equivalent capacitance value. The signal, the first feedback capacitor Coupled between the inverting input and output of the first operational amplifier OP1, the output voltage of the first operational amplifier OP1 is the pixel output voltage. ).

[0050] The sampling and processing module 200 is used for the driving signal of the pixel unit. When the signal is at the reset level, the pixel output voltage is sampled for the first time to obtain the first sampled voltage value V1, and then the driving signal is applied. When the signal level is 0, the pixel output voltage is sampled a second time and a third time to obtain the second sampled voltage value V2 and the third sampled voltage value V3 respectively. The first sampled voltage value V1, the second sampled voltage value V2 and the third sampled voltage value V3 are processed and the amplified signal of the absolute value of (V3-2*V2+V1) is output as the capacitance detection signal.

[0051] Compared to Figure 1 and Figure 2 The capacitance detection circuit shown only performs the first and second samplings and differential amplification, resulting in the obtained first CDS voltage. Despite the influence of interference signals, in the capacitance detection circuit of this embodiment of the invention, the sampling and processing module 200 still maintains the first and second samplings, and adds a third sampling after the second sampling. By processing the first sampling voltage value V1, the second sampling voltage value V2 and the third sampling voltage value V3 obtained from the three samplings, the obtained capacitance detection signal is not only related to the first sampling voltage value V1 and the second sampling voltage value V2, but also to the third sampling voltage value V3.

[0052] The capacitance detection circuit of this invention can avoid drive signals. The effect of interference signals superimposed on the signal is as follows.

[0053] The sampling and processing module 200 maintains the first and second sampling as described above. As can be seen from the above description, the second sampled voltage value V2 and the first sampled voltage value V1 obtained from the second and first samplings are subjected to difference amplification processing, and the result satisfies the above equation (2), where This represents the voltage change of the interference signal during the time interval between the first and second sampling. When interference signals are present, 0, the first CDS voltage in equation (2) With the CDS voltage in equation (1) There is a discrepancy.

[0054] The sampling and processing module 200 also performs a third sampling, obtaining the third sampled voltage value V3, which is then processed using... Figure 1 The CDS circuit shown can also perform differential amplification on the third sampled voltage value V3 and the second sampled voltage value V2 obtained from the third and second samplings, resulting in a second CDS voltage. Satisfying equation (3):

[0055] (3)

[0056] In equation (3), This represents the voltage change of the interference signal during the time interval between the second and third sampling. Equation (3), compared to equation (2), does not represent the driving signal. voltage change This is because both the second and third samplings occur during the driving signal. The signal is acquired at the signal level, and the driving signal is acquired during the time interval between the second and third samples. voltage change It can be considered as 0.

[0057] When the sampling frequency of the CDS circuit is more than 10 times the interference frequency, it can be considered that the change in interference is similar in two adjacent sampling time intervals. That is, the voltage change of the interference signal in the interval between the first and second sampling can be considered equal to the voltage change of the interference signal in the interval between the second and third sampling, i.e., ΔV1=ΔV2. Based on this condition, the difference between the above equations (2) and (3) can be obtained as follows:

[0058] (4)

[0059] As shown in equation (4), by adjusting the first CDS voltage Second CDS voltage The difference is calculated, and the result no longer contains ΔV1 and ΔV2, meaning that the voltage change of the interference signal within the sampling time interval has been eliminated, indicating that the influence of the interference signal has been eliminated. The absolute value of is used for capacitance detection and is unaffected by the interference signal. Furthermore, from equations (4) and (1), it can be seen that: ,Right now Equal to the theoretical CDS voltage ,Right now The amplified signal, which theoretically does not change the difference between the pixel output voltage of the first and second sampling, can be used as the output capacitance detection signal.

[0060] From equation (4), we can see that, The signal is an amplified signal of the absolute value of (2V2-V1-V3) or the absolute value of (V3-2*V2+V1). Therefore, in this embodiment, the sampling and processing module 200 obtains V1, V2 and V3 through three samplings, processes them, and outputs an amplified signal of the absolute value of (V3-2*V2+V1) as the capacitance detection signal.

[0061] The capacitance detection circuit of the present invention will be further described below.

[0062] Reference Figure 4 and Figure 5In some embodiments of the capacitance detection circuit, the sampling and processing module 200 includes a first CDS circuit, a first CDS circuit, and a difference unit.

[0063] The first CDS circuit is used to perform the first sampling and the second sampling as described above, to obtain the first sampled voltage value V1 and the second sampled voltage value V2 respectively, and to perform differential amplification processing on the first sampled voltage value V1 and the second sampled voltage value V2 to output the first CDS voltage. The first CDS voltage It is an amplified signal of the absolute value of (V2-V1).

[0064] The second CDS circuit is used to perform the second and third sampling as described above, to obtain the second sampled voltage value V2 and the third sampled voltage value V3 respectively, and to perform differential amplification on the second sampled voltage value V2 and the third sampled voltage value V3 to output the second CDS voltage. The second CDS voltage The signal is an amplified signal of the absolute value of (V3-V2).

[0065] The difference unit is used to adjust the first CDS voltage. Second CDS voltage The difference is calculated, and the corresponding difference result is output. The difference result is an amplified signal of the absolute value of (V3-2*V2+V1), which can be used as a capacitance detection signal output.

[0066] Reference Figure 4 The difference unit can be implemented using an analog scheme. Specifically, the first CDS voltage can be first... Second CDS voltage Perform simulation subtraction, then perform analog-to-digital conversion (ADC) to obtain the representation. The digital code is output, which is the output signal of the sampling and processing module 200, i.e., the capacitance detection signal, and can be used for fingerprint detection.

[0067] This invention is not limited thereto; see reference. Figure 5 The difference unit can also be implemented digitally, specifically by first differentiating the first CDS voltage. Second CDS voltage Analog-to-digital conversion (ADC) is performed separately to obtain the values ​​representing the first CDS voltage. Second CDS voltage The digital code, then representing the first CDS voltage Second CDS voltage The digital code is subtracted to obtain the representation. The digital code is output, which is the output signal of the sampling and processing module 200, i.e., the capacitance detection signal, and can be used for fingerprint detection.

[0068] Reference Figure 6 In some embodiments, the capacitance detection circuit includes a pixel unit circuit 110 and a sampling and processing module 200. The sampling and processing module 200 includes a third CDS circuit, which performs the first, second, and third sampling described above to obtain a first sampling voltage value V1, a second sampling voltage value V2, and a third sampling voltage value V3, respectively. The sum of the first and third sampling voltage values ​​V1 and V3, plus twice the second sampling voltage value V2, is differentially amplified to output a third CDS voltage representing the amplified signal of the absolute value of (V3 - 2*V2 + V1). . Figure 7 The operating timing diagram of the third CDS circuit is shown.

[0069] Reference Figure 6 The third CDS circuit includes a first capacitor unit 211, a second capacitor unit 212, and a second operational amplifier OP2.

[0070] The first capacitor unit 211 includes a first sampling capacitor connected in parallel. and the third sampling capacitor First sampling capacitor and the third sampling capacitor The first end is respectively connected to a switching element and ( and (Also representing the control signal of the corresponding switching device) is coupled to the output terminal of the pixel unit circuit 110, and also through the switching element ( (Also indicating the control signal of the corresponding switching device) is coupled to a reference voltage. During the first sampling (e.g.) Figure 7 During the first sampling phase (as shown), the first sampling capacitor... Charged to the first sampling voltage value V1, and then the third sampling is performed (e.g. Figure 7 During the third sampling phase (as shown), the third sampling capacitor It is charged to the third sampling voltage value V3.

[0071] The second capacitor unit 212 includes two second sampling capacitors connected in parallel. Each second sampling capacitor The first end is respectively connected to a switching element ( (Also representing the control signal of the corresponding switching device) is coupled to the output terminal of the pixel unit circuit 110, and also through the switching element ( (Also representing the control signal of the corresponding switching device) coupled to the reference voltage During the second sampling (e.g.) Figure 7 During the second sampling phase (as shown), each second sampling capacitor It is charged to the second sampling voltage value V2.

[0072] First sampling capacitor Second sampling capacitor and the third sampling capacitor The capacitance values ​​are, for example, equal, i.e. = = .

[0073] The non-inverting input of the second operational amplifier OP2 is coupled to the first sampling capacitor. and the third sampling capacitor The second terminal, the inverting input terminal, is coupled to the two second sampling capacitors of the second capacitor unit 212. The second terminal. The third CDS circuit may also include two second feedback capacitors. A second feedback capacitor The first terminal is coupled to the non-inverting input of the second operational amplifier OP2, and the second terminal is connected to a switching device. and ( and (Also representing the control signal of the corresponding switching device) coupled to the reference voltage The positive output terminal of the second operational amplifier OP2, and the non-inverting input terminal and positive output terminal of the second operational amplifier OP2 are connected by a switching element. ( This also indicates the coupling of the control signal of the corresponding switching device; another second feedback capacitor. The first terminal is coupled to the inverting input of the second operational amplifier OP2, and the second terminal is connected to a switching device. and ( and (Also representing the control signal of the corresponding switching device) coupled to the reference voltage The negative output terminal of the second operational amplifier OP2, and the inverting input terminal and negative output terminal of the second operational amplifier OP2 are connected by a switching element. ( It also indicates the coupling of the control signal of the corresponding switching device.

[0074] Figure 6 The capacitance detection circuit shown can be used as follows: Figure 7 The working sequence shown executes the first to third sampling as described above, and samples the first sampling voltage V1, the second sampling voltage V2, and the third sampling voltage to the first sampling capacitor respectively. Second sampling capacitor and the third sampling capacitor Above, after sampling is completed, the third CDS circuit enters the following state: Figure 7 The amplified phase shown performs differential amplification on the sum of the first sampled voltage value V1 and the third sampled voltage value V3 and twice the second sampled voltage value V2. The output result can be expressed by equation (5):

[0075] (5)

[0076] It can be seen that, by utilizing, such Figure 6 The capacitance detection circuit shown can achieve the above-mentioned result by simulating the difference. The process of eliminating interference effects has been achieved.

[0077] In the capacitance detection circuit of this embodiment, the pixel unit circuit 110 can detect the equivalent capacitance value sampled by the pixel units of the sensing array when the target object approaches the sensing array. The signal is converted into pixel output voltage. The sampling and processing module 200 can sample the pixel output voltage for the first to third time, and process the corresponding first sampled voltage value V1, second sampled voltage value V2, and third sampled voltage value V3, outputting an amplified signal with the absolute value of (V3-2*V2+V1) as a capacitance detection signal. In this way, even if the driving signal... If there is superimposed interference (such as the human body being detected and the electronic device used to collect the fingerprint not sharing a common ground), the influence of the interference can be eliminated by using an amplified signal with the absolute value of (V3-2*V2+V1). The amplified signal with the absolute value of (V3-2*V2+V1) can be used as the capacitance detection signal, which is not affected by interference, thus helping to improve the accuracy of the detection results.

[0078] This invention also includes a fingerprint acquisition chip, comprising the capacitance detection circuit described in the above embodiments, wherein the target object is a finger fingerprint. Using the capacitance detection circuit, the equivalent capacitance value sampled by the pixel units of the sensor array when a finger fingerprint approaches the sensor array can be obtained. The signal is converted into pixel output voltage, and after the above three samplings, the amplified signal of the absolute value of (V3-2*V2+V1) is used as the capacitance detection signal, compared to... Figure 2 and Figure 3The capacitance detection circuit and detection method shown can eliminate the influence of interference superimposed on the driving signal, which helps to improve the accuracy of fingerprint detection, thereby helping to improve the performance of the fingerprint acquisition chip.

[0079] This invention also includes an electronic device comprising the fingerprint acquisition chip described in the above embodiments. As examples, the electronic device may be a mobile phone, laptop computer, tablet computer, desktop computer, smartwatch, navigation device, gaming device, wearable device, access control system, keyless entry system for automobiles, or keyless start system for automobiles, etc.

[0080] The fingerprint acquisition chip of the electronic device includes the capacitance detection circuit described in the above embodiments. Using the capacitance detection circuit, an equivalent capacitance value sampled by the pixel units of the sensor array when a fingerprint approaches the sensor array can be generated. The capacitance detection signal corresponding to the signal is compared to, for example, Figure 1 and Figure 2 The capacitance detection circuit and detection method shown can eliminate the influence of interference superimposed on the driving signal, which helps to improve the accuracy of fingerprint detection and thus helps to improve the performance of the electronic device.

[0081] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0082] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A capacitance detection circuit, characterized by, The pixel unit circuit is configured to convert a signal of an equivalent capacitance value sampled by a pixel unit of a sensing array when a target object approaches the sensing array into a pixel output voltage. The sampling and processing module is configured to, when a driving signal of the pixel unit is a reset level, sample the pixel output voltage for a first time to obtain a first sampling voltage value, when the driving signal is a signal level, sample the pixel output voltage for a second time and a third time in sequence to obtain a second sampling voltage value and a third sampling voltage value respectively, and process the first sampling voltage value, the second sampling voltage value and the third sampling voltage value to output an amplified signal of an absolute value of (V3-2*V2+V1) as a capacitance detection signal, where V1, V2 and V3 represent the first sampling voltage value, the second sampling voltage value and the third sampling voltage value respectively. The pixel unit circuit comprises: a first operational amplifier, a same-phase input end of which is coupled to a comparison voltage, and an opposite-phase input end of which is coupled to the signal of the equivalent capacitance value; and 2. The capacitance detection circuit of claim 1, wherein, a first feedback capacitor, coupled between the opposite-phase input end and an output end of the first operational amplifier. The sampling and processing module comprises: a first CDS circuit, configured to sample the pixel output voltage for the first time and the second time to obtain the first sampling voltage value and the second sampling voltage value respectively, and perform differential amplification processing on the first sampling voltage value and the second sampling voltage value to output a first CDS voltage, the first CDS voltage being an amplified signal of an absolute value of (V2-V1); 3. The capacitance detection circuit of claim 1, wherein, a second CDS circuit, configured to sample the pixel output voltage for the second time and the third time to obtain the second sampling voltage value and the third sampling voltage value respectively, and perform differential amplification processing on the second sampling voltage value and the third sampling voltage value to output a second CDS voltage, the second CDS voltage being an amplified signal of an absolute value of (V3-V2); and a difference unit, configured to obtain a difference between the first CDS voltage and the second CDS voltage, and output a corresponding difference result. The difference unit is configured to perform analog difference between the first CDS voltage and the second CDS voltage, and then perform analog-to-digital conversion to obtain a digital code representing an absolute value of (V3-2*V2+V1) and output the digital code. The difference unit is configured to perform analog-to-digital conversion on the first CDS voltage and the second CDS voltage respectively to obtain digital codes representing the first CDS voltage and the second CDS voltage respectively, and then perform digital difference between the digital codes representing the first CDS voltage and the second CDS voltage to obtain a digital code representing an absolute value of (V3-2*V2+V1) and output the digital code.

4. The capacitance detection circuit of claim 3, wherein, ​ 5. The capacitance detection circuit of claim 3, wherein, ​ 6. The capacitance detection circuit of claim 1, wherein, The sampling and processing module comprises a third CDS circuit, which is configured to perform the first sampling, the second sampling and the third sampling to obtain the first sampling voltage value, the second sampling voltage value and the third sampling voltage value respectively, perform differential amplification processing on the sum of the first sampling voltage value and the third sampling voltage value and twice the second sampling voltage value, and output a third CDS voltage of an amplified signal representing the absolute value of (V3-2*V2+V1).

7. The capacitance detection circuit of claim 6, wherein, The third CDS circuit comprises: a first capacitor unit comprising a first sampling capacitor and a third sampling capacitor arranged in parallel, first ends of the first sampling capacitor and the third sampling capacitor being coupled to an output end of the pixel unit circuit through switch elements and to a reference voltage through switch elements, the first sampling capacitor being charged to the first sampling voltage value and the third sampling capacitor being charged to the third sampling voltage value during the first sampling; a second capacitor unit comprising two second sampling capacitors arranged in parallel, first ends of the second sampling capacitors being coupled to the output end of the pixel unit circuit through switch elements and to the reference voltage through switch elements, each of the second sampling capacitors being charged to the second sampling voltage value during the second sampling; and a second operational amplifier, a non-inverting input end of which is coupled to second ends of the first sampling capacitor and the third sampling capacitor, and an inverting input end of which is coupled to second ends of the second sampling capacitors.

8. The capacitance detection circuit of claim 7, wherein, The third CDS circuit further comprises two second feedback capacitors, a first end of one of the second feedback capacitors being coupled to the non-inverting input end of the second operational amplifier and a second end of the second feedback capacitor being coupled to the reference voltage and a positive output end of the second operational amplifier through switch elements, the non-inverting input end of the second operational amplifier and the positive output end of the second operational amplifier being coupled through a switch element, a first end of the other of the second feedback capacitors being coupled to the inverting input end of the second operational amplifier and a second end of the second feedback capacitor being coupled to the reference voltage and a negative output end of the second operational amplifier through switch elements, the inverting input end of the second operational amplifier and the negative output end of the second operational amplifier being coupled through a switch element.

9. A fingerprint acquisition chip, characterized by The capacitive detection circuit according to any one of claims 1 to 8, wherein the target object is a finger print.

10. An electronic device, comprising: The finger print collection chip according to claim 9.

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