Display driving device, display equipment and panel defect detection method

Abstract

The invention provides a display driving device. The display driving device comprises a test signal generating circuit, a source electrode driving circuit and a test circuit, the test signal generation circuit generates a test signal in a panel detection stage. The source driving circuit is electrically connected with the switching circuit through a plurality of driving pins. The source driving circuit provides a test signal to the switching circuit through at least one driving pin in a panel detection stage in a time-sharing manner, so that the switching circuit generates a detection signal according to the test signal. The test circuit is electrically connected with one end of the detection line through a corresponding test pin. The test circuit receives a test signal in a panel detection stage, receives a detection signal on the detection line through the test pin, and judges whether the test signal and the detection signal meet a test condition or not so as to determine whether the display panel has defects or not. The invention further provides a display device and a panel defect detection method.

Description

Technical Field

[0001] This application relates to the field of touch technology, and in particular to a display driver, display device, and panel defect detection method. Background Technology

[0002] With the continuous development of electronic technology, most consumer electronics products, such as mobile phones, portable computers, personal digital assistants (PDAs), tablet computers, and media players, use displays as input / output devices to provide a more user-friendly human-computer interaction experience. Display devices typically include a display panel and driving circuitry to drive the displayed image. Display panel types typically include Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs). Display panels usually include multiple data lines and multiple scan lines. The integrity of the data lines and scan lines is crucial to the display effect of the panel. Currently, existing technologies typically employ additional circuit architectures or devices to perform integrity checks on the display panel, which is costly. Summary of the Invention

[0003] The main objective of this application is to provide a display driver, display device, and panel defect detection method, aiming to solve the problem of how to reduce the detection cost when performing completion inspection of display panels in the prior art.

[0004] The present application is described below from different aspects. It should be understood that the different implementation methods and beneficial effects described below can be referenced from each other.

[0005] In a first aspect, this application provides a display driving device electrically connected to a display panel; the display panel includes multiple data lines disposed in a display area and at least one switching circuit, at least one control line, and at least one detection line disposed in a non-display area; the display driving device includes multiple driving pins and at least two test pins; each driving pin is electrically connected to the switching circuit via a data line; the test pin is electrically connected to at least one end of the detection line; the display driving device further includes: Test signal generation circuit, used to generate test signals during the panel inspection stage; The source drive circuit is electrically connected to the test signal generation circuit and is electrically connected to the switch circuit through multiple drive pins and corresponding data lines. The drive pins of the source drive circuit are used to provide the test signal to the switch circuit through at least one drive pin during the panel detection stage. When the switch circuit is turned on under the control of the control line, it generates a detection signal according to the test signal. At least one test circuit; each test circuit is electrically connected to a test signal generation circuit and electrically connected to one end of a detection line through a corresponding test pin; the test circuit is used to receive test signals and receive detection signals on the detection line through the test pin during the panel detection stage, and to determine whether the test signals and detection signals meet the test conditions.

[0006] Secondly, this application provides a display device, including a display panel and at least one display driving device; the display panel includes multiple data lines disposed in the display area and at least one switching circuit, at least one control line, and at least one detection line disposed in the non-display area; the display driving device... Test signal generation circuit, used to generate test signals during the detection phase; The source drive circuit is electrically connected to the test signal generation circuit and is electrically connected to the switching circuit through multiple drive pins and corresponding data lines. The drive pins of the source drive circuit are used to provide the test signal to the switching circuit through at least one drive pin during the detection phase. When the switching circuit is turned on under the control of the control line, it generates a detection signal according to the test signal. At least one test circuit; each test circuit is electrically connected to a test signal generation circuit and electrically connected to one end of a detection line through a corresponding test pin; the test circuit is used to receive test signals and receive detection signals on the detection line through the test pin during the detection phase, and to determine whether the test signals and detection signals meet the test conditions.

[0007] Thirdly, this application provides a panel defect detection method applied to a display device; the display device includes a display panel and a display driving device; the display panel includes multiple data lines disposed in the display area and at least one switching circuit, at least one control line, and at least one detection line disposed in the non-display area; the display driving device includes multiple driving pins and at least two test pins; each driving pin is electrically connected to the switching circuit through a data line, and each test pin is electrically connected to the switching circuit; the test pins are electrically connected to at least one end of the detection line; the panel defect detection method includes: During the testing phase, the display driver's multiple drive pins output test signals to the corresponding data lines in a time-sharing manner. At least one switching circuit outputs at least one detection signal to the display driver; The display driver determines whether the test signal and the detection signal meet the test conditions; When the test signal and detection signal meet the test conditions, the display driver confirms that the display panel is free of defects; and When the test signal and detection signal do not meet the test conditions, the display driver confirms that there is a defect in the display panel.

[0008] Compared with the prior art, this application has the following advantages: The aforementioned display driving device, display equipment, and panel defect detection method utilize existing source driving circuits to transmit test signals. The test circuit identifies whether there are defects in the data lines within the display panel based on the test signals and the detection signals provided by the detection lines within the display panel, thereby reducing the detection cost in the panel defect detection process. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a display device provided in the first embodiment of this application.

[0011] Figure 2 This is a schematic diagram of a display device provided in the second embodiment of this application.

[0012] Figure 3 This is a schematic diagram of a display device provided in the third embodiment of this application.

[0013] Figure 4 This is a schematic diagram of a display device provided in the fourth embodiment of this application.

[0014] Figure 5 This is a schematic diagram of a display device provided in the fifth embodiment of this application.

[0015] Figure 6 for Figure 1 A schematic diagram of the test circuit in the first embodiment.

[0016] Figure 7 for Figure 1 A schematic diagram of the test circuit in the second embodiment.

[0017] Figure 8 for Figure 1 or Figure 2 The diagram shows the waveforms of the control signal, test signal, and detection signal when the display driver is driving the data line in a time-division manner during the panel inspection stage and the data line is free of defects.

[0018] Figure 9 for Figure 1 or Figure 2The diagram shows the waveforms of the control signal, test signal, and detection signal when the display driver is driving the data line in a time-division manner during the panel detection stage and the data line is open-circuited.

[0019] Figure 10 for Figure 1 or Figure 2 The diagram shows the waveforms of the control signal, test signal, and detection signal when the display driver simultaneously drives four data lines during the panel inspection stage and there are no defects in the four data lines.

[0020] Figure 11 for Figures 3 to 5 The diagram shows the waveforms of the control signal, test signal, and detection signal when the display driver is driving the data line in a time-division manner during the panel inspection stage and the data line is free of defects.

[0021] Figure 12 for Figures 3 to 5 The diagram shows the waveforms of the control signal, test signal, and detection signal when the display driver is driving the data line in a time-division manner during the panel detection stage and the data line has a short-circuit defect.

[0022] Figure 13 A flowchart illustrating the panel defect detection method according to a preferred embodiment of this application.

[0023] Figure 14 for Figure 13 A detailed flowchart of step S13.

[0024] Figure 15 for Figure 14 A flowchart illustrating the process prior to step S131.

[0025] Figure 16 for Figure 14 A flowchart illustrating the process prior to step S134.

[0026] Explanation of main component symbols Display devices 100A, 100B, 100C, 100D, 100E Display driver devices 20A, 20B, 20C, 20D, 20E Display panels 10A, 10B, 10C, 10D, 10E Display area 101 Data lines S1~Sn, Si~S(i+k) Non-display area 103 Switching circuit 11 Switching elements T1~Tn Test lines 12, 12A, 12B Control lines 13, 13A, 13B Test signal generation circuit 21 Source drive circuit 22 Drive unit 221 Test circuits 23, 23A, 23B Control circuit 24 Test pins PT_10, PT_11, PT_20, PT_21 Control pins PC_10, PC_11, PC_20, PC_21 Drive pins PS_1~PS_n, PS_1~PS_i, PS_i~PS_(i+k), PS_(k)~PS_(k+i) First direction X Second direction Y First enable signal En1 Second enable signal En2 First control signal Ctrl1 Second control signal Ctrl2 Indicator signal In Comparison Unit 231 Transmission unit 232 Test signal Stest Detection signal Sdet Steps S11~S15, S131~S138, S1310~S1313, S1340~S1343 The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0028] The terms "first," "second," and "third," etc., used in the specification and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising," and any variations thereof, are intended to cover non-exclusive inclusion.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] The specific embodiments of the display driving device, display equipment, and panel defect detection method of this application will be described below with reference to the accompanying drawings.

[0031] Please see Figure 1 This is a schematic diagram of the display device 100A according to the first embodiment of this application. In at least one embodiment of this application, the display device 100A can be a mobile device such as a personal computer, tablet computer, smartphone, personal digital assistant (PDA), game console, interactive network television (Internet Protocol Television, IPTV), smart wearable device, navigation device, etc., or a fixed device such as a desktop computer, server, digital television, etc. Specifically, the display device 100A can be a liquid crystal display or an organic light emitting diode (OLED) display with a self-emissive structure.

[0032] The display device 100A includes a display panel 10A and a display driver 20A.

[0033] The display panel 10A includes a display area 101 and a non-display area 103 surrounding the display area 101. The display area 101 includes multiple data lines S1 to Sn, where n is a positive integer and is odd. The multiple data lines S1 to Sn extend along a first direction X and are arranged parallel to each other. The non-display area 103 includes a switch circuit 11, a detection line 12, and a control line 13. In at least one embodiment of this application, the switch circuit 11 is located below the display area 101. The switch circuit 11 is electrically connected to the multiple data lines S1 to Sn. The switch circuit 11 includes multiple switching elements T1 to Tn. The control terminal of each switching element T1 to Tn is electrically connected to the display driver 20A via the control line 13. The first connection terminal of each switching element T1 to Tn is electrically connected to the corresponding data line S1 to Sn. The second connection terminal of each switching element T1 to Tn is electrically connected to the display driver 20A via the detection line 12. In at least one embodiment of this application, the switching elements T1~Tn are N-type field-effect transistors (NMOS); the control terminal is the gate, the first connection terminal is the source, and the second connection terminal is the drain. Detection line 12 and control line 13 are arranged around the display area 101. Detection line 12 is disposed outside the control line 13, and control line 13 is disposed between detection line 12 and display area 101.

[0034] The display driver device 20A includes a control pin PC_10, a detection pin PT_10, and multiple drive pins PS_1 to PS_k. Here, k is a positive integer less than or equal to n. In at least one embodiment of this application, k is equal to n. The control pin PC_10 is electrically connected to control line 13 and is used to transmit switch control signals to the switch circuit 11. The detection pin PT_10 is electrically connected to detection line 12. The multiple drive pins PS_1 to PS_k are electrically connected to multiple data lines S1 to Sn.

[0035] The display driver 20A includes a test signal generation circuit 21, a source drive circuit 22, a test circuit 23, and a control circuit 24.

[0036] The test signal generation circuit 21 is used to generate a test signal. In at least one embodiment of this application, the test signal can be a fixed voltage or a signal of other waveforms.

[0037] The source drive circuit 22 is electrically connected to the test signal generation circuit 21, the control circuit 24, and the display panel 10A. The source drive circuit 22 receives the second enable signal En2 output by the control circuit 24 and switches to the detection phase when the second enable signal En2 is at the first level. The source drive circuit 22 includes multiple drive units 221. Each drive unit 221 corresponds to one data line Si. In the detection phase, the drive unit 221 outputs the test signal to the corresponding data line Si through the corresponding drive pin PS_i. In the display drive phase, the drive unit 221 outputs the data signal to the corresponding data line Si through the corresponding drive pin PS_i.

[0038] Test circuit 23 is electrically connected to test signal generation circuit 21 and control circuit 24. Test circuit 23 receives a first enable signal En1 generated by control circuit 24. When the first enable signal En1 is at a first level, test circuit 23 switches to the detection stage. In the detection stage, test circuit 23 receives the test signal generated by test signal generation circuit 21 as a reference, receives the detection signal output by display panel 10A through detection pin PT_10 as the detection object, and determines whether the test signal and detection signal meet the test conditions. When the test signal and detection signal meet the test conditions, test circuit 23 identifies a defect in display panel 10A and outputs an indication signal In at a first level. When the test signal and detection signal do not meet the test conditions, test circuit 23 identifies a defect in display panel 10A and outputs an indication signal In at a second level.

[0039] The control circuit 24 is electrically connected to the test circuit 23 and the source drive circuit 22. The control circuit 24 outputs a first enable signal En1 to the test circuit 23, a second enable signal En2 to the source drive circuit 22, a first control signal Ctrl1 to the control line 13, and receives an indication signal In. When it receives the first-level indication signal In, the control circuit 24 identifies that the display panel 10A is defect-free; when it receives the second-level indication signal In, the control circuit 24 identifies that the display panel 10A has a defect.

[0040] The testing phase includes a panel testing phase. When the control signal on control line 13 is high, the display driver 20A is in the panel testing phase. During this phase, the source driver circuit 22 controls the drive pins PS_1 to PS_n to output test signals to the corresponding data lines Si in a time-division multiplexing manner. The test circuit 23 receives the test signals and also receives the detection signal on detection line 12 through the detection pin PT_1. The test circuit 23 determines whether the test signal and the detection signal meet the test conditions. When both meet the conditions, the test circuit 23 identifies that the data line Si corresponding to the current drive pin PS_i is normal; when they do not meet the conditions, the test circuit 23 identifies that the data line Si corresponding to the current drive pin PS_i has a defect. When the difference between the test signal and the detection signal is greater than a preset value, it indicates that the data line Si does not meet the open-circuit detection conditions, and the test circuit 23 identifies an open circuit on the data line Si. Figure 8 For example, when the source drive circuit 22 controls the first drive pin PS_1 to output a square wave signal, and the detection pin PT_1 also receives a square wave signal on the detection line 12, then the test signal and the detection signal meet the panel open circuit test conditions, and the data line S1 corresponding to the first drive pin PS_1 is not open. When the source drive circuit 22 controls the second drive pin PS_1 to output a square wave signal, and the detection pin PT_1 also receives a square wave signal on the detection line 12, then the test signal and the detection signal meet the panel open circuit test conditions, and the data line S2 corresponding to the second drive pin PS_2 is not open. The detection process of the test circuit 23 for other data lines S3~Sn is similar and will not be described again here. Figure 9 For example, when the source drive circuit 22 controls the second drive pin PS_1 to output a square wave signal, if the detection pin PT_1 receives a floating detection signal on the detection line 12, then the identification test signal and the detection signal do not meet the panel open circuit test conditions, and the data line S2 corresponding to the second drive pin PS_2 is open.

[0041] In another embodiment of this application, the driving unit 221 can be divided into multiple driving groups. Each driving group includes the same number of driving units 221. During the panel detection stage, the source driving circuit 22 controls multiple driving pins PS_i~PS_(i+k) within the same driving group to simultaneously output test signals to the corresponding multiple data lines Si~S(i+k). The test circuit 23 receives the test signals and receives the detection signals on the detection line 12 through the detection pin PT_1. The test circuit 23 determines whether the test signals and detection signals meet the panel open circuit test conditions. When the test signals and detection signals meet the panel open circuit test conditions, the test circuit 23 identifies that the multiple data lines Si~S(i+k) corresponding to the multiple driving pins PS_i~PS_(i+k) are normal; when the test signals and detection signals do not meet the panel open circuit test conditions, the test circuit 23 identifies that the multiple data lines Si~S(i+k) corresponding to the multiple driving pins PS_i~PS_(i+k) are simultaneously open-circuited. When the difference between the test signal and the detection signal is greater than a preset value, it indicates that the corresponding multiple data lines Si~S(i+k) do not meet the panel open circuit detection conditions. At this time, the test circuit 23 identifies that there is an open circuit on the corresponding multiple data lines Si~S(i+k). Figure 10 For example, when the source drive circuit 22 controls the first to fourth drive pins PS_1~PS_4 to output square wave signals, and the detection pin PT_1 receives the detection signal on the detection line 12, which is also a square wave signal, then the identification test signal and the detection signal meet the panel open circuit test conditions, and the data lines S1~S4 corresponding to the first to fourth drive pins PS_1~PS_4 are not simultaneously open.

[0042] The aforementioned display device 100A utilizes the existing source drive circuit 22 for test signal transmission. The test circuit 23 identifies whether there are defects in the data lines S1~Sn within the display panel 10A based on the test signal and the detection signal provided by the detection lines 12 within the display panel 10A, thereby reducing the detection cost during the panel defect process. Simultaneously, by utilizing the grouping mode of the drive units 221, the detection speed of defects on the display panel 10A can be accelerated.

[0043] Please see Figure 2 This is a schematic diagram of the display device 100B according to the second embodiment provided in this application. The structure of the display panel 10B is similar to... Figure 1 The structure of the display panel 10A in the first embodiment is the same, and the specific electrical connections will not be described again here. The display driving device 20B in the second embodiment has a structure that is largely the same as that in the first embodiment. That is to say, the description of the display driving device 20A in the first embodiment can be basically applied to the display driving device 20B in the second embodiment. The main difference between the two is that the display driving device 20B includes two test circuits 23.

[0044] Two test circuits 23 are respectively disposed on both sides of the source drive circuit 22. One test circuit 23 is electrically connected to one end of the detection line 12, and the other test circuit 23 is electrically connected to the other end of the detection line 12.

[0045] The testing phase includes the circuit testing phase and the panel testing phase.

[0046] In at least one embodiment of this application, during the line detection stage, one test circuit 23 is used to transmit test signals, and another test circuit 23 is used to receive detection signals and determine whether the test signals and detection signals meet the line open circuit test conditions; when the test signals and detection signals meet the line open circuit test conditions, the test circuit 23 identifies that the detection line 12 is normal; when the test signals and detection signals do not meet the test conditions, the test circuit 23 identifies that the detection line 12 is open.

[0047] In other embodiments, during the circuit detection phase, two test circuits 23 simultaneously receive test signals, and at least one of the multiple drive units 221 provides test signals to the display panel 10B. Both test circuits 23 simultaneously receive detection signals on the detection line 12. When at least one of the two test circuits 23 identifies that the test signal and detection signal do not meet the circuit open circuit test conditions, the control circuit 24 identifies that the detection line 12 has an open circuit. That is, when one test circuit 23 identifies that the test signal and detection signal meet the conditions, and the other test circuit 23 identifies that the test signal and detection signal do not meet the circuit open circuit test conditions, the control circuit 24 identifies that the detection line 12 has an open circuit, and the open circuit exists on the side of the detection line 12 connected to the test circuit 23 whose test signal and detection signal do not meet the circuit open circuit test conditions. When both test circuits 23 simultaneously identify that the test signal and detection signal do not meet the circuit open circuit test conditions, the control circuit 24 identifies that the detection line 12 has an open circuit, and the open circuit exists at both ends of the detection line 12 or at the bottom of the detection line 12 away from the display drive device 20B.

[0048] In at least one embodiment of this application, during the panel testing stage, two test circuits 23 simultaneously receive test signals, and at least one of them receives a detection signal; the test circuit 23 that receives the detection signal determines whether the test signal and the detection signal meet the panel open-circuit test conditions. When the test signal and the detection signal meet the panel open-circuit test conditions, the test circuit 23 identifies that the data line Si corresponding to the current driving pin PS_i is normal; when the test signal and the detection signal do not meet the panel open-circuit test conditions, the test circuit 23 identifies that the data line Si corresponding to the current driving pin PS_i has a defect.

[0049] In other embodiments, the driving unit 221 can be divided into multiple driving groups. Each driving group includes the same number of driving units 221. During the panel detection stage, the source driving circuit 22 controls multiple driving pins PS_i~PS_(i+k) within the same driving group to simultaneously output test signals to the corresponding multiple data lines Si~S(i+k). The test circuit 23 receives the test signals and receives the detection signals on the detection line 12 through the detection pin PT_1. The test circuit 23 determines whether the test signals and detection signals meet the panel open circuit test conditions. When the test signals and detection signals meet the panel open circuit test conditions, the test circuit 23 identifies that the multiple data lines Si~S(i+k) corresponding to the multiple driving pins PS_i~PS_(i+k) are normal; when the test signals and detection signals do not meet the panel open circuit test conditions, the test circuit 23 identifies that the multiple data lines Si~S(i+k) corresponding to the multiple driving pins PS_i~PS_(i+k) are simultaneously open-circuited. When the difference between the test signal and the detection signal is greater than the preset value, it indicates that the corresponding multiple data lines Si~S(i+k) do not meet the panel open circuit detection conditions. At this time, the test circuit 23 identifies that there is an open circuit on the corresponding multiple data lines Si~S(i+k).

[0050] The aforementioned display device 100B has the same technical effects as display device 100A, and will not be described in detail here. In addition, display device 100B can also detect the integrity of the detection line 12.

[0051] Please see Figure 3 This is a schematic diagram of the display device 100C according to the third embodiment provided in this application. The structure of the display panel 10C is similar to... Figure 1 The structure of the display panel 10B in the second embodiment is basically the same, and the specific electrical connections will not be described in detail here. The main difference between the two is that the display panel 10C includes two detection lines 12A~12B. The display driving device 20C in the second embodiment has a similar structure to the display driving device 20B in the second embodiment. That is to say, the description of the display driving device 20B in the second embodiment can be basically applied to the display driving device 20C in the third embodiment. The main difference between the two is that the display driving device 20C includes four test circuits 23.

[0052] One detection line 12A is electrically connected to the odd-numbered data lines S1, S3, ..., Sn, and is used to transmit the detection signals generated on the odd-numbered data lines S1, S3, ..., Sn. The other detection line 12B is electrically connected to the even-numbered data lines S2, S4, ..., S(n-1), and is used to transmit the detection signals generated on the even-numbered data lines S2, S4, ..., S(n-1).

[0053] The four test circuits 23 are divided into two groups. Two test circuits 23 in one group are electrically connected to the same detection line 12A, and two test circuits 23 in the other group are electrically connected to another detection line 12A. At the same time, within the same group, one test circuit 23 is electrically connected to one end of the detection line 12B, and the other end is electrically connected to the other end of the detection line 12B.

[0054] The testing phase includes the circuit testing phase and the panel testing phase.

[0055] During the line testing phase, among the two test circuits 23 in the same group, one test circuit 23 is used to transmit test signals, and the other test circuit 23 is used to receive detection signals and determine whether the test signals and detection signals meet the line open circuit test conditions. When the test signals and detection signals meet the test conditions, the test circuit 23 identifies that the corresponding detection lines 12A and 12B are normal. When the test signals and detection signals do not meet the line open circuit test conditions, the test circuit 23 identifies that the corresponding detection lines 12A and 12B are open.

[0056] Specifically, during the line testing phase, open and short circuit conditions of test lines 12A and 12B can be detected. When the test circuit 23 connected to test line 12A and acting as the transmission end transmits a test signal, and the test circuit 23 connected to the second test line 12B and acting as the transmission end receives a floating signal, if the test circuit 23 connected to test line 12A and acting as the receiving end receives a test signal, but the test circuit 23 connected to test line 12B and acting as the receiving end does not receive a test signal, then the test circuit 23 connected to test line 12A and acting as the receiving end identifies that there is no short circuit between the two test lines 12A and 12B.

[0057] When the test circuit 23 connected to and acting as the receiver of detection line 12A receives a detection signal, and the test circuit 23 connected to and acting as the receiver of detection line 12B receives a detection signal, the test circuit 23 identifies a short circuit between the two detection lines 12A and 12B.

[0058] The test circuit 23, connected to the detection line 12A and serving as the receiving end, further determines whether the test signal and the detection signal meet the line open circuit test conditions. If the test signal and the detection signal meet the line open circuit test conditions, the test circuit 23 identifies that the detection line 12A is not open. If the test signal and the detection signal do not meet the line open circuit test conditions, the test circuit 23 identifies that the detection line 12A is open.

[0059] During the panel testing phase, two test circuits 23 within the same group simultaneously receive test signals, with at least one of them receiving a detection signal. The test circuit 23 receiving the detection signal determines whether the test signal and the detection signal meet the panel open-circuit test conditions. When the test signal and the detection signal meet the panel open-circuit test conditions, the test circuit 23 identifies that the data line Si corresponding to the current drive pin PS_i is normal; when the test signal and the detection signal do not meet the panel open-circuit test conditions, the test circuit 23 identifies that the data line Si corresponding to the current drive pin PS_i is open-circuited.

[0060] During the panel inspection stage, the specific nature of the defect can be determined as either an open circuit or a short circuit. Specifically, multiple drive units 221 output test signals to the corresponding data lines S1~Sn in a time-division manner. When the i-th drive unit 221 provides a test signal to the i-th data line Si, and the adjacent drive unit 221 does not provide a test signal to the (i+1)-th data line S(i+1), where i is an odd number, the detection line 12A electrically connected to the i-th data line Si provides a detection signal to a set of test circuits 23, and the detection line 12B electrically connected to the (i+1)-th data line S(i+1) provides a detection signal to the set of test circuits 23. If the set of test circuits 23 receiving the detection signal from detection line 12A all identify that the test signal and the detection signal do not meet the panel open circuit test conditions, and the set of test circuits 23 receiving the detection signal from detection line 12B also identify that the test signal and the detection signal do not meet the panel open circuit test conditions, then an open circuit defect is identified as existing in the i-th data line Si.

[0061] by Figure 11 For example, when the source drive circuit 22 controls the first drive pin PS_1 to output a square wave signal and the second drive pin PS_2 to output a floating signal, the detection signals on the detection lines 12 corresponding to the detection pins PT_10 and PT_11 are square wave signals, and the detection signals on the detection lines 12 corresponding to the detection pins PT_20 and PT_21 are floating signals. Then, the test signal and the detection signal meet the panel open circuit test conditions, and there is no open circuit with the data line S1 corresponding to the first drive pin PS_1. Similarly, when the source drive circuit 22 controls the second drive pin PS_1 to output a square wave signal and the third drive pin PS_3 to output a floating signal, the detection signals on the detection lines 12 corresponding to the detection pins PT_10 and PT_11 are square wave signals, and the detection signals on the detection lines 12 corresponding to the detection pins PT_20 and PT_21 are floating signals. Then, the test signal and the detection signal meet the panel open circuit test conditions, and there is no open circuit with the data line S2 corresponding to the second drive pin PS_2. The testing process for other data lines S3~Sn by test circuit 23 is similar and will not be described in detail here.

[0062] When the source drive circuit 22 controls the first drive pin PS_1 to output a square wave signal and the second drive pin PS_2 to output a floating signal, if the detection signals on the detection lines 12 corresponding to the detection pins PT_10, PT_11, PT_20 and PT_21 are all floating signals, then the identification test signal and the detection signal do not meet the panel open circuit test conditions, and there is an open circuit with the data line S1 corresponding to the first drive pin PS_1.

[0063] During short-circuit detection, the display driver 20C sets up a test circuit 23 connected to the first detection line 12A to receive a test signal, and sets up a test circuit connected to the second detection line 12B to receive a floating signal. The display driver 20C determines whether at least two test circuits 23 electrically connected to the two detection lines have both received a detection signal. If at least two test circuits 23 electrically connected to the two detection lines have both received a detection signal, the display driver 20C identifies a short circuit between the current data line Si and its adjacent data line S(i-1) or S(i+1). If at least two test circuits 23 electrically connected to only one detection line 12A or 12B have received a detection signal, the display driver 20C identifies no short circuit between the current data line Si and its adjacent data line S(i-1) or S(i+1).

[0064] by Figure 12 For example, when the source drive circuit 22 controls the first drive pin PS_1 to output a square wave signal and the second drive pin PS_2 to output a floating signal, if the detection signals received by the detection pins PT_10, PT_11, PT_20 and PT_21 are square wave signals, then the identification test signal and the detection signal do not meet the test conditions, and there is a short circuit between the data line S1 corresponding to the first drive pin PS_1 and the data line S2 corresponding to the second drive pin PS_2.

[0065] The aforementioned display device 100C has the same technical effects as the display device 100C, and will not be described in detail here. In addition, the display device 100C can also determine whether the defect is an open circuit or a short circuit, thereby further improving the accuracy of the detection results.

[0066] Please see Figure 4 This is a schematic diagram of the display device 100D according to the fourth embodiment provided in this application. The structure of the display panel 10D is similar to... Figure 3The structure of the display panel 10C in the third embodiment is basically the same, and the specific electrical connections will not be described in detail here. The main difference between the two is that the display panel 10D includes two control lines 13A to 13B. The display driving device 20D in the fourth embodiment is basically the same as the display driving device 20C in the third embodiment. That is to say, the description of the display driving device 20C in the third embodiment can be basically applied to the display driving device 20D in the fourth embodiment.

[0067] Multiple switching elements T1~Tn are divided into odd-numbered switch groups and even-numbered switch groups according to their arrangement order. In the odd-numbered switch group, an odd number of switching elements T1, T3, ..., Tn correspond to an odd number of data lines S1, S3, ..., Sn, and the control terminals of the odd-numbered switching elements T1, T3, ..., Tn are electrically connected to control line 13A. Control line 13A is used to control the conduction and cutoff of the odd-numbered switching elements T1, T3, ..., Tn. In the even-numbered switch group, an even number of switching elements T2, T4, ..., T(n-1) correspond to an even number of data lines S2, S4, ..., S(n-1), and the control terminals of the even-numbered switching elements T2, T4, ..., T(n-1) are electrically connected to control line 13B. Control line 13B is used to control the conduction and cutoff of the even-numbered switching elements T2, T4, ..., T(n-1).

[0068] When a test signal is received on any one of the odd-numbered data lines S1, S3, ..., Sn, the control line 13B corresponding to the even-numbered data lines S2, S4, ..., S(n-1) can control the corresponding even-numbered switching elements T2, T4, ..., T(n-1) to be in the off state. Conversely, when a test signal is received on any one of the even-numbered data lines S2, S4, ..., S(n-1), the control line 13A corresponding to the odd-numbered data lines S1, S3, ..., Sn can control the corresponding odd-numbered switching elements T1, T3, ..., Tn to be in the off state.

[0069] In addition, during short-circuit detection, the two control lines 13A~13B can simultaneously control all switching elements T1~Tn to be in the on state at the same time.

[0070] The aforementioned display device 100D has the same technical effect as display device 100C, and will not be described in detail here. Furthermore, display device 100D divides the switching elements T1~Tn into odd and even arrays, and adjusts the number of switches in the on state among the switching elements T1~Tn according to the detection purpose, reducing the impact of the switching elements T1~Tn on panel defects, thereby further improving the accuracy of the detection results.

[0071] Please see Figure 5This is a schematic diagram of the display device 100E according to the fifth embodiment of this application. The display device 100E includes a display panel 10E and a plurality of display driving devices 20E. The structure of the display panel 10E is basically the same as that of the display panels 10A-10B in the first and second embodiments, and the specific electrical connections are not described here. In other embodiments, the structure of the display panel 10E may also adopt the structure of the display panels 10C-10D in the third and fourth embodiments. The structure of the display driving device 20E and the description of the display driving devices 20A-20D in the first to fourth embodiments are basically applicable to the display driving device 20E of the fifth embodiment. The main difference is that only at least one test circuit 23 of the two display driving devices 20E located at opposite edges is electrically connected to the detection line 12.

[0072] When multiple display driving devices 20E all adopt the display driving device 20A of the first embodiment, the test circuit 23 in the two display driving devices 20E located at opposite edges is electrically connected to the two opposite ends of the detection line 12.

[0073] When multiple display driving devices 20E all employ the display driving device 20B of the second embodiment, at least one test circuit 23 in two display driving devices 20E located at opposite edges is electrically connected to the two opposite ends of the detection line 12. That is, the left-side test circuit 23 in the left-side display driving device 20E can be electrically connected to the left end of the detection line 12 simultaneously, and the right-side test circuit 23 in the right-side display driving device 20E can be electrically connected to the right end of the detection line 12.

[0074] When multiple display driving devices 20E all adopt the display driving device 20C of the third embodiment, one or two test circuits 23 located on the left side of the display driving device 20E are electrically connected to the left end of the detection line 12, and the display driving device 20E located on the left side is electrically connected to the left end of one control line 13. One or two test circuits 23 located on the right side of the display driving device 20E are electrically connected to the right end of the detection line 12, and the display driving device 20E located on the right side is simultaneously electrically connected to the right ends of two control lines 13.

[0075] When multiple display driving devices 20E all employ the display driving device 20D of the fourth embodiment, one or two test circuits 23 located on the left side of the display driving device 20E are electrically connected to the left end of the detection line 12, and the display driving device 20E located on the left side is also electrically connected to the left end of both control lines 13. Similarly, one or two test circuits 23 located on the right side of the display driving device 20E are electrically connected to the right end of the detection line 12, and the display driving device 20E located on the right side is also electrically connected to the right end of both control lines 13.

[0076] The aforementioned display device 100E has the same technical effects as display devices 100A to 100D, and will not be described in detail here. Furthermore, in display device 100E, the display panel 10E is divided into sections and electrically connected to different display driving devices 20E, allowing for section-based testing of the display panel 10E. During testing, only the test circuits 23 located in the display driving devices 20E on the left and right sides are used to detect defects in the display panel 10E, ensuring the completeness of the testing while reducing operational difficulty.

[0077] Please see Figure 6 This is a schematic diagram of the test circuit 23A according to the first embodiment of this application. The test circuit 23A includes a comparison unit 231. The comparison unit 231 receives a first enable signal En1, a test signal Stest, and a detection signal Sdet output by the control circuit 24. The comparison unit 231 further outputs an indication signal In to the control circuit 24. When the first enable signal En1 is at a first level, the comparison unit 231 is in the detection phase. The comparison unit 231 compares whether the test signal Stest and the detection signal Sdet meet the test conditions. If the test signal Stest and the detection signal Sdet meet the test conditions, the comparison unit 231 outputs an indication signal In at the first level; if the test signal Stest and the detection signal Sdet do not meet the test conditions, the comparison unit 231 outputs an indication signal In at the second level. When the first enable signal En1 is at the second level, the comparison unit 231 stops working.

[0078] Please see Figure 7 This is a schematic diagram of the test circuit 23B according to the second embodiment provided in this application. The structure of the test circuit 23B is similar to... Figure 6The test circuit 23A in the first embodiment shown has a basically the same structure, and the specific electrical connections will not be described in detail here. The main difference between the two is that the test circuit 23B further includes a transmission unit 232. The transmission unit 232 receives the first enable signal En1, the test signal Stest, and the detection signal Sdet output by the control circuit 24, and the transmission unit 232 further outputs an indication signal In to the control circuit 24. During the line detection stage, only one of the comparison unit 231 and the transmission unit 232 in the test circuit 23B works. That is, during the line detection stage, in the same test circuit 23B, when the comparison unit 231 is working, the transmission unit 232 stops working; when the comparison unit 231 stops working, the transmission unit 232 works. When the comparison unit 231 is working, it is used to receive the detection signal Sdet on the detection line 12. When the transmission unit 232 is working, it outputs the received test signal Stest and provides it to the detection line 12 through the terminal.

[0079] The test circuit 23B described above can reduce costs by using different modules to perform the comparison and transmission functions of the test circuit 23B.

[0080] Please see Figure 13 , Figure 13 This is a schematic flowchart illustrating a panel defect detection method provided in this application. The panel defect detection method can be applied to display devices 100C~100E. Display devices 100C~100E may include, for example... Figures 3 to 7 The diagram shows more or fewer hardware components, or different component arrangements. It is understood that the implementation of the panel defect detection method is not limited to applications... Figures 4 to 7 The display devices 100C~100E shown are for illustrative purposes only. The panel defect detection method includes the following steps: In step S11, during the detection phase, the display driver 20C~20E controls multiple driver pins PS_1~PS_n to output test signals to the corresponding data lines S1~Sn in a time-division manner.

[0081] In step S12, at least one switching circuit 11 outputs at least one detection signal to the display driving device 20D~20E.

[0082] Step S13: Display drive devices 20C~20E determine whether the test signal and detection signal meet the test conditions.

[0083] Step S14: When the test signal and detection signal meet the test conditions, the display driving device 20C~20E confirms that the display panel 10C~10E has no defects.

[0084] Step S15: When the test signal and detection signal do not meet the test conditions, the display driving device 20C~20E confirms that the display panel 10C~10E has a defect.

[0085] The above-mentioned panel defect detection method uses the existing source drive circuit 22 to transmit test signals. The test circuit 23 identifies whether there are defects in the data lines S1 to Sn in the display panels 10C to 10E based on the test signals and the detection signals provided by the detection lines 12 in the display panels 10D to 10E, which can reduce the detection cost in the panel defect detection process.

[0086] Please refer to the following: Figure 14 This is a detailed flowchart of step S13. The testing phase includes the circuit testing phase and the panel testing phase.

[0087] In step S131, during the line detection stage, a test circuit 23 is set up to transmit test signals, and another test circuit 23 is set up to receive detection signals.

[0088] Step S132: Determine whether the test signal and the detection signal meet the test conditions.

[0089] Step S133: When the test signal and detection signal meet the test conditions, the display drive device 20C~20E confirms that there are no defects in the detection line 12.

[0090] Step S134: When the test signal and detection signal do not meet the test conditions, the display drive device 20C~20E confirms that the detection line 12 has a defect.

[0091] In at least one embodiment of this application, in the display driver device 20C structure, i.e., when only one detection line 12 exists, the display driver device 20C can only detect open circuit conditions. In the display driver devices 20D~20E structures, i.e., when two detection lines exist, the display driver devices 20D~20E can detect both open circuit and short circuit conditions of detection lines 12A and 12B. When the test circuit 23 connected to detection line 12A and serving as the transmission end transmits a test signal, and the test circuit 23 connected to the second detection line 12B and serving as the transmission end receives a floating signal, if the test circuit 23 connected to detection line 12A and serving as the receiving end receives a detection signal, but the test circuit 23 connected to detection line 12B and serving as the receiving end does not receive a detection signal, then the test circuit 23 connected to detection line 12A and serving as the receiving end identifies that there is no short circuit between the two detection lines 12A and 12B.

[0092] When the test circuit 23 connected to and serving as the receiving end of detection line 12A receives a detection signal, and the test circuit 23 connected to and serving as the receiving end of detection line 12B receives a detection signal, the test circuit 23 identifies a short circuit between the two detection lines.

[0093] The test circuit 23, which is connected to the detection line 12A and serves as the receiving end, further determines whether the test signal and the detection signal meet the test conditions. If the test signal and the detection signal meet the test conditions, the test circuit 23 identifies that there is no open circuit in the detection line 12A. If the test signal and the detection signal do not meet the test conditions, the test circuit 23 identifies that there is an open circuit in the detection line 12A.

[0094] In step S135, during the panel detection stage, the source drive circuit 22 controls multiple drive pins PS_1~PS_n to output test signals to the display panels 10D~10E in a time-division manner.

[0095] In at least one embodiment of this application, the source drive circuit 22 controls multiple drive pins PS_1 to PS_n to output test signals to the display panels 10D to 10E in a time-division manner.

[0096] In other embodiments, the multiple driving units 221 can be divided into multiple driving groups. Each driving group includes the same number of driving units 221. During the panel detection stage, the source driving circuit 22 controls multiple driving pins PS_i~PS_(i+k) in the same driving group to simultaneously output test signals to the corresponding multiple data lines Si~S(i+k).

[0097] Step S136: Determine whether the test signal and the detection signal meet the test conditions.

[0098] Step S137: When the test signal and detection signal meet the test conditions, the display drive device 20D~20E confirms that there are no defects in the data lines S1~Sn.

[0099] Step S138: When the test signal and detection signal do not meet the test conditions, the display drive device 20D~20E confirms that the data lines S1~Sn have defects.

[0100] In at least one embodiment of this application, the source drive circuit 22 outputs test signals to the corresponding data lines S1~Sn in a time-division manner. When the i-th drive unit 221 provides a test signal to the i-th data line Si, and the adjacent (i+1)-th data line S(i+1) does not receive a test signal, the detection line 12A electrically connected to the i-th data line Si provides a detection signal to a set of test circuits 23, and the detection line 12B electrically connected to the (i+1)-th data line S(i+1) provides a detection signal to the set of test circuits 23. When all test circuits 23 receiving the detection signal on detection line 12A identify that the test signal and the detection signal do not meet the test conditions, and when all test circuits 23 receiving the detection signal on detection line 12B identify that the test signal and the detection signal do not meet the test conditions, then an open circuit defect is identified between the i-th data line Si.

[0101] For example, when the source drive circuit 22 controls the first drive pin PS_1 to output a square wave signal and the second drive pin PS_2 to output a floating signal, if the detection signals on the detection lines 12 corresponding to the detection pins PT_10, PT_11, PT_20 and PT_21 are all floating signals, then the identification test signal and the detection signal do not meet the open circuit test conditions, and there is an open circuit with the data line S1 corresponding to the first drive pin PS_1.

[0102] Please refer to the following: Figure 15 Before step S131, the panel defect detection method further includes the following steps: Step S1310: Set up a test circuit 23 connected to the first detection line 12A and serving as a transmission end to transmit test signals, and set up a test circuit 23 connected to the second detection line 12B and serving as a transmission end to receive floating signals.

[0103] Step S1311: Determine whether both test circuits 23, which are the receiving ends, have received the detection signal.

[0104] In step S1312, when both test circuits 23, which serve as receivers, receive the detection signal, a short circuit is identified between the two detection lines 12.

[0105] In step S1313, if only one of the two test circuits 23 that serve as the receiving end receives the detection signal, it is identified that there is no short circuit between the two detection lines 12.

[0106] Please refer to the following: Figure 16 Before step S134, the panel defect detection method further includes the following steps: In step S1340, a test circuit 23 connected to the first detection line 12A is configured to receive test signals, and a test circuit connected to the second detection line 12B is configured to receive floating signals.

[0107] Step S1341: Determine whether at least two test circuits 23 electrically connected to the two detection lines have received detection signals.

[0108] In step S1342, when at least two test circuits 23 electrically connected to the two detection lines receive the detection signal, there is a short circuit between the current data line Si and its adjacent data line S(i-1) or S(i+1).

[0109] In step S1343, when at least two test circuits 23 electrically connected to only one detection line 12A or 12B receive a detection signal, there is no short circuit between the current data line Si and its adjacent data line S(i-1) or S(i+1).

[0110] For example, when the source drive circuit 22 controls the first drive pin PS_1 to output a square wave signal and the second drive pin PS_2 to output a floating signal, if the detection signals received by the detection pins PT_10, PT_11, PT_20 and PT_21 are square wave signals, then a short circuit is identified between the data line S1 corresponding to the first drive pin PS_1 and the data line S2 corresponding to the second drive pin PS_2.

[0111] Simultaneously, the panel defect detection method can also inspect the integrity of the detection line 12. Furthermore, the method can determine whether the defect is an open circuit or a short circuit, thereby further improving the accuracy of the detection results.

[0112] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment, depending on actual needs.

[0113] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0114] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices described in the specification may also be implemented by a single unit or device through software or hardware. Terms such as "first," "second," etc., are used to indicate names and do not indicate any specific order.

[0115] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, any appropriate changes and variations made to the above embodiments within the essential spirit and scope of this application should fall within the scope of protection claimed by this application.

Claims

1. A display driving apparatus electrically connected with a display panel; the display panel comprises a plurality of data lines arranged in a display area and at least one switching circuit, at least one control line and at least one detection line arranged in a non-display area; the display driving apparatus comprises a plurality of driving pins and at least two test pins; each of the driving pins is electrically connected with the switching circuit through one of the data lines; characterized in that, The test pin is electrically connected with at least one end of the detection line; the display driving device further comprises: a test signal generating circuit for generating a test signal in a panel detection stage; a source driving circuit electrically connected with the test signal generating circuit and electrically connected with the switch circuit through a plurality of driving pins and corresponding data lines; the source driving circuit is configured to provide the test signal to the switch circuit through at least one driving pin in the panel detection stage in time, and the switch circuit is configured to generate a detection signal according to the test signal when turned on under the control of the control line; and at least one test circuit; each test circuit is electrically connected with the test signal generating circuit and electrically connected with one end of the detection line through a corresponding test pin; the test circuit is configured to receive the test signal and receive the detection signal on the detection line through the test pin in the panel detection stage, and determine whether the test signal and the detection signal meet a test condition.

2. The display driving apparatus according to claim 1, wherein The display driving device comprises two test circuits; the two test circuits are oppositely arranged on both sides of the source driving circuit; one of the test circuits is electrically connected with one end of the detection line, and the other test circuit is electrically connected with the other end of the detection line.

3. The display driving device according to claim 2, wherein The detection stage comprises a line detection stage; the test condition comprises a detection line open circuit test condition; in the line detection stage, one of the test circuits is configured to transmit the test signal, and the other test circuit is configured to receive the detection signal and determine whether the test signal and the detection signal meet the detection line open circuit test condition.

4. The display driving apparatus according to claim 1, wherein A plurality of driving pins are divided into a plurality of pin groups; each pin group comprises at least two adjacent driving pins; in the panel detection stage, the source driving circuit controls different pin groups to output the test signal to the display panel in time; at any time, the driving pins in the same pin group simultaneously output the test signal to the display panel.

5. The display driving apparatus according to claim 1, wherein The display driving device comprises four control pins; the control pins are divided into a first control group and a second control group; the switch circuit comprises a plurality of switch elements; the plurality of switch elements are divided into an odd switch group and an even switch group according to the arrangement order; the control pins in the first control group are electrically connected with the control ends of each switch element in the odd switch group; the control pins in the second control group are electrically connected with the control ends of each switch element in the even switch group; when the source driving circuit outputs the test signal through the driving pins in the odd pin group in time, the switch elements in the odd switch group are in the on state, and when the source driving circuit outputs the test signal through the driving pins in the even pin group, the switch elements in the even switch group are in the on state.

6. The display driving apparatus according to claim 1, wherein The display panel comprises two detection lines; the display driving device comprises four test circuits; wherein, two test circuits connected to two ends of the same detection line are located on two sides of the source driving circuit; the driving pins are divided into odd pin group and even pin group; the driving pins in the odd pin group provide the test signal to the display panel in time; two test circuits connected to the same detection line receive the detection signal generated by the odd data line according to the test signal; the driving pins in the even pin group provide the test signal to the display panel in time; two test circuits connected to the same detection line receive the detection signal generated by the even data line according to the test signal.

7. The display driving device according to claim 6, wherein The detection stage comprises a line detection stage; in the line detection stage, one test circuit is used as a transmission end and the other test circuit is used as a receiving end to determine whether the test signal and the detection signal meet the test condition.

8. The display driving apparatus according to claim 6, wherein The display driving device comprises four control pins; the control pins are divided into first control group and second control group; the switch circuit comprises a plurality of switch elements; a plurality of switch elements are divided into odd switch group and even switch group according to the arrangement order; the control pins in the first control group are electrically connected to the control end of each switch element in the odd switch group; the control pins in the second control group are electrically connected to the control end of each switch element in the even switch group; when the source driving circuit outputs the test signal through the driving pins in the odd pin group, a plurality of switch elements in the odd switch group are in the on state; when the source driving circuit outputs the test signal through the driving pins in the even pin group, a plurality of switch elements in the even switch group are in the on state.

9. The display driving apparatus according to claim 6, wherein A plurality of driving pins are divided into a plurality of pin groups; each pin group comprises at least two adjacent driving pins; in the detection stage, the source driving circuit controls the driving pins in the same pin group to output the test signal to the display panel at the same time.

10. A display device comprising a display panel and at least one display driving apparatus; the display panel comprising a plurality of data lines arranged in a display area and at least one switching circuit, at least one control line and at least one detection line arranged in a non-display area; characterized in that, The display driving device adopts the display driving device of any one of claims 1 to 9.

11. The display device of claim 10, wherein, Wherein, Two ends of the detection line are connected to the display driving device located on two sides of the display device; in the detection stage, the display driving device connected to the detection line.

12. A panel defect detection method applied to a display device; the display device comprising a display panel and a display driving apparatus; the display panel comprising a plurality of data lines arranged in a display area and at least one switching circuit, at least one control line and at least one detection line arranged in a non-display area; the display driving apparatus comprising a plurality of driving pins and at least two test pins; each of the driving pins is electrically connected to the switching circuit through one of the data lines, and each of the test pins is electrically connected to the switching circuit. The test pin is electrically connected to at least one end of the detection line; characterized in that, The panel defect detection method comprises: In the detection stage, the display driving device outputs the test signal to the corresponding data line through a plurality of driving pins in time; The at least one switch circuit outputs at least one detection signal to the display driving device; The display driving device judges whether the test signal and the detection signal meet the test condition; The display driving device confirms that the display panel has no defect when the test signal and the detection signal satisfy a test condition; and The display driving device confirms that the display panel has a defect when the test signal and the detection signal do not satisfy the test condition.

13. The panel defect detection method of claim 12, wherein, The detection stage includes a line detection stage; and the display driving device includes a source driving circuit and two test circuits; The two test circuits are respectively arranged on two sides of the source driving circuit and are electrically connected to two ends of the same detection line. The panel defect detection method includes: In the line detection stage, one of the test circuits is arranged to transmit the test signal, and another test circuit electrically connected to the same detection line is arranged to receive the detection signal; It is judged whether the test signal and the detection signal satisfy a line open circuit test condition; The test circuit identifies that the detection line is normal when the test signal and the detection signal satisfy the line open circuit test condition; and 14. The panel defect detection method of claim 13, wherein, The test circuit identifies that the detection line has an open circuit when the test signal and the detection signal do not satisfy the line open circuit test condition. The detection stage includes a panel detection stage; and the panel defect detection method further includes: In the panel detection stage, the source driving circuit controls a plurality of driving pins to output the test signal to the display panel in time division; It is judged whether the test signal and the detection signal satisfy a panel open circuit test condition; The test circuit identifies that the data line corresponding to the current driving pin is normal when the test signal and the detection signal satisfy the panel open circuit test condition; and 15. The panel defect detection method of claim 13, wherein, The test circuit identifies that the data line corresponding to the current driving pin has an open circuit when the test signal and the detection signal do not satisfy the panel open circuit test condition. The display panel includes two detection lines; and before the test circuit transmitting the test signal and the test circuit receiving the detection signal are arranged, the panel defect detection method further includes: The test circuit connected to the first detection line and serving as the transmission end transmits the test signal, and the test circuit connected to the second detection line and serving as the transmission end receives a floating signal; It is judged whether both of the test circuits serving as the receiving end receive the detection signal; When both of the test circuits serving as the receiving end receive the detection signal, it is identified that there is a short circuit between the two detection lines; and 16. The panel defect detection method of claim 14, wherein, When only one of the test circuits serving as the receiving end receives the detection signal, it is identified that there is no short circuit between the two detection lines. The display panel includes two detection lines; and before the test circuit transmitting the test signal and the test circuit receiving the detection signal are arranged, the panel defect detection method further includes: The test circuit connected to the first detection line receives the test signal, and the test circuit connected to the second detection line receives a floating signal; determining whether at least two of the test circuits electrically connected to the two detection lines both receive the detection signal; when at least two of the test circuits electrically connected to the two detection lines both receive the detection signal, it is identified that there is a short circuit between the current data line and the data line adjacent thereto; and when only at least one of the test circuits electrically connected to one of the detection lines receives the detection signal, it is identified that there is no short circuit between the current data line and the data line adjacent thereto.

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