An intelligent compensation driving circuit and an intelligent compensation driving method

Abstract

The application discloses an intelligent compensation driving circuit and an intelligent compensation driving method. The circuit comprises a driving circuit, a delay circuit, a voltage sampling circuit, a result register and a plurality of comparators, a driving compensation circuit for increasing the driving current of the driving circuit, a control logic circuit for determining a target slope and a plurality of reference voltages, and a driving external power tube. The voltage sampling circuit samples the gate high-level driving signal, inputs the plurality of reference voltages to a plurality of second input ends, controls the delay circuit to generate equal interval delay pulses, sequentially opens the plurality of comparators to quantize the gate high-level driving signal to obtain a quantization result, determines the time interval of the Miller platform according to the quantization result, drives the driving circuit, controls the driving compensation circuit to be opened in the time interval, drives the external power tube, and completes the slope and the Miller platform correction. The application can dynamically adjust the slope, timely correct the Miller platform, and reduce the switching loss.

Description

Technical Field

[0001] This application relates to the technical field of power drive circuits, and in particular to an intelligent compensation drive circuit and an intelligent compensation drive method. Background Technology

[0002] In the era of the new energy boom, drive circuits are ubiquitous, but due to factors such as circuit structure, the switching losses of power transistors account for an increasingly large proportion of current power circuits.

[0003] In power drive circuits, there are two main types of losses: (1) The slope is not as expected. If the slope is too low, the power drive switching will be too slow, resulting in significant switching losses. (2) Miller plateau. The Miller plateau in the drive amplifier circuit is particularly noticeable in power drives, and the switching losses caused by the Miller plateau are very large.

[0004] The existing power drive compensation circuits are fixed compensation circuits and can only correct the slope, but cannot take into account the Miller platform. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes an intelligent compensation drive circuit that can dynamically adjust the slope and correct it in a timely manner when the Miller plateau occurs, thereby reducing the switching losses of the power transistor.

[0006] This application also provides an intelligent compensation driving method and a power driving circuit.

[0007] According to a first aspect embodiment of the present application, an intelligent compensation driving circuit is applied to a power driving circuit, the power driving circuit having an external power transistor, the intelligent compensation driving circuit comprising:

[0008] A driving circuit is used to output a gate high-level driving signal to the gate of the external power transistor;

[0009] The drive feedback circuit includes a delay circuit, a voltage sampling circuit, a result register, and multiple comparators. The delay circuit includes a delay signal input terminal and multiple delay control terminals. Each comparator includes a first input terminal, a second input terminal, a control terminal, and a comparison output terminal. The input terminal of the voltage sampling circuit is connected to the gate of the external power transistor, and its output terminal is connected to multiple first input terminals. The multiple control terminals are connected one-to-one with the multiple delay control terminals, and the multiple comparison output terminals are all connected to the result register. The delay circuit generates an equally spaced delay pulse to sequentially enable the multiple comparators to quantize the gate high-level drive signal, obtaining a quantization result. The interval time of the equally spaced delay pulse is the target delay, and the quantization result is stored in the result register.

[0010] A drive compensation circuit is used to output a compensation current to the drive circuit to increase the drive current of the drive circuit.

[0011] A control logic circuit is connected to the delay signal input terminal, the driving circuit, and the driving compensation circuit, respectively. The control logic circuit is used to acquire the shutdown voltage, the on-hold voltage, the target delay, and the total number of sampling points of the external power transistor; determine the target slope and multiple reference voltages based on the shutdown voltage, the on-hold voltage, the target delay, and the total number of sampling points, where each reference voltage represents a standard voltage value corresponding to a sampling point under the target slope; output a PWM signal to drive the driving circuit to generate a gate high-level driving signal to drive the external power transistor; control the voltage sampling circuit to sample the gate high-level driving signal, input multiple reference voltages to multiple second input terminals one-to-one, control the delay circuit to generate an equally spaced delay pulse, and read the quantization result from the result register; determine the Miller plateau time interval based on the quantization result; output a PWM signal to drive the driving circuit, and control the driving compensation circuit to turn on within the time interval to generate a compensation driving signal to drive the external power transistor until the quantization result characterizes the slope and Miller plateau correction.

[0012] The intelligent compensation driving circuit according to the embodiments of this application has at least the following beneficial effects:

[0013] This application embodiment quantizes the gate high-level drive signal into multiple points using a drive feedback circuit. The time interval of the Miller plateau can be determined based on the number of consecutive 0s or 1s in the quantization result. When the drive circuit is turned on again, the control logic circuit controls the drive compensation circuit to increase the drive current at the beginning of the Miller plateau time interval. At the end of the time interval, the drive compensation circuit is turned off, and sampling is performed again. This process is repeated until all quantization results are either all 1s or all 0s, at which point the slope and Miller plateau correction are complete. The intelligent compensation drive circuit of this application embodiment can dynamically adjust the slope and correct for Miller plateaus in a timely manner, thereby reducing the switching losses of the power transistor.

[0014] According to some embodiments of this application, the delay circuit adopts a delay chain structure in which multiple delay units are connected in series. The input end of the delay chain structure is connected to the control logic circuit, and the output ends of the multiple delay units are connected to the multiple control ends one by one. The delay time of each delay unit is the target delay.

[0015] According to some embodiments of this application, the drive compensation circuit adopts a series structure of multiple current sources connected in series, the output terminal of the series structure is connected to the output terminal of the drive circuit, and each current source is connected to the control logic circuit.

[0016] According to some embodiments of this application, the voltage sampling circuit employs a voltage follower.

[0017] According to some embodiments of this application, the driving circuit includes:

[0018] A level shifting circuit, the input of which is connected to the control logic circuit;

[0019] The gate drive circuit has its input terminal connected to the output terminal of the level transfer circuit, and its output terminal connected to the gate of the external power transistor.

[0020] The intelligent compensation driving method according to a second aspect embodiment of this application is applied to the intelligent compensation driving circuit as described in the first aspect embodiment above, the intelligent compensation driving method comprising:

[0021] Obtain the shutdown voltage, on-hold voltage, target delay, and total number of sampling points of the external power transistor;

[0022] The target slope and multiple reference voltages are determined based on the shutdown voltage, the on-up sustaining voltage, the target delay, and the total number of sampling points. The reference voltages characterize the standard voltage values ​​corresponding to the sampling points under the target slope.

[0023] The output PWM signal drives the drive circuit to generate a gate high-level drive signal to drive the external power transistor;

[0024] The voltage sampling circuit is controlled to sample the gate high-level drive signal, and multiple reference voltages are input to multiple second input terminals one by one. The delay circuit is controlled to generate an equally spaced delay pulse, and the quantization result in the result register is read.

[0025] The time interval of the Miller platform is determined based on the quantization results;

[0026] The output PWM signal drives the drive circuit, and controls the drive compensation circuit to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizes the slope and Miller plateau correction is completed.

[0027] The intelligent compensation driving method according to the embodiments of this application has at least the following beneficial effects:

[0028] This application embodiment quantizes the gate high-level drive signal into multiple points using a drive feedback circuit. The time interval of the Miller plateau can be determined based on the number of consecutive 0s or 1s in the quantization result. When the drive circuit is turned on again, the control logic circuit controls the drive compensation circuit to increase the drive current at the beginning of the Miller plateau time interval. At the end of the time interval, the drive compensation circuit is turned off, and sampling is performed again. This process is repeated until all quantization results are either all 1s or all 0s, at which point the slope and Miller plateau correction are complete. The intelligent compensation drive method of this application embodiment can dynamically adjust the slope and correct it promptly when the Miller plateau occurs, thereby reducing the switching losses of the power transistor.

[0029] According to some embodiments of this application, the quantization result includes a plurality of quantized values ​​arranged in sequence, the number of quantized values ​​being equal to the number of comparators, and determining the time interval of the Miller platform based on the quantization result includes:

[0030] The states of each quantization value are determined sequentially. The states of the quantization values ​​include a first state and a second state. The first state indicates that the actual driving voltage is higher than the reference voltage, and the second state indicates that the actual driving voltage is lower than the reference voltage. The actual driving voltage indicates the quantization voltage value of the gate high-level driving signal corresponding to the sampling point.

[0031] The time interval is defined as the interval between consecutive sampling points in the second state.

[0032] According to some embodiments of this application, the drive compensation circuit adopts a series structure of multiple current sources connected in series, the output terminal of the series structure is connected to the output terminal of the drive circuit, and each current source is connected to the control logic circuit.

[0033] The output PWM signal drives the drive circuit and controls the drive compensation circuit to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizing the slope and Miller plateau correction is completed, including:

[0034] The output PWM signal drives the drive circuit, and controls the activation of one current source within the time interval to generate a compensation drive signal to drive the external power transistor.

[0035] The voltage sampling circuit is controlled to sample the compensation drive signal, and multiple reference voltages are input to multiple second input terminals one by one. The delay circuit is controlled to generate an equally spaced delay pulse, and the quantization result in the result register is read.

[0036] The time interval of the Miller platform is determined based on the quantization results;

[0037] The output PWM signal drives the drive circuit, and within the time interval, controls the addition of one current source to generate a compensation drive signal to drive the external power transistor until all the quantization values ​​of the quantization result are in the first state.

[0038] According to some embodiments of this application, the output PWM signal drives the drive circuit and controls the drive compensation circuit to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizing the slope and Miller plateau correction is completed, including:

[0039] The output PWM signal drives the drive circuit, and controls the drive compensation circuit to be turned on within the target interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizes the slope and Miller plateau correction is completed. The target interval is within the time interval, and the length of the target interval is less than the length of the time interval.

[0040] According to some embodiments of this application, the constraint formula for the target slope is:

[0041] ;

[0042] ;

[0043] in, The target slope, The on-state sustaining voltage, The shut-off voltage, The total number of sampling points, Delay the target;

[0044] The constraint formula for the reference voltage is:

[0045] ;

[0046] in, For the first The reference voltage corresponding to each sampling point The shut-off voltage, The on-state sustaining voltage, The total number of sampling points.

[0047] The power drive circuit according to a third aspect embodiment of this application includes the intelligent compensation drive circuit described in the first aspect embodiment. Since the power drive circuit employs all the technical solutions of the intelligent compensation drive circuit of the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0048] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0049] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0050] Figure 1 This is an electrical schematic diagram of the MOS parasitic capacitance of a power drive circuit according to an embodiment of this application;

[0051] Figure 2 This is an electrical schematic diagram of an embodiment of the intelligent compensation drive circuit of this application;

[0052] Figure 3 This is an electrical schematic diagram of a drive feedback circuit according to an embodiment of this application;

[0053] Figure 4 This is an electrical schematic diagram of a gate driving circuit and a driving compensation circuit according to an embodiment of this application;

[0054] Figure 5 This is a quantitative schematic diagram of a drive feedback circuit according to an embodiment of this application;

[0055] Figure 6 This is a waveform diagram of the drive signal of the external power transistor before modification according to an embodiment of this application;

[0056] Figure 7 This is a modified drive signal waveform diagram of an embodiment of the present application for an external power transistor;

[0057] Figure 8 This is a flowchart of an embodiment of the intelligent compensation driving method of this application.

[0058] Figure label:

[0059] External power transistor 100;

[0060] Intelligent compensation drive circuit 200, level transfer circuit 211, gate drive circuit 212, drive feedback circuit 220, delay circuit 221, voltage sampling circuit 222, result register 223, comparator 224, drive compensation circuit 230, control logic circuit 240. Detailed Implementation

[0061] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0062] In the description of this application, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0063] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0064] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0065] In power drive circuits, there are two main types of losses: (1) The slope is not as expected. If the slope is too low, the power drive switching will be too slow, resulting in significant switching losses. (2) Miller plateau. The Miller plateau in the drive amplifier circuit is particularly noticeable in power drives, and the switching losses caused by the Miller plateau are very large.

[0066] The Miller plateau in the driver amplifier circuit, especially in power drives, is very pronounced, and it introduces significant switching losses. (Reference) Figure 1 , Figure 1 This is an electrical schematic diagram of the MOS parasitic capacitance of a power drive circuit according to an embodiment of this application. During the turn-on process of the MOS transistor, the Vgs voltage rises, and the drive current Ig mainly charges Cgs; when Vgs reaches the turn-on voltage Vgs(th), the MOS transistor begins to conduct, Ids rises rapidly, and Vds begins to decrease slightly; as Vgs continues to rise, it charges Cgs; as Vds drops significantly and rapidly, the d-terminal voltage of Cgd drops rapidly, and the drive current Ig, in addition to charging Cgs, mainly charges Cgd. During this period, Vgs hardly increases, entering the Miller plateau (e.g., ...). Figure 5 (From point a to point b in the diagram); as Cgd fills, Vgs continues to increase, and the MOSFET is fully turned on.

[0067] It should be noted that the principle of the Miller platform is existing technology known to those skilled in the art, and will not be explained in detail here.

[0068] The existing power drive compensation circuits are fixed compensation circuits and can only correct the slope, but cannot take into account the Miller platform.

[0069] The intelligent compensation drive circuit 200 of this application embodiment can dynamically adjust the slope and correct it in time when the Miller plateau is generated, thereby reducing the switching loss of the power transistor.

[0070] The following will combine Figures 1 to 8 The intelligent compensation drive circuit 200 of the embodiments of this application will be clearly and completely described. Obviously, the embodiments described below are some embodiments of this application, not all embodiments.

[0071] The intelligent compensation drive circuit 200 according to the first aspect embodiment of this application is applied to a power drive circuit, the power drive circuit having an external power transistor 100, and the intelligent compensation drive circuit 200 including a drive circuit, a drive feedback circuit 220, a drive compensation circuit 230, and a control logic circuit 240.

[0072] The driving circuit is used to output a high-level gate drive signal to the gate of the external power transistor 100;

[0073] The drive feedback circuit 220 includes a delay circuit 221, a voltage sampling circuit 222, a result register 223, and multiple comparators 224. The delay circuit 221 includes a delay signal input terminal and multiple delay control terminals. Each comparator 224 includes a first input terminal, a second input terminal, a control terminal, and a comparison output terminal. The input terminal of the voltage sampling circuit 222 is connected to the gate of the external power transistor 100, and its output terminal is connected to multiple first input terminals respectively. The multiple control terminals are connected one-to-one with the multiple delay control terminals, and the multiple comparison output terminals are all connected to the result register 223. The delay circuit 221 is used to generate an equally spaced delay pulse to sequentially enable multiple comparators 224 to quantize the gate high-level drive signal and obtain the quantization result. The interval time of the equally spaced delay pulse is the target delay, and the quantization result is stored in the result register 223.

[0074] The drive compensation circuit 230 is used to output compensation current to the drive circuit to increase the drive current of the drive circuit.

[0075] The control logic circuit 240 is connected to the delay signal input terminal, the drive circuit, and the drive compensation circuit 230, respectively. The control logic circuit 240 is used to obtain the turn-off voltage, the on-hold voltage, the target delay, and the total number of sampling points of the external power transistor 100; determine the target slope and multiple reference voltages based on the turn-off voltage, the on-hold voltage, the target delay, and the total number of sampling points. The reference voltages represent the standard voltage values ​​corresponding to the sampling points under the target slope; output a PWM signal to drive the drive circuit to generate a gate high-level drive signal to drive the external power transistor 100; control the voltage sampling circuit 222 to sample the gate high-level drive signal, input multiple reference voltages to multiple second input terminals one by one, control the delay circuit 221 to generate an equally spaced delay pulse, and read the quantization result in the result register 223; determine the time interval of the Miller plateau based on the quantization result; output a PWM signal to drive the drive circuit, and control the on-hand drive compensation circuit 230 to generate a compensation drive signal to drive the external power transistor 100 within the time interval, until the quantization result represents the slope and the Miller plateau correction is completed.

[0076] refer to Figure 2 , Figure 3 and Figure 5 , Figure 2 This is an electrical schematic diagram of an intelligent compensation drive circuit 200 according to an embodiment of this application. Figure 3 This is an electrical schematic diagram of a drive feedback circuit 220 according to an embodiment of this application. Figure 5 This is a quantization schematic diagram of a drive feedback circuit 220 according to an embodiment of this application.

[0077] First, the shutdown voltage of the external power transistor 100 needs to be set. , Start-up sustaining voltage Target delay and the total number of sampling points This allows us to determine the target slope and multiple reference voltages.

[0078] The constraint formula for the target slope is:

[0079] ;Formula (1)

[0080] ;Formula (2)

[0081] in, For the target slope, To enable the sustaining voltage, To turn off the voltage, The total number of sampling points. Delay the target;

[0082] The constraint formula for the reference voltage is:

[0083] ;Formula (3)

[0084] in, For the first The reference voltage corresponding to each sampling point To turn off the voltage, To enable the sustaining voltage, This represents the total number of sampling points.

[0085] The control logic circuit 240 controls the delay circuit 221 to generate an equally spaced delay pulse (the interval time is...). ), sequentially open Comparator 224 quantizes the gate high-level drive signal into At each point, each comparator 224 compares the actual drive voltage quantized by the gate high-level drive signal with the corresponding reference voltage. Compare them. When the actual drive voltage is... The voltage is higher than the reference voltage at the point. At this time, the result register 223 contains =1; when the actual driving voltage is When the voltage is lower than the reference voltage At this time, the result register 223 contains It is 0.

[0086] The control logic circuit 240 can determine the time interval of the Miller platform by judging the number of consecutive 0s in the result register 223. For example, the quantization result is... (i.e., 11000000000), indicating that the time interval from the third sampling point to the 11th sampling point is at the Miller plateau.

[0087] The control logic circuit 240 controls the drive compensation circuit 230 to be turned on at the beginning of the time interval and turns it off at the end of the time interval. This allows it to output compensation current to the drive circuit during the time interval of the Miller platform, thereby increasing the drive current of the drive circuit and improving the Miller platform. At the same time, it can also correct the slope by increasing the drive current.

[0088] The operation of the intelligent compensation driving circuit 200 in this embodiment is as follows:

[0089] First, set the shutdown voltage of the external power transistor 100. , Start-up sustaining voltage Target delay and the total number of sampling points At this point, the target slope and multiple reference voltages can be calculated using formulas (1), (2), and (3);

[0090] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, thereby generating a gate high-level drive signal to drive the external power transistor 100, and the first drive turns it on.

[0091] The control voltage sampling circuit 222 performs the first sampling of the gate high-level drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and obtains the quantization result through multiple comparators 224, which is then stored in the result register 223.

[0092] Read the quantization result from result register 223;

[0093] The time interval of the Miller platform is determined based on the number of consecutive zeros in the quantization results and the corresponding sampling points;

[0094] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, enabling the second drive. At the beginning of the time interval, it controls the drive compensation circuit 230 to turn on, and at the end of the time interval, it controls the drive compensation circuit 230 to turn off, generating a compensation drive signal to drive the external power transistor 100 and perform a second sampling. This process continues until the quantization result is obtained. All values ​​are 1, at which point the slope and Miller plateau corrections are complete.

[0095] According to the intelligent compensation drive circuit 200 of this application embodiment, the gate high-level drive signal is quantized into multiple points by the drive feedback circuit 220. The time interval of the Miller plateau can be determined based on the number of consecutive 0s or 1s in the quantization result. When the drive circuit is turned on again, the control logic circuit 240 controls the drive compensation circuit 230 to increase the drive current of the drive circuit at the beginning of the Miller plateau time interval. At the end of the time interval, the drive compensation circuit 230 is turned off, and sampling is performed again. This process continues until the quantization result is all 1s or all 0s, at which point the slope and Miller plateau correction are completed. The intelligent compensation drive circuit 200 of this application embodiment can dynamically adjust the slope and correct it in time when the Miller plateau occurs, thereby reducing the switching losses of the power transistor.

[0096] In some embodiments of this application, reference is made to Figure 3 , Figure 3 This is an electrical schematic diagram of a drive feedback circuit 220 according to an embodiment of this application. The delay circuit 221 adopts a delay chain structure in which multiple delay units are connected in series. The input terminal of the delay chain structure is connected to the control logic circuit 240, and the output terminals of the multiple delay units are connected to multiple control terminals one-to-one. The delay time of each delay unit is the target delay. The delay chain structure in which multiple delay units are connected in series has a simple circuit structure, low cost, and good stability.

[0097] It should be noted that the delay circuit 221 can also adopt other structures such as "shift register + high-speed synchronous clock" or "multiphase clock generator", which should not be regarded as a limitation of this application.

[0098] In some embodiments of this application, reference is made to Figure 4 , Figure 4 This is an electrical schematic diagram of a gate driving circuit 212 and a driving compensation circuit 230 according to an embodiment of this application. The driving compensation circuit 230 adopts a series structure of multiple current sources connected in series. The output terminal of the series structure is connected to the output terminal of the driving circuit, and each current source is connected to the control logic circuit 240. When compensation is required, the control logic circuit 240 outputs a corresponding compensation value. Enable the corresponding compensation transistor to increase the drive current of the gate drive.

[0099] It should be noted that the gate drive current of the external power transistor 100 = the original gate drive current + the compensation current; the compensation and drive capability (i.e. the magnitude of the compensation current output by each current source) are set according to the actual load conditions (power transistor characteristic parameters) that need to be driven externally.

[0100] The specific work process is as follows:

[0101] First, set the shutdown voltage of the external power transistor 100. , Start-up sustaining voltage Target delay and the total number of sampling points At this point, the target slope and multiple reference voltages can be calculated using formulas (1), (2), and (3);

[0102] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, thereby generating a gate high-level drive signal to drive the external power transistor 100, and the first drive turns it on.

[0103] The control voltage sampling circuit 222 performs the first sampling of the gate high-level drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and obtains the quantization result through multiple comparators 224, which is then stored in the result register 223.

[0104] Read the quantization result from result register 223;

[0105] The time interval of the Miller platform is determined based on the number of consecutive zeros in the quantization results and the corresponding sampling points;

[0106] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, the second drive is turned on, and at the beginning of the time interval, it controls the turn on a current source and at the end of the time interval, it controls the turn off the drive compensation circuit 230 to generate a compensation drive signal to drive the external power transistor 100 and perform a second sampling.

[0107] If the quantization result obtained from the second sampling is still not all 1s, it indicates that the current compensated by one current source is insufficient. Therefore, the time interval of the Miller platform is determined, and after the third drive is initiated, a new current source is added at the beginning of the time interval, and the drive compensation circuit 230 is turned off at the end of the time interval to generate a compensation drive signal to drive the external power transistor 100, and a third sampling is performed. This process is repeated until the quantization result is obtained. All values ​​are 1. At this point, the slope and Miller plateau corrections are complete, and the compensation values ​​are saved. Enter normal working mode (the saved compensation value is used for slope correction in normal working mode, which means that multiple rounds of correction judgment are not required, and the compensation value can be called directly at the corresponding time).

[0108] The compensation current in this application embodiment is adjustable, highly flexible, and can ensure adequate compensation without easily overcompensating.

[0109] In some embodiments of this application, reference is made to Figure 3 , Figure 3 This is an electrical schematic diagram of a drive feedback circuit 220 according to an embodiment of this application. The voltage sampling circuit 222 uses a voltage follower. The core advantage of using a voltage follower is that it can accurately and stably extract the sampling signal without interfering with the original drive signal, perfectly adapting to the characteristics of the gate drive signal, which are "high speed, susceptible to load, and strong electromagnetic interference".

[0110] It should be noted that the voltage sampling circuit 222 can also adopt other structures such as high-speed logic buffers, which should not be regarded as a limitation of this application.

[0111] In some embodiments of this application, reference is made to Figure 2 , Figure 2 This is an electrical schematic diagram of an intelligent compensation drive circuit 200 according to an embodiment of this application. The drive circuit includes a level shifting circuit 211 and a gate drive circuit 212. The input terminal of the level shifting circuit 211 is connected to the control logic circuit 240; the input terminal of the gate drive circuit 212 is connected to the output terminal of the level shifting circuit 211, and the output terminal is connected to the gate of the external power transistor 100. The level shifting circuit 211 converts the low-voltage level output by the control logic circuit 240 into the high-voltage level required for gate driving, and the gate drive circuit 212 is responsible for driving the gate of the external power transistor 100.

[0112] It should be noted that the specific structure and working principle of the level transfer circuit 211 and the gate drive circuit 212 are existing technologies known to those skilled in the art, and will not be described in detail here.

[0113] The intelligent compensation driving method according to a second aspect embodiment of this application, applied to the intelligent compensation driving circuit 200 as described in the first aspect embodiment above, includes:

[0114] Obtain the shutdown voltage, on-hold voltage, target delay, and total number of sampling points of the external power transistor 100;

[0115] The target slope and multiple reference voltages are determined based on the off voltage, on sustaining voltage, target delay and total number of sampling points. The reference voltages characterize the standard voltage values ​​corresponding to the sampling points under the target slope.

[0116] The output PWM signal drives the drive circuit to generate a gate high-level drive signal to drive the external power transistor 100.

[0117] The control voltage sampling circuit 222 samples the gate high-level drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and reads the quantization result in the result register 223;

[0118] The time interval of the Miller platform is determined based on the quantification results;

[0119] The output PWM signal drives the drive circuit, and controls the drive compensation circuit 230 to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor 100 until the quantization result characterizes the slope and Miller plateau correction is completed.

[0120] refer to Figure 2 , Figure 3 and Figure 5 , Figure 2 This is an electrical schematic diagram of an intelligent compensation drive circuit 200 according to an embodiment of this application. Figure 3 This is an electrical schematic diagram of a drive feedback circuit 220 according to an embodiment of this application. Figure 5 This is a quantization schematic diagram of a drive feedback circuit 220 according to an embodiment of this application.

[0121] First, the shutdown voltage of the external power transistor 100 needs to be set. , Start-up sustaining voltage Target delay and the total number of sampling points This allows us to determine the target slope and multiple reference voltages.

[0122] The constraint formula for the target slope is:

[0123] ;Formula (1)

[0124] ;Formula (2)

[0125] in, For the target slope, To enable the sustaining voltage, To turn off the voltage, The total number of sampling points. Delay the target;

[0126] The constraint formula for the reference voltage is:

[0127] ;Formula (3)

[0128] in, For the first The reference voltage corresponding to each sampling point To turn off the voltage, To enable the sustaining voltage, This represents the total number of sampling points.

[0129] The control logic circuit 240 controls the delay circuit 221 to generate an equally spaced delay pulse (the interval time is...). ), sequentially open Comparator 224 quantizes the gate high-level drive signal into At each point, each comparator 224 compares the actual drive voltage quantized by the gate high-level drive signal with the corresponding reference voltage. Compare them. When the actual drive voltage is... The voltage is higher than the reference voltage at the point. At this time, the result register 223 contains =1; when the actual driving voltage is When the voltage is lower than the reference voltage At this time, the result register 223 contains It is 0.

[0130] The control logic circuit 240 can determine the time interval of the Miller platform by judging the number of consecutive 0s in the result register 223. For example, the quantization result is... (i.e., 11000000000), indicating that the time interval from the third sampling point to the 11th sampling point is at the Miller plateau.

[0131] The control logic circuit 240 controls the drive compensation circuit 230 to be turned on at the beginning of the time interval and turns it off at the end of the time interval. This allows it to output compensation current to the drive circuit during the time interval of the Miller platform, thereby increasing the drive current of the drive circuit and improving the Miller platform. At the same time, it can also correct the slope by increasing the drive current.

[0132] The operation of the intelligent compensation driving circuit 200 in this embodiment is as follows:

[0133] First, set the shutdown voltage of the external power transistor 100. , Start-up sustaining voltage Target delay and the total number of sampling points At this point, the target slope and multiple reference voltages can be calculated using formulas (1), (2), and (3);

[0134] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, thereby generating a gate high-level drive signal to drive the external power transistor 100, and the first drive turns it on.

[0135] The control voltage sampling circuit 222 performs the first sampling of the gate high-level drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and obtains the quantization result through multiple comparators 224, which is then stored in the result register 223.

[0136] Read the quantization result from result register 223;

[0137] The time interval of the Miller platform is determined based on the number of consecutive zeros in the quantization results and the corresponding sampling points;

[0138] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, enabling the second drive. At the beginning of the time interval, it controls the drive compensation circuit 230 to turn on, and at the end of the time interval, it controls the drive compensation circuit 230 to turn off, generating a compensation drive signal to drive the external power transistor 100 and perform a second sampling. This process continues until the quantization result is obtained. All values ​​are 1, at which point the slope and Miller plateau corrections are complete.

[0139] In addition, it should be noted that the parameters and Miller effect of each external power transistor 100 are different, and each power transistor in the power drive circuit needs to be equipped with a corresponding set of drive circuit, drive feedback circuit 220 and drive compensation circuit 230 of this application embodiment.

[0140] According to the intelligent compensation driving method of this application embodiment, the gate high-level driving signal is quantized into multiple points by the driving feedback circuit 220. The time interval of the Miller plateau can be determined based on the number of consecutive 0s or 1s in the quantization result. When the driving circuit is turned on again, the control logic circuit 240 controls the driving compensation circuit 230 to increase the driving current of the driving circuit at the beginning of the Miller plateau time interval. At the end of the time interval, the driving compensation circuit 230 is turned off, and sampling is performed again. This process is repeated until all quantization results are 1s or all 0s, at which point the slope and Miller plateau correction are completed. The intelligent compensation driving method of this application embodiment can dynamically adjust the slope and correct it in time when the Miller plateau occurs, thereby reducing the switching losses of the power transistor.

[0141] In some embodiments of this application, reference is made to Figure 3 , Figure 3 This is an electrical schematic diagram of a drive feedback circuit 220 according to an embodiment of this application. The quantization result includes multiple quantized values ​​arranged in sequence, the number of quantized values ​​being equal to the number of comparators 224. The time interval of the Miller plateau is determined based on the quantization result, including:

[0142] The states of each quantization value are determined sequentially. The states of the quantization values ​​include a first state and a second state. The first state indicates that the actual driving voltage is higher than the reference voltage, and the second state indicates that the actual driving voltage is lower than the reference voltage. The actual driving voltage indicates the quantization voltage value of the gate high-level driving signal corresponding to the sampling point.

[0143] The time interval is defined as the interval between consecutive sampling points in the second state.

[0144] The control logic circuit 240 controls the delay circuit 221 to generate an equally spaced delay pulse (the interval time is...). ), sequentially open Comparator 224 quantizes the gate high-level drive signal into At each point, each comparator 224 compares the actual drive voltage quantized by the gate high-level drive signal with the corresponding reference voltage. Compare them. When the actual drive voltage is... The voltage is higher than the reference voltage at the point. At this time, the result register 223 contains =1; when the actual driving voltage is When the voltage is lower than the reference voltage At this time, the result register 223 contains It is 0.

[0145] The control logic circuit 240 can determine the time interval of the Miller platform by judging the number of consecutive 0s in the result register 223. For example, the quantization result is... (i.e., 11000000000), indicating that the time interval from the third sampling point to the 11th sampling point is at the Miller plateau.

[0146] In some embodiments of this application, reference is made to Figure 4 , Figure 4 This is an electrical schematic diagram of a gate driving circuit 212 and a driving compensation circuit 230 according to an embodiment of this application. The driving compensation circuit 230 adopts a series structure of multiple current sources connected in series. The output terminal of the series structure is connected to the output terminal of the driving circuit, and each current source is connected to the control logic circuit 240.

[0147] The output PWM signal drives the drive circuit, and controls the drive compensation circuit 230 to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor 100 until the quantization result characterization of the slope and Miller plateau correction is completed, including:

[0148] The output PWM signal drives the drive circuit, and controls the opening of one current source within the time interval to generate a compensation drive signal to drive the external power transistor 100.

[0149] The control voltage sampling circuit 222 samples the compensation drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and reads the quantization result in the result register 223;

[0150] The time interval of the Miller platform is determined based on the quantification results;

[0151] The output PWM signal drives the drive circuit, and controls the addition of a current source within the time interval to generate a compensation drive signal to drive the external power transistor 100 until all quantized values ​​of the quantization result are in the first state.

[0152] When compensation is required, the control logic circuit 240 outputs the corresponding compensation value. Enable the corresponding compensation transistor to increase the drive current of the gate drive.

[0153] It should be noted that the gate drive current of the external power transistor 100 = the original gate drive current + the compensation current; the compensation and drive capability (i.e. the magnitude of the compensation current output by each current source) are set according to the actual load conditions (power transistor characteristic parameters) that need to be driven externally.

[0154] The specific work process is as follows:

[0155] First, set the shutdown voltage of the external power transistor 100. , Start-up sustaining voltage Target delay and the total number of sampling points At this point, the target slope and multiple reference voltages can be calculated using formulas (1), (2), and (3);

[0156] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, thereby generating a gate high-level drive signal to drive the external power transistor 100, and the first drive turns it on.

[0157] The control voltage sampling circuit 222 performs the first sampling of the gate high-level drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and obtains the quantization result through multiple comparators 224, which is then stored in the result register 223.

[0158] Read the quantization result from result register 223;

[0159] The time interval of the Miller platform is determined based on the number of consecutive zeros in the quantization results and the corresponding sampling points;

[0160] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, the second drive is turned on, and at the beginning of the time interval, it controls the turn on a current source and at the end of the time interval, it controls the turn off the drive compensation circuit 230 to generate a compensation drive signal to drive the external power transistor 100 and perform a second sampling.

[0161] If the quantization result obtained from the second sampling is still not all 1s, it indicates that the current compensated by one current source is insufficient. Therefore, the time interval of the Miller platform is determined, and after the third drive is initiated, a new current source is added at the beginning of the time interval, and the drive compensation circuit 230 is turned off at the end of the time interval to generate a compensation drive signal to drive the external power transistor 100, and a third sampling is performed. This process is repeated until the quantization result is obtained. All values ​​are 1. At this point, the slope and Miller plateau corrections are complete, and the compensation values ​​are saved. Enter normal working mode (the saved compensation value is used for slope correction in normal working mode, which means that multiple rounds of correction judgment are not required, and the compensation value can be called directly at the corresponding time).

[0162] The compensation current in this application embodiment is adjustable, highly flexible, and can ensure adequate compensation without easily overcompensating.

[0163] In some embodiments of this application, reference is made to Figure 5 , Figure 5 This is a quantization schematic diagram of the drive feedback circuit 220 according to an embodiment of this application. It outputs a PWM signal to drive the drive circuit and controls the drive compensation circuit 230 to be activated within a time interval to generate a compensation drive signal to drive the external power transistor 100 until the quantization result characterizing the slope and Miller plateau correction is completed, including:

[0164] The output PWM signal drives the drive circuit, and controls the drive compensation circuit 230 to be turned on within the target interval, so as to generate a compensation drive signal to drive the external power transistor 100 until the quantization result characterization slope and Miller plateau correction are completed. The target interval is within the time interval, and the length of the target interval is less than the length of the time interval.

[0165] Understandably, considering the resolution of quantization, the Miller plateau may occur between two sampling points. If compensation begins at the beginning of the time interval, it may result in overcompensation, generating an over-turn-on voltage and increasing circuit interference.

[0166] To better understand the operation of the intelligent compensation drive circuit 200 in this application embodiment, a specific embodiment will be described in detail below.

[0167] refer to Figure 6 and Figure 7 , Figure 6 This is a waveform diagram of the drive signal of the external power transistor 100 before modification according to an embodiment of this application. Figure 7 This is a modified drive signal waveform diagram of an embodiment of the external power transistor 100 according to this application.

[0168] First, set the shutdown voltage of the external power transistor 100. V, turn on sustaining voltage V, target delay ns, total number of sampling points , V, with 10 levels of drive compensation capability, Miller plateau occurs at 2.5V and lasts for 40ns;

[0169] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, thereby generating a gate high-level drive signal to drive the external power transistor 100, and the first drive turns it on.

[0170] The control voltage sampling circuit 222 performs the first sampling of the gate high-level drive signal, inputs multiple reference voltages to multiple second input terminals one by one, controls the delay circuit 221 to generate an equally spaced delay pulse, and obtains the quantization result through multiple comparators 224, which is then stored in the result register 223.

[0171] Read the quantization result from result register 223. (i.e., 11000000000), indicating that the time interval from the third sampling point to the 11th sampling point is at the Miller plateau;

[0172] The control logic circuit 240 outputs a PWM signal to drive the drive circuit, and the second drive is turned on. At the beginning of the time interval (20ns after the drive is turned on), it controls the turn-on of one current source. At the end of the time interval (60ns after the drive is turned on), it controls the turn-off of the drive compensation circuit 230 to generate a compensation drive signal to drive the external power transistor 100 and perform a second sampling.

[0173] If the quantization result obtained from the second sampling is still not all 1s, it indicates that the current compensated by one current source is insufficient. Therefore, the time interval of the Miller platform is determined, and after the third drive is initiated, a new current source is added at the beginning of the time interval, and the drive compensation circuit 230 is turned off at the end of the time interval to generate a compensation drive signal to drive the external power transistor 100, and a third sampling is performed. This process is repeated until the quantization result is obtained. All values ​​are 1. At this point, the slope and Miller plateau corrections are complete, and the compensation values ​​are saved. It will then enter normal working mode.

[0174] One embodiment of this application also provides a power drive circuit, including the intelligent compensation drive circuit 200 of the first aspect embodiment described above. Since the power drive circuit employs all the technical solutions of the intelligent compensation drive circuit 200 of the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0175] Additionally, one embodiment of this application provides a control device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory can be connected via a bus or other means.

[0176] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0177] The non-transient software program and instructions required to implement the intelligent compensation driving method of the above embodiments are stored in memory. When executed by the processor, the intelligent compensation driving method of the above embodiments is executed.

[0178] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0179] Furthermore, one embodiment of this application provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, such as the processor of the aforementioned control device, causing the processor to perform the intelligent compensation driving method in the above embodiment.

[0180] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0181] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. An intelligent compensation drive circuit, applied to a power drive circuit, wherein the power drive circuit has an external power transistor, characterized in that, The intelligent compensation drive circuit includes: A driving circuit is used to output a gate high-level driving signal to the gate of the external power transistor; The drive feedback circuit includes a delay circuit, a voltage sampling circuit, a result register, and multiple comparators. The delay circuit includes a delay signal input terminal and multiple delay control terminals. Each comparator includes a first input terminal, a second input terminal, a control terminal, and a comparison output terminal. The input terminal of the voltage sampling circuit is connected to the gate of the external power transistor, and its output terminal is connected to multiple first input terminals. The multiple control terminals are connected one-to-one with the multiple delay control terminals, and the multiple comparison output terminals are all connected to the result register. The delay circuit generates an equally spaced delay pulse to sequentially enable the multiple comparators to quantize the gate high-level drive signal, obtaining a quantization result. The interval time of the equally spaced delay pulse is the target delay, and the quantization result is stored in the result register. A drive compensation circuit is used to output a compensation current to the drive circuit to increase the drive current of the drive circuit. A control logic circuit is connected to the delay signal input terminal, the driving circuit, and the driving compensation circuit, respectively. The control logic circuit is used to acquire the shutdown voltage, the on-hold voltage, the target delay, and the total number of sampling points of the external power transistor; determine the target slope and multiple reference voltages based on the shutdown voltage, the on-hold voltage, the target delay, and the total number of sampling points, where each reference voltage represents a standard voltage value corresponding to a sampling point under the target slope; output a PWM signal to drive the driving circuit to generate a gate high-level driving signal to drive the external power transistor; control the voltage sampling circuit to sample the gate high-level driving signal, input multiple reference voltages to multiple second input terminals one-to-one, control the delay circuit to generate an equally spaced delay pulse, and read the quantization result from the result register; determine the Miller plateau time interval based on the quantization result; output a PWM signal to drive the driving circuit, and control the driving compensation circuit to turn on within the time interval to generate a compensation driving signal to drive the external power transistor until the quantization result characterizes the slope and Miller plateau correction.

2. The intelligent compensation drive circuit according to claim 1, characterized in that, The delay circuit adopts a delay chain structure in which multiple delay units are connected in series. The input end of the delay chain structure is connected to the control logic circuit, and the output ends of the multiple delay units are connected to the multiple control ends one by one. The delay time of each delay unit is the target delay.

3. The intelligent compensation drive circuit according to claim 1, characterized in that, The drive compensation circuit adopts a series structure of multiple current sources connected in series. The output terminal of the series structure is connected to the output terminal of the drive circuit, and each current source is connected to the control logic circuit.

4. The intelligent compensation drive circuit according to claim 1, characterized in that, The voltage sampling circuit uses a voltage follower.

5. The intelligent compensation drive circuit according to claim 1, characterized in that, The driving circuit includes: A level shifting circuit, the input of which is connected to the control logic circuit; The gate drive circuit has its input terminal connected to the output terminal of the level transfer circuit, and its output terminal connected to the gate of the external power transistor.

6. A smart compensation driving method, characterized in that, The intelligent compensation driving method, applied to the intelligent compensation driving circuit as described in any one of claims 1 to 5, comprises: Obtain the shutdown voltage, on-hold voltage, target delay, and total number of sampling points of the external power transistor; The target slope and multiple reference voltages are determined based on the shutdown voltage, the on-up sustaining voltage, the target delay, and the total number of sampling points. The reference voltages characterize the standard voltage values ​​corresponding to the sampling points under the target slope. The output PWM signal drives the drive circuit to generate a gate high-level drive signal to drive the external power transistor; The voltage sampling circuit is controlled to sample the gate high-level drive signal, and multiple reference voltages are input to multiple second input terminals one by one. The delay circuit is controlled to generate an equally spaced delay pulse, and the quantization result in the result register is read. The time interval of the Miller platform is determined based on the quantization results; The output PWM signal drives the drive circuit, and controls the drive compensation circuit to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizes the slope and Miller plateau correction is completed.

7. The intelligent compensation driving method according to claim 6, characterized in that, The quantization result includes multiple quantized values ​​arranged in sequence, the number of quantized values ​​being equal to the number of comparators. Determining the time interval of the Miller platform based on the quantization result includes: The states of each quantization value are determined sequentially. The states of the quantization values ​​include a first state and a second state. The first state indicates that the actual driving voltage is higher than the reference voltage, and the second state indicates that the actual driving voltage is lower than the reference voltage. The actual driving voltage indicates the quantization voltage value of the gate high-level driving signal corresponding to the sampling point. The time interval is defined as the interval between consecutive sampling points in the second state.

8. The intelligent compensation driving method according to claim 7, characterized in that, The drive compensation circuit adopts a series structure of multiple current sources connected in series. The output terminal of the series structure is connected to the output terminal of the drive circuit, and each current source is connected to the control logic circuit. The output PWM signal drives the drive circuit and controls the drive compensation circuit to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizing the slope and Miller plateau correction is completed, including: The output PWM signal drives the drive circuit, and controls the activation of one current source within the time interval to generate a compensation drive signal to drive the external power transistor. The voltage sampling circuit is controlled to sample the compensation drive signal, and multiple reference voltages are input to multiple second input terminals one by one. The delay circuit is controlled to generate an equally spaced delay pulse, and the quantization result in the result register is read. The time interval of the Miller platform is determined based on the quantization results; The output PWM signal drives the drive circuit, and within the time interval, controls the addition of one current source to generate a compensation drive signal to drive the external power transistor until all the quantization values ​​of the quantization result are in the first state.

9. The intelligent compensation driving method according to claim 6, characterized in that, The output PWM signal drives the drive circuit and controls the drive compensation circuit to be turned on within the time interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizing the slope and Miller plateau correction is completed, including: The output PWM signal drives the drive circuit, and controls the drive compensation circuit to be turned on within the target interval to generate a compensation drive signal to drive the external power transistor until the quantization result characterizes the slope and Miller plateau correction is completed. The target interval is within the time interval, and the length of the target interval is less than the length of the time interval.

10. The intelligent compensation driving method according to claim 6, characterized in that, The constraint formula for the target slope is: ； ； in, The target slope, The on-state sustaining voltage, The shut-off voltage, The total number of sampling points, Delay the target; The constraint formula for the reference voltage is: ； in, For the first The reference voltage corresponding to each sampling point The shut-off voltage, The on-state sustaining voltage, The total number of sampling points.

Images