Channel estimation analog circuit implementation method and system based on storage and calculation all-in-one device, processing equipment and storage medium

Abstract

The invention relates to a channel estimation simulation circuit implementation method and system based on a storage and calculation integrated device, processing equipment and a storage medium, and the method comprises the steps: obtaining a pilot frequency structure matrix and a probability graph model of a to-be-measured channel estimation task, and determining the initialization probability of each state of each variable node in the probability graph model; the configuration of a storage and calculation all-in-one device array is carried out, and the storage and calculation all-in-one device array comprises an initial input array, an iterative calculation array and a result output array; the initialization probability serves as input of the initial input array, the iterative calculation array is used for completing iterative calculation of mutual information transmission of variable nodes and check nodes in a probability graph model of a to-be-tested channel estimation task, and the result output array is used for outputting a processing result when an iteration stop condition is met; according to the processing result output by the result output array, continuous channel estimation results in the to-be-tested channel estimation task are determined, and the method and the device can be widely applied to the technical field of signal processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, in particular to a channel estimation analog circuit implementation method and system based on a memory-computing integrated device, a processing device and a storage medium. BACKGROUND

[0002] At present, the fifth generation mobile communication technology (5G) introduces key technologies such as multiple input and output (MIMO), wide spectrum bandwidth (such as 100MHz and above) and high frequency band (such as millimeter wave). However, at the initial stage of 5G commercialization, one particularly prominent problem restricts the further development of user experience and technology: 5G terminal high power consumption, short standby time. Compared with mature 4G terminals, the power consumption of 5G terminals has increased significantly, which has become the core bottleneck restricting the terminal endurance and product competitiveness.

[0003] The reason for the dramatic increase in 5G terminal energy consumption is multifaceted and systematic. Research shows that only the communication power consumption of 5G terminals is 50% to 100% higher than that of 4G terminals. The stacking of the above hardware capabilities puts unprecedentedly stringent requirements on the underlying signal processing algorithms. Taking the key link of channel estimation as an example, in the MIMO system, the dimension of the channel parameters to be estimated increases sharply with the number of antennas and the number of subcarriers. The existing classical estimation algorithms based on least squares (LS) or linear minimum mean square error (LMMSE) have a computational complexity proportional to the square or even cube of the number of antennas, which becomes a heavy burden for baseband processing units (such as DSP, FPGA), consuming a large amount of computing resources and time, which directly translates into significant power consumption overhead.

[0004] Therefore, a new channel estimation method and system is urgently needed, which can significantly reduce the computational complexity of the algorithm without sacrificing estimation accuracy and communication performance, thereby fundamentally alleviating the power consumption pressure of 5G terminals and improving the endurance, laying a foundation for the popularization of 5G technology and the green and low-carbon design of the next generation communication system. SUMMARY

[0005] To solve the above problems, the present application provides a channel estimation analog circuit implementation method and system based on a memory-computing integrated device, a processing device and a storage medium, which can significantly reduce the computational complexity of the algorithm without sacrificing estimation accuracy and communication performance.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions: in the first aspect, a channel estimation analog circuit implementation method based on a memory-computing integrated device is provided, comprising: acquire a pilot structure matrix and a probabilistic graph model of a to-be-tested channel estimation task, and determine an initialization probability of each state of each variable node in the probabilistic graph model according to a pilot signal observed by a receiving end, a variance of uniform quantization of a channel, and a noise variance; configure a memory-compute integrator array based on the probabilistic graph model of the to-be-tested channel estimation task, the determined initialization probability, and the pilot structure matrix, wherein the memory-compute integrator array comprises an initial input array, an iterative computation array, and a result output array; the initialization probability is used as an input of the initial input array; the iterative computation array is used to complete iterative computation of information transmission between variable nodes and check nodes in the probabilistic graph model of the to-be-tested channel estimation task; and the result output array is used to output a processing result when an iteration stop condition is met; determine a continuous channel estimation result in the to-be-tested channel estimation task according to the processing result output by the result output array.

[0007] In a second aspect, a system for implementing a channel estimation simulation circuit based on a memory-compute integrator is provided, and the system comprises: an acquisition unit configured to acquire a pilot structure matrix and a probabilistic graph model of a to-be-tested channel estimation task, and determine an initialization probability of each state of each variable node in the probabilistic graph model according to a pilot signal observed by a receiving end, a variance of uniform quantization of a channel, and a noise variance; a memory-compute integrator array configuration unit configured to configure a memory-compute integrator array based on the probabilistic graph model of the to-be-tested channel estimation task, the determined initialization probability, and the pilot structure matrix, wherein the memory-compute integrator array comprises an initial input array, an iterative computation array, and a result output array; the initialization probability is used as an input of the initial input array; the iterative computation array is used to complete iterative computation of information transmission between variable nodes and check nodes in the probabilistic graph model of the to-be-tested channel estimation task; and the result output array is used to output a processing result when an iteration stop condition is met; a channel estimation result determination unit configured to determine a continuous channel estimation result in the to-be-tested channel estimation task according to the processing result output by the result output array.

[0008] In a third aspect, a processing device is provided, and the processing device comprises computer program instructions, wherein the computer program instructions are used to implement corresponding steps of the channel estimation simulation circuit implementation method based on a memory-compute integrator when the computer program instructions are executed by the processing device.

[0009] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores computer program instructions, wherein the computer program instructions are used to implement corresponding steps of the channel estimation simulation circuit implementation method based on a memory-compute integrator when the computer program instructions are executed by a processor.

[0010] The present application has the following advantages due to the above technical scheme: 1、 The present application takes advantage of the storage-computation integrated device, loads the static variable in the probability graph iterative inference process into the storage-computation integrated device, so as to overcome the energy consumption caused by the storage access in the iterative process.

[0011] 2、 The present application transfers the discrete fixed-point number operation involved in the iterative process to the analog domain, breaks through the power consumption bottleneck of the digital circuit, and realizes the energy efficiency of the terminal baseband signal processing to be improved by orders of magnitude.

[0012] 3、 The traditional digital MAC unit is composed of a multiplier and an adder, occupies a significant area, and needs multiple memory accesses, three times of reading and one time of writing for each operation, which leads to a large amount of energy and delay overhead, while the storage-computation integrated device based on the unified probability graph used in the present application completes the matrix-vector multiplication in one step, can realize the time complexity of O(1), and thus greatly reduces the access times and energy consumption.

[0013] In summary, the present application can be widely applied in the field of signal processing technology. BRIEF DESCRIPTION OF DRAWINGS

[0014] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Throughout the drawings, the same reference designates the same elements. In the drawings: Figure 1 is a method flow diagram provided by an embodiment of the present application; Figure 2 is a unified signal model diagram provided by an embodiment of the present application; Figure 3 is a connection relationship diagram between the check nodes and the variable nodes in the probability graph model provided by an embodiment of the present application; Figure 4 is a structure diagram of the memristor array provided by an embodiment of the present application. DETAILED DESCRIPTION

[0015] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0016] Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first", "second", and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0017] Spatially relative terms, such as "inner", "outer", "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures.

[0018] This invention provides a method for implementing a channel estimation analog circuit based on a memristor, comprising: acquiring the pilot structure matrix and probabilistic graphical model of the channel estimation task under test; determining the initialization probability of each state of each variable node in the probabilistic graphical model based on the pilot signal observed at the receiver, the variance of the channel uniform quantization, and the noise variance; configuring a memristor array based on the probabilistic graphical model of the channel estimation task under test, the determined initialization probabilities, and the pilot structure matrix, wherein the memristor array includes an initial input array, an iterative calculation array, and a result output array; the initialization probability is used as the input to the initial input array; the iterative calculation array is used to complete the iterative calculation of information transmission between variable nodes and verification nodes in the probabilistic graphical model of the channel estimation task under test; the result output array is used to output the processing result when the iteration stopping condition is met; and determining the continuous channel estimation result in the channel estimation task under test based on the processing result output by the result output array. This invention stores some static variables in a memristor or other memristor-based in-memristor, thereby transferring some traditional digital operations to the analog domain and using Kirchhoff's circuit laws for computation, breaking through the power consumption bottleneck of digital circuits.

[0019] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art. The ultra-low power universal baseband signal processing method and hardware circuit structure proposed in this invention are applicable to different types of application scenarios, and will now be described in detail with reference to specific embodiments.

[0020] Example 1 like Figure 1 As shown, this embodiment provides a method for implementing a channel estimation analog circuit based on a memory computing unit, including the following steps: S1. Obtain the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and determine the initial probability of each state of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance.

[0021] In-memory computing devices are integrated devices that combine storage and computing capabilities, such as resistive random access memory (RRAM), phase-change memory (PCM), magnetic memory (MRAM), and flash memory.

[0022] The channel estimation task is used to estimate the pilot signal observed at the receiver. The pilot structure matrix of the channel estimation task transmitted by the transmitter. To determine the continuous channel estimation results, the channel vector to be estimated is... , represents the first channel vector of the channel vector to be estimated . The channel state is discretized into states at equal intervals within the quantization range , that is , , represents the quantization boundary value represents the first state of the channel vector to be estimated . , is the state set space, and the value is different in the channel estimation task to be measured according to the number of channel discrete values.

[0023] The probability graph model is a corresponding to the pilot structure matrix, and is used for the unified probability graph model for the channel estimation task to be measured.

[0024] The specific process of the above step S1 is: S101, obtaining the pilot structure matrix sent by the sending end .

[0025] Specifically, the pilot structure matrix of the channel estimation task to be measured sent by the sending end is a matrix with dimensions , is the number of rows of the pilot structure matrix ; is the number of columns of the pilot structure matrix ; represents that there are sending end antennas, represents that the pilot occupies time slots.

[0026] Specifically, the unified signal model between the channel vector to be estimated , the pilot signal observed by the receiving end and the pilot structure matrix of the channel estimation task to be measured sent by the sending end is , as shown in Figure 2 (where Rx and Tx are the receiving end and the sending end, respectively), is noise, is continuous, is continuous, is an unknown discrete variable.

[0027] S102, based on the unified signal model of the channel estimation task, constructing a probability graph model of the channel estimation task to be measured according to the pilot structure matrix sent by the sending end .

[0028] Specifically, the probability graph model includes variable nodes Verification Node And undirected edges, where variable nodes The unknown variable represents the channel vector to be estimated in this invention. That is, each variable node corresponds to the channel vector to be estimated. One of the channel vectors; verification node This represents the coupling relationship between the pilot structure matrix transmitted by the transmitter for channel estimation, the pilot signal observed by the receiver, and the channel vector to be estimated; undirected edges are used to connect variable nodes and check nodes that have a connection relationship. Each variable node uniquely corresponds to the pilot structure matrix. A column vector in the array, where each check node uniquely corresponds to the pilot structure matrix. A row vector within the pilot structure matrix. The Middle Row vector representation , Pilot structure matrix No. Line number Column elements, representing validation nodes. With variable nodes The correlation between them, if the pilot structure matrix middle If the element is 1, then the check node is valid. With variable nodes If there is a connection relationship, and the pilot structure matrix has a connection relationship, then... middle If the element is 0, then the check node is validated. With variable nodes No connection exists.

[0029] To better illustrate the relationship between the pilot structure matrix and the probabilistic graphical model, as well as the relationship between variable nodes, check nodes, and undirected edges, the following Example 1 is presented and combined with... Figure 3 Let me introduce it.

[0030] Example 1: When the pilot structure matrix for OK, When the column matrix has a row vector in the third row of [0, 1, 1, 1, 0, 0], the probabilistic graphical model includes... One verification node, Number of variable nodes (at this time, (6), the third verification node in the probabilistic graphical model (at this time, 3) The connection relationships between the variables and the nodes are as follows: Figure 3As shown, the 2nd, 3rd, and 4th elements of this row vector are 1, and the 1st, 5th, and 6th elements are 0. Therefore, the 3rd check node is connected to the 2nd, 3rd, and 4th variable nodes via undirected edges, while the 3rd check node is not connected to the 1st, 5th, and 6th variable nodes. It should be noted that... Figure 3 Apart from the third verification node, the connection relationships between other verification nodes and variable nodes are not shown. The connection relationships between other verification nodes and variable nodes can be understood by referring to the connection relationship between the third verification node and variable nodes mentioned above.

[0031] S103. Based on the pilot signal observed at the receiving end. Pilot structure matrix transmitted by the transmitting end Variance of channel uniform quantization and noise variance Determine the initial probabilities of each state of each variable node in the probabilistic graphical model, that is, the probability of each variable node. corresponding The likelihood probability ratio.

[0032] Specifically, the initialization probability can be determined as follows: 1) Calculate the variance of uniform quantization of the channel. The MMSE estimator reduces estimation error by introducing a regularization term into the maximum likelihood solution, which is related to noise power and channel prior statistics.

[0033] 2) Based on the pilot signal observed at the receiving end Pilot structure matrix Variance of channel uniform quantization and noise variance Calculate the initial estimates for all variable nodes, where the initial estimates for all variable nodes are... ,in, Represents the pilot structure matrix The transpose of .

[0034] 3) Calculate the distance from the initial estimate of all variable nodes to the state set space of the variable nodes, where the variable nodes... Initial estimation results to the state set space distance .

[0035] 4) Based on the distances from the initial estimates of all variable nodes to the state set space, obtain the variable node values. Each state The initial probability values, where the variable nodes Each state initial probability of each state of the variable node .

[0036] 5) obtaining the initial probability of each state of each variable node according to the initial probability of each state of the variable node each state , obtaining the initial probability of each state of each variable node according to the initial probability of each state of the variable node state , taking the probability of the state of the variable node state as the reference probability, and taking the initial probability of the state of the variable node .

[0037] S2, constructing a probability configuration function according to the pilot structure matrix sent by the sending end and the observed pilot signal of the receiving end.

[0038] S3, configuring the memory-computing integrator array based on the probabilistic graphical model of the to-be-tested channel estimation task, the determined initial probability, and the probability configuration function constructed based on the pilot structure matrix.

[0039] Specifically, the memory-computing integrator array includes an initial input array, an iterative calculation array, and a result output array. The initial probability is input to the initial input array, the iterative calculation array is used to complete the iterative calculation of the information transmission between the variable nodes and the check nodes in the probabilistic graphical model of the to-be-tested channel estimation task, and the result output array is used to output the processing result when the iteration stopping condition is met.

[0040] Specifically, the input of the initial input array is a driving vector obtained based on the initial probability, and the output of the initial input array is a current for starting the iterative calculation array in the first iteration. The iterative calculation array includes a first iteration subarray, a second iteration subarray, and an external input array. The first iteration subarray is used to perform part of the message transmission between the check nodes and the variable nodes, the second iteration subarray and the external input array are used to perform part of the message transmission between the check nodes and the variable nodes to calculate the row input of the first iteration subarray, the row input voltage of the first iteration subarray is determined based on the row output of the second iteration subarray, the column output current of the first iteration subarray is converted into voltage and then delivered to the second iteration subarray as the column input of the second iteration subarray, the column input of the external input subarray is an external input voltage determined based on the probability configuration function, the row of the external input subarray and the second iteration subarray are connected in series, and the common row output current of the external input subarray and the second iteration subarray is converted into voltage and then input to the first iteration subarray as the row input voltage of the first iteration subarray. The column output of the result output array and the row concatenation of the first iteration sub-array are the probability of each state in each variable node when the iteration stop condition is met.

[0041] Specifically, the message passing from check node to variable node is:

[0042] wherein, represents the message passed between the check node and the variable node about the state value of the variable node ; represents the probability configuration function taking the logarithm; represents the message passed from the variable node to the check node about ; represents the value of the element in the candidate vector constructed by the undirected edge between the i-th check node and the j-th variable node ; represents the combination of all variable node states connected to the check node and having the value ; represents the combination of all variable node states connected to the check node and having the value ; represents the value of the element in the candidate vector corresponding to the variable node , , , , , , , represents the value taken from the variable node index set connected to the check node ; represents the value of the element in the candidate vector of the i-th row between the i-th check node and the j-th variable node . The message passing from variable node to check node is:

[0043] wherein, represents the message passed from the variable node to the check node about

[0044] . ​​​The information transmitted between them The message; For verification nodes l To variable node j Passing information about variable nodes j The state value is The message; Indicates the verification node From variable nodes A set of check node indexes with connections Take the value from the middle, but verify the node. Do not take .

[0045] S4. Based on the processing results output by the result output array, determine the continuous channel estimation results in the channel estimation task under test.

[0046] The channel estimation simulation circuit implementation method based on in-memory computing proposed in this embodiment can determine continuous channel estimation results in the channel estimation task under test based on the in-memory computing array unique to this invention. This invention can store some static variables involved in channel estimation in the in-memory computing array, and use the storage and computing performance of the in-memory computing array for computation, breaking through the power consumption bottleneck and significantly reducing its hardware resource consumption and power consumption.

[0047] based on Figure 1 This embodiment of the in-memory computing device uses a memristor as an example for illustration, but is not limited to this example. A memristor is the fourth basic circuit element after resistors, capacitors, and inductors. Its resistance is determined by the excitation and changes continuously. It features high integration density, fast operation speed, low power consumption, and non-volatility. A memristor array can complete vector and matrix multiplication and accumulation operations within one cycle. The multiplication factors are directly stored in the memristor array, eliminating the need for separate storage units.

[0048] When the in-memory computing unit is a memristor, the probability configuration function in step S2 is:

[0049] in, Indicates the verification node With variable nodes undirected edges between Variable nodes in the constructed candidate vector The corresponding element value; express ; This represents the mixed signal observed by the receiver from multiple antennas. The One signal; Represents the pilot structure matrix the first row vector, wherein satisfies the corresponding variable node is a variable node connected with the check node has a connection, denotes a variable node index set having a connection relationship with the check node .

[0050] Specifically, for any check node in the probabilistic graphical model, the embodiment can determine respective target variable nodes connected with the check node through undirected edges, and the target undirected edge is an undirected edge connecting the check node and the target variable node.

[0051] Specifically, the construction process of the above-mentioned probability configuration function includes: S201, obtaining the number of target undirected edges , respectively determining the internal order of each target undirected edge among all target undirected edges.

[0052] S202, constructing a plurality of candidate vectors obtained by arranging and combining target characters, and the number of candidate vectors is . For any candidate vector, if the element order of the target characters in the candidate vector is equal to the internal order of the target undirected edge, an association relationship is established between the target characters in the candidate vector and the target variable nodes connected with the target undirected edge, wherein the target characters correspond to .

[0053] S203, sequentially traversing each target undirected edge.

[0054] S204, for the th target undirected edge traversed, dividing the plurality of candidate vectors into a plurality of th candidate vectors to be processed, and constructing a probability configuration function according to each th candidate vector, the association relationship, the pilot structure matrix, the multi-antenna mixed signal observed by the receiving end, and the noise variance; wherein the th element in the th candidate vector is .

[0055] Specifically, the probability configuration function is constructed according to each th candidate vector, the association relationship, the pilot structure matrix, the multi-antenna mixed signal observed by the receiving end, and the noise variance, including: (1) For any candidate vector to be processed, a zero vector with the total number of elements equal to the total number of variable nodes is constructed, the node order of the target variable node associated with each target character in the candidate vector to be processed is determined as the unique corresponding permutation order of each target character, and each zero element in the zero vector with the position order equal to the permutation order is replaced by the target character uniquely corresponding to the permutation order to obtain a processed candidate vector, wherein the candidate vector to be processed is any first candidate vector.

[0056] (2) The target row vector uniquely corresponding to the check node is determined in the pilot structure matrix.

[0057] (3) The target row vector is multiplied by each processed candidate vector to obtain a plurality of corresponding numerical values and arranged into node blocking state column vectors, wherein the state number is

[0058] (4) The node blocking state column vectors are transversely spliced, and the probability configuration function is obtained according to the multi-antenna mixed signal observed by the receiving end and the noise variance .

[0059] For better illustration of the above execution process, the embodiment continues to introduce in combination with the above examples 1 and Figure 3

[0060] Example 1, for any check node , the variable nodes and target undirected edges connected to the check node can be determined in the probabilistic graphical model. As shown in Figure 3 , when is 3, the variable nodes connected to the third check node are the second, third and fourth variable nodes, and the number of target undirected edges is equal to 3, and each target undirected edge is the undirected edge between the third check node and the second, third and fourth variable nodes. The internal order of each target undirected edge in all target undirected edges is 1, 2 and 3 in turn.

[0061] The target characters include 0 and 1. At this time ​​equals 3, a plurality of candidate vectors obtained by permutation and combination of 3 target characters are constructed, at this time, the number of selected vectors is 23, i.e. 8 candidate vectors, which are (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0) and (1, 1, 1). It can be understood that the number of elements of the candidate vector is the same as the number of target undirected edges. The first, second and third target characters in the candidate vector are associated with the target variable nodes connected to the target undirected edges with internal orders 1, 2 and 3, i.e. the first, second and third target characters in the candidate vector are associated with the second, third and fourth variable nodes.

[0062] the internal order of the target undirected edge is 3, The first, second and third target undirected edges are traversed in turn, and each time a target undirected edge is traversed, the 8 candidate vectors are divided into a first candidate vector and a second candidate vector. For example, when the third target undirected edge is traversed, the first candidate vector includes (0, 0, 1), (0, 1, 1), (1, 0, 1) and (1, 1, 1), and the second candidate vector includes (0, 0, 0), (0, 1, 0), (1, 0, 0) and (1, 1, 0). equals 3, if the third element in the candidate vector is 1, it is determined as the first candidate vector, and if the third element in the candidate vector is 0, it is determined as the second candidate vector, at this time, the first candidate vector includes (0, 0, 1), (0, 1, 1), (1, 0, 1) and (1, 1, 1), and the second candidate vector includes (0, 0, 0), (0, 1, 0), (1, 0, 0) and (1, 1, 0).

[0063] Each of the above first candidate vector and second candidate vector is taken as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is taken as a candidate vector to be processed, a zero vector (0, 0, 0, 0, 0, 0) with a total number of elements equal to the total number of variable nodes 6 is constructed, the first, second and third target characters in the first candidate vector are associated with the second, third and fourth variable nodes, therefore, the second, third and fourth zero elements in the zero vector can be replaced by the first, second and third target characters in the first candidate vector, respectively, to obtain a corresponding processed first candidate vector (0, 0, 1, 1, 0, 0).

[0064] At this time, the embodiment traverses to the third target undirected edge, and four processed first candidate vectors and four processed second candidate vectors are obtained according to the target undirected edge. Then, the embodiment can determine the target row vector corresponding to the third check node in the pilot structure matrix, that is, the third row vector in the pilot structure matrix. The target row vector is multiplied by the four processed first candidate vectors respectively to obtain four corresponding numerical values, and the first node resistance state column vector is obtained by vertically arranging the four numerical values. The target row vector is multiplied by the four processed second candidate vectors respectively to obtain four corresponding numerical values, and the second node resistance state column vector is obtained by vertically arranging the four numerical values. The first node resistance state column vector and the second node resistance state column vector are horizontally spliced, and the probability configuration function corresponding to the third target undirected edge is obtained according to the pilot signal observed by the receiving end , variance of channel uniform quantization and .

[0065] Specifically, as Figure 4 shown, when the memory-computing integrated device is a memristor, at this time, the memory-computing integrated device array in step S3 is a memristor array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the probability graph model of the to-be-tested channel estimation task, and the specific implementation process is as follows: ①The configuration and calculation process of the initial input array is as follows: The scale of the initial input array is configured as , wherein is the number of columns of the pilot structure matrix , is the number of rows of the pilot structure matrix , is the number of states of , and is . is the candidate vector set, which represents the number of candidate vectors in the set (representing the combination of the states of all variable nodes except the variable node connected to the check node ). The input of the initial input array is the initialization probability voltage corresponding to the state value of the variable node, which is as follows:

[0066]

[0067] Based on the above input voltage, the output current sequence of the initial input array is as follows:

[0068] wherein the parameter is: ​​​

[0069] Parameters in the initial input array The value corresponding to the column of nodes where the parameter is located is:

[0070] wherein, represents the value satisfying The corresponding voltage input row index, specifically, the value of the element in the candidate vector of all variable nodes connected to the test node i is selected as The corresponding variable node is j The value of the parameter represents the element from the top down represents that the memristor array node is in a low state and can conduct, represents that the memristor array node is in a high resistance state and does not conduct. The value is The corresponding row voltage is accumulated, and the current is output at the output end, which is equivalent to the calculation in

[0071] ② The iterative calculation array includes a first iterative subarray, a second iterative subarray, and an external input array. The configuration and calculation process of the iterative calculation array are as follows: The size of the first iterative subarray is set to . The output of the initial input array is connected to the column input end of the first iterative subarray to start iteration. The voltage value of the row input end of the first iterative subarray in the first iteration is 0, and the complete operation in the first iterative subarray is wherein, when the value is :

[0072] When iterating, the row input voltage input by the corresponding row input end of the first iterative subarray is:

[0073] The element order in the column output current arrangement vector corresponding to the first iterative subarray is:

[0074] wherein, the parameter .

[0075] For the parameter located in the column of nodes, the value corresponding to the column of nodes is:​​​​

[0076] wherein, represents satisfying corresponding voltage input row index, the specific meaning is to select the element value in the candidate vector belonging to all variable nodes connected with the check node i corresponding variable node is j the value of the last iteration input of all check nodes whether it exists, if it exists, the value corresponding to the node is 1, otherwise the value corresponding to the node is 0, the special case is when k =1, the state value of the node is set to 1; represents the first element from top to bottom; represents that the memristor array node is in low state and can be turned on, represents that the memristor array node is in high resistance state and is not conductive. The value is corresponding row voltage accumulation, output current at the output end, equivalent to the calculation in

[0077] The configuration and calculation process of the second iteration subarray and the external input array are as follows: The scale of the second iteration subarray is , and the scale of the external input array is Unlike the first iteration subarray, the columns of the second iteration subarray and the external input array correspond to voltage input, the rows of the second iteration subarray and the external input array correspond to current readout, and the rows of the second iteration subarray and the external input subarray are connected in series. The output result of the first iteration subarray to the second iteration subarray input will undergo current to voltage conversion.

[0078] The input of the external input array is directly given by the external voltage, and the external input voltage of the external input array is:

[0079] wherein, the parameter .

[0080] The second iteration subarray and the external input array complete the calculation together as follows:

[0081] The common output of the second iteration subarray and the external input array is:​​​​

[0082] The relationship between the input of the first iteration sub-array and the output of the second iteration sub-array and the external input array is:

[0083] The row output of the second iteration sub-array The corresponding node state value configuration is:

[0084] Wherein, represents the that satisfies The corresponding column index, the specific meaning is selected with the check node i The variable node j connected and taking the value of The combination of all variable node states , if exists, the node value is configured as 1, if does not exist, the node value is configured as 0. represents the left-to-right Array node.

[0085] The row output of the external input array The corresponding node state value configuration is:

[0086] Wherein, represents the that satisfies The corresponding column index, the specific meaning is selected with the check node i The variable node j connected and taking the value of The combination of all variable node states , if exists, the node value is configured as 1, if does not exist, the node value is configured as 0. represents the left-to-right Array node.

[0087] ③ The configuration and calculation process of the result output array is: The scale of the result output array is , used to calculate the value probability of each state in each variable node , and the calculation completed by the result output array is: ​

[0088] The order of elements in the column output current arrangement vector corresponding to the result output array is:

[0089] For the variable node The value corresponding to the column node where the variable node is located is:

[0090] Wherein, The specific meaning is to select the value of the variable node j Connected to all check nodes about , if the value exists, it is 1, and if it does not exist, it is 0; The first element from top to bottom.

[0091] The values in the above five arrays are prepared before iteration.

[0092] When the storage and calculation integrated device is a memristor, at this time, the specific process of step S4 is: Considering that the channel is continuous, when the iteration reaches the preset iteration condition, the output of the result output array in the configured memristor array is used to determine the continuous channel estimation result in the to-be-measured channel estimation task in an interpolation manner.

[0093] Specifically, determining the continuous channel estimation result in the to-be-measured channel estimation task in an interpolation manner includes but is not limited to the following steps: S401, the log-likelihood ratio is pushed back to probability: when the iteration reaches the preset iteration condition, the output of the result output array in the configured memristor array is used to obtain the final decision variable node j The value of The probability .

[0094] S402, the probability j of the final decision variable node taking the value is normalized to obtain the probability j of the normalized final decision variable node taking the value .

[0095] S403, based on the probability j of the normalized final decision variable node taking the value , the continuous channel estimation result in the to-be-measured channel estimation task is determined in an interpolation manner, wherein, ,​ .

[0096] Example 2 This embodiment provides a channel estimation analog circuit implementation system based on a memory computing unit, characterized in that it includes: The acquisition unit is used to acquire the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and determine the initial probability of each state of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance. The in-memory computing array configuration unit is used to configure the in-memory computing array based on the probabilistic graphical model of the channel under test estimation task, the determined initialization probability, and the pilot structure matrix. The in-memory computing array includes an initial input array, an iterative calculation array, and a result output array. The initialization probability serves as the input to the initial input array. The iterative calculation array is used to perform iterative calculations to complete the information transfer between variable nodes and verification nodes in the probabilistic graphical model of the channel under test estimation task. The result output array is used to output the processing results when the iteration stopping condition is met. The channel estimation result determination unit is used to determine the continuous channel estimation results in the channel estimation task under test based on the processing results output by the result output array.

[0097] In a preferred embodiment, the specific process of obtaining the unit is as follows: Obtain the pilot structure matrix transmitted by the transmitting end; A unified signal model based on channel estimation tasks, using the pilot structure matrix transmitted by the transmitter. A probabilistic graphical model for the channel estimation task is constructed, wherein the unified signal model for the channel estimation task is... , The pilot signal observed at the receiving end. Let be the channel vector to be estimated; For noise, The pilot structure matrix for the channel estimation task transmitted by the transmitter. Pilot structure matrix number of rows; Pilot structure matrix The number of columns; Based on the pilot signal observed at the receiver, the pilot structure matrix transmitted at the transmitter, the variance of the channel uniform quantization, and the noise variance, the initial probability of each state of each variable node in the probabilistic graphical model is determined.

[0098] Specifically, based on the pilot signal observed at the receiver, the pilot structure matrix transmitted at the transmitter, the variance of the channel uniform quantization, and the noise variance, the initial probabilities of each state of each variable node in the probabilistic graphical model are determined, including: calculating variance of the channel uniform quantization; calculating initial estimation results of all variable nodes according to the pilot signal observed by the receiving end, the pilot structure matrix, the variance of the channel uniform quantization and the noise variance; calculating distances from the initial estimation results of all variable nodes to the state set space of the variable nodes; obtaining initial probability values of each state of the variable nodes according to the distances from the initial estimation results of all variable nodes to the state set space; obtaining initialization probabilities of each state of each variable node according to the initial probability values of each state of the variable nodes.

[0099] In a preferred embodiment, the input of the initial input array is a driving vector obtained based on the initialization probabilities, and the output of the initial input array is a current for starting the iteration calculation array in the first iteration; The iteration calculation array comprises a first iteration sub-array, a second iteration sub-array and an external input array, the second iteration sub-array and the external input array are used to calculate a row input of the first iteration sub-array, wherein a row input voltage of the first iteration sub-array is determined based on a row output of the second iteration sub-array, and a column output current of the first iteration sub-array is converted into a voltage and then input to the second iteration sub-array as a column input of the second iteration sub-array; in the first iteration, the row input of the first iteration sub-array is 0, and the column input of the first iteration sub-array is the output of the initial input array; a column input of the external input sub-array is an external input voltage determined based on a probability configuration function, the external input sub-array and the second iteration sub-array are connected in series in the row direction, and a common row output current of the external input sub-array and the second iteration sub-array is converted into a voltage and then input to the first iteration sub-array as a row input voltage of the first iteration sub-array; The result output array and the first iteration sub-array are connected in series in the row direction, and a column output of the result output array is a probability of each state in each variable node when an iteration stop condition is met.

[0100] The channel estimation simulation circuit implementation system based on the memory-compute integrated device provided in the embodiment can determine continuous channel estimation results in a to-be-measured channel estimation task based on the memory-compute integrated device array unique to the application. The application can store part of static variables involved in channel estimation in the memory-compute integrated device array, perform operations by using the storage and computing performance of the memory-compute integrated device array, break through the power bottleneck, and significantly reduce hardware resource consumption and power consumption.

[0101] The system provided in the embodiment is used to execute the above-mentioned method embodiments, and specific processes and detailed contents are referred to the above-mentioned embodiments, which will not be described herein.

[0102] Embodiment 3 This embodiment provides a processing device corresponding to the channel estimation simulation circuit implementation method based on in-memory computing provided in Embodiment 1. The processing device can be applied to client processing devices, such as mobile phones, laptops, tablets, desktop computers, etc., to execute the method of Embodiment 1.

[0103] The processing device includes a processor, a memory, a communication interface, and a bus. The processor, memory, and communication interface are connected via the bus to enable communication between them. The memory stores a computer program that can run on the processing device. When the processing device runs the computer program, it executes the channel estimation simulation circuit implementation method based on a memory-computing device provided in Embodiment 1.

[0104] In some implementations, the memory may be high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device.

[0105] In other implementations, the processor can be any type of general-purpose processor, such as a central processing unit (CPU) or a digital signal processor (DSP), and there is no limitation here.

[0106] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] Those skilled in the art will understand that the structure of the above-described computing device is only a partial structure related to the present invention and does not constitute a limitation on the computing device to which the present invention is applied. A specific computing device may include more or fewer components, or combine certain components, or have different component arrangements.

[0108] Example 4 This embodiment provides a computer program product corresponding to the channel estimation simulation circuit implementation method based on in-memory computing provided in Embodiment 1. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing the channel estimation simulation circuit implementation method based on in-memory computing described in Embodiment 1 are loaded.

[0109] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination thereof.

[0110] The computer-readable storage medium provided in the above embodiments has a similar implementation principle and technical effect to the above method embodiments, and will not be described again here.

[0111] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0112] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0113] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0114] The above embodiments are only used to illustrate the present invention. The structure, connection method and manufacturing process of each component can be varied. All equivalent transformations and improvements made on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.

Claims

1. A method for implementing a channel estimation analog circuit based on a memory computing unit, characterized in that, include: Obtain the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and determine the initial probability of each state of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance. Based on the probabilistic graphical model of the channel under test estimation task, the determined initialization probability, and the pilot structure matrix, an in-memory computing array is configured. The in-memory computing array includes an initial input array, an iterative calculation array, and a result output array. The initialization probability serves as the input to the initial input array. The iterative calculation array is used to perform iterative calculations to complete the information transfer between variable nodes and verification nodes in the probabilistic graphical model of the channel under test estimation task. The result output array is used to output the processing results when the iteration stopping condition is met. Based on the processing results output by the output array, the continuous channel estimation results in the channel estimation task under test are determined.

2. The method for implementing a channel estimation analog circuit based on a memory computing unit as described in claim 1, characterized in that, The process of acquiring the pilot structure matrix and probabilistic graphical model for the channel estimation task, and determining the initial probabilities of each state of each variable node in the probabilistic graphical model based on the pilot signal observed at the receiver, the variance of the channel uniform quantization, and the noise variance, includes: Obtain the pilot structure matrix transmitted by the transmitting end; A unified signal model based on channel estimation tasks, using the pilot structure matrix transmitted by the transmitter. A probabilistic graphical model for the channel estimation task is constructed, wherein the unified signal model for the channel estimation task is... , The pilot signal observed at the receiving end. Let be the channel vector to be estimated; For noise, The pilot structure matrix for the channel estimation task transmitted by the transmitter; Pilot structure matrix number of rows; Pilot structure matrix The number of columns; Based on the pilot signal observed at the receiver, the pilot structure matrix transmitted at the transmitter, the variance of the channel uniform quantization, and the noise variance, the initial probability of each state of each variable node in the probabilistic graphical model is determined.

3. The method for implementing a channel estimation analog circuit based on a memory computing unit as described in claim 2, characterized in that, The step of determining the initial probability of each state of each variable node in the probabilistic graphical model based on the pilot signal observed at the receiver, the pilot structure matrix transmitted by the transmitter, the variance of the channel uniform quantization, and the noise variance includes: Calculate the variance of uniform quantization of the channel; Based on the pilot signal observed at the receiver, the pilot structure matrix, the variance of the channel uniform quantization, and the noise variance, calculate the initial estimation results for all variable nodes; Calculate the distance from the initial estimate of all variable nodes to the state set space of the variable nodes; The initial probability values ​​of each state of the variable nodes are obtained based on the distance from the initial estimates of all variable nodes to the state set space. Based on the initial probability values ​​of each state of the variable node, the initial probability of each state of the variable node is obtained.

4. The method for implementing a channel estimation analog circuit based on a memory computing unit as described in claim 2, characterized in that, The message passing from the verification node to the variable node is as follows: in, Indicates the verification node To variable node Passing information about variable nodes between nodes The state value is The message; Represents the probability configuration function Take the logarithm; Represents variable nodes To the verification node The message conveyed about The news Represents the channel vector to be estimated The One channel vector; Indicates the first The verification node and the first Undirected edges between variable nodes The first candidate vector constructed Each element value; Indicates and verifies nodes Connected and variable nodes Values The combination of all variable node states; Indicates and verifies the node Connected and variable nodes Values The combination of all variable node states; Represents the variable nodes in the candidate vector The corresponding element value, ; express From the verification node A set of indexes of variable nodes with connections Take the value from; For the first The verification node and the first Undirected edges between variable nodes The first candidate vector constructed The element value of the row; The message passing from the variable node to the verification node is as follows: in, Represents variable nodes To the verification node The information transmitted between them The message; For verification nodes l To variable node j Passing information about variable nodes j The state value is The news.

5. The method for implementing a channel estimation analog circuit based on a memory computing unit as described in claim 4, characterized in that, The probability configuration function is constructed based on the pilot structure matrix transmitted by the transmitter and the pilot signal observed by the receiver. for: in, express ; This indicates the pilot signal observed at the receiver. The One signal; Represents the pilot structure matrix The first in Column vector.

6. The method for implementing a channel estimation analog circuit based on a memory computing unit as described in claim 5, characterized in that, The iterative computation array includes a first iterative subarray, a second iterative subarray, and an external input array, wherein, The configuration and calculation process of the first iteration subarray is as follows: The size of the first iteration subarray is set to ,in, Pilot structure matrix The number of columns, Pilot structure matrix the number of rows, for The number of states; The number of candidate vectors; In the first iteration, the voltage at the row input of the first iteration subarray is 0. The output of the initial input array is connected to the column input of the first iteration subarray to start the iteration. Values At that time, the calculation performed by the first iteration subarray is as follows: During iteration, the row input voltage input to the row input terminal corresponding to the first iteration subarray for: The element order in the column output current arrangement vector corresponding to the first iteration subarray is: Among them, parameters ; For the parameters in the first iteration subarray The value corresponding to the node in the column is: in, Indicates satisfaction of The corresponding voltage input row index, specifically, selects the node belonging to the test node. i The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of The value of the previous iteration input in all test nodes of If a node exists, its value is 1; otherwise, its value is 0. A special case exists when... k When =1, the state value of this node is set to 1; Indicates the order from top to bottom One element; values The corresponding row voltage is accumulated, and the output current is generated at the output terminal; The configuration and calculation process of the second iterative subarray and the external input array are as follows: The size of the second iteration subarray is The size of the external input array is The external input voltage of the external input array is: Among them, parameters ; The second iteration subarray and the external input array together complete the calculation as follows: The common output of the second iterative subarray and the external input array is: The relationship between the input of the first iteration subarray and the common output of the second iteration subarray and the external input array is as follows: Row output of the second iteration subarray The corresponding node status value is configured as follows: in, Indicates satisfaction of The corresponding column index, specifically, refers to the selection and verification of nodes. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If the node does not exist, its value is configured to 0. Indicates the number from left to right One array node; Row output of external input array The corresponding node status value is configured as follows: in, Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If the node does not exist, its value is configured to 0. Indicates the number from left to right Array nodes.

7. The method for implementing a channel estimation analog circuit based on a memory computing unit as described in claim 6, characterized in that, The configuration and calculation process of the initial input array is as follows: The initial input array size is configured as follows: The initial input to the input array is an input voltage that is proportional to the initialization probability of the state values ​​of the variable nodes. Based on the input voltage, the initial input array output current order is as follows: Among them, parameters for: Parameters in the initial input array The value corresponding to the node in the column is: in, Indicates satisfaction of The corresponding voltage input row index, specifically, selects the node belonging to the test node. i The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of If the value exists, the value corresponding to the node is set to 1; otherwise, it is set to 0. Indicates the order from top to bottom One element; values The corresponding row voltage is accumulated, and the output current is generated at the output terminal; The configuration and calculation process of the output array is as follows: The calculations performed by the output array are as follows: in, For each variable node Various states The probability of taking a value; The order of elements in the column output current arrangement vector corresponding to the output array is as follows: For the probability of taking values The value corresponding to the node in the column is: in, Specifically, it means selecting variable nodes. j All connected verification nodes China regarding of The value is 1 if it exists, and 0 if it does not exist; Indicates the order from top to bottom Each element.

8. A channel estimation analog circuit implementation system based on a memory computing unit, characterized in that, include: The acquisition unit is used to acquire the pilot structure matrix and probabilistic graphical model of the channel estimation task under test, and determine the initial probability of each state of each variable node in the probabilistic graphical model based on the pilot signal observed by the receiver, the variance of the channel uniform quantization and the noise variance. The in-memory computing array configuration unit is used to configure the in-memory computing array based on the probabilistic graphical model of the channel under test estimation task, the determined initialization probability, and the pilot structure matrix. The in-memory computing array includes an initial input array, an iterative calculation array, and a result output array. The initialization probability serves as the input to the initial input array. The iterative calculation array is used to perform iterative calculations to complete the information transfer between variable nodes and verification nodes in the probabilistic graphical model of the channel under test estimation task. The result output array is used to output the processing results when the iteration stopping condition is met. The channel estimation result determination unit is used to determine the continuous channel estimation results in the channel estimation task under test based on the processing results output by the result output array.

9. A processing device, characterized in that, It includes computer program instructions, wherein when executed by a processing device, the computer program instructions are used to implement the steps corresponding to the channel estimation analog circuit implementation method based on the in-memory computing unit as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, wherein when the computer program instructions are executed by a processor, they are used to implement the steps corresponding to the channel estimation simulation circuit implementation method based on the in-memory computing unit as described in any one of claims 1-7.

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