Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a fin over a substrate, a first portion of the fin including a plurality of first channel layers interleaved with a plurality of first sacrificial layers, and a second portion of the fin including a plurality of second channel layers interleaved with a plurality of second sacrificial layers; forming a trench extending through the fin; laterally recessing the plurality of first sacrificial layers and the plurality of second sacrificial layers at different etch rates; and replacing a remaining portion of the plurality of first sacrificial layers with a first gate structure, and replacing a remaining portion of the plurality of second sacrificial layers with a second gate structure.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs.

[0003] Such miniaturization also increases the complexity of handling and manufacturing ICs. For example, as integrated circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. Fin field-effect transistors (FinFETs) and gate all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels enclosed by gates on more than one side (e.g., the gates enclose the top and sidewalls of a semiconductor material “fin” extending from the substrate). GAA transistors have gate structures that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistors alternative names such as nanosheet transistors or nanowire transistors.

[0004] As the semiconductor industry further advances to sub-10 nanometer (nm) technology nodes in pursuit of higher device density, higher performance, and lower costs, challenges arising from manufacturing and design issues have led to stacked device structure configurations, such as complementary field-effect transistors (C-FETs), where n-type multi-gate transistors and p-type multi-gate transistors are vertically stacked one on top of the other. While existing C-FETs are generally sufficient, they are not satisfactory in all aspects. Summary of the Invention

[0005] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a fin structure protruding from a substrate, a first portion of the fin structure including a plurality of first channel layers interleaved with a plurality of first sacrificial layers, and a second portion of the fin structure including a plurality of second channel layers interleaved with a plurality of second sacrificial layers; forming a trench extending through the fin structure; after forming the trench, performing an etching process to laterally recess the plurality of first sacrificial layers and the plurality of second sacrificial layers, wherein the etchant of the etching process etches the plurality of first sacrificial layers and the plurality of second sacrificial layers at different rates; and after performing the etching process, replacing the remaining portions of the plurality of first sacrificial layers with a first gate structure and replacing the remaining portions of the plurality of second sacrificial layers with a second gate structure.

[0006] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first semiconductor layer stack over a substrate and forming a second semiconductor layer stack over the first semiconductor layer stack, the first semiconductor layer stack having a first upper semiconductor layer above a first lower semiconductor layer, and the second semiconductor layer stack having a second upper semiconductor layer above a second lower semiconductor layer; forming a first source / drain component coupled to the first upper semiconductor layer and the first lower semiconductor layer; forming a second source / drain component coupled to the second upper semiconductor layer and the second lower semiconductor layer; forming a first gate structure disposed adjacent to the first source / drain component and between the first upper semiconductor layer and the first lower semiconductor layer; and forming a second gate structure disposed adjacent to the second source / drain component and between the second upper semiconductor layer and the second lower semiconductor layer, wherein the first gate structure and the second gate structure have different gate lengths.

[0007] Further embodiments of this application provide a semiconductor device, including: a substrate; a lower source / drain component disposed above the substrate; a first plurality of nanostructures coupled to the lower source / drain component; a first gate structure enclosing each of the first plurality of nanostructures; an upper source / drain component located above the lower source / drain component; a second plurality of nanostructures coupled to the upper source / drain component; and a second gate structure enclosing each of the second plurality of nanostructures, wherein the first gate structure and the second gate structure have different gate lengths. Attached Figure Description

[0008] Embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A perspective view of a semiconductor device including a vertical C-FET according to one or more aspects of embodiments of the present disclosure is shown.

[0010] Figure 2 A flowchart is shown of a first method for forming a semiconductor device including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 13 , Figure 14 , Figure 32 Semiconductor devices according to various aspects of embodiments of the present disclosure are shown. Figure 2 Partial cross-sectional views during each manufacturing stage in the first method.

[0012] Figure 15 A flowchart is shown of a second method for forming a semiconductor device including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure.

[0013] Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 Semiconductor devices according to various aspects of embodiments of the present disclosure are shown. Figure 15 Partial cross-sectional views during each manufacturing stage in the second method.

[0014] Figure 21 A flowchart is shown of a third method for forming a semiconductor device including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure.

[0015] Figure 22 , Figure 23 , Figure 24 Semiconductor devices according to various aspects of embodiments of the present disclosure are shown. Figure 21 Partial cross-sectional views during each manufacturing stage in the third method.

[0016] Figure 25 A flowchart is shown of a fourth method for forming a semiconductor device including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure.

[0017] Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 Semiconductor devices according to various aspects of embodiments of the present disclosure are shown. Figure 25 Partial cross-sectional views during each manufacturing stage in the fourth method. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact.

[0019] For ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to cover a reasonable range of values ​​that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having characteristics related to the numerical value, a numerical value or range of values ​​covers a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" can include a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are + / - 15%, as known to those skilled in the art.

[0021] Integrated circuits comprise various circuit device components, such as transistors. Transistors with different configurations may be suited for different circuit functions due to their varying performance characteristics. A stacked multi-gate device refers to a semiconductor device comprising a bottom multi-gate device and a top multi-gate device stacked on top of the bottom multi-gate device. When the bottom and top multi-gate devices have different conductivity types, the stacked multi-gate device can be a complementary field-effect transistor (C-FET). The multi-gate device in a C-FET can be a FinFET or a GAA transistor. An n-type transistor (e.g., an NFET) comprises n-type doped source / drain pairs, and its majority carriers are electrons. A p-type transistor (PFET) comprises p-type doped source / drain pairs, and its majority carriers are holes. When an NFET and a PFET in a C-FET are manufactured with the same configuration (e.g., the same channel thickness, the same gate length), either the PFET or the NFET may not have its corresponding optimal performance. Furthermore, C-FETs can be configured to perform different functions (e.g., as part of a logic cell or as part of a memory cell) and / or can be used for different applications (e.g., high-performance computing (HPC) or low-current drive). Those different functions or applications may require C-FETs to exhibit different performance aspects (e.g., high current drive capability or low power consumption). In some instances, a shorter gate length may result in a lower channel resistance Rch, which can be beneficial in one aspect of transistor performance. However, if the gate length is too short, gate control capability may be unsatisfactory. A thinner channel thickness may result in better gate control capability. However, if the channel thickness is too thin, the channel resistance Rch may be too large. Embodiments of this disclosure depict several ways to form C-FETs with different performance by individually adjusting the configuration of the top multi-gate device and the bottom multi-gate device.

[0022] Various aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 A perspective view of a semiconductor device including a vertical C-FET according to one or more aspects of embodiments of the present disclosure is shown. Figure 2 , Figure 15 , Figure 21 , Figure 25 Each illustrates a flowchart of a method for forming a semiconductor device including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure. Figure 2 , Figure 15 , Figure 21 , Figure 25The methods illustrated are merely examples and are not intended to limit the embodiments of this disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and after each method, and for additional embodiments of the method, some described steps may be replaced, eliminated, or moved around. For simplicity, not all steps are described in detail herein. Furthermore, throughout this application and across different embodiments, the same reference numerals denote the same components having similar structures and compositions, unless otherwise stated. To avoid ambiguity, the X, Y, and Z directions in the figures are perpendicular to each other and are used consistently.

[0023] Figure 1 An exemplary semiconductor device (e.g., C-FET) 10 is depicted. The semiconductor device 10 includes a lower device 10L (e.g., a p-type transistor) and an upper device 10U (e.g., an n-type transistor) above the lower device 10L. The lower device 10L includes a channel layer 26'L enclosed by a bottom gate structure 72. The bottom gate structure 72 includes a gate dielectric layer 78 and a gate electrode 80L. The lower device 10L also includes a source / drain component (e.g., a p-type epitaxial source / drain component) 62L coupled to the channel layer 26'L and adjacent to the bottom gate structure 72.

[0024] The upper device 10U includes a channel layer 26'U enclosed by an upper gate structure 74. The upper gate structure 74 includes a gate dielectric layer 78 and a gate electrode 80U. The upper device 10U also includes a source / drain component (e.g., an n-type epitaxial source / drain component) 62U coupled to the channel layer 26'U and adjacent to the upper gate structure 74. An isolation layer 90 is disposed between the upper device 10U and the lower device 10L to electrically insulate the upper gate structure 74 of the upper device 10U from the bottom gate structure 72 of the lower device 10L. The configuration of the elements in the semiconductor device 10 described above is given for illustrative purposes and can be modified depending on the actual implementation. It should be understood that some components have been omitted in this figure for simplicity.

[0025] Now for reference Figure 2 and Figure 3Method 100 includes block 102, wherein a superlattice structure 204 is formed over a substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figures, the substrate 202 may include n-type well regions and p-type well regions for the fabrication of transistors of different conductivity types. When present, each of the n-type and p-type wells is formed in the substrate 202 and includes a doping distribution. n-type wells may include a doping distribution of n-type dopants, such as phosphorus (P) or arsenic (As). p-type wells may include a doping distribution of p-type dopants, such as boron (B). The doping in the n-type and p-type wells may be formed using ion implantation or thermal diffusion and may be considered as part of the substrate 202.

[0026] A superlattice structure 204 is formed above a substrate 202. The superlattice structure 204 can be deposited above the substrate 202 using epitaxial processes. Suitable epitaxial processes include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. For ease of reference, the superlattice structure 204 can be vertically divided into a bottom portion 204B, an intermediate sacrificial layer 206M on the bottom portion 204B, and a top portion 204T on the intermediate sacrificial layer 206M.

[0027] The bottom portion 204B includes multiple first channel layers (e.g., first channel layers 208L1, 208L2, 208L3) interleaved with multiple first sacrificial layers (e.g., first sacrificial layers 206L1, 206L2, 206L3). The first channel layers 208L1, 208L2, 208L3 may be individually or collectively referred to as the first channel layer 208L. The first sacrificial layers 206L1, 206L2, 206L3 may be individually or collectively referred to as the first sacrificial layer 206L. The first sacrificial layer 206L and the first channel layer 208L are deposited alternately, one after the other, to form the bottom portion 204B of the superlattice structure 204. The first sacrificial layer 206L and the first channel layer 208L may have different semiconductor compositions. In some embodiments, the first channel layer 208L is formed of silicon (Si), and the first sacrificial layer 206L is formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the first sacrificial layer 206L allows for the selective removal or recessing of the first sacrificial layer 206L without causing substantial damage to the first channel layer 208L.

[0028] The top portion 204T includes multiple second channel layers (e.g., second channel layers 208U1, 208U2, 208U3) interleaved with multiple second sacrificial layers (e.g., second sacrificial layers 206U1, 206U2). Second channel layers 208U1, 208U2, and 208U3 may be individually or collectively referred to as second channel layer 208U. Second sacrificial layers 206U1 and 206U2 may be individually or collectively referred to as second sacrificial layer 206U. Second sacrificial layer 206U and second channel layer 208U are deposited alternately, one after the other, to form the top portion of the superlattice structure 204. Second sacrificial layer 206U and second channel layer 208U may have different semiconductor compositions. In some embodiments, second channel layer 208U is formed of silicon (Si), and second sacrificial layer 206U is formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the second sacrificial layer 206U allows for selective removal or recessing of the second sacrificial layer 206U without causing substantial damage to the second channel layer 208U. Channel layers 208L1, 208L2, 208L3, 208U1, 208U2, and 208U3 will provide nanostructures for C-FETs. In some embodiments, channel layers 208U1-208U2 will provide channel components for top GAA transistors in C-FETs, and channel layers 208L2-208L3 will provide channel components for bottom GAA transistors in C-FETs. The term "channel component" is used herein to refer to any portion of material used for a channel in a transistor having nanoscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion.

[0029] In some prior art techniques for forming C-FETs, the sacrificial layer 206 has an identical configuration (e.g., thickness, composition). In this embodiment, to optimize C-FET performance, the second sacrificial layer 206U and the first sacrificial layer 206L are configured with different germanium concentrations. The germanium concentration will result in different etch rates during subsequent etch processes, and thus different gate lengths. In the illustrated embodiment, the first sacrificial layer 206L has a first germanium content. In this embodiment, the first germanium content of the first sacrificial layer 206L is between about 5% and about 45%. If the first germanium content is less than 5%, an extended etch duration can be applied to remove the first sacrificial layer 206L during a subsequent channel release process, which may damage other components adjacent to the sacrificial layer. Furthermore, a low germanium content may result in low etch selectivity between the first sacrificial layer 206L and the first channel layer 208L. That is, the first sacrificial layer 206L may not be selectively removed even if the first channel layer 208L is not etched substantially, resulting in a reduced junction coverage area and increased parasitic resistance. If the first germanium content is greater than 45%, more germanium will diffuse into the first channel layer 208L, increasing the impurity concentration in the first channel layer 208L and degrading device performance. To achieve the etching rate difference described above, the second sacrificial layer 206U has a second germanium content greater than the first germanium content. In an embodiment, the second germanium content of the second sacrificial layer 206U is between about 10% and about 50%.

[0030] In this embodiment, etch selectivity also exists between the intermediate sacrificial layer 206M and the first sacrificial layer 206L, and also between the intermediate sacrificial layer 206M and the second sacrificial layer 206U. In this embodiment, the intermediate sacrificial layer 206M is formed of silicon-germanium, and the germanium content of the intermediate sacrificial layer 206M may differ from the first germanium content of the first sacrificial layer 206L and the second germanium content of the second sacrificial layer 206U, respectively. In this embodiment, the intermediate sacrificial layer 206M has a third germanium content greater than the first and second germanium contents. The third germanium content is between about 30% and about 100%. If the third germanium content is less than 30%, the etch selectivity between the intermediate sacrificial layer 206M and the other layers of the superlattice structure 204 may be too low to ensure complete and selective removal of the intermediate sacrificial layer 206M without substantially etching the channel layers 208U and 208L.

[0031] In some embodiments, the bottommost channel layer 208L3 of the first channel layer 208L has a thickness T1, and the topmost channel layer 208U1 of the second channel layer 208U has a thickness T2. Each of the thicknesses T1 and T2 is in the range of about 3 nm to about 30 nm. If the thickness T1 or T2 is greater than 30 nm, the aspect ratio of the superlattice structure 204 may increase, leading to increased process challenges. Furthermore, the parasitic capacitance associated with the semiconductor device 200 may also increase, which will adversely affect the performance of the semiconductor device 200; if the thickness T1 or T2 is less than 3 nm, the reduced thickness of the channel layers 208 (e.g., the first channel layer 208L and / or the second channel layer 208U) may increase the epitaxial difficulty for forming satisfactory layers in the superlattice structure 204. Each of the first sacrificial layers 206L has a thickness T3, and each of the second sacrificial layers 206U has a thickness T4. Each of the thicknesses T3 and T4 is in the range of about 2 nm to about 30 nm. If the thickness T3 or T4 is greater than 30 nm, the aspect ratio of the superlattice structure 204 may increase, leading to increased process challenges. Furthermore, the parasitic capacitance associated with the semiconductor device 200 may also increase, which will adversely affect the performance of the semiconductor device 200. If the thickness T3 or T4 is less than 2 nm, the reduced thickness of the sacrificial layer 206 (e.g., the first sacrificial layer 206L and / or the second sacrificial layer 206U) can reduce the process window for forming a satisfactory gate structure encapsulating the nanostructure. The intermediate sacrificial layer 206M has a thickness T5. The thickness T5 is in the range of about 2 nm to about 30 nm. If the thickness T5 is greater than 30 nm, the aspect ratio of the superlattice structure 204 may increase, leading to increased process challenges; if the thickness T5 is less than 2 nm, the reduced thickness of the intermediate sacrificial layer 206M can reduce the process window for forming an isolation layer disposed between the gate structure of the upper device and the gate structure of the lower device. In the illustrated embodiment, the topmost channel layer 208L1 of the first channel layer 208L and the bottommost channel layer 208U3 of the second channel layer 208U are in direct contact with the intermediate sacrificial layer 206M and will be released during subsequent fabrication processes to form nanostructures 2080N1 and 2080N2. The topmost channel layer 208L1 has a thickness T6. The bottommost channel layer 208U3 has a thickness T7. Thicknesses T6 and T7 can be less than thickness T1. In this embodiment, each of thicknesses T6 and T7 is less than about 10 nm (e.g., 0 ≤ T6 ≤ 10 nm; 0 ≤ T7 ≤ 10 nm). If thicknesses T6 or T7 are greater than 10 nm, the aspect ratio of the superlattice structure 204 may increase, leading to increased process challenges. Furthermore, the parasitic capacitance associated with the semiconductor device 200 may also increase, which will adversely affect the performance of the semiconductor device 200.

[0032] It should be pointed out that, Figure 3The superlattice structure 204 includes six (6) layers of channel layers 208 interleaved with six (6) layers of sacrificial layer 206, this is for illustrative purposes only and is not intended to limit the scope beyond what is specifically enumerated in the claims. It will be understood that any number of channel layers 208 may be included in the superlattice structure 204 and distributed within the bottom portion 204B and the top portion 204T. The number of layers depends on the desired number of channel components for the top GAA transistor and the bottom GAA transistor. In some embodiments, the number of channel layers 208 in the superlattice structure 204 may be between 2 and 10.

[0033] Now for reference Figure 4 and Figure 5 Method 100 includes a frame 104 in which a superlattice structure 204 and a top portion 202t of a substrate 202 are patterned to form a fin structure 210. Figure 4 A cross-sectional view of the intermediate structure 200 is depicted, and Figure 5 Depicting along Figure 4 The diagram shows a cross-sectional view of the intermediate structure 200 taken by line AA. After forming the superlattice structure 204, the superlattice structure 204 and the top portion 202t are then patterned to form a fin structure 210. The patterned portion of the substrate 202 may be referred to as a protrusion 202t, a mesa 202t, or a base fin 202t. For patterning purposes, a hard mask layer may be deposited over the superlattice structure 204. The hard mask layer may be a single layer or multiple layers. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer above the silicon oxide layer. Figures 4 to 5 As shown, each fin structure 210 extends vertically from the substrate 202 along the Z direction and longitudinally along the X direction. The fin structures 210 can be patterned using suitable processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels can then be used as an etching mask to etch the superlattice structure 204 and the substrate 202 to form the fin structure 210.

[0034] The intermediate structure 200 also includes an isolation component 212 formed around the fin structure 210. Figure 4As shown in the diagram, this is used to separate two adjacent fin structures 210. The isolation component 212 may also be referred to as a shallow trench isolation (STI) component 212. In an exemplary process, dielectric material for the isolation component 212 is deposited over the intermediate structure 200 (including the fin structures 210) using CVD, subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed to form the isolation component 212. Figure 4 As shown, the fin structure 210 rises above the isolation member 212. The dielectric material used for the isolation member 212 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0035] refer to Figure 2 and Figure 6Method 100 includes block 106, wherein a dummy gate stack 214 is formed over the channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 214 serves as a placeholder structure for the functional gate structure. Other processes and configurations are also possible. To form the dummy gate stack 214, a dummy dielectric layer 216, a dummy gate electrode layer 218, and a gate top hard mask layer 220 are deposited over the intermediate structure 200. The deposition of these layers may include using chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, other suitable deposition techniques, and / or combinations thereof. The dummy dielectric layer 216 may include silicon oxide, the dummy gate electrode layer 218 may include polysilicon, and the gate top hard mask layer 220 may be a multilayer structure including silicon oxide and silicon nitride. The gate top hard mask layer 220 is patterned using photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The etching process may include dry etching, wet etching, and / or other etching methods. Like the fin structure 210, the dummy gate stack 214 may also be patterned using dual patterning or multiple patterning techniques. Subsequently, using the patterned gate top hard mask 220 as an etching mask, the dummy dielectric layer 216 and the dummy gate electrode layer 218 are etched to form the dummy gate stack 214. The dummy gate stack 214 extends longitudinally along the Y direction to wrap over the fin structure 210 and rests on the isolation member 212. The portion of the fin structure 210 located below the dummy gate stack 214 defines a channel region 210C. The channel region 210C and the dummy gate stack 214 also define a source / drain region 210SD that does not vertically overlap with the dummy gate stack 214. The channel region 210C is disposed between the two source / drain regions 210SD along the Y direction. The source / drain regions may refer to a source region for forming a source and / or a drain region for forming a drain, individually or collectively, depending on the context.

[0036] Still referencing Figure 2 and Figure 6Method 100 includes block 108, wherein the source / drain region 210SD of the fin structure 210 is recessed to form a trench 224. The operation in block 108 may include forming at least one gate spacer 222 over the sidewalls of the dummy gate stack 214 before recessing the source / drain region 210SD. In some embodiments, forming at least one gate spacer 222 includes depositing one or more dielectric layers over the intermediate structure 200. In exemplary processes, the one or more dielectric layers are conformally deposited using CVD, SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, and / or combinations thereof. In some embodiments, the fin sidewall spacer 222' ( Figure 10 (As shown) can also be formed together with gate spacer 222. Fin sidewall spacer 222' and gate spacer 222 have the same composition. After forming gate spacer 222, an anisotropic etching process is performed on intermediate structure 200 to form trench 224. The etching process in block 108 can be a dry etching process or other suitable etching process. Exemplary dry etching processes can be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. Figure 6 As shown, the sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region 210C are exposed in the trench 224. In this embodiment, the trench 224 has substantially straight sidewalls. That is, after the trench 224 is formed, the channel layer 208 and the sacrificial layer 206 can have substantially uniform widths.

[0037] refer to Figure 2 and Figures 7 to 8 Method 100 includes a frame 110 in which an internal spacer component 226 is formed. (See reference) Figure 7In block 110, an etching process is performed to selectively and partially recess the sacrificial layer 206 exposed in trench 224 to form internal spacer recesses 225 without substantially etching the exposed channel layer 208. In this embodiment, the second sacrificial layer 206U has a second germanium content greater than the first sacrificial layer 206L, and the etchant of the etching process etches the second sacrificial layer 206U at a higher rate than it etches the first sacrificial layer 206L. In some embodiments, the etching process may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree to which the first sacrificial layer 206L and the second sacrificial layer 206U are recessed is controlled by the duration of the etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include the use of hydrogen fluoride (HF) or ammonium hydroxide (NH4OH). In the illustrated embodiment, the internal spacer recess 225 includes an internal spacer recess 225a disposed between channel layers 208U1 and 208U2, an internal spacer recess 225b disposed between channel layers 208U2 and 208U3, an internal spacer recess 225c disposed between channel layers 208L1 and 208L2, an internal spacer recess 225d disposed between channel layers 208L2 and 208L3, and an internal spacer recess 225e disposed between channel layer 208L3 and substrate 202. Internal spacer recesses 225a and 225b are formed above the intermediate sacrificial layer 206M, and internal spacer recesses 225c, 225d, and 225e are formed below the intermediate sacrificial layer 206M. During the etching process, internal spacer recesses 225c / 225d / 225e span a first width W1, and internal spacer recesses 225a / 225b span a second width W2 greater than the width W1. Similarly, the recessed first sacrificial layer 206L has a width greater than that of the recessed second sacrificial layer 206U.

[0038] refer to Figure 8 After forming the internal spacer recess 225, an internal spacer material layer is deposited over the intermediate structure 200 (including within the internal spacer recess 225). The internal spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited internal spacer material layer is then etched back to remove excess portions of the internal spacer material layer above the sidewalls of the dummy gate stack 214, gate spacer 222, and channel layer 208, thereby forming... Figure 8The internal spacer component 226 is shown. The internal spacer component 226 follows the shape of the internal spacer recess 225. In this embodiment, the internal spacer component 226 includes an internal spacer component 226a formed in the internal spacer recess 225a, an internal spacer component 226b formed in the internal spacer recess 225b, an internal spacer component 226c formed in the internal spacer recess 225c, an internal spacer component 226d formed in the internal spacer recess 225d, and an internal spacer component 226e formed in the internal spacer recess 225e. The internal spacer components 226a / 226b have a width W2, and the internal spacer components 226c / 226d / 226e have a width W1 that is smaller than the width W2.

[0039] As by Figure 7 and Figure 8 This indicates that the intermediate sacrificial layer 206M is also replaced by the intermediate dielectric layer 226M. In this illustrated embodiment, the intermediate sacrificial layer 206M remains unetched during the formation of the inner spacer recess 225. This can be achieved by selectively forming an inhibitor layer covering the exposed sidewalls of the intermediate sacrificial layer 206M. The inhibitor layer can be removed after the formation of the inner spacer component 226. Another etching process can then be performed to selectively remove the intermediate sacrificial layer 206M. Dielectric material can then be deposited in the spacer left by the selective removal of the intermediate sacrificial layer 206M to form the intermediate dielectric layer 226M. The intermediate dielectric layer 226M and the inner spacer component 226 can have the same composition or can be formed from different compositions. In some alternative embodiments, no inhibitor layer is formed to cover the exposed sidewalls of the intermediate sacrificial layer 206M during the formation of the inner spacer recess 225. The intermediate sacrificial layer 206M can be substantially removed during the formation of the inner spacer recess 225 (due to its higher germanium content). The internal spacer material layer can also be deposited in the spacers left by selectively removing the intermediate sacrificial layer 206M, thereby forming the intermediate dielectric layer 226M.

[0040] Still referencing Figure 2 and Figure 8Method 100 includes block 112, wherein a bottom source / drain component 230 is formed in trench 224. In some embodiments, prior to depositing the bottom source / drain component 230, a barrier layer (not shown) may be deposited over intermediate structure 200 to cover the sidewalls of the top portion 204T of superlattice structure 204. The barrier layer may also cover the sidewalls of intermediate dielectric layer 226M and channel layer 208L1. The barrier layer may include a dielectric material. After forming the barrier layer, the bottom source / drain component 230 may be formed using epitaxial processes such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process may use a gas and / or liquid precursor that interacts with the composition of substrate 202 and the channel layer 208 not covered by the barrier layer. In this embodiment, epitaxial growth of the bottom source / drain component 230 may occur from the top surface of substrate 202 and the exposed sidewalls of channel layers 208L2 and 208L3. A barrier layer (due to its dielectric composition) blocks the bottom source / drain components 230 formed on the sidewalls of channel layers 208U1-208U3 and 208L1. Figure 8 As shown, the bottom source / drain component 230 is physically contacted (or adjacent to) the channel layers 208L2 and 208L3. Depending on the design, the bottom source / drain component 230 can be n-type or p-type. In the depicted embodiment, the bottom source / drain component 230 is a p-type source / drain component and may comprise germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be doped in situ during the epitaxial process by introducing a p-type dopant (such as boron or gallium) or ex-situ using a junction implantation process. In some instances, an undoped semiconductor layer 228 (e.g., undoped silicon or undoped silicon-germanium) may be formed to fill the bottom portion of the trench 224 before the bottom source / drain component 230 is formed in the trench 224.

[0041] Still referencing Figure 2 and Figure 8Method 100 includes block 114, wherein a bottom contact etch stop layer (CESL) 232 and a bottom interlayer dielectric (ILD) layer 234 are formed over a bottom source / drain component 230. The bottom CESL 232 may comprise silicon nitride, silicon carbonitride, and / or other materials, and may be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In an embodiment, the bottom CESL 232 comprises silicon nitride. In some embodiments, the bottom CESL 232 is first conformally deposited on an intermediate structure 200, and the bottom ILD layer 234 is deposited over the bottom CESL 232 by spin coating, flowable CVD (FCVD), CVD, or other suitable deposition techniques. The bottom ILD layer 234 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The bottom CESL 232 and bottom ILD layer 234 may be etched back to the exposed sidewalls of the channel layers 208U1 and 208U2. Figure 8 In the illustrated embodiment, after etchback, the bottom CESL 232 is in direct contact with the internal spacer components 226b-226c, channel layers 208U3 and 208L1, and the intermediate dielectric layer 226M. The barrier layer can be removed during etchback of the bottom CESL 232 and the bottom ILD layer 234.

[0042] Still referencing Figure 2 and Figure 8Method 100 includes a frame 116 in which a top source / drain component 248 is formed over a bottom CESL 232 and a bottom ILD layer 234. The top source / drain component 248 can be formed using epitaxial processes such as VPE, UHV-CVD, molecular beam epitaxy, and / or other suitable processes. The epitaxial growth process can use a gaseous and / or liquid precursor that interacts with the composition of the channel layers (e.g., channel layers 208U1 and 208U2) of the top portion 204T of the superlattice structure 204. Epitaxial growth of the top source / drain component 248 can occur from the exposed sidewalls of the channel layers 208U1 and 208U2. The deposited top source / drain component 248 is in physical contact (or adjacent) to the channel layers of the top portion 204T of the superlattice structure 204. Depending on the design, the top source / drain component 248 can be n-type or p-type. In the depicted embodiment, the top source / drain component 248 is an n-type source / drain component and may comprise silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials. It may be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus, arsenic, or antimony) or ex-situ doped using a junction implantation process. In some embodiments, prior to forming the top source / drain component 248, another dielectric layer (e.g., silicon nitride) may be formed over the bottom CESL 232 and the bottom ILD layer 234. This other dielectric layer may be vertically sandwiched between the top source / drain component 248 and the bottom CESL 232 and the bottom ILD layer 234.

[0043] Still referencing Figure 2 and Figure 8Method 100 includes block 118, wherein a top CESL 250 and a top ILD layer 252 are deposited over a top source / drain component 248. The top CESL 250 may comprise silicon nitride, silicon carbonitride, and / or other materials known in the art, and may be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes and / or other suitable deposition or oxidation processes. In some embodiments, the top CESL 250 is first conformally deposited on the intermediate structure 200, and then the top ILD layer 252 is deposited over the top CESL 250 by spin coating, FCVD, CVD, or other suitable deposition techniques. The top ILD layer 252 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the top ILD layer 252, the intermediate structure 200 may be annealed to improve the integrity of the top ILD layer 252. To remove excess material and expose the top surface of the dummy gate electrode layer 218, a planarization process, such as a chemical mechanical polishing (CMP) process, may be implemented.

[0044] Now for reference Figure 2 and Figures 9 to 10 Method 100 includes block 120, wherein the dummy gate stack 214 and the sacrificial layer 206 are replaced by a gate structure. Figure 10 Depicting along Figure 9 The diagram shows a partial cross-sectional view of the intermediate structure 200 taken by line BB. Operations in block 120 may include: removing the dummy gate stack 214; releasing the channel layer 208 as channel members (including top channel members 2080U1, 2080U2 and bottom channel members 2080L1 and 2080L2) and nanostructures (including nanostructures 2080N1 and 2080N2). Removing the dummy gate stack 214 may include one or more etching processes selectively applied to the material in the dummy gate stack 214. For example, removing the dummy gate stack 214 may be implemented using selective wet etching, selective dry etching, or combinations thereof. Selective removal of the dummy gate stack 214 forms a gate trench (now filled by the outer portion 254O of the top gate structure 254T).

[0045] After removing the dummy gate stack 214, the sidewalls of the channel layer 208 and sacrificial layer 206 in the channel region 210C are exposed. Subsequently, the sacrificial layer 206 in the channel region 210C is selectively removed to release the channel layer 208 as channel components (including top channel components 2080U1, 2080U2, bottom channel components 2080L1 and 2080L2) and nanostructures (including nanostructures 2080N1 and 2080N2). Figure 9 In the illustrated embodiment, the top channel components 2080U1 and 2080U2 are in direct contact with the top source / drain component 248; the bottom channel components 2080L1 and 2080L2 are in direct contact with the bottom source / drain component 230; and the nanostructures 2080N1, 2080N2 and the intermediate dielectric layer 226M are in direct contact with the bottom CESL 232.

[0046] Selectively removing the first sacrificial layer 206L forms a first gate opening (now filled by the bottom gate structure 254B), and selectively removing the second sacrificial layer 206U forms a second gate opening (now filled by the inner portion 254I of the top gate structure 254T). The first gate opening spans a width greater than the width of the second gate opening. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some other embodiments, selective removal includes SiGe oxidation followed by silicon germanium oxide removal. For example, oxidation can be provided by ozone cleaning, and then the silicon germanium oxide is removed by an etchant such as NH4OH.

[0047] Then, a bottom gate structure 254B is formed in the first gate opening and adjacent to the bottom source / drain component 230, and a top gate structure 254T is formed in the second gate opening and adjacent to the top source / drain component 248, and is located in the gate trench. The bottom gate structure 254B and the top gate structure 254T may be referred to individually or collectively as gate structure 254. The bottom gate structure 254B is formed to enclose each of the bottom channel components 2080L1 and 2080L2, thereby forming a bottom multi-gate transistor 260B (e.g., similar to...). Figure 1 The device 10L in the middle is formed, and the top gate structure 254T is formed to enclose each of the top channel members 2080U1 and 2080U2, thereby forming a top multi-gate transistor 260T disposed above the bottom multi-gate transistor 260B (e.g., similar to the device 10L in the middle), and the top gate structure 254T is formed to enclose each of the top channel members 2080U1 and 2080U2, thereby forming a top multi-gate transistor 260T disposed above the bottom multi-gate transistor 260B (e.g., similar to the device 10L in the middle). Figure 1 (The device 10U in the middle).

[0048] Forming the bottom gate structure 254B and the top gate structure 254T includes forming a bottom gate dielectric layer 254a surrounding the channel members 2080L1 and 2080L2 and a top gate dielectric layer 254b surrounding the channel members 2080U1 and 2080U2. In an embodiment, the bottom gate dielectric layer 254a and the top gate dielectric layer 254b are formed simultaneously and have the same composition. For example, each of the bottom gate dielectric layer 254a and the top gate dielectric layer 254b includes an interface layer (not shown separately) and a high-k dielectric layer (not shown separately) above the interface layer. The interface layer may be formed over the channel members 2080U1-2080U2, 2080L1-2080L2 and the nanostructures 2080N1-2080N2, and covers the top and sidewall surfaces of the protrusion 202t. The interface layer can be formed by thermal oxidation, chemical oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), other suitable processes, or combinations thereof. In embodiments where the interface layer is formed by thermal oxidation, the interface layer is formed on a semiconductor surface (e.g., channel members 2080U1-2080U2, 2080L1-2080L2, and nanostructures 2080N1-2080N2) rather than a dielectric surface (e.g., isolation member 212). In some other embodiments, the interface layer can be conformally deposited over the substrate 202, including the isolation member 212. The interface layer comprises a dielectric material such as SiO2, SiGeO2, etc. xHigh-k dielectric layers may include HfSiO, SiON, other dielectric materials, or combinations thereof. In some embodiments, the interface layer is a group IV-based oxide layer, which generally refers to an oxide of a group IV-based material (i.e., a material comprising at least one group IV element (such as Si, Ge, C, etc.)). In some embodiments, the interface layer is a group III-V-based oxide layer, which generally refers to an oxide of a group III-V-based material (i.e., a material comprising at least one group III element (such as Al, Ga, In, B, etc.) and at least one group V element (such as N, P, As, Sb, etc.)). High-k dielectric layers may include dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide. Exemplary high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable components, or combinations thereof. In some embodiments, the high-k dielectric layer may include a high-k dielectric material, including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, other suitable high-k dielectric materials, or combinations thereof. Forming the bottom gate structure 254B and the top gate structure 254T also includes forming a bottom gate electrode 254c for the bottom gate structure 254B and a top gate electrode 254d for the top gate structure 254T. Each of the bottom gate electrode 254c and the top gate electrode 254d may include one or more power function layers with appropriate power functions, thereby enhancing the device performance of the corresponding transistor (e.g., reducing the threshold voltage).

[0049] In an embodiment where the bottom multi-gate transistor 260B is a p-type transistor and the top multi-gate transistor 260T is an n-type transistor, the bottom gate electrode 254c includes a p-type work function layer, and the top gate electrode 254d includes an n-type work function layer. The n-type work function layer may include a titanium-aluminum based metal, such as titanium aluminum carbon (TiAlC) or titanium aluminum (TiAl). The p-type work function layer may include titanium nitride (TiN), tungsten carbonitride (WCN), tantalum nitride (TaN), or molybdenum nitride (MoN). The gate electrodes 254c / 254d may also include a metal filler layer, including aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof.

[0050] The bottom gate structure 254B has a first gate length Lg1 along the X direction, and the inner portion 254I of the top gate structure 254T has a second gate length Lg2 that is less than the first gate length Lg1. In an embodiment, the ratio of the second gate length Lg2 to the first gate length Lg1 is greater than 0.3 and less than 1. If the ratio is less than 0.3, the inner portion 254I of the top gate structure 254T may be too short, resulting in weak gate control and increased leakage current. By forming gate structures with different gate lengths (Lg1, Lg2), the performance of the top multi-gate transistor 260T and the bottom multi-gate transistor 260B can be adjusted. Generally, the performance of a transistor with a longer gate length may be weaker than that of a transistor with a shorter gate length. In an embodiment, the bottom multi-gate transistor 260B is a p-type transistor, and the top multi-gate transistor 260T is an n-type transistor, and the performance of the bottom multi-gate transistor 260B is weaker than that of the top multi-gate transistor 260T.

[0051] Still referencing Figure 2 and Figure 9 Method 100 includes block 122, in which further processes are performed to complete the fabrication of semiconductor device 200. Such further processes may include forming a dielectric capping layer 255 over the top gate structure 254T. Such further processes may also include forming a silicide layer over the top source / drain components and forming a multilayer interconnect (MLI) structure over the intermediate structure 200. The MLI structure may include various interconnect components, such as vias and wires, disposed in dielectric layers (such as etch stop layers and ILD layers). In some embodiments, vias are vertical interconnect components configured as interconnect device level contacts, such as source / drain contacts formed over the top source / drain components 248. Other processes may be further implemented.

[0052] Method 100 can be applied to form an IC structure 300 with improved performance (e.g., enhanced speed, reduced power consumption, or a reduced performance difference between NFETs and PFETs). For example, semiconductor device 200 is part of IC structure 300. (Reference) Figure 11 , Figures 12A to 12B and Figure 13 The IC structure 300 includes at least an array of memory cells. The array may include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NVRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. In an embodiment, the array includes multiple SRAM cells, which typically provide memory or storage space capable of retaining data when powered on. In this embodiment, each SRAM cell includes one or more C-FETs 200 as described above.

[0053] Figure 11 An exemplary circuit diagram for a single-port SRAM cell (e.g., a 1-bit SRAM cell) is shown. The single-port SRAM cell includes pull-up transistors PU-1 and PU-2; pull-down transistors PD-1 and PD-2; and transmission gate transistors PG-1 and PG-2. As shown in the circuit diagram, transistors PU-1 and PU-2 are P-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are N-type transistors. The drains of pull-up transistors PU-1 and PD-1 are coupled together, and the drains of pull-up transistors PU-2 and PD-2 are coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a first data latch. The gates of transistors PU-2 and PD-2 are coupled together and to the drains of transistors PU-1 and PD-1 to form a first memory node SN1. The gates of transistors PU-1 and PD-1 are coupled together and to the drains of transistors PU-2 and PD-2 to form a complementary first memory node SNB1. The sources of pull-up transistors PU-1 and PU-2 are coupled to the power supply voltage Vdd, and the sources of pull-down transistors PD-1 and PD-2 are coupled to voltage Vss, which may be electrically grounded in some embodiments. The first memory node SN1 of the first data latch is coupled to the bit line BL through a transmission gate transistor PG-1, and the complementary first memory node SNB1 is coupled to the complementary bit line BLB through a transmission gate transistor PG-2. The first memory node SN1 and the complementary first memory node SNB1 are complementary nodes that are typically at opposite logic levels (logic high or logic low). The gates of transmission gate transistors PG-1 and PG-2 are coupled to the word line WL. In this embodiment, the p-type transistors (e.g., PU-1, PU-2) have a gate length that is greater than that of the n-type transistors (e.g., PD-1, PD-2, PG-1, PG-2).

[0054] In this embodiment, the SRAM cell is a C-FET-based SRAM cell. Figure 12A The partial front layout of the SRAM cells in IC structure 300 is shown. Figure 12BA partial back-side layout of the SRAM cell of IC structure 300 is shown. The SRAM cell includes an active region 305a disposed in each p-type doped region and an active region 305b disposed in each n-type doped region. After the channel release process, the active regions 305a and 305b can resemble active region 210. The SRAM cell of IC structure 300 includes gate structures 310a, 310b, 310c, and 310d that enclose the channel regions of the active regions 305a and 305b to form individual transistors such as pull-down transistors PD-1 and PD-2, pull-up transistors PU-1 and PU-2, and transmission gate transistors PG-1 and PG-2. Gate structure 310a and active region 305a form part of pull-down transistor PD-1, gate structure 310b and active region 305a form part of transfer gate transistor PG-1, gate structure 310a and active region 305b form part of transfer gate transistor PG-2, and gate structure 310b and active region 305b form part of pull-down transistor PD-2. Gate structure 310c and active region 305a form part of pull-up transistor PU-1, and gate structure 310d and active region 305b form part of pull-up transistor PU-2. Each of gate structures 310a and 310b may be similar to top gate structure 254T, and each of gate structures 310c and 310d may be similar to bottom gate structure 254B. The SRAM cell has cell 380. IC structure 300 also includes a plurality of gate isolation components 390 configured to cut at least one of gate structures 310a-310d into physically and electrically isolated segments.

[0055] Figure 13 Depicting along Figures 12A to 12B The diagram shown is a partial cross-sectional view of the SRAM cell of IC structure 300, taken by line CC. (As shown by...) Figure 13 This indicates that pull-down transistor PD-1 is formed above pull-up transistor PU-1. Pull-down transistor PD-1 and transfer gate transistor PG-1 are similar to top multi-gate transistor 260T, and pull-up transistor PU-1 is similar to bottom multi-gate transistor 260B. That is, the gate lengths of transfer gate transistor PG-1 and pull-down transistor PD-1 are smaller than the gate length of pull-up transistor PU-1.

[0056] By reducing the gate lengths of transmission gate transistors PG-1 and PG-2 and pull-down transistors PD-1 and PD-2, the saturation current Isat of transmission gate transistors PG-1 and PG-2 can be reduced. Therefore, the "α ratio" of the saturation current (which is the ratio of the saturation current Isat of the pull-up transistors to the saturation current Isat of the transmission gate transistors) can be increased to obtain a wider write window and thus better write margin.

[0057] Reference Figures 3 to 13 In the embodiments described above, the first sacrificial layer 206L of the superlattice structure 204 has a germanium content lower than that of the second sacrificial layer 206U, and the resulting semiconductor device 200 and IC structure 300 include a C-FET having a top multi-gate device and a bottom multi-gate device, wherein the gate length Lg1 of the gate structure of the bottom multi-gate device is greater than the gate length Lg2 of the gate structure of the top multi-gate device. The top multi-gate device can be an n-type device or a p-type device, and the bottom multi-gate device can be a p-type device or an n-type device. Figure 14 In another alternative embodiment, the first sacrificial layer 206L of the superlattice structure 204 has a greater germanium content than the second sacrificial layer 206U, and the resulting semiconductor device 400 includes a C-FET having a top multi-gate device 260T' and a bottom multi-gate device 260B', wherein the gate length Lg1' of the gate structure 254B' of the bottom multi-gate device 260B' is less than the gate length Lg2' of the inner portion 254I' of the gate structure 254T' of the top multi-gate device 260T'. The ratio of gate length Lg2' to gate length Lg1' is greater than 1 and less than 3. If the ratio is greater than 0.3, the bottom gate structure may be too short, resulting in weak gate control and increased leakage current. The top multi-gate device 260T' can be an n-type device or a p-type device, and the bottom multi-gate device 260B' can be a p-type device or an n-type device. In this embodiment, the semiconductor device 400 includes an n-type top multi-gate device 260T' and a p-type bottom multi-gate device 260B'. Compared to existing C-FETs with the same gate length for both bottom-gate and top-gate devices, the n-type top-gate device 260T' with an increased gate length Lg2' can consume less power than existing C-FET n-type top-gate devices. Semiconductor device 400 also includes internal spacer components 226', and the internal spacer components 226a'-226b' formed above the intermediate dielectric layer 226M have a width W2 smaller than the width W1 of the internal spacer components 226c', 226d', and 226e' formed below the intermediate dielectric layer 226M. Other components of semiconductor device 400 similar to those of semiconductor device 200 are indicated by the same reference numerals, and for simplicity, redundant descriptions of those similar components are omitted.

[0058] In an embodiment, semiconductor device 400 may be a portion comprising a logic cell (e.g., a NOR gate) including one or more C-FETs. A path is defined as wiring that distributes signals within a circuit. A critical path is where the primary control depends on the circuit speed (or signal distribution speed) depending on the specific circuit application. A path is called a critical path if the circuit speed varies significantly with transistor performance; a path is called a non-critical path if the circuit speed is substantially independent of transistor performance. It is advantageous to have different configurations for critical and non-critical paths during field operation to reduce power consumption while maintaining satisfactory circuit speed. In an embodiment, to achieve lower power consumption, the n-type transistors in the non-critical path may be configured similarly to the top multi-gate device 260T' of semiconductor device 400, and the p-type transistors in the critical path may be configured similarly to the bottom multi-gate device 260B' of semiconductor device 400. Other suitable applications are also possible.

[0059] In the above embodiments, the performance of the C-FET is optimized by separately optimizing the gate lengths of the top multi-gate device and the bottom multi-gate device. In another embodiment, the performance of the C-FET can be optimized by separately optimizing the channel thickness of the top multi-gate device and the bottom multi-gate device. Figure 15 A flowchart illustrating a method 500 for forming a semiconductor device 600 including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure, is shown. Figures 16 to 20 Description method 500, Figures 16 to 20 This is a partial cross-sectional view of the semiconductor device 600 at different manufacturing stages according to an embodiment of method 500.

[0060] Now for reference Figure 15 and Figure 16Method 500 includes a frame 502 in which a superlattice structure 604 is formed over a substrate 202. The fabrication process for forming the superlattice structure 604 is the same as that for the superlattice structure 204. Differences between the superlattice structure 604 and the superlattice structure 204 include the dimensional relationships between the different layers within the superlattice structure 604. More specifically, the superlattice structure 604 includes a bottom portion 604B, an intermediate sacrificial layer 606M on the bottom portion 604B, and a top portion 604T on the intermediate sacrificial layer 606M. The bottom portion 604B includes a plurality of first channel layers (e.g., first channel layers 608L1, 608L2, 608L3) interleaved with a plurality of first sacrificial layers (e.g., first sacrificial layers 606L1, 608L2, 608L3). The first channel layers 608L1, 608L2, 608L3 may be individually or collectively referred to as the first channel layer 608L. The first sacrificial layers 606L1, 606L2, and 606L3 may be individually or collectively referred to as the first sacrificial layer 606L. In some embodiments, the first channel layer 608L is formed of silicon (Si), and the first sacrificial layer 606L is formed of silicon germanium (SiGe).

[0061] The top portion 604T includes multiple second channel layers (e.g., second channel layers 608U1, 608U2, 608U3) interleaved with multiple second sacrificial layers (e.g., second sacrificial layers 606U1, 606U2). The second channel layers 608U1, 608U2, and 608U3 may be individually or collectively referred to as the second channel layer 608U. The second sacrificial layers 606U1 and 606U2 may be individually or collectively referred to as the second sacrificial layer 606U. In some embodiments, the second channel layer 608U is formed of silicon (Si), and the second sacrificial layer 606U is formed of silicon germanium (SiGe). In the illustrated embodiment, the first sacrificial layer 606L and the second sacrificial layer 606U have the same germanium content, which is less than the third germanium content of the intermediate sacrificial layer 606M. Channel layers 608L1, 608L2, 608L3, 608U1, 608U2, and 608U3 will provide a nanostructure for the C-FET. In some embodiments, second channel layers 608U1-608U2 will provide a channel component for the top GAA transistor in the C-FET, and channel layers 608L2-608L3 will provide a channel component for the bottom GAA transistor in the C-FET. The term "channel component" is used herein to refer to any portion of material used for a channel in a transistor having nanoscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. In some prior art for forming the C-FET, the first channel layer 608L1 and the second channel layer 608U1 have the same thickness. In this embodiment, to optimize the performance of the C-FET, the first channel layer 608L1 and the second channel layer 608U1 are configured to have different thicknesses. The intermediate sacrificial layer 606M may be the same as the intermediate portion 206M.

[0062] In the illustrated embodiment, each of the first channel layers 608L2-608L3 has a thickness T1', and each of the second channel layers 608U1-608U2 has a thickness T2'. T1' has the same range as the thickness T1, and the thickness T2' is greater than the thickness T1' and less than about 30 nm. In various embodiments, the thickness of the bottommost second channel layer 608U3, which is in direct contact with the intermediate sacrificial layer 606M, can be equal to or less than the thickness T2', and the thickness of the top first channel layer 608L1, which is in direct contact with the intermediate sacrificial layer 606M, can be equal to or less than the thickness T1'. In one embodiment, the thickness of the bottommost second channel layer 608U3 is equal to the thickness of the top first channel layer 608L1. By forming first channel layers 608L1-608L2 and second channel layers 608U1-608U2 with different thicknesses, the channel resistance Rch and short-channel effect of the bottom multi-gate device and the top multi-gate device can be adjusted. Therefore, the performance of bottom multi-gate devices and top multi-gate devices can be optimized separately.

[0063] After the superlattice structure 604 is formed, the operations in blocks 104-122 described above are performed to complete the fabrication of the semiconductor device 600. Figure 17 A partial cross-sectional view of semiconductor device 600 is depicted during operation in blocks 104-122. Semiconductor device 600 is similar to semiconductor device 200. For ease of description, similar and / or identical components between the two semiconductor devices 200 and 600 are indicated by the same reference numerals, and repeated descriptions are omitted for simplicity. The main differences between the two semiconductor devices 200 and 600 are described in detail. The first difference between the two semiconductor devices 200 and 600 includes: the bottom transistor 600B of semiconductor device 600 includes channel layers 6080L1 and 6080L2 each having a wafer height H1; the top transistor 600T of semiconductor device 600 includes channel layers 6080U1 and 6080U2 each having a wafer height H2; and the wafer height H1 is smaller than the wafer height H2. In embodiments, the ratio between wafer height H2 and wafer height H1 is in the range of about 1 to about 3. If the ratio is greater than 3, the gate control capability of the top multi-gate transistor may be too poor, resulting in poor precise control of the drain current, or the channel layer of the bottom multi-gate transistor may be too thin, resulting in high channel resistance for the bottom multi-gate transistor. In one embodiment, the top multi-gate transistor includes an n-type multi-gate transistor, and the bottom multi-gate transistor includes a p-type multi-gate transistor, and the semiconductor device 600 may be part of another SRAM cell of the IC structure 300 described above. That is, the n-type transistor in the other SRAM cell may have a channel layer thicker than that of the p-type transistor in the other SRAM cell. In another embodiment, the top multi-gate transistor includes a p-type multi-gate transistor, and the bottom multi-gate transistor includes an n-type multi-gate transistor.

[0064] The second difference between the two semiconductor devices 200 and 600 includes: semiconductor device 600 also includes nanostructures 6080N1 and 6080N2. Nanostructures 6080N1 and 6080N2 can have different wafer thicknesses. The third difference between the two semiconductor devices 200 and 600 includes: semiconductor device 600 also includes internal spacer components, such as internal spacer components 626a, 626b, 626c, 626d, and 626e. The widths of the internal spacer components 626a-626e of semiconductor device 600 can be substantially the same.

[0065] Reference Figure 17 In the described embodiment, the chip height H2 of the top multi-gate transistor 600T is greater than the chip height H1 of the bottom multi-gate transistor 600B. Figure 18In another embodiment, an optional semiconductor device 600' is depicted. Semiconductor device 600' is similar to semiconductor device 600, and one difference between semiconductor device 600 and semiconductor device 600' includes that the top multi-gate transistor 600T' and the bottom multi-gate transistor 600B' have different wafer height relationships. More specifically, the bottom multi-gate transistor 600B' includes channel layers 6080L1' and 6080L2' each having a wafer height H1', ​​and the top multi-gate transistor 600T' includes channel layers 6080U1' and 6080U2' each having a wafer height H2', and the wafer height H1' is greater than the wafer height H2'. In this embodiment, the ratio of wafer height H2' to wafer height H1' is greater than about 0.3 and less than 1. If the ratio is less than 0.3, the gate control capability of the bottom multi-gate transistor 600B' may be too poor, resulting in poor precise control of the drain current, or the channel layer of the top multi-gate transistor 600T' may be too thin, resulting in high channel resistance for the top multi-gate transistor. In one embodiment, the top multi-gate transistor 600T' includes an n-type multi-gate transistor, and the bottom multi-gate transistor 600B' includes a p-type multi-gate transistor, and the semiconductor device 600' may be located in a non-critical path of another logic cell similar to the logic cell described above. In another embodiment, the top multi-gate transistor includes a p-type multi-gate transistor, and the bottom multi-gate transistor includes an n-type multi-gate transistor.

[0066] The above reference Figure 9 , Figure 14 , Figure 17 and Figure 18 Four embodiments have been described. The key concepts of those four embodiments (e.g., different gate lengths, different chip heights) can be combined to form four different alternative embodiments.

[0067] Figure 19 The first of four alternative embodiments is depicted. (Reference) Figure 19 The image shows a semiconductor device 700. In this embodiment, the semiconductor device 700 includes an internal spacer component 226, a bottom gate structure 254B, an internal portion 254I of a top gate structure, and channel layers 6080U1-6080U2 and 6080L1-6080L2. (Refer to the above...) Figure 9 and Figure 17 The gate length relationship and channel plate height relationship have already been described, and for simplicity, repeated descriptions have been omitted. In an embodiment, semiconductor device 700 may be part of another SRAM cell in an IC structure to increase the α ratio of that other SRAM cell.

[0068] Figure 20 The second of four alternative embodiments is depicted. (See reference) Figure 20 The image shows a semiconductor device 700'. In this embodiment, the semiconductor device 700' includes an internal spacer component 226', a bottom gate structure 254B', an internal portion 254I' of a top gate structure, and channel layers 6080U1'-6080U2' and 6080L1'-6080L2'. (Refer to above) Figure 14 and Figure 18 The gate length relationship and channel plate height relationship have already been described, and for simplicity, repeated descriptions have been omitted. In an embodiment, the semiconductor device 700' may be located in a non-critical path of another logic cell.

[0069] Two additional embodiments of the four alternative embodiments are not explicitly shown in the accompanying drawings. However, it should be noted that a third embodiment of the four alternative embodiments may include a C-FET having an internal portion 2541 and a bottom gate structure 254B, an internal spacer component 226, and also having channel layers 6080U1'-6080U2' and 6080L1'-6080L2'. A fourth embodiment of the four alternative embodiments may include a C-FET having an internal portion 2541' and a bottom gate structure 254B', an internal spacer component 226', and also having channel layers 6080U1-6080U2 and 6080L1-6080L2.

[0070] The performance of C-FETs can also be optimized by separately optimizing the gate height of top-multi-gate devices and bottom-multi-gate devices. Figure 21 A flowchart illustrating a method 800 for forming a semiconductor device 900 including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure, is shown. Figures 22 to 23 Description method 800, Figures 22 to 23 This is a partial cross-sectional view of the semiconductor device 900 at different manufacturing stages according to an embodiment of method 800.

[0071] Now for reference Figure 21 and Figure 22Method 800 includes a frame 802 in which a superlattice structure 904 is formed over a substrate 202. The fabrication process for forming the superlattice structure 904 is the same as that for the superlattice structure 204. Differences between the superlattice structure 904 and the superlattice structure 204 include the dimensional relationships between the different layers within the superlattice structure 904. More specifically, the superlattice structure 904 includes a bottom portion 904B, an intermediate sacrificial layer 206M on the bottom portion 904B, and a top portion 904T on the intermediate sacrificial layer 206M. The bottom portion 904B includes a plurality of first channel layers (e.g., first channel layers 208L1, 208L2, 208L3) interleaved with a plurality of first sacrificial layers (e.g., first sacrificial layers 906L1, 906L2, 906L3). The first sacrificial layers 906L1, 906L2, 906L3 may be individually or collectively referred to as the first sacrificial layer 906L. In some embodiments, the first channel layer 208L is formed of silicon (Si), and the first sacrificial layer 906L is formed of silicon germanium (SiGe). The top portion 904T includes a plurality of second channel layers (e.g., second channel layers 208U1, 208U2, 208U3) interleaved with a plurality of second sacrificial layers (e.g., second sacrificial layers 906U1, 906U2). The second sacrificial layers 906U1 and 906U2 may be referred to individually or collectively as the second sacrificial layer 906U. In some embodiments, the second channel layer 208U is formed of silicon (Si), and the second sacrificial layer 906U is formed of silicon germanium (SiGe). The first channel layer 208L and the second channel layer 208U may have the same thickness. In the illustrated embodiment, the first sacrificial layer 906L and the second sacrificial layer 906U have the same germanium content, which is less than the third germanium content of the intermediate sacrificial layer 206M.

[0072] In some prior art techniques for forming C-FETs, the first sacrificial layer 906L and the second sacrificial layer 906U have the same thickness, and therefore, the heights of the inner portions of the bottom gate structure and the top gate structure can be the same. In this embodiment, to optimize C-FET performance, the first sacrificial layer 906L and the second sacrificial layer 906U are configured to have different thicknesses. In the illustrated embodiment, each of the first sacrificial layers 906L has a thickness T3', and each of the second sacrificial layers 906U has a thickness T4'. T3' has the same range as thickness T3, and thickness T4' is greater than thickness T4 and less than about 30 nm. By forming first sacrificial layers 906L and second sacrificial layers 906U with different thicknesses, the spacing used to form the gate structure therein can be adjusted. Therefore, the thickness and / or number of different layers in the gate structure of the bottom multi-gate device and the top multi-gate device can be optimized individually.

[0073] After the superlattice structure 904 is formed, the operations in blocks 104-122 described above are performed to complete the fabrication of the semiconductor device 900. Figure 23 A partial cross-sectional view of semiconductor device 900 is depicted during operation in blocks 104-122. Semiconductor device 900 is similar to semiconductor device 200. For ease of description, similar and / or identical components between the two semiconductor devices 200 and 900 are indicated by the same reference numerals, and repeated descriptions are omitted for simplicity. The main differences between the two semiconductor devices 200 and 900 are described in detail. The first difference between the two semiconductor devices 200 and 900 includes: the bottom multi-gate transistor 900B of semiconductor device 900 includes a gate structure 954B having a first gate height Hg1; the internal portion 954I of the top gate structure 954T of the top multi-gate transistor 900T includes a second gate height Hg2. The second gate height Hg2 is greater than the first gate height Hg1. In an embodiment, the top multi-gate transistor 900T includes an n-type multi-gate transistor, and the bottom multi-gate transistor 900B includes a p-type multi-gate transistor. In another embodiment, the top multi-gate transistor 900T includes a p-type multi-gate transistor, and the bottom multi-gate transistor 900B includes an n-type multi-gate transistor. A second difference between the two semiconductor devices 200 and 900 includes that semiconductor device 900 also includes internal spacer components, such as internal spacer components 926a, 926b, 926c, 926d, and 926e. The widths of the internal spacer components 926a-926e of semiconductor device 900 can be substantially the same. However, the internal spacer components 926a-926e can have different heights. In this embodiment, the height of the internal spacer components 926a-926b formed above the intermediate dielectric layer 226M is greater than the height of the internal spacer components 926c-926e formed below the intermediate dielectric layer 226M.

[0074] Reference Figure 23 In the embodiments described above, the gate height Hg2 of the top multi-gate transistor 900T is greater than the gate height Hg1 of the bottom multi-gate transistor 900B. In the embodiments described above... Figure 24In another embodiment, an optional semiconductor device 900' is depicted. Semiconductor device 900' is similar to semiconductor device 900, and one difference between semiconductor device 900 and semiconductor device 900' includes that the top multi-gate transistor 900T' and the bottom multi-gate transistor 900B' have different gate height relationships. More specifically, the bottom multi-gate transistor 900B' includes a bottom gate structure with a gate height Hg1', and the top multi-gate transistor 900T' includes a top gate structure 954T', which includes an internal portion 954I' with a gate height Hg2', and the height Hg1' is greater than the height Hg2'. In this embodiment, semiconductor device 900' also includes internal spacer components 926a', 926b', 926c', 926d', and 926e'. The widths of the internal spacer components 926a'-926e' of semiconductor device 900' can be substantially the same. However, the internal spacer components 926a'-926e' can have different heights. In this embodiment, the height of the internal spacer components 926a'-926b' formed above the intermediate dielectric layer 226M is less than the height of the internal spacer components 926c'-926e' formed below the intermediate dielectric layer 226M.

[0075] The above reference Figure 9 , Figure 14 , Figure 17 , Figure 18 , Figure 23 and Figure 24 Six main embodiments have been described. Two or three of the key concepts in those six embodiments (e.g., different gate lengths, different wafer heights, different gate heights) can be combined to form different alternative embodiments to flexibly adjust the performance of the C-FET.

[0076] The performance of C-FETs can also be optimized by separately optimizing the composition of the channel layers for top-gate and bottom-gate devices. Figure 25 A flowchart illustrating a method 1000 for forming a semiconductor device 1100 including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure, is shown. Figures 26 to 27 Description method 1000, Figures 26 to 27 These are partial cross-sectional views of the semiconductor device 1100 at different manufacturing stages according to an embodiment of method 1000.

[0077] Now for reference Figure 25 and Figure 26Method 1000 includes a frame 1002 in which a superlattice structure 1104 is formed over a substrate 202. The fabrication process for forming the superlattice structure 1104 is the same as that for the superlattice structure 204. Differences between the superlattice structure 1104 and the superlattice structure 204 include that the superlattice structures 204 and 1104 have different compositions. More specifically, the superlattice structure 1104 includes a bottom portion 1104B, an intermediate sacrificial layer 206M on the bottom portion 1104B, and a top portion 1104T on the intermediate sacrificial layer 206M. The bottom portion 1104B includes a plurality of first channel layers (e.g., first channel layers 1108L1, 1108L2, 1108L3) interleaved with a plurality of first sacrificial layers (e.g., first sacrificial layers 1106L1, 1106L2, 1106L3). The first sacrificial layers 1106L1, 1106L2, and 1106L3 may be individually or collectively referred to as the first sacrificial layer 1106L. The top portion 1104T includes a plurality of second channel layers (e.g., second channel layers 1108U1, 1108U2, and 1108U3) interleaved with a plurality of second sacrificial layers (e.g., second sacrificial layers 1106U1 and 1106U2). The second sacrificial layers 1106U1 and 1106U2 may be individually or collectively referred to as the second sacrificial layer 1106U.

[0078] In some prior art techniques for forming C-FETs, both the first channel layer in the bottom portion and the second channel layer in the top portion are formed of silicon. In this embodiment, to optimize C-FET performance, the first channel layer 1108L and / or the second channel layer 1108U are formed of silicon germanium. In the illustrated embodiment, both the first channel layer 1108L and the second channel layer 1108U comprise silicon germanium with the same first germanium content, and both the first sacrificial layer 1106L and the second sacrificial layer 1106U comprise silicon germanium with the same second germanium content, which is greater than the first germanium content of the first channel layer 1108L and / or the second channel layer 1108U and less than the germanium content of the intermediate sacrificial layer 206M. In this embodiment, the first germanium content is less than 30%, the second germanium content is between about 40% and about 50%, and the germanium content of the intermediate sacrificial layer 206M is between about 60% and about 100%. The higher second germanium content and the highest germanium content in the intermediate sacrificial layer 206M provide etch selectivity among the three SiGe-based channel layers and sacrificial layers in the superlattice structure 1104.

[0079] After the superlattice structure 1104 is formed, the operations in blocks 104-122 described above are performed to complete the fabrication of the semiconductor device 1100. Figure 27A partial cross-sectional view of semiconductor device 1100 during operation in boxes 104-122 is depicted. Semiconductor device 1100 is similar to semiconductor devices 200 and 600. For ease of description, similar and / or identical parts between semiconductor devices 200, 600, and 1100 are indicated by the same reference numerals, and repeated descriptions are omitted for simplicity. The main differences between the two semiconductor devices 200 and 1100 are described in detail. The first difference between the two semiconductor devices 200 and 1100 includes: the bottom multi-gate transistor 1100B of semiconductor device 1100 includes channel members 11080L1 and 11080L2 formed by channel layers 1108L2 and 1108L3; and the top multi-gate transistor 1100T of semiconductor device 1100 includes channel members 11080U1 and 11080U2 formed by channel layers 1108U1 and 1108U3, wherein channel members 11080U1-11080U2 and 11080L1-11080L2 are formed of silicon germanium having a germanium content of less than 30%. Semiconductor device 1100 also includes nanostructures 11080N1 and 11080N2 formed by channel layers 1108U3 and 1108L1, and includes silicon germanium having a germanium content of less than 30%. Another difference between the two semiconductor devices 200 and 1100 includes: the bottom multi-gate transistor 1100B includes internal spacer components 626c-626e, and the top multi-gate transistor 1100T includes internal spacer components 626a-626b. The internal spacer components 626a-626e have the same width. In one embodiment, the top multi-gate transistor 1100T includes an n-type multi-gate transistor, and the bottom multi-gate transistor 1100B includes a p-type multi-gate transistor. In another embodiment, the top multi-gate transistor 1100T includes a p-type multi-gate transistor, and the bottom multi-gate transistor 1100B includes an n-type multi-gate transistor.

[0080] Reference Figure 27 In the embodiments described above, both the first channel layer 1108L and the second channel layer 1108U comprise silicon germanium having the same first germanium content. Figure 28In another embodiment, an optional semiconductor device 1100' is depicted. Semiconductor device 1100' is similar to semiconductor device 1100, and one difference between semiconductor device 1100 and semiconductor device 1100' includes that the first channel layer of the bottom multi-gate transistor 1100B' and the second channel layer of the top multi-gate transistor 1100T' have different compositions. More specifically, in the illustrated embodiment, the bottom multi-gate transistor 1100B' includes channel components 11080L1-11080L2 formed of silicon-germanium, and the top multi-gate transistor 1100T' includes channel components 2080U1 and 2080U2 formed of silicon. Semiconductor device 1100' also includes nanostructures 2080N1 and 11080N2. In the embodiment, the top multi-gate transistor 1100T' includes an n-type multi-gate transistor, and the bottom multi-gate transistor 1100B' includes a p-type multi-gate transistor. In another embodiment, the top multi-gate transistor 1100T' includes a p-type multi-gate transistor, and the bottom multi-gate transistor 1100B' includes an n-type multi-gate transistor. Although not shown, method 1000 can also be applied to manufacture semiconductor devices including a top multi-gate transistor having a channel component formed of silicon germanium and a bottom multi-gate transistor having a channel component formed of silicon.

[0081] The concept of Method 1000 can also be referenced above. Figure 9 , Figure 14 , Figure 17 , Figure 18 , Figure 23 and Figure 24 Other combinations of embodiments described. For example, Figures 29 to 30 Partial cross-sectional views of semiconductor device 1200 during various manufacturing processes are depicted. Semiconductor device 1200 is similar to semiconductor devices 200 and 1100. For ease of description, similar and / or identical components among semiconductor devices 200, 1100, and 1200 are denoted by the same reference numerals, and redundant descriptions are omitted for simplicity. The main differences between semiconductor devices 200, 1100, and 1200 are described in detail. More specifically, Figure 29 A superlattice structure 1204 formed above a substrate 202 is depicted. The superlattice structure 1204 includes channel layers 1108 interleaved with a sacrificial layer 206. Specifically, the first channel layer 1108L and the second channel layer 1108U comprise silicon-germanium with the same first germanium content. The superlattice structure 1204 also includes the above-mentioned reference... Figure 3 The sacrificial layer 206 is described. That is, the first sacrificial layer 206L and the second sacrificial layer 206U have different germanium contents. It should be noted that the germanium contents of both the first sacrificial layer 206L and the second sacrificial layer 206U are greater than the germanium contents of the channel layer 1108.

[0082] After forming the superlattice structure 1204, the operations in blocks 104-122 described above are performed to complete the process by which the superlattice structure 1204 is formed. Figure 30 The manufacturing of semiconductor device 1200 is shown. The differences between semiconductor devices 200, 1100, and 1200 include: semiconductor device 1200 includes a reference... Figure 27 The described channel components 11080U1-11080U2 and 11080L1 and 11080L2, and also include references Figure 9 The gate structures 254B and 254I and the internal spacer component 226 are described. That is, the channel component of the semiconductor device 1200 may include silicon germanium, and the gate lengths of the internal portions of the gate structure of the bottom multi-gate transistor 1200B and the gate structure of the top multi-gate transistor 1200T of the semiconductor device 1200 are different.

[0083] Reference Figure 30 In the embodiments described above, the channel components of the bottom multi-gate transistor 1200B and the top multi-gate transistor 1200T both comprise silicon germanium.

[0084] In the Figure 31 In another embodiment, an optional semiconductor device 1200' is depicted. Semiconductor device 1200' is similar to semiconductor device 1200, and one difference between semiconductor device 1200 and semiconductor device 1200' includes that the channel components of the bottom multi-gate transistor 1200B' of semiconductor device 1200' and the channel components of the top multi-gate transistor 1200T' of semiconductor device 1200' are different. In this illustrated embodiment, the bottom multi-gate transistor 1200B' includes channel components 2080U1 and 2080U2 formed of silicon, and the top multi-gate transistor 1200T' includes channel components 11080L1 and 11080L2 formed of silicon germanium.

[0085] This disclosure includes embodiments that optimize different aspects of the bottom-gate and top-gate transistors of a C-FET (e.g., gate length, channel sheet thickness, gate height, and channel component composition) to achieve different performance improvements. These different aspects can be applied individually or combined in various ways to form different C-FETs. While only some of those combinations are explicitly shown or described, it should be understood that this disclosure covers all such combinations.

[0086] Refer to the above Figures 2 to 31 In the described embodiments, the semiconductor devices all include nanostructures in direct contact with the intermediate dielectric layer 226M (e.g., Figure 9(as shown in 2080N1 and 2080N2). In some alternative embodiments, such as by... Figure 32 This indicates that such nanostructures can be omitted. Figure 32 A partial cross-sectional view of optional semiconductor device 200' is depicted. Semiconductor device 200' is similar to semiconductor device 200, and one of the differences between semiconductor device 200 and 200' is that semiconductor device 200' does not include 2080N1 and 2080N2. That is, the intermediate dielectric layer 226M is in direct contact with the top gate structure 254T and the bottom gate structure 254B. This optional embodiment can also be applied to the above reference. Figures 13 to 31 Any of the embodiments described.

[0087] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their fabrication. For example, embodiments of this disclosure provide a C-FET device having a top-multiple-gate device and a bottom-multiple-gate device. One or more features of the top-multiple-gate device and the bottom-multiple-gate device can be optimized to improve the performance of the C-FET device. Such features may include gate length, gate height, channel sheet thickness, and / or channel component composition.

[0088] This disclosure provides for many different embodiments. Semiconductor structures and methods of manufacturing thereof are disclosed herein. In one exemplary aspect, this disclosure relates to a method. The method includes: forming a fin-shaped structure protruding from a substrate, a first portion of the fin-shaped structure including a plurality of first channel layers interleaved with a plurality of first sacrificial layers, and a second portion of the fin-shaped structure including a plurality of second channel layers interleaved with a plurality of second sacrificial layers; forming a trench extending through the fin-shaped structure; after forming the trench, performing an etching process to laterally recess the plurality of first sacrificial layers and the plurality of second sacrificial layers, wherein the etchant of the etching process etches the plurality of first sacrificial layers and the plurality of second sacrificial layers at different rates; and after performing the etching process, replacing the remaining portions of the plurality of first sacrificial layers with a first gate structure and replacing the remaining portions of the plurality of second sacrificial layers with a second gate structure.

[0089] In some embodiments, the plurality of first sacrificial layers may include silicon-germanium with a first germanium concentration, and the plurality of second sacrificial layers may include silicon-germanium with a second germanium concentration greater than the first germanium concentration. In some embodiments, the length of the first gate structure is greater than the length of the second gate structure. In some embodiments, the method may also include: forming a first source / drain component coupled to the plurality of first channel layers before replacement; and forming a second source / drain component coupled to the plurality of second channel layers, the first source / drain component and the second source / drain component having different conductivity types. In some embodiments, the method may also include: forming a first internal spacer component adjacent to the remaining portions of the plurality of first sacrificial layers after performing an etching process; and forming a second internal spacer component adjacent to the remaining portions of the plurality of second sacrificial layers. In some embodiments, the first internal spacer component and the second internal spacer component have different widths. In some embodiments, the fin structure may also include an intermediate portion vertically disposed between the first portion and the second portion, and the method may also include: selectively removing the intermediate portion to form an opening; and forming a dielectric layer in the opening. In some embodiments, the intermediate portion may include silicon-germanium, and the germanium concentration of the intermediate portion is greater than the germanium concentration of the plurality of first sacrificial layers and the germanium concentration of the plurality of second sacrificial layers. In some embodiments, each of the plurality of first trench layers has a first thickness, and each of the plurality of second trench layers has a second thickness different from the first thickness.

[0090] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes: forming a first semiconductor layer stack over a substrate and forming a second semiconductor layer stack over the first semiconductor layer stack, the first semiconductor layer stack having a first upper semiconductor layer above a first lower semiconductor layer, and the second semiconductor layer stack having a second upper semiconductor layer above a second lower semiconductor layer; forming a first source / drain component coupled to the first upper semiconductor layer and the first lower semiconductor layer; forming a second source / drain component coupled to the second upper semiconductor layer and the second lower semiconductor layer; forming a first gate structure adjacent to the first source / drain component and disposed between the first upper semiconductor layer and the first lower semiconductor layer; and forming a second gate structure adjacent to the second source / drain component and disposed between the second upper semiconductor layer and the second lower semiconductor layer, the first gate structure and the second gate structure having different gate lengths.

[0091] In some embodiments, the first semiconductor layer stack and the second semiconductor layer stack have the same width. In some embodiments, the first source / drain component may include a p-type dopant, the second source / drain component may include an n-type dopant, and the gate length of the first gate structure is greater than the gate length of the second gate structure. In some embodiments, the thickness of the first lower semiconductor layer is less than the thickness of the second upper semiconductor layer. In some embodiments, the method may also include: forming a first internal spacer disposed between the first gate structure and the first source / drain component; and forming a second internal spacer disposed between the second gate structure and the second source / drain component. In some embodiments, the first internal spacer and the second internal spacer have different widths. In some embodiments, the method may also include: forming a dielectric layer between the first semiconductor layer stack and the second semiconductor layer stack, wherein the dielectric layer, the first internal spacer, and the second internal spacer have the same composition.

[0092] In another exemplary aspect, embodiments of this disclosure relate to a semiconductor device. The semiconductor device includes: a substrate; a lower source / drain component disposed above the substrate; a first plurality of nanostructures coupled to the lower source / drain component; a first gate structure enclosing each of the first plurality of nanostructures; an upper source / drain component located above the lower source / drain component; a second plurality of nanostructures coupled to the upper source / drain component; and a second gate structure enclosing each of the second plurality of nanostructures, wherein the first gate structure and the second gate structure have different gate lengths.

[0093] In some embodiments, the lower source / drain component may include a p-type dopant, the upper source / drain component may include an n-type dopant, and the gate length of the first gate structure is greater than the gate length of the second gate structure. In some embodiments, the semiconductor device may also include: a first internal spacer disposed between the first gate structure and the lower source / drain component; and a second internal spacer disposed between the second gate structure and the upper source / drain component, wherein the first internal spacer and the second internal spacer have different widths. In some embodiments, the thickness of each of the first plurality of nanostructures is different from the thickness of each of the second plurality of nanostructures.

[0094] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a fin structure protruding from a substrate, a first portion of the fin structure including a plurality of first channel layers interleaved with a plurality of first sacrificial layers, and a second portion of the fin structure including a plurality of second channel layers interleaved with a plurality of second sacrificial layers; forming a trench extending through the fin structure; after forming the trench, performing an etching process to laterally recess the plurality of first sacrificial layers and the plurality of second sacrificial layers, wherein the etchant of the etching process etches the plurality of first sacrificial layers and the plurality of second sacrificial layers at different rates; and after performing the etching process, replacing the remaining portions of the plurality of first sacrificial layers with a first gate structure and replacing the remaining portions of the plurality of second sacrificial layers with a second gate structure.

[0095] In some embodiments, the plurality of first sacrificial layers comprise silicon-germanium with a first germanium concentration, and the plurality of second sacrificial layers comprise silicon-germanium with a second germanium concentration greater than the first germanium concentration. In some embodiments, the length of the first gate structure is greater than the length of the second gate structure. In some embodiments, the method further comprises: forming a first source / drain component coupled to the plurality of first channel layers before the replacement; and forming a second source / drain component coupled to the plurality of second channel layers, wherein the first source / drain component and the second source / drain component have different conductivity types. In some embodiments, the method further comprises: forming a first internal spacer component adjacent to the remaining portions of the plurality of first sacrificial layers after performing the etching process; and forming a second internal spacer component adjacent to the remaining portions of the plurality of second sacrificial layers. In some embodiments, the first internal spacer component and the second internal spacer component have different widths. In some embodiments, the fin structure further comprises an intermediate portion vertically disposed between the first portion and the second portion, and the method further comprises: selectively removing the intermediate portion to form an opening; and forming a dielectric layer in the opening. In some embodiments, the intermediate portion comprises silicon-germanium, and the germanium concentration of the intermediate portion is greater than the germanium concentrations of the plurality of first sacrificial layers and the plurality of second sacrificial layers. In some embodiments, each of the plurality of first channel layers has a first thickness, and each of the plurality of second channel layers has a second thickness different from the first thickness.

[0096] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first semiconductor layer stack over a substrate and forming a second semiconductor layer stack over the first semiconductor layer stack, the first semiconductor layer stack having a first upper semiconductor layer above a first lower semiconductor layer, and the second semiconductor layer stack having a second upper semiconductor layer above a second lower semiconductor layer; forming a first source / drain component coupled to the first upper semiconductor layer and the first lower semiconductor layer; forming a second source / drain component coupled to the second upper semiconductor layer and the second lower semiconductor layer; forming a first gate structure disposed adjacent to the first source / drain component and between the first upper semiconductor layer and the first lower semiconductor layer; and forming a second gate structure disposed adjacent to the second source / drain component and between the second upper semiconductor layer and the second lower semiconductor layer, wherein the first gate structure and the second gate structure have different gate lengths.

[0097] In some embodiments, the first semiconductor layer stack and the second semiconductor layer stack have the same width. In some embodiments, the first source / drain component includes a p-type dopant, the second source / drain component includes an n-type dopant, and the gate length of the first gate structure is greater than the gate length of the second gate structure. In some embodiments, the thickness of the first lower semiconductor layer is less than the thickness of the second upper semiconductor layer. In some embodiments, the method further includes: forming a first internal spacer disposed between the first gate structure and the first source / drain component; and forming a second internal spacer disposed between the second gate structure and the second source / drain component. In some embodiments, the first internal spacer and the second internal spacer have different widths. In some embodiments, the method further includes: forming a dielectric layer between the first semiconductor layer stack and the second semiconductor layer stack, wherein the dielectric layer, the first internal spacer, and the second internal spacer have the same composition.

[0098] Further embodiments of this application provide a semiconductor device, including: a substrate; a lower source / drain component disposed above the substrate; a first plurality of nanostructures coupled to the lower source / drain component; a first gate structure enclosing each of the first plurality of nanostructures; an upper source / drain component located above the lower source / drain component; a second plurality of nanostructures coupled to the upper source / drain component; and a second gate structure enclosing each of the second plurality of nanostructures, wherein the first gate structure and the second gate structure have different gate lengths.

[0099] In some embodiments, the lower source / drain component includes a p-type dopant, the upper source / drain component includes an n-type dopant, and the gate length of the first gate structure is greater than the gate length of the second gate structure. In some embodiments, the semiconductor device further includes: a first internal spacer disposed between the first gate structure and the lower source / drain component; and a second internal spacer disposed between the second gate structure and the upper source / drain component, wherein the first internal spacer and the second internal spacer have different widths. In some embodiments, the thickness of each of the first plurality of nanostructures is different from the thickness of each of the second plurality of nanostructures.

[0100] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor device, comprising: forming a fin structure protruding from a substrate, a first portion of the fin structure including a plurality of first channel layers interleaved with a plurality of first sacrificial layers, and a second portion of the fin structure including a plurality of second channel layers interleaved with a plurality of second sacrificial layers; forming a trench extending through the fin structure; after forming the trench, performing an etching process to laterally recess the plurality of first sacrificial layers and the plurality of second sacrificial layers, wherein an etchant of the etching process etches the plurality of first sacrificial layers and the plurality of second sacrificial layers at different rates; and after performing the etching process, replacing remaining portions of the plurality of first sacrificial layers with a first gate structure, and replacing remaining portions of the plurality of second sacrificial layers with a second gate structure.

2. The method of claim 1, wherein, the plurality of first sacrificial layers comprise silicon germanium having a first germanium concentration, and the plurality of second sacrificial layers comprise silicon germanium having a second germanium concentration greater than the first germanium concentration.

3. The method of claim 2, wherein, a length of the first gate structure is greater than a length of the second gate structure.

4. The method of claim 1, further comprising: prior to the replacing, forming a first source / drain component coupled to the plurality of first channel layers; and forming a second source / drain component coupled to the plurality of second channel layers, wherein the first source / drain component and the second source / drain component have different conductivity types.

5. The method of claim 1, further comprising: after performing the etching process, forming a first internal spacer component abutting the remaining portions of the plurality of first sacrificial layers; and forming a second internal spacer component abutting the remaining portions of the plurality of second sacrificial layers.

6. The method of claim 5, wherein, the first internal spacer component and the second internal spacer component have different widths.

7. The method of claim 1, wherein, the fin structure further includes an intermediate portion disposed vertically between the first portion and the second portion, and the method further comprises: selectively removing the intermediate portion to form an opening; and forming a dielectric layer in the opening.

8. The method of claim 7, wherein, the intermediate portion comprises silicon germanium, and a germanium concentration of the intermediate portion is greater than a germanium concentration of the plurality of first sacrificial layers and a germanium concentration of the plurality of second sacrificial layers.

9. A method of forming a semiconductor device, comprising: forming a first semiconductor layer stack over a substrate and a second semiconductor layer stack over the first semiconductor layer stack, the first semiconductor layer stack having a first upper semiconductor layer over a first lower semiconductor layer, and the second semiconductor layer stack having a second upper semiconductor layer over a second lower semiconductor layer; forming a first source / drain component coupled to the first upper semiconductor layer and the first lower semiconductor layer; forming a second source / drain component coupled to the second upper semiconductor layer and the second lower semiconductor layer; forming a first gate structure disposed adjacent to the first source / drain component and between the first upper semiconductor layer and the first lower semiconductor layer; and forming a second gate structure disposed adjacent to the second source / drain component and between the second upper semiconductor layer and the second lower semiconductor layer. forming a second gate structure adjacent to the second source / drain component and disposed between the second upper semiconductor layer and the second lower semiconductor layer, wherein the first gate structure and the second gate structure have different gate lengths.

10. A semiconductor device, comprising: a substrate; a lower source / drain component disposed above the substrate; a first plurality of nanostructures coupled to the lower source / drain component; a first gate structure wrapping each of the first plurality of nanostructures; an upper source / drain component above the lower source / drain component; a second plurality of nanostructures coupled to the upper source / drain component; and a second gate structure wrapping each of the second plurality of nanostructures, wherein the first gate structure and the second gate structure have different gate lengths. ​

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