Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a groove in the substrate, sequentially forming a first oxide layer and a second oxide layer on the surface of the substrate, the side wall of the groove and the bottom wall of the groove, and filling a shielding gate material layer in the groove, the second oxide layer and the shield gate material layer are covered with a mask material layer; patterning the mask material layer to form a first opening, and etching back a part of the shield gate material layer to form a shield gate; forming a third oxide layer, wherein the top wall of the third oxide layer on the shield gate is lower than the surface of the substrate; the third oxide layer is removed, and a part of the second oxide layer is etched back to form a second opening in the groove; a fourth oxide layer is formed to fill the second opening, a part of the fourth oxide layer and the first oxide layer are etched back, the mask material layer is removed, and the remaining fourth oxide layer in the groove serves as a dielectric layer on the shield gate. The performance and the yield of the semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device. Background Technology

[0002] Shielded Gate Trench (SGT) field-effect transistors effectively resolve the trade-off between on-resistance and parasitic capacitance, while simultaneously reducing system conduction and switching losses and improving system efficiency. Specifically, in a shielded gate FET, a shield electrode is placed below the gate electrode, which significantly reduces the gate-drain capacitance. Furthermore, the drift region of the shielded gate FET has a high concentration of impurity carriers, providing additional benefits to the device's breakdown voltage and consequently reducing on-resistance.

[0003] However, the performance and yield of shielded gate field-effect transistors can be further improved. Summary of the Invention

[0004] In view of this, this application aims to provide a method for manufacturing a semiconductor device to improve the performance and yield of the semiconductor device.

[0005] The method for fabricating the semiconductor device provided in this application includes: A substrate is provided, on the surface of which a trench is formed, and a first oxide layer and a second oxide layer are sequentially formed on the inner wall of the trench. A shielding gate material layer is filled in the trench, and the shielding gate material layer is in contact with the second oxide layer. A mask material layer covers the second oxide layer and the shielding gate material layer. The mask material layer is patterned to form a first opening, the first opening exposes the second oxide layer and the shielding gate material layer in the trench, and a portion of the shielding gate material layer is etched back, with the remaining shielding gate material layer serving as the shielding gate; A third oxide layer is formed, which conformally covers the surface of the mask material layer, the sidewall of the mask material layer exposed by the first opening, the second oxide layer in the trench, and the surface of the shielding gate, wherein the top wall of the third oxide layer on the shielding gate is lower than the surface of the substrate; Remove the third oxide layer and etch back a portion of the second oxide layer to form a second opening in the trench, the sidewalls of the second opening exposing the first oxide layer and the bottom wall of the second opening exposing a portion of the shielding grid; A fourth oxide layer is formed to fill the second opening. A portion of the fourth oxide layer and a portion of the first oxide layer are etched back, and the mask material layer is removed to expose a portion of the sidewalls of the trench. The remaining fourth oxide layer and a portion of the first oxide layer in the trench serve as a dielectric layer on the shielding gate.

[0006] Optionally, when forming the third oxide layer, the top wall of the third oxide layer on the shielding grid is lower than the top wall of the second oxide layer on both sides of the shielding grid, so that when the third oxide layer is removed, the side wall of the second oxide layer in the trench is exposed earlier than the top wall of the second oxide layer.

[0007] Optionally, when forming the third oxide layer, the top wall of the third oxide layer on the second oxide layer in the trench is higher than the bottom wall of the mask material layer.

[0008] Optionally, an isotropic etching process is used to remove the third oxide layer, and a portion of the second oxide layer and the first oxide layer are etched back, wherein the etching rate of the second oxide layer is greater than the etching rate of the first oxide layer and the third oxide layer.

[0009] Optionally, the isotropic etching process includes a wet process.

[0010] Optionally, the third oxide layer and the fourth oxide layer are formed by high-density plasma chemical vapor deposition.

[0011] Optionally, the process gases used to form the third oxide layer and the fourth oxide layer both include hydrogen, and the hydrogen power required to form the third oxide layer is greater than the hydrogen power required to form the fourth oxide layer.

[0012] Optionally, when etching back the fourth oxide layer and the first oxide layer, the etching rate ratio of the fourth oxide layer and the first oxide layer is 0.8:1 to 1:0.8.

[0013] Optionally, the step of etching back a portion of the fourth oxide layer and a portion of the first oxide layer, and removing the mask material layer, further includes: The grinding process is performed with the mask material layer as the stop layer, and the mask material layer is removed by a wet process. A wet etching process is used to remove part of the fourth oxide layer and part of the first oxide layer, exposing the sidewalls of the trench and part of the shielding grid.

[0014] Optionally, the first oxide layer is formed by thermal oxidation, and the second oxide layer is formed by high aspect ratio vapor deposition.

[0015] In summary, the unexpected effect of this application is that after the shielding gate material layer is etched back to form a shielding gate in the trench, a third oxide layer is formed. The third oxide layer covers the inner wall of the first opening. On the one hand, the third oxide layer conformally covers the sidewall of the mask material layer exposed by the first opening, so that the interface between the mask material layer on the sidewall of the first opening and the oxide layer on the substrate is covered by the third oxide layer on the surface of the second oxide layer. Thus, during the subsequent etching of the third oxide layer, the interface between the mask material layer and the second oxide layer is still protected by the third oxide layer for most of the time, which can reduce or avoid the risk of the oxide layer under the mask material layer being etched too much and causing the mask material layer to peel off. On the other hand, the shielding gate on The top wall of the third oxide layer is lower than the substrate surface, making the thickness of the third oxide layer located on the sidewall of the second oxide layer less than the thickness of the third oxide layer on the shielding gate. This allows the sidewalls of the second oxide layer within the trench to be exposed earlier than the top wall during the etching of the third oxide layer. This enables earlier etching of the second oxide layer from its sidewalls, ensuring that the sidewalls of the second opening no longer retain the second oxide layer. Consequently, after the formation and re-etching of the fourth oxide layer, a shielding gate dielectric layer with a more uniform thickness and a smoother surface is formed. This not only improves the withstand voltage performance of the device (shielding gate dielectric layer) but also reduces the impact of leakage current, thereby improving product yield and reducing material costs. Furthermore, the second opening formed by etching the third oxide layer provides a larger process window for filling the second opening during the subsequent formation of the fourth oxide layer, improving the filling quality of the fourth oxide layer, avoiding voids, and further improving yield. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of forming a shielding gate in a trench in a substrate.

[0017] Figure 2 To and Figure 1 The corresponding electron microscope image.

[0018] Figure 3 A schematic diagram showing the process of filling trenches to form an HDP OX layer.

[0019] Figure 4 This is a schematic diagram of etching back the HDP OX layer, Harp OX layer, and WET OX layer to form a dielectric layer on the shielding gate.

[0020] Figure 5 To and Figure 4 The corresponding electron microscope image.

[0021] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application.

[0022] Figure 7This is a schematic diagram showing a substrate having trenches, a first oxide layer, a second oxide layer, a shielding gate material layer, and a mask material layer, provided in an embodiment of this application.

[0023] Figure 8 This is a schematic diagram of a patterned mold material layer forming a first opening, provided for an embodiment of the application.

[0024] Figure 9 This is a schematic diagram of the formation of a shielding barrier provided in the embodiment.

[0025] Figure 10 This is a schematic diagram of the formation of the third oxide layer provided in an embodiment of this application.

[0026] Figure 11 This is a schematic diagram showing the formation of a second opening by etching back the third oxide layer and the second oxide layer, as provided in an embodiment of this application.

[0027] Figure 12 This is a schematic diagram of the formation of the fourth oxide layer provided in an embodiment of this application.

[0028] Figure 13 This is a schematic diagram of the grinding of the fourth oxide layer provided in an embodiment of this application.

[0029] Figure 14 This is a schematic diagram of the fourth oxide layer and the first oxide layer in the etch-back portion of the embodiment of this application to form a dielectric layer on the shielding gate.

[0030] The attached figures are labeled as follows: 100 - Substrate; 101 - Oxide layer on substrate; 110 - Trench; 210 - First oxide layer; 220 - Second oxide layer; 230 - Mask material layer; 240a - Shielding gate material layer; 240 - Shielding gate; 250 - First opening; 250a - T-shaped first opening; 310 - Third oxide layer; 320 - Second opening; 330 - Fourth oxide layer. Detailed Implementation

[0031] Figures 1 to 5 This is a schematic diagram of a process for manufacturing a shielded gate field-effect transistor.

[0032] like Figure 1 and Figure 2 As shown, a shielded gate (SG) is formed in a trench in the substrate. A WET OX layer (silicon oxide layer formed by wet oxidation process) and a Harp OX layer (silicon oxide layer formed by high aspect ratio chemical vapor deposition process) are formed sequentially on the inner wall of the trench. The Harp OX layer surrounds the shielded gate from the sidewall and bottom wall of the shielded gate (SG). A WET OX layer, a Harp OX layer and a SIN layer (silicon nitride layer) are sequentially covered on the surface of the substrate. Figure 2 To and Figure 1 Corresponding electron microscope schematic diagram.

[0033] like Figure 3 As shown, an HDP OX layer is formed to cover the SIN layer and fill the trench.

[0034] like Figure 4 and Figure 5 As shown, the HDP OX layer, Harp OX layer, and WET OX layer are etched back to form a dielectric layer on the shielding gate in the trench. Figure 5 To and Figure 4 Corresponding electron microscope schematic diagrams. Due to the different functional positioning and corresponding formation processes of the HDP OX layer, Harp OX layer, and WET OX layer, the etching rates during etching of the three layers differ, thus forming... Figure 4 and Figure 5 The shielding grid shown has an uneven surface and uneven thickness dielectric layer (IPO, Inter Poly OX). Figure 5 The red box in the middle is Figure 4 The morphology of the top surface of the material in the trench not only affects product yield but may also lead to a reduction in device performance, such as reducing the device's withstand voltage and increasing the device's leakage current.

[0035] On the other hand, if the HDP OX layer is not formed, and instead the WET OX layer and Harp OX layer are directly etched back to form the shielding gate dielectric layer in the trench, it is still difficult to form a shielding gate dielectric layer with a flat surface and uniform thickness. Moreover, it may also cause the SIN layer to peel off from the substrate surface.

[0036] Therefore, this application provides a method for manufacturing a semiconductor device. The method includes: providing a substrate, forming trenches on the surface of the substrate, sequentially forming a first oxide layer and a second oxide layer on the inner wall of the trenches, filling the trenches with a shielding gate material layer in contact with the second oxide layer, and covering the second oxide layer and the shielding gate material layer with a mask material layer; patterning the mask material layer to form a first opening, the first opening exposing the second oxide layer and the shielding gate material layer in the trenches, and etching back a portion of the shielding gate material layer, with the remaining shielding gate material layer serving as a shielding gate; forming a third oxide layer, the third oxide layer conforming to the shape... The surface of the mask material layer, the sidewall of the mask material layer exposed by the first opening, the second oxide layer in the trench, and the surface of the shielding gate are covered. The top wall of the third oxide layer on the shielding gate is lower than the substrate surface. The third oxide layer is removed, and part of the second oxide layer is etched back to form a second opening in the trench. The sidewall of the second opening exposes the first oxide layer, and the bottom wall of the second opening exposes part of the shielding gate. A fourth oxide layer is formed to fill the second opening. Part of the fourth oxide layer and part of the first oxide layer are etched back, and the mask material layer is removed to expose part of the sidewall of the trench. The remaining fourth oxide layer and part of the first oxide layer in the trench serve as the dielectric layer on the shielding gate. An unexpected effect of this application is that after the shielding gate material layer is etched back to form a shielding gate in the trench, a third oxide layer is formed. The third oxide layer covers the inner wall of the first opening. On the one hand, the third oxide layer conformally covers the sidewall of the mask material layer exposed by the first opening, so that the interface between the mask material layer on the sidewall of the first opening and the oxide layer on the substrate is covered by the third oxide layer on the surface of the second oxide layer. Thus, during the subsequent etching of the third oxide layer, the interface between the mask material layer and the second oxide layer is still protected by the third oxide layer for most of the time, which can reduce or avoid the risk of the oxide layer under the mask material layer being etched too much and causing the mask material layer to peel off. On the other hand, the third oxide layer on the shielding gate... The top wall of the oxide layer is lower than the substrate surface, making the thickness of the third oxide layer located on the sidewall of the second oxide layer less than the thickness of the third oxide layer on the shielding gate. This allows the sidewalls of the second oxide layer within the trench to be exposed earlier than the top wall during the etching of the third oxide layer. This enables earlier etching of the second oxide layer from its sidewalls, ensuring that the sidewalls of the second opening no longer retain the second oxide layer. Consequently, after the formation and re-etching of the fourth oxide layer, a shielding gate dielectric layer with a more uniform thickness and a smoother surface is formed. This not only improves the withstand voltage performance of the device (shielding gate dielectric layer) but also reduces the impact of leakage current, thereby improving product yield and reducing material costs. Furthermore, the second opening formed by etching the third oxide layer provides a larger process window for filling the second opening during the subsequent formation of the fourth oxide layer, improving the filling quality of the fourth oxide layer, avoiding voids, and further increasing yield.

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] Figure 6 A flowchart of a method for manufacturing a semiconductor device provided in the embodiments of this application is shown below. Figure 6 As shown, the method for manufacturing a semiconductor device includes: S100: A substrate is provided, on the surface of which a trench is formed, and a first oxide layer and a second oxide layer are sequentially formed on the inner wall of the trench. A shielding gate material layer is filled in the trench, and the shielding gate material layer is in contact with the second oxide layer. A mask material layer is covered on the second oxide layer and the shielding gate material layer. S200: The mask material layer is patterned to form a first opening, the first opening exposes the second oxide layer and the shielding gate material layer in the trench, and a portion of the shielding gate material layer is etched back, the remaining shielding gate material layer serves as a shielding gate; S300: A third oxide layer is formed, which conformally covers the surface of the mask material layer, the sidewall of the mask material layer exposed by the first opening, the second oxide layer in the trench, and the surface of the shielding gate, wherein the top wall of the third oxide layer on the shielding gate is lower than the surface of the substrate; S400: Remove the third oxide layer and etch back a portion of the second oxide layer to form a second opening in the trench, the sidewall of the second opening exposing the first oxide layer, and the bottom wall of the second opening exposing a portion of the shielding grid; S500: A fourth oxide layer is formed to fill the second opening, a portion of the fourth oxide layer and a portion of the first oxide layer are etched back, and the mask material layer is removed to expose a portion of the sidewall of the trench. The remaining fourth oxide layer and a portion of the first oxide layer in the trench serve as a dielectric layer on the shielding gate.

[0039] Figures 7-14 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 7-14 The method for fabricating the semiconductor device provided in this application will be described in detail.

[0040] First, such as Figure 7As shown, in step S100, a substrate 100 is provided, a trench 110 is formed on the surface of the substrate 100, a first oxide layer 210 and a second oxide layer 220 are sequentially formed on the sidewall and bottom wall of the trench 110, a shielding gate material layer 240a is filled in the trench 110, the shielding gate material layer 240a is in contact with the second oxide layer 220, and a mask material layer 230 is covered on the second oxide layer 220 and the shielding gate material layer 240a.

[0041] The substrate 100 can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), or it can be an organic semiconductor material or other semiconductor materials known in the art.

[0042] In some optional examples, the formation is as follows Figure 7 The steps of the illustrated structure may include, for example, forming a trench 110 in a substrate 100; then, performing a thermal oxidation process (e.g., dry thermal oxidation or wet thermal oxidation) to form a first oxide layer 210, the first oxide layer 210 conformally covering the surface of the substrate 100 and the inner walls (bottom and sidewalls) of the trench 110; then, performing a HRAPCVD (high aspect ratio chemical vapor deposition) process to form a second oxide layer 220, the second oxide layer 220 conformally covering the surface of the first oxide layer 210, including the surface of the first oxide layer 210 located on the surface of the substrate 100 and the inner walls of the trench 110, the first oxide layer 210 and the second oxide layer 220... The oxide layer 220 does not completely fill the trench 110; next, a shielding gate material layer 240a is formed to cover the surface of the second oxide layer 220 and fill the trench 110; next, a polishing process is performed to remove part of the shielding gate material layer 240a and part of the oxide layer on the surface of the substrate 100, remove the shielding gate material layer 240a above the substrate 100, and retain the shielding gate material layer 240a in the trench 110; next, a mask layer material layer is formed to cover the shielding gate material layer 240a. To distinguish it from the oxide layer in the trench 110, the various oxide layers remaining on the surface of the substrate 100 are collectively referred to as the substrate oxide layer 101.

[0043] The shielding gate material layer 240a can be any suitable conductive material, such as polysilicon or metal, and the mask material layer 230 can include a pad layer (not shown in the figure) and a silicon nitride layer formed in sequence.

[0044] Next, as Figures 8-9As shown, in step S200, the mask material layer 230 is patterned to form a first opening 250. The first opening 250 exposes the second oxide layer 220 and the shielding gate material layer 240a in the trench 110, and a portion of the shielding gate material layer 240a is etched back, with the remaining shielding gate material layer 240a serving as the shielding gate 240.

[0045] Specifically, such as Figure 8 As shown, the mask material layer 230 is patterned to form a first opening 250 (e.g., rectangular) in the mask material layer 230. The sidewalls of the first opening 250 expose the mask material layer 230 (i.e., silicon nitride layer) and the oxide layer 101 on the substrate (including the junction between the two). The bottom wall of the first opening 250 exposes the second oxide layer 220 and the shielding gate material layer 240a in the trench 110. The shape and size of the first opening 250 may be the same as or close to the formation and size of the opening of the trench 110. In other words, the first opening 250 and the trench 110 may be defined using the same mask.

[0046] like Figure 9 As shown, the shielding grid material layer 240a is etched back, causing the middle portion of the first opening 250 to extend downwards, forming a T-shaped first opening 250a. The remaining shielding grid material layer 240a in the trench 110 serves as the shielding grid 240. In one example, a wet process can be used to etch back the shielding grid material layer 240a, and the thickness of the etched back shielding grid material layer 240a can be determined according to the height requirements of the shielding grid 240.

[0047] Next, as Figure 10 As shown, in step S300, a third oxide layer 310 is formed. The third oxide layer 310 conformally covers the surface of the mask material layer 230, the sidewall of the mask material layer 230 exposed by the first opening 250, the second oxide layer 220 in the trench 110, and the surface of the shielding gate 240. The top wall of the third oxide layer 310 on the shielding gate 240 is lower than the surface of the substrate 100.

[0048] Specifically, the third oxide layer 310 can be formed, for example, by using HDP-CVD (high-density plasma chemical vapor deposition), so that the third oxide layer 310 conformally covers the surface of the mask material layer 230 and the inner wall of the T-shaped first opening 250a, that is, it covers the surface of the mask material layer 230, the mask material layer 230 exposed by the first opening 250, the sidewall of the oxide layer 101 on the substrate, the surface of the shielding gate 240 in the trench 110, and the surface and sidewall (outer wall) of the second oxide layer 220.

[0049] It should be noted that, on the one hand, when forming the third oxide layer 310, the top wall of the third oxide layer 310 on the shielding gate 240 is lower than the top walls of the second oxide layers 220 on both sides of the shielding gate 240. That is, the third oxide layer 310 does not fill the etch-back space when forming the shielding gate 240, resulting in the thickness of the third oxide layer 310 on the shielding gate 240 being greater than the thickness of the third oxide layer 310 on the sidewalls of the second oxide layer 220. On the other hand, when forming the third oxide layer 310, the top wall of the third oxide layer 310 on the surface of the second oxide layer 220 in the trench 110 is higher than the bottom wall of the mask material layer 230, so that the junction between the mask material layer 230 and the oxide layer 101 on the substrate is covered (protected) by the third oxide layer 310 on the surface of the second oxide layer 220. As can be seen from the above two aspects, the thickness of the third oxide layer 310 should not be too thick or too thin. If the thickness of the third oxide layer 310 is too thick, the top wall of the third oxide layer 310 on the shielding gate 240 will be higher than the top wall of the second oxide layer 220 on both sides of the shielding gate 240. If the thickness of the third oxide layer 310 is too thin, the top wall of the third oxide layer 310 on the surface of the second oxide layer 220 in the trench 110 will be lower than the bottom wall of the mask material layer 230 (the junction of the mask material layer 230 and the oxide layer 101 on the substrate), so that the junction of the mask material layer 230 and the second oxide layer 220 is only covered by the thinner third oxide layer 310 on the side wall.

[0050] In addition, the process gas used to form the third oxide layer 310 may include hydrogen, and the hydrogen power can be relatively increased to control the thickness of the third oxide layer 310. For example, the hydrogen power required to form the third oxide layer 310 may be greater than the hydrogen power required to form the fourth oxide layer.

[0051] Next, as Figure 11 As shown, in step S400, the third oxide layer 310 is removed and a portion of the second oxide layer 220 is etched back to form a second opening 320 in the trench 110. The sidewall of the second opening 320 exposes the first oxide layer 210, and the bottom wall of the second opening 320 exposes a portion of the shielding grid 240.

[0052] Specifically, an isotropic etching process (e.g., wet etching) can be used to etch away the third oxide layer 310, and a portion of the second oxide layer 220 and a portion of the first oxide layer 210 can be etched back to form a second opening 320 within the trench 110. The bottom wall of the second opening 320 is lower than the shielding gate 240, exposing a portion of the height of the shielding gate 240. The sidewall of the second opening 320 exposes the first oxide layer 210 on the sidewall of the trench 110. Although the third oxide layer 310, the second oxide layer 220, and the first oxide layer 210 are all oxide layers (made of the same or similar materials, such as silicon oxide), the different fabrication processes result in different film quality and density, leading to different etching rates in wet etching. In this application, the etching rate of the second oxide layer 220 is greater than that of the first oxide layer 210 and the third oxide layer 310, while the etching rate of the third oxide layer 310 is relatively close to that of the first oxide layer 210.

[0053] In etching the third oxide layer 310, the thickness of the third oxide layer 310 on the shielding gate 240 is greater than the thickness of the third oxide layer 310 on the sidewall of the second oxide layer 220. This allows the sidewall of the second oxide layer 220 in the trench 110 to be exposed earlier than its top wall. This enables earlier etching of the second oxide layer 220 from its sidewall, ensuring that the second oxide layer 220 is etched back after the third oxide layer 310 is removed, making the bottom wall of the second opening 320 as flush as possible with the top wall of the shielding gate 240. At this point, the sidewall of the second opening 320 no longer retains the second oxide layer 220, exposing the first oxide layer 210. In addition, during the etching process described above, the junction between the silicon nitride layer and the oxide layer 101 on the substrate in the sidewall of the mask material layer 230 is mostly protected by the third oxide layer 310, which can reduce or avoid the risk of the silicon nitride layer being peeled off due to excessive etching of the oxide layer 101 on the substrate below the silicon nitride layer.

[0054] Next, as Figures 12-14 As shown, in step S500, a fourth oxide layer 330 is formed to fill the second opening 320, a portion of the fourth oxide layer 330 and the first oxide layer 210 are etched back, and the mask material layer 230 is removed to expose a portion of the sidewall of the trench 110. The remaining fourth oxide layer 330 and a portion of the first oxide layer 210 in the trench 110 serve as the dielectric layer on the shielding gate.

[0055] Specifically, such as Figure 12As shown, a fourth oxide layer 330 is formed to cover the surface of the second oxide layer 220 and fill the second opening 320. A suitable process can be selected to form the fourth oxide layer 330, making its film quality and density similar to the first oxide layer 210, thereby ensuring that the etching rates of the fourth oxide layer 330 and the first oxide layer 210 are similar during wet etching (e.g., the wet etching ratio of the fourth oxide layer 330 to the first oxide layer 210 is 0.8:1 to 1:0.8). In one example, HDP-CVD (high-density plasma chemical vapor deposition) can be used to form the fourth oxide layer 330, so that the fourth oxide layer 330 conformally covers the surface of the mask material layer 230 and the inner wall of the second opening 320, and fills the second opening 320. In addition, since the second opening 320 has a larger opening width (i.e. the opening width of the trench 110), it can provide a larger process window when the fourth oxide layer 330 is filled in the second opening 320, which is beneficial to improving the filling quality of the fourth oxide layer 330 and avoiding the formation of voids.

[0056] like Figure 13 As shown, a polishing process is performed with the mask material layer 230 as the stop layer, followed by a wet process to remove the mask material layer 230, exposing the oxide layer 101 on the substrate and the fourth oxide layer 330 in the trench 110.

[0057] like Figure 14 As shown, the oxide layer 101, a portion of the fourth oxide layer 330, and a portion of the first oxide layer 210 on the substrate are etched back to expose a portion of the sidewalls of the trench 110. The remaining fourth oxide layer 330 and a portion of the first oxide layer 210 within the trench 110 serve as the dielectric layer on the shielding gate. Specifically, a wet process can be used to simultaneously remove the oxide layer 101, the first oxide layer 210, and the fourth oxide layer 330 on the substrate. The etching rates of the fourth oxide layer 330 and the first oxide layer 210 are relatively close, for example, the ratio of their etching rates is 0.8:1 to 1:0.8. The etching depth (etching amount) is controlled by the etching time so that the remaining fourth oxide layer 330 has a preset thickness and covers the shielding gate 240. At this time, since the surfaces of the fourth oxide layer 330 and the first oxide layer 210 in the trench 110 were basically flush before the etching, the etching rates of the four oxide layers 330 and the first oxide layer 210 were relatively close during the etching process, so that the surfaces of the remaining fourth oxide layer 330 and the first oxide layer 210 after etching were still basically flush. The fourth oxide layer 330 and the first oxide layer 210 above the shielding gate 240 have a flat surface. In other words, the dielectric layer on the shielding gate has a relatively uniform thickness and a relatively flat surface.

[0058] In summary, this application provides a method for manufacturing a semiconductor device. The method includes providing a substrate, forming trenches on the surface of the substrate, sequentially forming a first oxide layer and a second oxide layer on the inner wall of the trenches, filling the trenches with a shielding gate material layer in contact with the second oxide layer, and covering the second oxide layer and the shielding gate material layer with a mask material layer; patterning the mask material layer to form a first opening, the first opening exposing the second oxide layer and the shielding gate material layer in the trenches, and etching back a portion of the shielding gate material layer, with the remaining shielding gate material layer serving as a shielding gate; forming a third oxide layer, the third oxide layer conformally... The mask material layer surface, the sidewall of the mask material layer exposed by the first opening, the second oxide layer in the trench, and the surface of the shielding gate are covered. The top wall of the third oxide layer on the shielding gate is lower than the substrate surface. The third oxide layer is removed, and part of the second oxide layer is etched back to form a second opening in the trench. The sidewall of the second opening exposes the first oxide layer, and the bottom wall of the second opening exposes part of the shielding gate. A fourth oxide layer is formed to fill the second opening. Part of the fourth oxide layer and part of the first oxide layer are etched back, and the mask material layer is removed to expose part of the sidewall of the trench. The remaining fourth oxide layer and part of the first oxide layer in the trench serve as the dielectric layer on the shielding gate. An unexpected effect of this application is that after the shielding gate material layer is etched back to form a shielding gate in the trench, a third oxide layer is formed. The third oxide layer covers the inner wall of the first opening. On the one hand, the third oxide layer conformally covers the sidewall of the mask material layer exposed by the first opening, so that the interface between the mask material layer on the sidewall of the first opening and the oxide layer on the substrate is covered by the third oxide layer on the surface of the second oxide layer. Thus, during the subsequent etching of the third oxide layer, the interface between the mask material layer and the second oxide layer is still protected by the third oxide layer for most of the time, which can reduce or avoid the risk of the oxide layer under the mask material layer being etched too much and causing the mask material layer to peel off. On the other hand, the third oxide layer on the shielding gate... The top wall of the oxide layer is lower than the substrate surface, making the thickness of the third oxide layer located on the sidewall of the second oxide layer less than the thickness of the third oxide layer on the shielding gate. This allows the sidewalls of the second oxide layer within the trench to be exposed earlier than the top wall during the etching of the third oxide layer. This enables earlier etching of the second oxide layer from its sidewalls, ensuring that the sidewalls of the second opening no longer retain the second oxide layer. Consequently, after the formation and re-etching of the fourth oxide layer, a shielding gate dielectric layer with a more uniform thickness and a smoother surface is formed. This not only improves the withstand voltage performance of the device (shielding gate dielectric layer) but also reduces the impact of leakage current, thereby improving product yield and reducing material costs. Furthermore, the second opening formed by etching the third oxide layer provides a larger process window for filling the second opening during the subsequent formation of the fourth oxide layer, improving the filling quality of the fourth oxide layer, avoiding voids, and further increasing yield.

[0059] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0060] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0061] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0062] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, on the surface of which a trench is formed, and a first oxide layer and a second oxide layer are sequentially formed on the inner wall of the trench. A shielding gate material layer is filled in the trench, and the shielding gate material layer is in contact with the second oxide layer. A mask material layer covers the second oxide layer and the shielding gate material layer. The mask material layer is patterned to form a first opening, the first opening exposes the second oxide layer and the shielding gate material layer in the trench, and a portion of the shielding gate material layer is etched back, with the remaining shielding gate material layer serving as the shielding gate; A third oxide layer is formed, which conformally covers the surface of the mask material layer, the sidewall of the mask material layer exposed by the first opening, the second oxide layer in the trench, and the surface of the shielding gate, wherein the top wall of the third oxide layer on the shielding gate is lower than the surface of the substrate; Remove the third oxide layer and etch back a portion of the second oxide layer to form a second opening in the trench, the sidewalls of the second opening exposing the first oxide layer and the bottom wall of the second opening exposing a portion of the shielding grid; A fourth oxide layer is formed to fill the second opening. A portion of the fourth oxide layer and a portion of the first oxide layer are etched back, and the mask material layer is removed to expose a portion of the sidewalls of the trench. The remaining fourth oxide layer and a portion of the first oxide layer in the trench serve as a dielectric layer on the shielding gate.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, When the third oxide layer is formed, the top wall of the third oxide layer on the shielding grid is lower than the top wall of the second oxide layer on both sides of the shielding grid, so that when the third oxide layer is removed, the side wall of the second oxide layer in the trench is exposed earlier than the top wall of the second oxide layer.

3. The method for fabricating a semiconductor device according to claim 1 or 2, characterized in that, When the third oxide layer is formed, the top wall of the third oxide layer on the second oxide layer in the trench is higher than the bottom wall of the mask material layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The third oxide layer is removed using an isotropic etching process, and a portion of the second oxide layer and a portion of the first oxide layer are etched back. The etching rate of the second oxide layer is greater than the etching rates of the first oxide layer and the third oxide layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The isotropic etching process includes a wet etching process.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The third oxide layer and the fourth oxide layer are formed by high-density plasma chemical vapor deposition.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The process gases used to form the third oxide layer and the fourth oxide layer both include hydrogen. The hydrogen power required to form the third oxide layer is greater than the hydrogen power required to form the fourth oxide layer.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, When etching back the fourth oxide layer and the first oxide layer, the etching rate ratio of the fourth oxide layer and the first oxide layer is 0.8:1 to 1:0.

8.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of etching back the fourth oxide layer and part of the first oxide layer, and removing the mask material layer, further includes: The grinding process is performed with the mask material layer as the stop layer, and the mask material layer is removed by a wet process. A wet etching process is used to remove part of the fourth oxide layer and part of the first oxide layer, exposing the sidewalls of the trench and part of the shielding grid.

10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first oxide layer is formed by thermal oxidation, and the second oxide layer is formed by high aspect ratio vapor deposition.

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