Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate which comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially formed; doped regions of first and second conductivity types formed in the barrier layer; the grid electrode, the source electrode and the drain electrode are electrically contacted with the two doped regions respectively. The manufacturing method of the device comprises the following steps: providing a semiconductor substrate; doped regions of two conductive types are formed in the barrier layer through ion implantation; and forming a gate electrode, a source electrode and a drain electrode at positions in contact with the doped region. According to the invention, ion implantation is adopted to replace the traditional P-GaN epitaxial growth and etching process, a step structure does not need to be formed on the surface of the device, and the highly planarized surface of the device is realized. Therefore, the damage of etching to the barrier layer is avoided, the reliability and performance of the device are improved, the subsequent process difficulty is greatly reduced, the manufacturing process is simplified, and a process basis is provided for the miniaturization development of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Gallium nitride (GaN), as a representative material of third-generation wide-bandgap semiconductors, has shown great potential in high-frequency, high-efficiency, and high-power power electronics applications due to its excellent physical properties such as high breakdown electric field, high saturated electron drift velocity, and high thermal conductivity. Heterojunctions formed based on two group III nitrides with different bandgap widths (e.g., AlGaN and GaN) can induce a high concentration of two-dimensional electron gas (2DEG) at the interface, thereby forming a conductive channel. Gallium nitride high electron mobility transistors fabricated using this principle are typically depletion-mode (D-mode) devices, meaning the channel is already conducting when the gate is at zero bias.

[0003] However, in many power conversion applications, normally-off (i.e., enhancement-mode, E-mode) devices are typically required to prevent shoot-through short circuits caused by gate drive circuit failure at power-up. To achieve enhancement-mode gallium nitride (GaN) devices, a mainstream approach in the prior art is to epitaxially grow a P-type GaN layer on the AlGaN barrier layer in the gate region. The built-in electric field of the P-GaN / AlGaN junction depletes the underlying two-dimensional electron gas, thereby raising the device's threshold voltage and achieving enhancement-mode operation.

[0004] However, this technology based on P-type GaN gates has the following inherent drawbacks:

[0005] The trade-off between process compatibility and performance: To achieve a sufficiently high threshold voltage, the P-type GaN layer needs to effectively deplete the channel. This typically requires a thinner AlGaN barrier layer underneath, but this significantly increases the channel sheet resistance (Rsh), resulting in higher on-resistance and impacting overall device performance.

[0006] Process damage and reliability issues: When forming the gate structure, the P-type GaN layer outside the gate region needs to be removed by dry etching. This etching process can easily cause irreversible physical damage to the thin AlGaN barrier layer underneath, resulting in increased device leakage current and severely reducing the long-term reliability of the device.

[0007] Contact resistance issue: Traditional source-drain ohmic contacts usually require etching away the barrier layer, depositing metal, and annealing. This process is complex and results in high contact resistance, which limits further improvement in device performance.

[0008] Miniaturization Challenges: As devices evolve towards higher frequencies and smaller sizes, the distinct "step" structure formed after etching the P-type GaN layer poses a significant challenge to subsequent processes such as photolithography alignment and metal deposition. The tolerance for alignment deviations is extremely low, severely impacting the manufacturing yield and uniformity of small-sized devices.

[0009] Therefore, the industry urgently needs a new type of enhanced gallium nitride device structure and its manufacturing method to overcome the above-mentioned problems in the existing technology, while ensuring high threshold voltage, achieving low on-resistance, low contact resistance, high reliability, and making it easier to achieve precise manufacturing of small-sized devices. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a novel enhanced gallium nitride device structure and its manufacturing method, so as to overcome the problems of high on-resistance, process damage, large contact resistance and difficulty in miniaturization caused by the use of P-GaN gate structure in the prior art.

[0011] To address the aforementioned technical problems, the present invention provides a semiconductor device, comprising:

[0012] A semiconductor substrate, comprising a substrate, a buffer layer, a channel layer and a barrier layer formed sequentially;

[0013] The first type of conductivity doped region is formed in the barrier layer;

[0014] A doped region of the second conductivity type is formed in the barrier layer, and the conductivity properties of the second conductivity type are opposite to those of the first conductivity type.

[0015] Gate, the gate comprising gate metal in contact with a doped region of a first conductivity type; and

[0016] Source and drain, the source and drain comprising source and drain metals in contact with a doped region of a second conductivity type;

[0017] The gate, source, and drain are formed on the same side of the semiconductor substrate with a planarized surface.

[0018] Preferably, the substrate material is selected from silicon, silicon carbide, sapphire, gallium nitride, or diamond.

[0019] Preferably, the buffer layer comprises doped gallium nitride, doped aluminum gallium nitride, or a superlattice structure formed by alternating doped gallium nitride and doped aluminum gallium nitride.

[0020] Preferably, the channel layer is an undoped gallium nitride layer.

[0021] Preferably, the barrier layer is an undoped gallium aluminum nitride layer.

[0022] Preferably, the materials of the gate metal and / or source / drain metal are selected from titanium, titanium nitride, aluminum, tungsten, niobium, platinum, tantalum, vanadium, nickel, molybdenum, gold, or any combination thereof.

[0023] Preferably, a doped region of the first conductivity type is further formed in the channel layer.

[0024] Preferably, a doped region of the second conductivity type is further formed in the channel layer.

[0025] Preferably, the first conductivity type is P-type and the second conductivity type is N-type.

[0026] Preferably, the doped region of the first conductivity type includes a P-type dopant, which is selected from magnesium, beryllium, zinc, or any combination thereof.

[0027] Preferably, the doped region of the second conductivity type includes an N-type dopant, wherein the N-type dopant is silicon.

[0028] Preferably, the doping concentration of the P-type doped region and / or the doping concentration of the N-type doped region is 10. 13 -10 22 cm -3 .

[0029] Preferably, the semiconductor substrate further includes a capping layer disposed on the barrier layer; wherein the doped regions of the first conductivity type and the doped regions of the second conductivity type extend into the capping layer.

[0030] Preferably, the thickness of the capping layer is 1-1000 nm.

[0031] Preferably, the thickness of the capping layer is 40-100 nm.

[0032] Preferably, the thickness of the doped region of the first conductivity type is 40-100 nm.

[0033] Preferably, the thickness of the barrier layer is 1-100 nm.

[0034] Preferably, the thickness of the barrier layer is 10-30 nm.

[0035] Preferably, the depth of the doped region of the first conductivity type and / or the doped region of the second conductivity type is 1-500 nm.

[0036] Preferably, the length of the doped region of the first conductivity type and / or the doped region of the second conductivity type is 1 nm-100 μm.

[0037] Preferably, the lower surface of the gate metal and the lower surface of the source / drain metal are located on the same plane.

[0038] Preferably, the maximum step height of the planarized surface of the semiconductor substrate is less than 500 nm.

[0039] Preferably, the maximum step height is less than 10 nm.

[0040] Preferably, the semiconductor device further includes a metal field plate electrically connected to the source electrode.

[0041] Preferably, the material of the metal field plate is selected from titanium, titanium nitride, aluminum, tungsten, copper, aluminum-copper alloy or any combination thereof.

[0042] The present invention also provides a method for manufacturing a semiconductor device, comprising the following steps:

[0043] Step 1: Provide a semiconductor substrate, which includes a substrate, a buffer layer, a channel layer and a barrier layer formed sequentially;

[0044] Step 2: By ion implantation, a first conductivity type doped region and a second conductivity type doped region are formed in the semiconductor substrate within the barrier layer, wherein the conductivity properties of the second conductivity type are opposite to those of the first conductivity type.

[0045] Step 3: Form the gate, source, and drain, wherein the gate is in contact with a doped region of the first conductivity type, and the source and drain are in contact with a doped region of the second conductivity type.

[0046] In the process between step two and step three, the surface of the semiconductor substrate is a planarized surface.

[0047] Preferably, in step one, the provided semiconductor substrate further includes a capping layer formed on the barrier layer.

[0048] Preferably, in step two, a doped region of the first conductivity type is further formed in the channel layer.

[0049] Preferably, in step two, a doped region of the second conductivity type is further formed in the channel layer.

[0050] Preferably, in step two, the first conductivity type is P-type and the second conductivity type is N-type.

[0051] Preferably, in step two, the spacing between the doped region of the first conductivity type and the doped region of the second conductivity type is 1 nm-1 mm.

[0052] Preferably, in step two, the step of forming a doped region by ion implantation includes: performing multiple ion implantations with different energies and doses to form a uniform doping concentration within a predetermined depth of the doped region.

[0053] Preferably, during ion implantation in step two, a mask is used to define the formation locations of doped regions of the first conductivity type and / or doped regions of the second conductivity type.

[0054] Preferably, the mask is a photoresist mask.

[0055] Preferably, during ion implantation in step two, a protective dielectric layer is provided on the surface of the semiconductor substrate.

[0056] Preferably, after ion implantation in step two, the method further includes a step of removing the protective dielectric layer.

[0057] Preferably, in step three, the gate, source, and drain are formed synchronously in a self-aligned manner.

[0058] Preferably, in step three, the gate, source, and drain are formed separately.

[0059] Preferably, the step of self-aligned synchronous formation of the gate, source, and drain includes: forming a dielectric layer on a semiconductor substrate; etching the dielectric layer to form a contact via that simultaneously exposes a doped region of a first conductivity type and a doped region of a second conductivity type; depositing a metal layer in the contact via and on the dielectric layer, and patterning the metal layer to form the gate, source, and drain.

[0060] Preferably, the length of the contact via is less than, equal to or greater than the length of the doped region it exposes, and the overlap between the contact via and the doped region is greater than 1%.

[0061] Preferably, the spacing between adjacent contact vias is 1 nm-1 mm.

[0062] Preferably, after step two and before step three, the method further includes: annealing the semiconductor substrate to repair lattice damage caused by ion implantation and activate the dopant.

[0063] Preferably, the annealing process includes furnace tube annealing, rapid thermal annealing, or laser annealing.

[0064] Preferably, after step three, the method further includes annealing the gate, source, and drain.

[0065] Preferably, after step three, the method further includes forming a metal field plate electrically connected to the source electrode.

[0066] As described above, the semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0067] (1) By using ion implantation to form the doped region, the etching step in the traditional P-GaN gate process is avoided, fundamentally eliminating the step structure on the device surface and achieving a highly planar surface. This planar structure greatly reduces the difficulty of subsequent photolithography and etching processes, providing a process basis for further miniaturization of device size (e.g., achieving a smaller gate-source pitch).

[0068] (2) By avoiding irreversible damage to the barrier layer caused by dry etching, the reliability of the device during long-term operation is improved. At the same time, by forming heavily doped source and drain regions through ion implantation and forming metal contacts with them, the contact resistance can be effectively reduced, thereby reducing the overall on-resistance of the device.

[0069] (3) The method of the present invention can simultaneously form gate, source and drain electrodes using a self-aligned process, which reduces the use of photomasks and alignment steps, simplifies the overall manufacturing process, and helps to improve production efficiency and reduce manufacturing costs. Attached Figure Description

[0070] Figure 1 The diagram shows a process flow diagram of the semiconductor device manufacturing method of the present invention;

[0071] Figure 2 The diagram shows a cross-sectional structure after a semiconductor substrate is provided during the manufacturing process of the semiconductor device of the present invention.

[0072] Figure 3 The diagram shows a cross-sectional structure after a doped region of the first conductivity type is formed during the manufacturing process of the semiconductor device of the present invention.

[0073] Figure 4 The diagram shows a cross-sectional structure after a doped region of the second conductivity type is formed during the manufacturing process of the semiconductor device of the present invention.

[0074] Figure 5 The diagram shows a cross-sectional structure after removing the mask and protective dielectric layer during the manufacturing process of the semiconductor device of the present invention.

[0075] Figure 6 The diagram shows a cross-sectional structure after the contact via is formed during the manufacturing process of the semiconductor device of the present invention.

[0076] Figure 7 The diagram shows a cross-sectional structure of the semiconductor device after the gate, source, and drain are formed during the manufacturing process of the present invention.

[0077] Figure 8 The diagram shows a cross-sectional structure after the metal field plate is formed in the manufacturing process of the semiconductor device of the present invention.

[0078] Figure 9The diagram shown is a cross-sectional view of the semiconductor device including the capping layer according to the present invention.

[0079] Explanation of reference numerals in the attached figures:

[0080] 101: Substrate; 102: Buffer layer; 103: Channel layer; 104: Barrier layer; 105: Protective dielectric layer; 106: First mask; 107: Doped region of first conductivity type; 108: Second mask; 109: Doped region of second conductivity type; 110: Source; 111: Gate; 112: Drain; 113: Interlayer dielectric; 114: Metal field plate. Detailed Implementation

[0081] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0082] This invention provides a semiconductor device, comprising:

[0083] A semiconductor substrate, comprising a substrate 101, a buffer layer 102, a channel layer 103, and a barrier layer 104 formed sequentially.

[0084] A doped region 107 of the first conductivity type is formed in the barrier layer 104;

[0085] A doped region 109 of a second conductivity type is formed in the barrier layer 104, and the conductivity properties of the second conductivity type are opposite to those of the first conductivity type.

[0086] Gate 111, gate 111 includes gate metal in contact with a doped region 107 of a first conductivity type; and

[0087] Source 110 and drain 112, the source 110 and drain 112 include source and drain metals in contact with the doped region 109 of the second conductivity type;

[0088] In this invention, the gate 111, source 110, and drain 112 are formed on the same side of the semiconductor substrate with a planarized surface. This invention forms doped regions through direct ion implantation within the semiconductor layer, replacing the traditional epitaxial growth of P-GaN followed by etching. This fundamentally avoids the "step" structure formed on the semiconductor surface by etching, resulting in excellent device surface flatness. This planarized structure creates conditions for subsequent precision processes such as self-alignment and avoids reliability issues caused by damage to the barrier layer 104 during etching, while also reducing the device's contact resistance.

[0089] In some embodiments, the material of the substrate 101 is selected from silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium nitride (GaN), or diamond. It can also be other materials suitable for the epitaxial growth of III-V semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), or composite substrates such as silicon-on-insulator (SOI). The substrate 101 can be conductive or semi-insulating, and its selection can be based on a comprehensive consideration of factors such as cost, heat dissipation performance, and lattice matching with the epitaxial layer. For example, silicon carbide substrates have excellent thermal conductivity, making them suitable for high-power device applications; while silicon substrates have significant cost advantages, facilitating large-scale production.

[0090] In some embodiments, the buffer layer 102 comprises doped gallium nitride, doped aluminum gallium nitride (AlGaN), or a superlattice structure formed by alternating layers of doped gallium nitride and doped aluminum gallium nitride. The purpose of the buffer layer 102 is to suppress the upward extension of dislocations by addressing the difference in lattice constant and coefficient of thermal expansion between the transition substrate 101 and the functional layer. Therefore, the buffer layer 102 may also be a multilayer gradient composition AlGaN layer, a combination of aluminum nitride (AlN) nucleation layers and AlGaN layers, or a nitride alloy layer containing indium (In) or other group III elements. The doping in the buffer layer 102 may be deep-level acceptor doping, such as carbon (C) or iron (Fe), to increase its resistivity, enhance the confinement of channel carriers, and reduce leakage current.

[0091] In some embodiments, the channel layer 103 is an undoped gallium nitride layer. The channel layer 103 can also be an undoped indium gallium nitride (InGaN) layer; introducing indium can further enhance the polarization effect and increase the concentration of two-dimensional electron gas in the channel. The thickness of the channel layer 103 can be designed according to the device's operating voltage, frequency, and other requirements.

[0092] In some embodiments, the barrier layer 104 is an undoped gallium aluminum nitride layer. The barrier layer 104 may also be an aluminum indium nitride (AlInN) layer, an aluminum nitride (AlN) layer, or a composite barrier layer structure composed of a thin AlN layer and an AlGaN layer. The percentage of aluminum in the barrier layer 104 can be adjusted according to the balance requirements of the two-dimensional electron gas concentration and gate leakage current.

[0093] In some embodiments, the materials for the gate metal and / or source / drain metals are selected from titanium (Ti), titanium nitride (TiN), aluminum (Al), tungsten (W), niobium (Nb), platinum (Pt), tantalum (Ta), vanadium (V), nickel (Ni), molybdenum (Mo), gold (Au), or any combination thereof. For the source 110 and drain 112, a multilayer metal stack structure, such as Ti / Al / Ni / Au, Ti / Al / Mo / Au, etc., is typically used to form a good ohmic contact, and the metal is alloyed with the semiconductor through an annealing process. For the gate 111, a Schottky contact or ohmic contact can be formed as needed, and a multilayer metal structure, such as Ni / Au, Pt / Au, TiN / W, etc., can also be used to obtain the required work function, stability, and reliability.

[0094] In some embodiments, a doped region 107 of a first conductivity type is further formed in the channel layer 103.

[0095] In some embodiments, a doped region 109 of a second conductivity type is further formed in the channel layer 103. Extending the doped region into the channel layer 103 helps to achieve the desired threshold voltage and device conduction characteristics.

[0096] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type, which constitutes a typical structure of an enhancement-mode gallium nitride transistor, achieving normally-off characteristics by depleting the underlying channel through the P-type region.

[0097] In some embodiments, the doped region 107 of the first conductivity type includes a P-type dopant, which is selected from magnesium (Mg), beryllium (Be), zinc (Zn), or any combination thereof.

[0098] In some embodiments, the doped region 109 of the second conductivity type includes an N-type dopant, which is silicon (Si). It can also be other group IV elements, such as germanium (Ge) or carbon (C), or group VI elements, such as oxygen (O).

[0099] In some embodiments, the doping concentration of the P-type doped region and / or the doping concentration of the N-type doped region is 10. 13 -10 22 cm -3 By precisely controlling the type and concentration of dopants, key electrical parameters such as the threshold voltage and on-resistance of the device can be effectively adjusted.

[0100] In some embodiments, refer to Figure 9The semiconductor substrate also includes a capping layer 115 disposed on the barrier layer 104; wherein, a doped region 107 of a first conductivity type and a doped region 109 of a second conductivity type extend into the capping layer 115. The capping layer 115 is typically a gallium nitride layer, which protects the underlying barrier layer 104 from damage by subsequent processes and can be used to adjust the surface potential. By adding the capping layer 115, a preferred barrier layer 104 thickness and a P-type doped region thickness can be achieved simultaneously, thereby optimizing the two-dimensional electron gas concentration and mobility while obtaining an ideal threshold voltage, resolving the contradiction between barrier layer thickness and threshold voltage that is difficult to balance in traditional structures.

[0101] In some embodiments, the thickness of the capping layer 115 is 1-1000 nm.

[0102] In some embodiments, the thickness of the capping layer 115 is preferably 40-100 nm.

[0103] In some embodiments, the thickness of the doped region 107 of the first conductivity type is 40-100 nm.

[0104] In some embodiments, the thickness of the barrier layer 104 is 1-100 nm.

[0105] In some embodiments, the thickness of the barrier layer 104 is preferably 10-30 nm to obtain a high-concentration, high-mobility two-dimensional electron gas, which helps to reduce the on-resistance of the device.

[0106] In some embodiments, the depth of the doped region 107 of the first conductivity type and / or the doped region 109 of the second conductivity type is 1-500 nm.

[0107] In some embodiments, the length of the doped region 107 of the first conductivity type and / or the doped region 109 of the second conductivity type is 1 nm-100 μm.

[0108] In some embodiments, the lower surfaces of the gate metal and the source / drain metal are located on the same plane. This further demonstrates the planarization feature of the device structure of the present invention, a structural advantage that can be obtained by employing a self-aligned synchronous fabrication process.

[0109] In some embodiments, the maximum step height of the planarized surface of the semiconductor substrate is less than 500 nm.

[0110] In some embodiments, the maximum step height is preferably less than 10 nm. Such a small step height allows for a larger process window for subsequent photolithography, etching, and other processes, improving the yield and uniformity of device manufacturing. This advantage is particularly pronounced for devices where critical dimensions such as gate-source pitch (Lgs) are constantly shrinking.

[0111] In some embodiments, refer to Figure 8 and Figure 9 The semiconductor device also includes a metal field plate 114, which is electrically connected to the source 110. The metal field plate 114 can regulate the electric field distribution in the device's off state, effectively weakening the electric field spike effect at the edges of electrodes such as the gate 111 and drain 112, thereby reducing the device's leakage current and significantly increasing the device's breakdown voltage, thus improving the device's withstand voltage capability and long-term operational reliability.

[0112] In some embodiments, the material of the metal field plate 114 is selected from titanium, titanium nitride, aluminum, tungsten, copper, aluminum-copper alloys, or any combination thereof. The metal field plate 114 may also be a multilayer metal stack, such as Ti / Al / TiN, to meet the requirements of conductivity and process stability.

[0113] This invention also provides a method for manufacturing a semiconductor device, referring to... Figure 1 It includes the following steps:

[0114] Step 1: Provide a semiconductor substrate, which includes a substrate 101, a buffer layer 102, a channel layer 103 and a barrier layer 104 formed sequentially.

[0115] Step 2: By ion implantation, a first conductivity type doped region 107 and a second conductivity type doped region 109 are formed in the semiconductor substrate within the barrier layer 104, wherein the conductivity properties of the second conductivity type are opposite to those of the first conductivity type.

[0116] Step 3: Form gate 111, source 110 and drain 112, wherein gate 111 is in contact with doped region 107 of first conductivity type, and source 110 and drain 112 are in contact with doped region 109 of second conductivity type.

[0117] In this method, the surface of the semiconductor substrate is planarized between step two and step three. The core of this method lies in using ion implantation to directly form doped regions on a planar semiconductor substrate, avoiding the high-step etching steps in traditional processes, simplifying the overall process flow, and fundamentally improving the flatness of the device surface.

[0118] The following will combine Figures 2 to 8 This describes a specific manufacturing process.

[0119] Reference Figure 2 A semiconductor substrate is provided. The semiconductor substrate includes a substrate 101, and a buffer layer 102, a channel layer 103, and a barrier layer 104 sequentially epitaxially grown on the substrate 101. These epitaxial layers are typically formed using techniques such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0120] Reference Figure 3 First, a protective dielectric layer 105 is formed on the surface of the semiconductor substrate to protect the semiconductor surface during subsequent ion implantation. Then, a first mask 106, such as a photoresist mask, is formed on the protective dielectric layer 105. The first mask 106 has openings that expose locations where doped regions of a first conductivity type are to be formed. Next, ion implantation is performed using the first mask 106 as a shield to form doped regions 107 of the first conductivity type in the barrier layer 104.

[0121] Reference Figure 4 After removing the first mask 106, a second mask 108 is formed on the protective dielectric layer 105. The second mask 108 has openings that expose the locations where a second conductivity type doped region is to be formed. Then, using the second mask 108 as a shield, ion implantation is performed to form a second conductivity type doped region 109 in the barrier layer 104 (and may further extend into the channel layer 103). Although the accompanying drawings show the sequence of forming the first conductivity type doped region first and then the second conductivity type doped region, those skilled in the art will understand that the order of these two steps can be reversed.

[0122] Reference Figure 5 After completing all ion implantation steps, the second mask 108 is removed. At this point, for activation annealing, the protective dielectric layer 105 can be retained as an annealing protection layer, or the protective dielectric layer 105 can be removed first (e.g., ...). Figure 5 (As shown), a new annealing protective layer is then grown. Annealing is then performed to repair lattice damage and activate the dopant. After annealing, any existing annealing protective layer is removed.

[0123] Reference Figure 6 On the annealed semiconductor substrate, a new dielectric layer (still denoted by 105 in the figure, but can be a newly formed layer) is deposited, and contact vias are formed in the dielectric layer 105 by photolithography and etching. These vias expose the underlying doped regions 107 of the first conductivity type and the doped regions 109 of the second conductivity type, respectively. Since the device surface is highly flat at this time, this step can precisely form contact vias with very small spacing.

[0124] Reference Figure 7 Metal electrodes are formed in the contact vias and on the dielectric layer 105 through metal deposition and patterning processes. Specifically, a gate electrode 111 is formed in the vias exposing a first conductivity type doped region 107, and a source electrode 110 and a drain electrode 112 are formed in the vias exposing a second conductivity type doped region 109. This formation process can be self-aligned simultaneous formation or separate formation.

[0125] Finally refer to Figure 8 The interlayer dielectric 113 and the metal field plate 114 electrically connected to the source electrode 110 can be further formed to complete the fabrication of the device.

[0126] In some embodiments, in step one, the provided semiconductor substrate further includes a capping layer 115 (e.g., formed on the barrier layer 104) Figure 9 (As shown). The capping layer 115 can be formed in situ during the same epitaxial growth process as the buffer layer 102, the channel layer 103, and the barrier layer 104. For example, by adjusting the source gas flow rate in the MOCVD process, a gallium nitride layer can be grown as a capping layer after the barrier layer is grown. This provides a foundation for the subsequent formation of high-performance device structures with doped regions of specific thicknesses.

[0127] In some embodiments, in step two, a doped region 107 of the first conductivity type is further formed in the channel layer 103.

[0128] In some embodiments, in step two, a doped region 109 of the second conductivity type is further formed in the channel layer 103.

[0129] In some embodiments, in step two, the first conductivity type is P-type and the second conductivity type is N-type.

[0130] In some embodiments, in step two, the spacing between the doped region 107 of the first conductivity type and the doped region 109 of the second conductivity type is 1 nm-1 mm. Since the semiconductor structure surface is flat when the two doped regions are formed, it is advantageous to achieve a smaller spacing through processes such as photolithography, thereby reducing device size and improving integration density.

[0131] In some embodiments, step two, forming the doped region by ion implantation, includes performing multiple ion implantations with different energies and doses to form a uniform doping concentration within a predetermined depth of the doped region. For example, a high-energy, low-dose deep implantation can be performed first, followed by one or more low-energy, high-dose shallow implantations, thereby forming an approximately flat "box-shaped" doping distribution, which helps ensure the consistency of electrical properties within the doped region.

[0132] In some embodiments, during the ion implantation step two, a mask is used to define the formation locations of doped regions 107 of a first conductivity type and / or doped regions 109 of a second conductivity type. The step of forming the mask may include: firstly spin-coating a layer of photoresist onto a semiconductor substrate, then exposing it using a photolithography machine, and then developing it, thereby removing the photoresist in the areas where ion implantation is required, while retaining the photoresist in the areas where implantation is not required, thus forming an implantation window.

[0133] In some embodiments, the mask is a photoresist mask. The mask can also be a hard mask, such as silicon oxide, silicon nitride, or a metal layer. Hard masks have better implantation resistance, but the process is relatively complex.

[0134] In some embodiments, during ion implantation, a protective dielectric layer 105, such as silicon oxide (SiO2) or silicon nitride (SiN), is formed on the surface of the semiconductor substrate. x Aluminum nitride (AlN) or aluminum oxide (Al2O3) is used to reduce the damage to the lattice structure of the semiconductor surface caused by high-energy ion bombardment and protect the device surface. This protective dielectric layer 105 can be formed by methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD).

[0135] In some embodiments, after ion implantation, the method further includes a step of removing the protective dielectric layer 105. The removal process may employ wet chemical etching, such as using a hydrofluoric acid solution to remove silicon oxide; or it may employ dry etching, such as reactive ion etching (RIE).

[0136] In some embodiments, in step three, the gate 111, source 110, and drain 112 are formed synchronously in a self-aligned manner. This self-aligned synchronous formation method eliminates the need for high-precision photolithography alignment steps to define the gate, source, and drain electrodes separately, simplifying the process flow, reducing manufacturing costs, and enabling smaller electrode spacing, which is beneficial for device miniaturization and high-frequency performance improvement.

[0137] In some embodiments, the step of self-aligned synchronous formation of gate 111, source 110, and drain 112 includes: forming a dielectric layer 105 on a semiconductor substrate; etching the dielectric layer 105 to form contact vias that simultaneously expose doped regions 107 of a first conductivity type and doped regions 109 of a second conductivity type; depositing a metal layer within the contact vias and on the dielectric layer 105, and patterning the metal layer to form gate 111, source 110, and drain 112. In this process, the material of the formed dielectric layer can be silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, or a low dielectric constant material, etc., and the formation method can include PECVD, HDP-CVD, ALD, etc. Etching the dielectric layer typically employs dry etching techniques using photoresist as a mask, such as reactive ion etching. Before metal deposition, a pre-cleaning step is usually performed to remove the native oxide layer at the bottom of the via. Metal deposition can employ PVD, CVD, or ALD techniques, and a barrier / adhesion layer (such as TiN / TaN) can be deposited first. The patterning of metal layers can be achieved using subtractive methods (etching) or additive methods (lifting processes).

[0138] In some embodiments, in step three, the gate 111, source 110, and drain 112 are formed separately. Separate formation provides greater process flexibility, for example, allowing the selection of different metal materials or different annealing treatments for the gate and source / drain electrodes.

[0139] Specifically, one possible process flow is as follows: First, a dielectric layer is deposited on a semiconductor substrate that has undergone ion implantation and activation annealing, and windows are opened by photolithography and etching to expose only the doped regions 109 of the second conductivity type. Next, a metal stack (e.g., Ti / Al / Ni / Au) for forming ohmic contacts is deposited and patterned to form the source 110 and drain 112, followed by a dedicated source-drain contact annealing to form low-resistance ohmic contacts. After this, a new window is opened in the dielectric layer through a separate photolithography and etching step to expose the underlying doped regions 107 of the first conductivity type. Then, a thin gate dielectric layer is selectively deposited, followed by a gate metal stack (e.g., Ni / Au) with a specific work function, and finally the gate 111 is formed by patterning. The advantage of this process flow is that it decouples process steps with different thermal budget requirements. For example, it completes the source and drain contact annealing, which requires higher temperatures, first, avoiding the impact on the subsequently formed gate structure, which may be temperature-sensitive. At the same time, it also achieves independence in material selection, allowing the selection of the optimal metal material system for the source and drain electrodes and the gate, thereby enabling more flexible comprehensive optimization of device performance.

[0140] In some embodiments, the length of the contact via is less than, equal to, or greater than the length of the doped region it exposes, and the overlap between the contact via and the doped region is greater than 1%. Ensuring sufficient overlap guarantees good electrical contact and reduces contact resistance.

[0141] In some embodiments, the spacing between adjacent contact vias is 1 nm-1 mm.

[0142] In some embodiments, after step two and before step three, the method further includes annealing the semiconductor substrate to repair lattice damage caused by ion implantation and activate the dopant. A dielectric layer can be regrowed to protect the semiconductor surface before annealing. This step is necessary to restore the crystal quality and electrical properties of the semiconductor material.

[0143] In some embodiments, the annealing process includes furnace tube annealing, rapid thermal annealing (RTA), or laser annealing. The annealing temperature, time, and atmosphere (e.g., nitrogen, argon) need to be optimized based on the type of dopant and the characteristics of the semiconductor material to fully activate the dopant while avoiding damage to the material.

[0144] In some embodiments, after step three, the method further includes annealing the gate 111, source 110 and drain 112 to further improve the contact characteristics between the metal and the semiconductor and form a stable low-resistance ohmic contact.

[0145] In some embodiments, after step three, the method further includes forming a metal field plate 114 electrically connected to the source 110.

[0146] One approach is to integrate it with interconnects, a process known as damascene processing. In this approach, the formation of the metal field 114 is integrated into the multilayer metal interconnect process of the semiconductor backend-of-line (BEOL) process. This approach is particularly suitable for processes using copper (Cu) as the interconnect metal. Specifically, the process first deposits one or more electrically insulating interlayer dielectrics 113, such as low-k materials or conventional silicon oxide and silicon nitride, on the structure where the gate, source, and drain electrodes have already been formed. Next, using photolithography and dry etching processes, trench patterns are etched in the interlayer dielectric 113 to define the metal field 114 and other interconnects, and contact vias for connecting the underlying source electrode 110 are also etched simultaneously. In advanced processes, this can be accomplished in one step using a dual damascene process. Then, metal is filled into the formed trenches and vias. For copper processes, this typically includes depositing a barrier / backer layer (such as TaN / Ta), depositing a copper seed layer, and filling copper via electrochemical deposition (ECD). Finally, planarization is performed using a chemical mechanical polishing (CMP) process to remove excess metal from the dielectric layer surface, thereby forming embedded metal field plates 114 and interconnects within the dielectric layer 113.

[0147] Another approach is to form it as a separate step, known as a subtractive process. In this approach, the formation of the metal field 114 is a separate, proprietary process step, not performed in the same step as other interconnects. This approach is particularly suitable for processes using aluminum (Al) as the primary metal. The process first deposits a passivation or isolation dielectric layer as an insulating substrate on the completed device structure. Subsequently, one or more layers of metal, such as an aluminum-copper (AlCu) alloy stack including an adhesion / barrier layer (e.g., Ti / TiN) and an anti-reflection coating (ARC), are deposited comprehensively across the entire wafer surface using methods such as physical vapor deposition (PVD). After metal deposition, a photoresist pattern precisely defining the shape of the metal field 114 is formed on the metal layer using photolithography. Then, using this photoresist pattern as a mask, dry etching techniques such as reactive ion etching (RIE) are employed, using chlorine- or fluorine-containing plasma chemical gases, to remove the metal areas not protected by the photoresist. Finally, the remaining photoresist mask is removed by plasma ashing or wet chemical stripping, leaving a metal field plate 114 of the desired shape on the passivation layer. It is worth noting that the metal field plate 114 can be formed on any suitable metal interconnect layer (e.g., first metal layer M1, second metal layer M2, etc.), and its specific location and formation method can be flexibly selected according to the overall design and integration scheme of the device.

[0148] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0149] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising a substrate, a buffer layer, a channel layer and a barrier layer formed sequentially; A doped region of the first conductivity type is formed in the barrier layer; A doped region of a second conductivity type is formed in the barrier layer, the conductivity of the second conductivity type being opposite to that of the first conductivity type; A gate, the gate comprising a gate metal in contact with a doped region of the first conductivity type; as well as Source and drain, the source and drain comprising source and drain metals in contact with a doped region of the second conductivity type; The gate, the source, and the drain are formed on the same side of the semiconductor substrate with a planarized surface.

2. The semiconductor device according to claim 1, characterized in that: The substrate is made of a material selected from silicon, silicon carbide, sapphire, gallium nitride, or diamond.

3. The semiconductor device according to claim 1, characterized in that: The buffer layer includes doped gallium nitride, doped aluminum gallium nitride, or a superlattice structure formed by alternating doped gallium nitride and doped aluminum gallium nitride.

4. The semiconductor device according to claim 1, characterized in that: The channel layer is an undoped gallium nitride layer.

5. The semiconductor device according to claim 1, characterized in that: The barrier layer is an undoped gallium aluminum nitride layer.

6. The semiconductor device according to claim 1, characterized in that: The materials of the gate metal and / or the source / drain metal are selected from titanium, titanium nitride, aluminum, tungsten, niobium, platinum, tantalum, vanadium, nickel, molybdenum, gold, or any combination thereof.

7. The semiconductor device according to claim 1, characterized in that: The doped region of the first conductivity type is further formed in the channel layer.

8. The semiconductor device according to claim 1, characterized in that: The doped region of the second conductivity type is further formed in the channel layer.

9. The semiconductor device according to claim 1, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type.

10. The semiconductor device according to claim 9, characterized in that: The doped region of the first conductivity type includes a P-type dopant, which is selected from magnesium, beryllium, zinc, or any combination thereof.

11. The semiconductor device according to claim 9, characterized in that: The doped region of the second conductivity type includes an N-type dopant, wherein the N-type dopant is silicon.

12. The semiconductor device according to claim 9, characterized in that: The doping concentration of the P-type doped region and / or the doping concentration of the N-type doped region is 10. 13 -10 22 cm -3 .

13. The semiconductor device according to claim 1, characterized in that: The semiconductor substrate further includes a capping layer disposed on the barrier layer; wherein the doped regions of the first conductivity type and the doped regions of the second conductivity type extend into the capping layer.

14. The semiconductor device according to claim 13, characterized in that: The thickness of the capping layer is 1-1000 nm.

15. The semiconductor device according to claim 14, characterized in that: The thickness of the capping layer is 40-100 nm.

16. The semiconductor device according to claim 13 or 14, characterized in that: The thickness of the doped region of the first conductivity type is 40-100 nm.

17. The semiconductor device according to claim 1, characterized in that: The thickness of the barrier layer is 1-100 nm.

18. The semiconductor device according to claim 17, characterized in that: The thickness of the barrier layer is 10-30 nm.

19. The semiconductor device according to claim 1, characterized in that: The depth of the doped region of the first conductivity type and / or the doped region of the second conductivity type is 1-500 nm.

20. The semiconductor device according to claim 1, characterized in that: The length of the doped region of the first conductivity type and / or the doped region of the second conductivity type is 1 nm-100 μm.

21. The semiconductor device according to claim 1, characterized in that: The lower surface of the gate metal and the lower surface of the source / drain metal are located on the same plane.

22. The semiconductor device according to claim 1 or 21, characterized in that: The maximum step height of the planarized surface of the semiconductor substrate is less than 500 nm.

23. The semiconductor device according to claim 1, characterized in that: The maximum step height is less than 10 nm.

24. The semiconductor device according to claim 1, characterized in that: Also includes: A metal field plate, which is electrically connected to the source electrode.

25. The semiconductor device according to claim 24, characterized in that: The material of the metal field plate is selected from titanium, titanium nitride, aluminum, tungsten, copper, aluminum-copper alloy or any combination thereof.

26. A method for manufacturing a semiconductor device, characterized in that, include: Step 1: Provide a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, a buffer layer, a channel layer and a barrier layer formed sequentially; Step 2: By ion implantation, a first conductivity type doped region and a second conductivity type doped region are formed in the semiconductor substrate within the barrier layer, wherein the conductivity properties of the second conductivity type are opposite to those of the first conductivity type. Step 3: Forming a gate, a source, and a drain, wherein the gate is in contact with a doped region of the first conductivity type, and the source and drain are in contact with doped regions of the second conductivity type; In particular, after step two and before step three, the surface of the semiconductor substrate is a planarized surface.

27. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step two, the doped region of the first conductivity type is further formed in the channel layer.

28. The method for manufacturing a semiconductor device according to claim 26 or 27, characterized in that: In step two, the doped region of the second conductivity type is further formed in the channel layer.

29. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step two, the first conductivity type is P-type, and the second conductivity type is N-type.

30. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step two, the spacing between the doped region of the first conductivity type and the doped region of the second conductivity type is 1 nm-1 mm.

31. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step two, the step of forming a doped region by ion implantation includes: performing multiple ion implantations with different energies and doses to form a uniform doping concentration within a predetermined depth of the doped region.

32. The method for manufacturing a semiconductor device according to claim 26, characterized in that: During ion implantation in step two, a mask is used to define the formation locations of doped regions of the first conductivity type and / or doped regions of the second conductivity type.

33. The method for manufacturing a semiconductor device according to claim 32, characterized in that: The mask is a photoresist mask.

34. The method for manufacturing a semiconductor device according to claim 26, characterized in that: During the ion implantation in step two, a protective dielectric layer is disposed on the surface of the semiconductor substrate.

35. The method for manufacturing a semiconductor device according to claim 34, characterized in that: Following the ion implantation in step two, the method further includes the step of removing the protective dielectric layer.

36. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step three, the gate, source, and drain are formed synchronously in a self-aligned manner.

37. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step three, the gate, source, and drain are formed separately.

38. The method for manufacturing a semiconductor device according to claim 36, characterized in that: The step of self-aligned synchronous formation of the gate, source, and drain includes: forming a dielectric layer on the semiconductor substrate; etching the dielectric layer to form a contact via that simultaneously exposes a doped region of the first conductivity type and a doped region of the second conductivity type; depositing a metal layer in the contact via and on the dielectric layer; and patterning the metal layer to form the gate, source, and drain.

39. The method for manufacturing a semiconductor device according to claim 38, characterized in that: The length of the contact via is less than, equal to or greater than the length of the doped region it exposes, and the overlap between the contact via and the doped region is greater than 1%.

40. The method for manufacturing a semiconductor device according to claim 38, characterized in that: The spacing between adjacent contact vias is 1 nm to 1 mm.

41. The method for manufacturing a semiconductor device according to claim 26, characterized in that: After step two and before step three, the method further includes: annealing the semiconductor substrate to repair lattice damage caused by the ion implantation and activate the dopant.

42. The method for manufacturing a semiconductor device according to claim 41, characterized in that: The annealing process includes furnace tube annealing, rapid thermal annealing, or laser annealing.

43. The method for manufacturing a semiconductor device according to claim 26, characterized in that: After step three, the method further includes annealing the gate, source, and drain.

44. The method for manufacturing a semiconductor device according to claim 26, characterized in that: After step three, the method further includes: forming a metal field plate electrically connected to the source electrode.

45. The method for manufacturing a semiconductor device according to claim 26, characterized in that: In step one, the provided semiconductor substrate further includes a capping layer formed on the barrier layer.

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