Semiconductor device structure and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor device structure comprises a substrate, a bottom doped region, a drift region, a first doped region, a second doped region and a plurality of mutually independent third doped regions, the third doped regions are located in the drift region and are connected with the first doped region, and the number, depth and doping concentration of the third doped regions in the longitudinal direction are flexibly adjusted. JFETs with different pinch-off voltages can be designed, and an original GSD structure does not need to be changed. And the multi-channel structure enables the current capability of the JFET to be improved. Compared with the prior art, the embodiment of the invention can realize different pinch-off voltages by adjusting the process structure under the condition of the original GSD structure, the pinch-off voltage diversity is better, and the electrical performance is better.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device structure and its fabrication method. Background Technology

[0002] Junction Field-Effect Transistors (JFETs) in related technologies, such as conventional vertical depletion pinch-off JFET structures, typically include a P-type substrate. The P-type substrate contains a P-type bottom doped region, an N-type drift region, and a heavily doped P-type region. In cases of parasitic behavior, and given that the plateau's IMP type is generally fixed, pinch-off is difficult to achieve, making it challenging to fabricate parasitic JFETs. Even if pinch-off occurs, the P-type bottom doped region and the heavily doped P-type region actually form depletion regions with the N-type drift region, and these two depletion regions are connected to achieve vertical pinch-off. Therefore, even if this structure can achieve pinch-off, it can only achieve a single pinch-off voltage. Consequently, conventional JFETs typically only achieve a single pinch-off voltage Vp, failing to meet the requirements for designing different pinch-off voltages. Summary of the Invention

[0003] The present invention aims to provide a semiconductor device structure and a method for fabricating the semiconductor device structure, which can achieve different pinch-off voltages without changing the original GSD structure by adjusting the process structure, resulting in better pinch-off voltage diversity and better electrical performance.

[0004] The embodiments of the present invention can be implemented as follows: In a first aspect, the present invention provides a semiconductor device structure, comprising: Substrate; The bottom doped region is located within the substrate; A drift region is located within the substrate and adjacent to the top of the bottom doped region; A first doped region is located on the bottom doped region and around the drift region, and the first doped region is in contact with both the drift region and the bottom doped region. The second doped region is located within the drift region and exposes the top surface, and the second doped region and the bottom doped region are located on both sides of the drift region along a direction perpendicular to the substrate; Several independent third doped regions are located within the drift region and between the second doped region and the bottom doped region. The third doped region penetrates the drift region and connects to the first doped region in a first direction, wherein the first direction is parallel to the substrate. The first doped region, the second doped region, the third doped region, and the bottom doped region have the same conductivity type, which is opposite to that of the drift region.

[0005] In an optional embodiment, the third doped regions are distributed sequentially at intervals along a direction perpendicular to the substrate, and are all parallel to the bottom doped regions.

[0006] In an alternative implementation, the distance between each two adjacent third doped regions increases sequentially along the direction away from the bottom doped region.

[0007] In an optional implementation, the doping concentration of the third doped region is greater than that of the first doped region; the doping concentration of the second doped region is greater than that of the first doped region.

[0008] In an alternative implementation, the doping concentration of the third doped region is the same or gradually decreases along the direction away from the bottom doped region.

[0009] In an optional embodiment, the semiconductor device structure further includes: A top isolation structure is located on the top surface of the drift region; The source region and the drain region are located within the drift region and exposed on the top surface, and the source region and the drain region are located on both sides of the top isolation structure along a second direction, wherein the second direction is parallel to the substrate and perpendicular to the first direction.

[0010] In an optional embodiment, the semiconductor device structure further includes: A first isolation structure is located around the drift region and exposes its top surface, and the first isolation structure is located between the drift region and the first doped region.

[0011] In an optional embodiment, the semiconductor device structure further includes: A fourth doped region surrounds the first doped region and is independent of the first doped region, and the conductivity type of the fourth doped region is opposite to that of the first doped region; A buried layer is located within the substrate and below the bottom doped region and the fourth doped region. The bottom of the bottom doped region and the bottom of the fourth doped region are in contact with the buried layer. The conductivity type of the buried layer is the same as that of the fourth doped region. A second isolation structure is located around the first doped region and exposes its top surface, and the second isolation structure is located between the first doped region and the fourth doped region.

[0012] In an optional embodiment, the semiconductor device structure further includes: A fifth doped region is located within the substrate and surrounds the fourth doped region, and the fifth doped region has the same conductivity type as the first doped region. A third isolation structure is located around the fourth doped region and exposes its top surface, and the third isolation structure is located between the fourth doped region and the fifth doped region; The device isolation structure is located around the fifth doped region and exposes the top surface.

[0013] In a second aspect, the present invention provides a method for fabricating a semiconductor device structure, used to fabricate the semiconductor device structure as described in the foregoing embodiments, the method comprising: Provide a substrate; A bottom doped region is formed within the substrate; A drift region is formed in the substrate adjacent to the bottom doped region; A first doped region is formed on the bottom doped region and around the drift region, wherein the first doped region is in contact with the drift region and the bottom doped region, respectively.

[0014] Several independent third doped regions are formed within the drift region. The third doped regions penetrate the drift region and connect to the first doped region in a direction parallel to the substrate. A second doped region is formed in the drift region, wherein the second doped region exposes the top surface, and the second doped region and the bottom doped region are respectively located on both sides of the drift region along a direction perpendicular to the substrate, and the third doped region is located between the second doped region and the bottom doped region; The first doped region, the second doped region, the third doped region, and the bottom doped region have the same conductivity type, which is opposite to that of the drift region.

[0015] The beneficial effects of the semiconductor device structure and the method for fabricating the semiconductor device structure provided in the embodiments of the present invention include: The semiconductor device structure and its fabrication method provided in this invention include a bottom doped region and a drift region formed within a substrate, with the drift region adjacent to the top of the bottom doped region. A first doped region is also disposed around the bottom doped region and the drift region, and this first doped region contacts both the drift region and the bottom doped region. A second doped region is also disposed within the drift region, exposing its top surface, and is located on opposite sides of the drift region along a direction perpendicular to the substrate. Several independent third doped regions are also disposed within the drift region, located between the second and bottom doped regions, and extending through the drift region and connecting to the first doped region in a direction parallel to the substrate. The first, second, and third doped regions have the same conductivity type, which is opposite to that of the drift region. In actual operation, the second, third, and bottom doped regions can all form depletion regions with the drift region, thereby achieving pinch-off. By flexibly adjusting the number, depth, and doping concentration of the third doped region in the vertical direction, JFETs with different pinch-off voltages can be designed without changing the original GSD structure. Furthermore, this multi-channel structure enhances the current capability of the JFET. Compared to existing technologies, this invention allows for the achievement of different pinch-off voltages within the existing GSD structure through adjustments to the process structure, resulting in better pinch-off voltage diversity and superior electrical performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a JFET device in the prior art; Figure 2 A partial top view of a semiconductor device structure is provided for embodiments of the present invention; Figure 3 To provide embodiments of the present invention, a semiconductor device structure is provided along... Figure 2 Schematic diagram of the cross-sectional structure along the AA direction; Figure 4 To provide embodiments of the present invention, a semiconductor device structure is provided along... Figure 2 Schematic diagram of the cross-sectional structure in the middle BB direction; Figure 5 To provide embodiments of the present invention, a semiconductor device structure is provided along... Figure 2 A schematic diagram of the cross-sectional structure along the CC direction; Figure 6This is a schematic diagram of the depletion region in the pinch-off state.

[0018] Icons: 100 - Semiconductor device structure; 110 - Substrate; 111 - Base layer; 112 - Epitaxial layer; 120 - Bottom doped region; 130 - Drift region; 131 - Source region; 132 - Drain region; 133 - First isolation structure; 140 - First doped region; 150 - Second doped region; 151 - Top isolation structure; 160 - Third doped region; 170 - Fourth doped region; 171 - Second isolation structure; 180 - Buried layer; 190 - Fifth doped region; 191 - Third isolation structure; 192 - Device isolation structure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0023] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0024] As disclosed in the background section, see Figure 1Existing vertical depletion pinch-off JFET structures typically include a P-type substrate, a P-type bottom doped region, an N-type drift region, and a heavily doped P-type region. The P-type bottom doped region and the heavily doped P-type region form depletion regions with the N-type drift region, and these two depletion regions are connected to achieve vertical pinch-off. However, this structure has the following drawbacks and limitations: 1. In cases where parasitic behavior is required, the platform's IMP type is generally fixed, making pinch-off difficult and thus hindering the fabrication of parasitic JFETs. 2. Even if pinch-off is achieved, this structure can only achieve a single pinch-off voltage, making it difficult to meet the needs of designing different pinch-off voltages.

[0025] To address the aforementioned problems, this invention provides a novel semiconductor device structure and its fabrication method. By adding several third doped regions with the opposite conductivity type to the drift region within the drift region, multiple depletion regions can be formed, facilitating better vertical pinch-off and enhancing current carrying capacity through multiple channels, resulting in a larger current throughput. Furthermore, different pinch-off voltages can be directly achieved by controlling parameters such as the number, concentration, and depth of the third doped regions. Through adjustments to the process structure, different pinch-off voltages can be achieved within the existing GSD structure, resulting in greater pinch-off voltage diversity. It should be noted that features in the embodiments of this invention can be combined with each other unless otherwise specified. The following detailed description, using embodiments and accompanying drawings, outlines the overall structure, working principle, and technical effects of the semiconductor device structure provided by this invention, as well as the detailed steps, implementation principles, and technical effects of the supporting methods.

[0026] See Figures 2 to 5 This invention provides a semiconductor device structure 100 that can achieve different pinch-off voltages without changing the original GSD structure by adjusting the process structure, resulting in better pinch-off voltage diversity and better electrical performance.

[0027] The semiconductor device structure 100 provided in this embodiment of the invention may include a substrate 110, a bottom doped region 120, a drift region 130, a first doped region 140, a second doped region 150, and several independent third doped regions 160.

[0028] The bottom doped region 120 and the drift region 130 are both located within the substrate 110, with the drift region 130 adjacent to and above the bottom doped region 120, meaning the drift region 130 is located above and in contact with the bottom doped region 120. The first doped region 140 is located on the bottom doped region 120 and around the drift region 130, and the first doped region 140 is in contact with both the drift region 130 and the bottom doped region 120. The second doped region 150 is located within the drift region 130 and exposes its top surface, with the second doped region 150 and the bottom doped region 120 located on opposite sides of the drift region 130 along a direction perpendicular to the substrate 110. Several independent third doped regions 160 are located within the drift region 130 and between the second doped region 150 and the bottom doped region 120. The third doped regions 160 penetrate the drift region 130 and connect to the first doped region 140 in a first direction parallel to the substrate 110. The first doped region 140, the second doped region 150, the third doped region 160 and the bottom doped region 120 have the same conductivity type, which is opposite to that of the drift region 130.

[0029] It should be noted that the semiconductor device structure 100 mentioned in this embodiment refers to a JFET device structure. Since the drift region 130 has several third doped regions 160 with opposite conductivity types, and the third doped regions 160 penetrate the drift region 130 along a first direction parallel to the substrate 110 and connect to the first doped region 140 with the same conductivity type, the first doped region 140 is located above the bottom doped region 120 and around the drift region 130, and contacts both the drift region 130 and the bottom doped region 120. Therefore, by adjusting the spacing (i.e., doping depth), doping concentration, and number of the third doped regions 160, the distribution and width of the depletion region can be adjusted, thereby adjusting the pinch-off voltage Vp of the JFET device. Therefore, by flexibly adjusting the number, depth, and doping concentration of the third doped regions 160 in the vertical direction, JFETs with different pinch-off voltages can be designed without changing the original GSD structure (i.e., the original gate, source, and drain region 131 layout). Furthermore, this multi-channel structure can improve the current capability of the JFET. Compared to existing technologies, the embodiments of the present invention can achieve different pinch-off voltages within the original GSD structure by adjusting the process structure, resulting in better pinch-off voltage diversity and better electrical performance.

[0030] See also Figure 6 , Figure 6The dashed lines in the diagram represent the depletion region. Specifically, the first doped region 140, the second doped region 150, the third doped region 160, and the bottom doped region 120 can all be P-type doped, while the drift region 130 can be N-type doped. The first doped region 140 is connected to the bottom doped region 120, the second doped region 150, and the third doped region 160, allowing the second doped region 150 and the third doped region 160 to be connected to a voltage via the first doped region 140, thus forming depletion regions at the junction of the second doped region 150 and the third doped region 160 and the surrounding drift region 130. As the applied voltage gradually increases, the vertical width of the depletion region gradually increases until the applied voltage reaches the pinch-off voltage Vp, causing multiple depletion regions to connect and achieving vertical pinch-off. The design of multiple depletion regions makes pinch-off easier to achieve, and the multi-channel design also improves current capability and electrical performance. Here, the width of the depletion region required for pinch-off can be adjusted by adjusting the depth, concentration, and number of the third doped region 160, thereby adjusting the pinch-off voltage Vp. This allows JFET devices with various excellent pinch-off voltages Vp to be designed and fabricated on the same platform without adjusting the process structure.

[0031] In some embodiments, the third doped regions 160 are distributed sequentially at intervals along a direction perpendicular to the substrate 110, and are all parallel to the bottom doped region 120. Specifically, there are multiple third doped regions 160, and the multiple third doped regions 160 are parallel to each other, and the longitudinal width of the multiple third doped regions 160 may be the same.

[0032] In some embodiments, the distance between every two adjacent third doped regions 160 increases sequentially in the direction away from the bottom doped region 120. Specifically, when actually fabricating multiple third doped regions 160, they can be formed by ion implantation at different depths using the same mask, and the spacing between adjacent third doped regions 160 increases sequentially from bottom to top, which can make the depletion region more uniform. The concentration and number of third doped regions 160 can be adjusted according to the required pinch-off voltage Vp.

[0033] In some embodiments, the doping concentration of the third doped region 160 is greater than that of the first doped region 140; the doping concentration of the second doped region 150 is greater than that of the first doped region 140. Specifically, the doping concentration of the third doped region 160 is also greater than that of the drift region 130. Typically, the doping concentrations of the second doped region 150 and the third doped region 160 need to be relatively higher, while the doping concentration of the drift region 130 needs to be relatively lower. This allows the depletion region formed by the third doped region 160 / the second doped region 150 and the drift region 130 to advance as far into the drift region 130 as possible, thereby achieving better turn-off.

[0034] Furthermore, in an optional embodiment, the doping concentration of the third doped region 160 is the same or gradually decreases along the direction away from the bottom doped region 120. Preferably, the doping concentration of the third doped region 160 is the same, thereby reducing the fabrication difficulty and processes. Of course, the doping concentration of the third doped region 160 can also gradually decrease from bottom to top, ensuring that the depletion region can be completely distributed.

[0035] The longitudinal depletion pinch-off JFET structure provided in this invention allows for flexible adjustment of the number of third doped regions 160 in the longitudinal direction. Furthermore, by adjusting the IMP (Ion Implantation) process, the depth and concentration of the P-type IMP at the G-terminus can be controlled, i.e., the spacing and concentration of the third doped regions 160 can be controlled. This enables the design of JFETs with various pinch-off voltages Vp. Moreover, this multi-channel design enhances the current capability of the JFET, significantly increasing the versatility of device design requirements.

[0036] Furthermore, in this JFET structure, a high concentration of the third doped region 160 and a low concentration of the N-type current channel region (NDF), i.e., a low concentration of the drift region 130, are generally required. This allows the depletion region of the third doped region 160 and the NDF junction to be pushed as far as possible into the N-type drift region 130, thus achieving better turn-off. In terms of fabrication, different depths of IMP are fabricated using the same mask, and the spacing between the third doped regions 160 decreases from top to bottom to ensure a more uniform distribution of the depletion region. The number and concentration of the third doped region 160 can be adjusted according to the required pinch-off voltage.

[0037] Those skilled in the art will understand that, in practical applications, the pinch-off voltage Vp, doping concentration, depth, and number of the third doped region 160 can vary considerably depending on the device material, JFET device structure, and application. The relationship between these two factors also varies considerably. Therefore, this application does not impose any specific limitations on these aspects.

[0038] It is worth noting that the substrate 110 here is a P-type substrate 110, and the substrate 110 includes a base layer 111 and an epitaxial layer 112. The epitaxial layer 112 is located on the base layer 111, and the drift layer, the bottom doped region 120, and the first doped region 140 are all located within the epitaxial layer 112. The material of the substrate 110 here can be silicon, germanium, or germanium-silicon, or it can also be an SOI substrate 110.

[0039] Please continue reading Figures 2 to 5 In some embodiments, the semiconductor device structure 100 may further include a top isolation structure 151, a source region 131, and a drain region 132.

[0040] In this embodiment, the top isolation structure 151 is located on the top surface of the drift region 130; the source region 131 and the drain region 132 are located within the drift region 130 and expose the top surface, and the source region 131 and the drain region 132 are located on both sides of the top isolation structure 151 along a second direction, wherein the second direction is perpendicular to the first direction and parallel to the substrate 110. Specifically, the top isolation structure 151 includes spaced-apart silicide barrier layers (SAB) and exposes the top surface of the second doped region 150. Meanwhile, the source region 131 and the drain region 132 are also located on both sides of the second doped region 150.

[0041] In some embodiments, the semiconductor device structure 100 may further include a first isolation structure 133, which is located around the drift region 130 and exposes the top surface, and is located between the drift region 130 and the first doped region 140.

[0042] Specifically, the first isolation structure 133 may be a shallow trench isolation structure (STI), and a heavily doped P first contact region is formed on the top of the first doped region 140. The doping concentration of the first contact region is greater than that of the first doped region 140 to better bring out the first doped region 140. The first isolation structure 133 is located between the first contact region and the drift region 130, and the first isolation structure 133 does not block the contact between the drift region 130 and the first doped region 140.

[0043] In some embodiments, the semiconductor device structure 100 may further include a fourth doped region 170, a buried layer 180, and a second isolation structure 171. The fourth doped region 170 surrounds the first doped region 140 and is independent of the first doped region 140, and the conductivity type of the fourth doped region 170 is opposite to that of the first doped region 140. The buried layer 180 is located within the substrate 110 and below the bottom doped region 120 and the fourth doped region 170. The bottom of the bottom doped region 120 and the bottom of the fourth doped region 170 are both in contact with the buried layer, and the conductivity type of the buried layer 180 is the same as that of the fourth doped region 170. The second isolation structure 171 is located around the first doped region 140 and exposes the top surface, and the second isolation structure 171 is located between the first doped region 140 and the fourth doped region 170.

[0044] Specifically, the buried layer 180 can be an N-type buried layer 180 structure (NBL), with the bottom doped region 120 located on the buried layer 180. The fourth doped region 170 is an N-type doped region located on the buried layer 180 and can serve as a shielded N-well (SNW). A heavily doped N second contact region is formed on top of the fourth doped region 170. The second isolation structure 171 can also be a shallow trench isolation structure (STI) located between the second contact region and the first doped region 140.

[0045] In some embodiments, the semiconductor device structure 100 may further include a fifth doped region 190, a third isolation structure 191, and a device isolation structure 192. The fifth doped region 190 is located within the substrate 110 and surrounds the fourth doped region 170, and the fifth doped region 190 has the same conductivity type as the first doped region 140. The third isolation structure 191 is located around the fourth doped region 170 and exposes its top surface, and the third isolation structure 191 is located between the fourth doped region 170 and the fifth doped region 190. The device isolation structure 192 is located around the fifth doped region 190 and exposes its top surface.

[0046] Specifically, the fifth doped region 190 is a P-type doped region and is located within the epitaxial layer 112 in the substrate 110, thereby enabling the extraction of the substrate 110. A heavily P-doped third contact region is also formed on top of the fifth doped region 190, and the third isolation structure 191 can also be a shallow trench isolation structure (STI) located between the third contact region and the fourth doped region 170. The device isolation structure 192 can also be a shallow trench isolation structure (STI) and surrounds and contacts the fifth doped region 190, thereby isolating the semiconductor device structure 100 from other surrounding devices.

[0047] This invention also provides a method for fabricating a semiconductor device structure 100. The method may include: providing a substrate 110; forming a bottom doped region 120 within the substrate 110; forming a drift region 130 adjacent to the bottom doped region 120 within the substrate 110; forming a first doped region 140 on the bottom doped region 120 and around the drift region 130, wherein the first doped region 140 contacts both the drift region 130 and the bottom doped region 120. A plurality of independent third doped regions 160 are formed within the drift region 130, and the third doped regions 160 penetrate the drift region 130 and connect to the first doped regions 140 in a first direction parallel to the substrate 110. A second doped region 150 is formed in the drift region 130, wherein the second doped region 150 exposes the top surface, and the second doped region 150 and the bottom doped region 120 are located on both sides of the drift region 130 along the direction perpendicular to the substrate 110, respectively, and a third doped region 160 is located between the second doped region 150 and the bottom doped region 120; wherein the first doped region 140, the second doped region 150, the third doped region 160 and the bottom doped region 120 have the same conductivity type and the opposite conductivity type to the drift region 130.

[0048] It should be noted that when providing the substrate 110, an epitaxial layer 112 can be first epitaxially grown on the base layer 111, and then a bottom doped region 120 can be formed within the epitaxial layer 112 by ion implantation. A drift region 130 can then be formed within the epitaxial layer 112 by ion implantation. A first doped region 140 can then be formed around the bottom doped region 120 by ion implantation. Multiple third doped regions 160 can then be formed using the same mask and by controlling the ion implantation depth, and finally a second doped region 150 can be formed by ion implantation.

[0049] It is worth noting that multiple third doped regions 160 are formed here by drilling IMPs at different depths using the same mask. Specifically, this can be achieved by controlling the ion implantation concentration and implantation energy to form the third doped regions 160 at different depths within the drift region 130.

[0050] In summary, the semiconductor device structure 100 and its fabrication method provided in this embodiment of the invention form a bottom doped region 120 and a drift region 130 within a substrate 110, with the drift region 130 adjacent to the top of the bottom doped region 120. A first doped region 140 is also disposed around the bottom doped region 120 and the drift region 130, and the first doped region 140 contacts both the drift region 130 and the bottom doped region 120. A second doped region 150 is also disposed within the drift region 130, with the top surface exposed, and the second doped region 150 and the bottom doped region 120 are located on opposite sides of the drift region 130 along a direction perpendicular to the substrate 110. Several independent third doped regions 160 are also disposed within the drift region 130. The third doped regions 160 are located between the second doped region 150 and the bottom doped region 120, and extend through the drift region 130 and connect to the first doped region 140 in a direction parallel to the substrate 110. The first doped region 140, the second doped region 150, and the third doped region 160 have the same conductivity type, which is opposite to that of the drift region 130. In actual operation, the second doped region 150, the third doped region 160, and the bottom doped region 120 can all form depletion regions with the drift region 130, thereby achieving pinch-off. By flexibly adjusting the number, depth, and doping concentration of the third doped regions 160 in the vertical direction, JFETs with different pinch-off voltages can be designed without changing the original GSD structure. Furthermore, this multi-channel structure can improve the current capability of the JFET. Compared to existing technologies, the embodiments of the present invention can achieve different pinch-off voltages within the original GSD structure by adjusting the process structure, resulting in better pinch-off voltage diversity and better electrical performance.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device structure, characterized in that, include: Substrate; The bottom doped region is located within the substrate; A drift region is located within the substrate and adjacent to the top of the bottom doped region; A first doped region is located on the bottom doped region and around the drift region, and the first doped region is in contact with both the drift region and the bottom doped region. The second doped region is located within the drift region and exposes the top surface, and the second doped region and the bottom doped region are located on both sides of the drift region along a direction perpendicular to the substrate; Several independent third doped regions are located within the drift region and between the second doped region and the bottom doped region. The third doped region penetrates the drift region and connects to the first doped region in a first direction, wherein the first direction is parallel to the substrate. The first doped region, the second doped region, the third doped region, and the bottom doped region have the same conductivity type, which is opposite to that of the drift region.

2. The semiconductor device structure according to claim 1, characterized in that, The third doped regions are distributed sequentially at intervals along a direction perpendicular to the substrate, and are all parallel to the bottom doped regions.

3. The semiconductor device structure according to claim 2, characterized in that, Along the direction away from the bottom doped region, the distance between each two adjacent third doped regions increases sequentially.

4. The semiconductor device structure according to claim 3, characterized in that, The doping concentration of the third doped region is greater than that of the first doped region; the doping concentration of the second doped region is greater than that of the first doped region.

5. The semiconductor device structure according to claim 3, characterized in that, Along the direction away from the bottom doped region, the doping concentration of the third doped region is the same or gradually decreases.

6. The semiconductor device structure according to any one of claims 1-5, characterized in that, The semiconductor device structure also includes: A top isolation structure is located on the top surface of the drift region; The source region and the drain region are located within the drift region and exposed on the top surface, and the source region and the drain region are located on both sides of the top isolation structure along a second direction, wherein the second direction is parallel to the substrate and perpendicular to the first direction.

7. The semiconductor device structure according to any one of claims 1-5, characterized in that, The semiconductor device structure also includes: A first isolation structure is located around the drift region and exposes its top surface, and the first isolation structure is located between the drift region and the first doped region.

8. The semiconductor device structure according to any one of claims 1-5, characterized in that, The semiconductor device structure also includes: A fourth doped region surrounds the first doped region and is independent of the first doped region, and the conductivity type of the fourth doped region is opposite to that of the first doped region; A buried layer is located within the substrate and below the bottom doped region and the fourth doped region. The bottom of the bottom doped region and the bottom of the fourth doped region are in contact with the buried layer. The conductivity type of the buried layer is the same as that of the fourth doped region. A second isolation structure is located around the first doped region and exposes its top surface, and the second isolation structure is located between the first doped region and the fourth doped region.

9. The semiconductor device structure according to claim 8, characterized in that, The semiconductor device structure also includes: A fifth doped region is located within the substrate and surrounds the fourth doped region, and the fifth doped region has the same conductivity type as the first doped region. A third isolation structure is located around the fourth doped region and exposes its top surface, and the third isolation structure is located between the fourth doped region and the fifth doped region; The device isolation structure is located around the fifth doped region and exposes the top surface.

10. A method for fabricating a semiconductor device structure, characterized in that, The method includes: Provide a substrate; A bottom doped region is formed within the substrate; A drift region is formed in the substrate adjacent to the bottom doped region; A first doped region is formed on the bottom doped region and around the drift region, wherein the first doped region is in contact with the drift region and the bottom doped region, respectively; A plurality of independent third doped regions are formed within the drift region. The third doped regions penetrate the drift region along a first direction and connect to the first doped regions, wherein the first direction is parallel to the substrate. A second doped region is formed in the drift region, wherein the second doped region exposes the top surface, and the second doped region and the bottom doped region are respectively located on both sides of the drift region along a direction perpendicular to the substrate, and the third doped region is located between the second doped region and the bottom doped region; The first doped region, the second doped region, the third doped region, and the bottom doped region have the same conductivity type, which is opposite to that of the drift region.

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