Terminal structure and preparation method thereof, semiconductor device and vehicle

Abstract

The invention relates to a terminal structure and a preparation method thereof, a semiconductor device and a vehicle, and the terminal structure comprises a substrate of a first conduction type, and the substrate is provided with at least one field limiting ring of a second conduction type; a plurality of well regions of a second conduction type are arranged on the field limiting ring in the substrate along the length direction of the field limiting ring at intervals; a plurality of well regions with the same conduction type as the field limiting ring are arranged on the field limiting ring in the substrate in the length direction of the field limiting ring at intervals, a two-dimensional depletion model of a traditional field ring terminal is converted into a three-dimensional depletion model, and the terminal structure of the three-dimensional depletion model can better relieve the curvature effect of an electric field at the tail end of the field limiting ring; and the pressure resistance of the terminal structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a terminal structure and a preparation method thereof, a semiconductor device and a vehicle. BACKGROUND

[0002] Power semiconductor is a semiconductor device for power processing, which can process and convert electric energy and is a core device of power electronic systems, widely used in consumer electronics, electric vehicles, industrial electronics and other fields. Power devices include power diodes, power switching devices and power integrated circuits.

[0003] The power device generally includes an active region in the center and a terminal region at the edge; wherein the terminal region at the edge is mainly to expand the electric field distribution of the terminal region, reduce the terminal electric field concentration effect, and improve the withstand voltage of the terminal region. Generally speaking, the terminal of the power device is a spherical or cylindrical junction, and if no special terminal structure design is performed, the curvature effect will cause the breakdown voltage of the terminal region to be much lower than that of the parallel plane junction of the active region, resulting in that the actual withstand voltage of the device is much lower than the design value.

[0004] The current terminal structure includes a field limiting ring structure or a terminal expansion structure (JTE), etc. The field limiting ring structure terminal is widely used in the terminal structure of IGBT devices, MOSFET devices, etc. The existing mainstream method is to increase the field limiting ring structure in the terminal region, to form a plurality of field limiting rings with the same doping type as the main junction in the terminal region, to improve the withstand voltage of the device. If the withstand voltage requirement of the device is high, the number of field limiting rings can be increased accordingly, and the number of field limiting rings can be increased to more than ten or even dozens, but this will cause a great waste of chip area, and the withstand voltage that the terminal can withstand will gradually tend to saturation. SUMMARY

[0005] The embodiments of the present application provide a terminal structure and a preparation method thereof, a semiconductor device and a vehicle, which improve the withstand voltage capability of the device to at least partially solve the above technical problems.

[0006] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a terminal structure is provided, comprising: a substrate of a first conductive type, the substrate having at least one field limiting ring of a second conductive type; a plurality of well regions of the second conductive type are arranged at intervals along the length direction of the field limiting ring on the field limiting ring in the substrate.

[0007] In a possible implementation, the substrate has a plurality of field limiting rings of the second conductive type; the plurality of well regions of the adjacent field limiting rings are arranged oppositely.

[0008] In a possible implementation, the substrate has a plurality of field limiting rings of the second conductivity type; and the plurality of well regions adjacent to the field limiting rings are arranged alternately.

[0009] In a possible implementation, the substrate has a first surface and a second surface arranged oppositely, at least one of the field limiting rings is arranged on the first surface of the substrate; and a buffer layer, a collector region and a collector metal layer are sequentially stacked on the second surface of the substrate.

[0010] In a possible implementation, the plurality of well regions are arranged non-uniformly on the field limiting ring.

[0011] In a possible implementation, the first conductivity type is N type and the second conductivity type is P type; or the first conductivity type is P type and the second conductivity type is N type.

[0012] In a possible implementation, the substrate has a main junction, and a plurality of main junction region well regions of the second conductivity type are arranged on the main junction in the substrate.

[0013] In a possible implementation, the plurality of main junction region well regions are arranged oppositely to the plurality of well regions of the field limiting ring adjacent to the main junction, or the plurality of main junction region well regions are arranged alternately to the plurality of well regions of the field limiting ring adjacent to the main junction.

[0014] In a second aspect, the present application provides a preparation method of a terminal structure, comprising: providing a substrate of a first conductivity type; forming a first mask plate on a first surface of the substrate, the first mask plate having at least one field limiting ring diffusion window, performing ion implantation on the field limiting ring diffusion window and pushing well to form a corresponding field limiting ring of a second conductivity type; forming a second mask plate on the first surface of the substrate, the second mask plate having a plurality of well region diffusion windows arranged alternately corresponding to the at least one field limiting ring, performing ion implantation on the well region diffusion window and pushing well to form a corresponding well region of the second conductivity type; sequentially forming a buffer layer, a collector region and a collector metal layer on a second surface of the substrate; and the first surface and the second surface are arranged oppositely to form a terminal structure.

[0015] In a third aspect, the present application provides a semiconductor device, comprising an active region and a terminal region, the terminal region is arranged around the active region, and the terminal region comprises the terminal structure in the above embodiments.

[0016] In a third aspect, the application also provides a vehicle comprising the terminal structure in the above embodiments, or comprising the semiconductor device in the above embodiments.

[0017] The terminal structure provided by the embodiments of the application has the plurality of well regions with the same conductive type as the field limiting ring and arranged at intervals along the length direction of the field limiting ring on the field limiting ring in the substrate, converts a two-dimensional depletion model of a traditional field ring terminal into a three-dimensional depletion model, and the terminal structure of the three-dimensional depletion model can better relieve the curvature effect of the electric field at the end of the field limiting ring and improve the withstand voltage performance of the terminal structure.

[0018] Other features and advantages of the application will be described in detail in the following detailed description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0019] In order to more completely understand the application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0020] Figure 1 is a structural schematic diagram of a prior art terminal structure.

[0021] Figure 2 is a top view of a terminal structure in an exemplary embodiment disclosed by the application.

[0022] Figure 3 is another top view of a terminal structure in an exemplary embodiment disclosed by the application.

[0023] Figure 4 is Figure 2 is a sectional structure schematic diagram along the Z1 direction in the above.

[0024] Figure 5 is Figure 2 is another sectional structure schematic diagram along the Z1 direction in the above.

[0025] Figure 6 is Figure 2 is still another sectional structure schematic diagram along the Z1 direction in the above.

[0026] Figure 7 is Figure 2 is a sectional structure schematic diagram along the Z2 direction in the above.

[0027] Figure 8 is Figure 3A cross-sectional structural diagram along the Z3 direction.

[0028] Figure 9 yes Figure 3 Another cross-sectional structural diagram along the Z3 direction.

[0029] Figure 10 yes Figure 3 Another cross-sectional structural diagram along the Z3 direction.

[0030] Figures 11-18 This is a process flow diagram of the preparation method of the terminal structure in the exemplary embodiments disclosed in this application; Figure 19 This is a schematic flowchart of the steps in the preparation method of the terminal structure in an exemplary embodiment of this application.

[0031] Explanation of reference numerals in the attached figures: 1. Emitter metal layer; 2. Field oxide layer; 3. Main junction; 31. Main junction region well region; 4. First field confinement ring; 41. First field confinement ring well region; 5. Second field confinement ring; 51. Second field confinement ring well region; 6. Third field confinement ring; 61. Third field confinement ring well region; 7. Fourth field confinement ring; 71. Fourth field confinement ring well region; 8. Drift region; 9. Buffer layer; 10. Collector region; 11. Collector metal layer; A. First mask; B. Second mask. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0033] Please see Figure 1 , Figure 1 This is a schematic diagram of the existing terminal structure. The mainstream approach to the terminal structure of existing semiconductor devices is to form multiple field-limiting loops in the terminal region. Figure 1 The diagram shows an application using four field-limiting rings. This multi-field-limiting-ring structure is widely used in power devices such as power diodes and power MOSFETs. When the voltage withstand capability of semiconductor devices is high, existing technologies correspondingly increase the number of field-limiting rings, from a dozen to dozens. Understandably, due to the limited area of ​​semiconductor devices, this approach leads to the gradual saturation of the voltage withstand capability, and significantly wastes semiconductor device area. Currently, there is an urgent need to optimize the field-limiting ring structure to minimize the area of ​​the terminal structure while ensuring the device's voltage withstand capability, thereby achieving high-efficiency utilization of chip area.

[0034] In view of this, this application proposes a termination structure, which transforms the two-dimensional depletion model of the traditional field ring termination into a three-dimensional depletion model by arranging multiple well regions of the same conductivity type as the field ring at intervals along the length of the field ring on the field confinement ring in the substrate. The three-dimensional depletion model termination structure can better alleviate the curvature effect of the electric field at the end of the field confinement ring and improve the voltage withstand performance of the termination structure.

[0035] According to the first aspect disclosed in this application, a terminal structure is provided; please refer to [link / reference]. Figure 2 , Figure 2 This is a top view of a terminal structure according to an exemplary embodiment of this application. The terminal structure includes a substrate of a first conductivity type, the substrate having at least one field-limiting ring of a second conductivity type; and a plurality of well regions of the second conductivity type are spaced apart along the length direction of the field-limiting ring on the field-limiting ring within the substrate. By spaced apart on the field-limiting ring within the substrate a plurality of well regions of the same conductivity type as the field-limiting ring, this application transforms the two-dimensional depletion model of the traditional field-limiting ring terminal into a three-dimensional depletion model, which can better alleviate the curvature effect of the electric field at the end of the field-limiting ring and improve the withstand voltage performance of the terminal structure.

[0036] Please refer to the following: Figure 2 and Figure 4 , Figure 4 yes Figure 2 A cross-sectional structural diagram along the Z1 direction is shown. The terminal structure provided by this invention includes a substrate of a first conductivity type, the substrate including a drift region 8, and at least one field-limiting ring on the first surface of the substrate. At least one field-limiting ring can be fabricated on the first surface of the drift region 8 using existing processes. Then, multiple well regions are formed on the corresponding field-limiting rings using processes such as masking, multiple spaced diffusion windows, ion implantation, and push-well techniques. This transforms the traditional two-dimensional depletion model of the field-limiting ring terminal into a three-dimensional depletion model, which can better alleviate the curvature effect of the electric field at the end of the field-limiting ring and improve the voltage withstand performance of the terminal structure.

[0037] It is understood that the terminal structure of this application may include a field limiting ring, on which multiple well regions are spaced apart. The terminal structure of this application may also include multiple field limiting rings, on which multiple well regions are spaced apart.

[0038] Please continue reading. Figure 2 and Figure 4This application will be further described using a substrate having four field confinement rings of the second conductivity type as an example. A first field confinement ring 4, a second field confinement ring 5, a third field confinement ring 6, and a fourth field confinement ring 7 are formed on the first surface of the drift region 8. This application further provides multiple first field confinement ring well regions 41 spaced apart on the first field confinement ring 4, multiple second field confinement ring well regions 51 spaced apart on the second field confinement ring 5, multiple third field confinement ring well regions 61 spaced apart on the third field confinement ring 6, and multiple fourth field confinement ring well regions 71 spaced apart on the fourth field confinement ring 7. The first field confinement ring 4, the second field confinement ring 5, the third field confinement ring 6, the fourth field confinement ring 7, the first field confinement ring well region 41, the second field confinement ring well region 51, the third field confinement ring well region 61, and the fourth field confinement ring well region 71 all have the same conductivity type, which is the second conductivity type. The drift region 8 has the first conductivity type.

[0039] Taking the N-type conductivity of drift region 8 as an example, the working principle of this application is explained in detail below.

[0040] The field-limiting rings in existing termination structures are generally arranged in a ring shape around the active region. The potential distribution at the termination can be adjusted by changing the number of field-limiting rings, the ring spacing, the ring depth, and the doping concentration to alleviate the curvature effect caused by the cylindrical junction of the main junction in the semiconductor device, thus extending the curved potential outwards. Therefore, the extension direction of the termination depletion region is mainly in two directions: Direction 1, extending from the main junction from the field-limiting ring to the cutoff ring (e.g., ...). Figure 1 The y-axis direction shown); Direction 2, the pn junction formed by the chip surface field confinement ring and drift region extends towards the back of the chip (e.g., the direction of the y-axis shown); Figure 1 (The z-axis direction is shown in the diagram). It should be noted that the y-axis direction is the direction from the active region to the terminal region, which is the length direction of the terminal or semiconductor device; the x-axis direction is the width direction of the terminal or semiconductor device; the x-axis direction is perpendicular to the y-axis direction, forming a two-dimensional plane parallel to the surface of the semiconductor device; and the z-axis direction is a plane perpendicular to the semiconductor device, which is the depth direction of the semiconductor device.

[0041] This application, based on the traditional field-limiting ring termination structure, adds a set of spaced-apart P-wells of the same doping type as the field-limiting rings in a direction perpendicular to the length of each field-limiting ring. The expansion direction of the termination depletion region becomes: Direction 1, extending from the main junction from the field-limiting ring towards the cutoff ring (e.g., Figure 1 The y-axis direction shown); Direction 2, the pn junction formed by the chip surface field confinement ring and drift region extends towards the back of the chip (e.g., the direction of the y-axis shown); Figure 1 The z-axis direction shown); Direction 3, the additional set of P-wells and the drift region form a pn junction that extends in the direction perpendicular to the y-axis (e.g., Figure 2(as shown in the x-axis direction); thus transforming the two-dimensional depletion model of the traditional field ring terminal into a three-dimensional depletion model.

[0042] Specifically, the termination structure provided in this application, in the y-axis direction, optimizes the radius of curvature of the main junction and the cylindrical junction at the end of the field-limiting ring due to the presence of multiple spaced P-wells. This extends the bending potential at the ends of the main junction and field-limiting ring outwards, reducing the peak electric field at the ends of the main junction and field-limiting ring, resulting in a more uniform electric field distribution in the semiconductor device and preventing surface breakdown to some extent. In the x-axis direction, the PN junction formed by the alternating distribution of multiple spaced P-wells and N-drift regions can share the voltage of the semiconductor device in the y-axis and z-axis under the device's breakdown voltage conditions, thereby increasing the device's breakdown voltage performance without increasing the termination area.

[0043] The termination structure provided in this application, under the device withstand voltage condition, increases the proportion of parallel planar junctions and decreases the proportion of cylindrical junctions at the termination edge to a certain extent. This results in a more complete depletion of the space charge region in the z-axis direction of the N-drift region under the same voltage condition, which in turn suppresses the expansion of the electric field in the y-axis to a certain extent. The benefit of reducing the expansion of the electric field in the y-axis direction is that it can shorten the safety distance from the last field limiting ring to the cutoff ring, greatly shortening the termination size and significantly improving the chip's usable area.

[0044] In some embodiments, the substrate has a plurality of field-limiting rings of a second conductivity type; and a plurality of well regions adjacent to the field-limiting rings are disposed opposite to each other.

[0045] In this embodiment, the terminal structure provided by this application includes four field limiting rings, each field limiting ring having multiple well regions. Furthermore, the multiple well regions on adjacent field limiting rings are arranged opposite to each other. Please continue reading. Figure 2 , Figure 2 This is a top view of the terminal structure in an exemplary embodiment disclosed in this application. A plurality of first field-limiting ring well regions 41 are spaced apart on the first field-limiting ring 4, and a plurality of second field-limiting ring well regions 51 are spaced apart on the second field-limiting ring 5. The plurality of first field-limiting ring well regions 41 and the plurality of second field-limiting ring well regions 51 are arranged opposite to each other. In practical applications, a one-to-one correspondence can be adopted. It is understood that a plurality of third field-limiting ring well regions 61 are spaced apart on the third field-limiting ring 6, and a plurality of fourth field-limiting ring well regions 71 are spaced apart on the fourth field-limiting ring 7. The plurality of third field-limiting ring well regions 61 and the plurality of fourth field-limiting ring well regions 71 are arranged opposite to each other. This terminal structure can better alleviate the curvature effect of the electric field at the end of the field-limiting ring, improve the overall voltage withstand capability of the chip, and make the electrical performance more stable.

[0046] In some embodiments, the substrate has a plurality of field-limiting rings of a second conductivity type; the plurality of well regions of adjacent field-limiting rings are staggered.

[0047] In this embodiment, please refer to Figure 3 , Figure 3 This is another top view of the terminal structure in an exemplary embodiment disclosed in this application. For example... Figure 3 As shown, this embodiment is another embodiment of this application. A first field limiting ring 4, a second field limiting ring 5, a third field limiting ring 6, and a fourth field limiting ring 7 are formed on the first surface of the drift region 8. Multiple first field limiting ring well regions 41 are spaced apart on the first field limiting ring 4, multiple second field limiting ring well regions 51 are spaced apart on the second field limiting ring 5, multiple third field limiting ring well regions 61 are spaced apart on the third field limiting ring 6, and multiple fourth field limiting ring well regions 71 are spaced apart on the fourth field limiting ring 7. The first field limiting ring 4, the second field limiting ring 5, the third field limiting ring 6, the fourth field limiting ring 7, the first field limiting ring well region 41, the second field limiting ring well region 51, the third field limiting ring well region 61, and the fourth field limiting ring well region 71 all have the same conductivity type, which is the second conductivity type. The drift region 8 has the first conductivity type.

[0048] Specifically, this application employs an alternating arrangement of multiple well regions in adjacent field limiting rings. For example, multiple first field limiting ring well regions 41 are alternating with multiple second field limiting ring well regions 51, and multiple second field limiting ring well regions 51 are alternating with multiple third field limiting ring well regions 61. This terminal structure configuration can better alleviate the curvature effect of the electric field at the end of the field limiting ring, improve the overall voltage withstand capability of the chip, and make the electrical performance more stable.

[0049] In some embodiments, a main junction is provided in the substrate, and a plurality of main junction regions of a second conductivity type are spaced apart on the main junction in the substrate.

[0050] In this embodiment, please continue to refer to Figure 2 and Figure 3 The substrate contains a main junction 3, and multiple main junction region well regions 31 of a second conductivity type are spaced apart on the main junction 3 within the substrate. To improve withstand voltage performance, the termination structure provided in this application provides multiple main junction region well regions 31 spaced apart in the edge region of the main junction 3. Due to the presence of multiple main junction region well regions 31, the main junction 3 has a larger radius of curvature during withstand voltage operation, thereby more effectively expanding the electric field and improving the withstand voltage capability.

[0051] The foregoing description illustrates two embodiments of the terminal structure provided in this application. One embodiment uses multiple field limiting rings, each with multiple well regions, and the well regions of adjacent field limiting rings are arranged opposite each other. The other embodiment uses multiple field limiting rings, each with multiple well regions, and the well regions of adjacent field limiting rings are arranged alternately. Based on these two embodiments, this application also provides multiple main junction region well regions of a second conductivity type at intervals on the main junction, corresponding to two different scenarios.

[0052] In the first scenario, multiple well regions of the main junction and multiple well regions of the field limiting ring adjacent to the main junction are arranged opposite each other. Please continue reading. Figure 2 and Figure 4 The multiple main junction region well regions 31 and the multiple first field limiting ring well regions 41 of the first field limiting ring 4 adjacent to the main junction 3 are arranged opposite to each other.

[0053] In the second scenario, multiple well regions of the main junction and multiple well regions of the field limiting ring adjacent to the main junction are staggered. Please refer to [link / reference]. Figure 3 and Figure 8 The multiple main junction region well regions 31 and the multiple first field-limiting ring well regions 41 of the first field-limiting ring 4 adjacent to the main junction 3 are staggered. In practical applications, taking N-type as the first conductivity type and P-type as the second conductivity type as an example, the P-wells of the main junction region and the P-wells of the field-limiting ring region are distributed in a comb-like interlocking pattern, which can improve the coupling degree of the space charge region and enhance the terminal withstand voltage.

[0054] In practical applications, the two embodiments described above can be combined with the two situations described above. Preferably, multiple well regions are spaced apart on both the main junction and the multiple field limiting rings, and the multiple well regions between the main junction and adjacent field limiting rings, and between field limiting rings, are correspondingly arranged. Alternatively, multiple well regions are spaced apart on both the main junction and the multiple field limiting rings, and the multiple well regions between the main junction and adjacent field limiting rings, and between field limiting rings, are staggered.

[0055] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0056] In this embodiment, N-type semiconductor refers to an intrinsic semiconductor doped with donor impurities. N-type includes N+ type and N... Type, N+ type is highly doped, N The type is lightly doped. A P-type semiconductor is a semiconductor obtained by doping an intrinsic semiconductor with acceptor impurities. P-type includes P+ and P-type. P+ type is highly doped, P The type is low doping. The dopant element in the P-type doped region can be boron (B) and boron fluoride (BF2), etc., while the dopant element in the N-type doped region can be phosphorus (P), arsenic (As) and hydrogen (H), etc., and there are no specific restrictions on either.

[0057] In some embodiments, the substrate has a first surface and a second surface disposed opposite to each other, and at least one field limiting ring is disposed on the first surface of the substrate; a buffer layer, a collector region and a collector metal layer are sequentially stacked on the second surface of the substrate.

[0058] Please see Figure 3 and Figure 8 The terminal structure provided in this application has a buffer layer 9, a collector region 10, and a collector metal layer 11 stacked sequentially on the second surface of the substrate. In practical applications, the buffer layer 9 is an FS buffer layer (FieldStop Buffer Layer).

[0059] In some embodiments, the junction depth of the well region is smaller than the junction depth of the field limiting ring. For example... Figure 4 As shown, Figure 4 for Figure 2 A cross-sectional structural diagram along the Z1 direction is shown. The junction depth of the first field-limiting ring well region 41 is less than the junction depth of the first field-limiting ring 4, and the junction depth of the second field-limiting ring well region 51 is less than the junction depth of the second field-limiting ring 5. Similarly, the junction depths of the third field-limiting ring 6 and the fourth field-limiting ring 7 can be deduced.

[0060] In some embodiments, such as Figure 4 As shown, the junction depth of the main junction region 31 is less than the junction depth of the main junction.

[0061] In some embodiments, the junction depth of the well region is equal to the junction depth of the field-limiting ring. For example... Figure 5 As shown, Figure 5 yes Figure 2 Another cross-sectional view of the structure along the Z1 direction. The junction depth of the first field-limiting ring well region 41 is equal to the junction depth of the first field-limiting ring 4, and the junction depth of the second field-limiting ring well region 51 is equal to the junction depth of the second field-limiting ring 5. Similarly, the third field-limiting ring 6 and the fourth field-limiting ring 7 can be deduced.

[0062] In some embodiments, such as Figure 5 As shown, the junction depth of the main junction region 31 is equal to the junction depth of the main junction.

[0063] In some embodiments, the junction depth of the well region is greater than the junction depth of the field limiting ring. For example... Figure 6 As shown, Figure 6 yes Figure 2Another cross-sectional structural diagram along the Z1 direction. The junction depth of the first field-limiting ring well region 41 is greater than the junction depth of the first field-limiting ring 4, and the junction depth of the second field-limiting ring well region 51 is greater than the junction depth of the second field-limiting ring 5. Similarly, the junction depths of the third field-limiting ring 6 and the fourth field-limiting ring 7 can be deduced.

[0064] In some embodiments, such as Figure 6 As shown, the junction depth of the main junction region well region 31 is greater than the junction depth of the main junction.

[0065] Please see Figure 7 , Figure 7 yes Figure 2 A cross-sectional view of the structure along the z2 direction is shown. Specifically, the cross-sectional structure of the terminal structure provided in this application, when tangent to the z2 axis, can be shown as follows: Figure 7 As shown, since the z2 axis is exactly offset from the well regions on the main junction and the field limiting ring, its cross-sectional schematic diagram is consistent with the existing terminal structure.

[0066] In practical applications, the well junction depth, doping concentration, number, length, and shape distribution of the well regions need to be comprehensively considered based on the electrical characteristics of the device. The well region shape can be any shape such as rectangular, square, or elliptical. In some embodiments, multiple well regions can be uniformly spaced on the field limiting ring. Multiple well regions can also be non-uniformly spaced on the field limiting ring. It should be noted that this embodiment uses four field limiting rings as an example for illustration; in practical applications, one field limiting ring or five field limiting rings can be used, etc.

[0067] In another embodiment, multiple field limiting rings are used, each with multiple well regions, and the well regions of adjacent field limiting rings are staggered. Figures 8-10 As shown, Figure 8 yes Figure 3 A cross-sectional structural diagram along the Z3 direction. Figure 9 yes Figure 3 Another cross-sectional structural diagram along the Z3 direction. Figure 10 yes Figure 3 Another cross-sectional structural diagram along the Z3 direction shows that, with the well regions staggered, the junction depth of the well region can be less than the junction depth of the field limiting ring (specifically as shown in the diagram). Figure 8 As shown), it can also be equal to the junction depth of the field-limiting loop (specifically as shown). Figure 9 As shown), it can also be greater than the junction depth of the field limiting loop (specifically as shown). Figure 10 (As shown) The termination structure provided in this application, based on the traditional field-limiting ring termination structure, adds a set of spaced P-wells with the same doping type as the field-limiting rings in the direction perpendicular to the length extension of each field-limiting ring. When the device is in the forward blocking state, a forward bias voltage is applied to the back collector, and a reverse bias voltage is applied to the main junction. The space charge region extends to both sides of the PN junction, and the P-wells are in a fully depleted state. The presence of the P-wells improves the radius of curvature of the main junction and the cylindrical junction at the end of the field-limiting ring, extending the bending potential at the cylindrical junction outward and reducing the peak electric field at the cylindrical junction. The presence of the P-wells allows the space charge region on both sides of the PN junction to extend along the X-axis direction, transforming the two-dimensional depletion of the traditional field-limiting ring termination into three-dimensional depletion. Since the space charge region in the X-axis direction shares the voltage of the termination in the Y and Z axes, this reduces the chip termination size and chip thickness to a certain extent, greatly increasing the chip's usable area and increasing the device's breakdown voltage performance without increasing the termination area.

[0068] According to the second aspect disclosed in this application, a method for preparing a terminal structure is provided. Please refer to [link to relevant documentation]. Figure 19 This includes the following steps: S110, Provides a substrate of a first conductivity type; S120. A first mask A is formed on the first surface of the substrate. The first mask A has at least one field-limiting ring diffusion window. Ion implantation is performed on the field-limiting ring diffusion window and a sink is pushed to form a corresponding field-limiting ring of the second conductivity type. S130. A second mask B is formed on the first surface of the substrate. The second mask B has a plurality of well diffusion windows spaced apart, corresponding to at least one field limiting ring. Ion implantation is performed on the well diffusion windows and well push-in is performed to form a well region of the corresponding second conductivity type. S140, a buffer layer, a collector region, and a collector metal layer are sequentially formed on the second surface of the substrate; the first surface and the second surface are disposed opposite to each other to form a terminal structure.

[0069] Based on the terminal structure provided in this application, there are two embodiments, taking the relative arrangement of well regions on multiple field limiting rings as an example, combined with the appendix. Figure 11 To the attached Figure 18 The method for preparing the terminal structure of this application is described below. Please refer to the following: Figures 11-18 , Figures 11-18 This is a process flow diagram of the preparation method of the terminal structure in an exemplary embodiment disclosed in this application. Figures 11-15 This is a top view. Figures 16-18 This is a sectional view.

[0070] Step 1, such as Figure 11As shown, the fabrication method provided in this application first provides a substrate of a first conductivity type, the doping concentration and thickness of which are predetermined by a voltage rating. A lightly doped silicon wafer can be selected to form the N-drift region 8 of the terminal structure.

[0071] Step 2, as follows Figure 12 As shown, a field oxide process is performed on the first surface of the drift region 8 to grow a field oxide layer 2 with a thickness of 0.8 μm to 1.5 μm on the silicon substrate surface (refer to...). Figure 16 The process involves photolithography of field oxide to fabricate a first mask A for field-limiting ring implantation, sputtering a sacrificial oxide layer and performing a first boron ion implantation, etching the sacrificial oxide layer, and then performing a push-well and annealing process. It should be noted that in this step, the first mask A also has a main junction diffusion window to correspond to the main junction 3, thereby forming the main junction 3.

[0072] Step 3, as follows Figure 13 and Figure 14 As shown, oxide is deposited, followed by secondary photolithography to fabricate a second mask B. The second mask B includes diffusion windows for multiple well regions corresponding to the field confinement ring. A sacrificial oxide layer is sputtered, and secondary boron ion implantation is performed. After etching the sacrificial oxide layer, well pushing and annealing are conducted to obtain the desired result. Figure 14 The terminal structure is shown. It should be noted that in this step, multiple main junction region well diffusion windows corresponding to the main junction 3 can also be formed on the second mask B, thereby forming multiple spaced main junction region well regions 31 on the main junction 3. Preferably, the second mask B also forms multiple main junction region well diffusion windows corresponding to the main junction, with the main junction region well diffusion windows positioned opposite to adjacent well diffusion windows.

[0073] Step 4, as Figure 15 As shown, phosphorus silicate glass is deposited and photolithographically etched to form the main junction contact holes. A metallic aluminum film is sputtered onto the surface and then reverse-etched. Silicon nitride is deposited onto the surface and then reverse-etched to form the emitter metal layer 1. This step is an existing process and will not be described in detail.

[0074] Step 5: Continue reading Figure 16 The substrate was flipped, and after thinning the back side, a buffer layer was prepared by hydrogen ion implantation.

[0075] Step 6, please refer to Figure 17 Boron ion implantation was performed on the back side to create the back-side collector region 10.

[0076] Step 7, please refer to Figure 18 By sputtering and alloying multiple metal electrodes on the back side to fabricate a collector metal layer 11, the terminal structure described in this application can be obtained.

[0077] It should be noted that between steps three and four, the active region of the semiconductor device can also be fabricated; this is an existing process and will not be elaborated upon here. This ultimately yields a semiconductor device containing both an active region and a termination region.

[0078] It is understandable that, taking the staggered arrangement of well regions on multiple field-limiting rings as an example, the P-wells in the main junction region and the P-wells in the field-limiting ring region are distributed in a comb-like interlocking pattern. The purpose is to maximize the coupling degree of the space charge region and enhance the terminal breakdown voltage. The forward blocking state of this structure is similar to the above-described fabrication method, mainly differing in the structure of the second mask B. In another embodiment, the second mask B has multiple well diffusion windows that are staggered and spaced apart, corresponding to the multiple field-limiting rings, thus allowing the well regions on the generated multiple field-limiting rings to be staggered. Preferably, the second mask B also has multiple main junction region well diffusion windows corresponding to the main junction, with the main junction region well diffusion windows staggered with adjacent well diffusion windows.

[0079] Taking P-wells as an example, in some embodiments, the P-wells can be evenly spaced or non-uniformly arranged in the X-axis direction. The junction depth, doping concentration, number, length, and shape distribution of the P-wells can be comprehensively considered based on the electrical characteristics of the device. The shape of the P-wells can be any shape such as rectangular, square, or elliptical. The P-wells can be freely set on either side of the field-limiting ring, and the P-wells on both sides of the field-limiting ring can be asymmetrical structures. When the doping concentration and junction depth of the P-wells are the same as those of the field-limiting ring, the P-wells can share the same mask as the field-limiting ring implantation, without adding a new mask and without increasing mask costs.

[0080] In some embodiments, the terminal structure further includes a field plate structure, which can mitigate interference from impurity charges on the device surface. The material and length of the field plate structure are not limited and can be adjusted according to the electrical characteristics of the terminal.

[0081] In some embodiments, the drift region structure of the semiconductor device can be an NPT structure, a PT structure, an SPT structure, or an FS structure; the semiconductor material of the termination structure is made of Si, SiC, GaAs, or GaN; the dielectric material of the dielectric layer of the semiconductor device is a high-k dielectric material such as SiO2, HfO2, Al2O3, or Si3N4. The fabrication of the N-type field stop layer can be performed before the fabrication of the cellular MOS structure and the termination structure; or a bilayer epitaxial material with an N-type field stop layer and an N-drift region can be directly selected as the silicon wafer material for the process start, which can replace the FS field stop layer formed by hydrogen implantation.

[0082] According to a third aspect disclosed in this application, a semiconductor device is provided, the semiconductor device including an active region and a termination region, the termination region being disposed around the active region, and the termination region including the termination structure described above. This semiconductor device possesses all the beneficial effects of the aforementioned termination structure, which will not be elaborated further herein.

[0083] In some embodiments, the semiconductor device is a power device, such as an IGBT device.

[0084] According to the fourth aspect disclosed in this application, a vehicle is provided that includes the aforementioned terminal structure or the aforementioned semiconductor device. This vehicle possesses all the beneficial effects of the aforementioned semiconductor device, which will not be elaborated upon here. The vehicle may be a gasoline-powered vehicle, a plug-in hybrid electric vehicle, or a new energy vehicle, etc., and this application does not specifically limit it in this regard.

[0085] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0087] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0088] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A terminal structure, characterized in that, include: A substrate of a first conductivity type, the substrate having at least one field confinement ring of a second conductivity type; On the field limiting ring within the substrate, a plurality of well regions of a second conductivity type are spaced apart along the length direction of the field limiting ring.

2. The terminal structure according to claim 1, characterized in that, The substrate has a plurality of field-limiting rings of a second conductivity type; the plurality of well regions adjacent to the field-limiting rings are arranged opposite each other.

3. The terminal structure according to claim 1, characterized in that, The substrate has a plurality of field-limiting rings of a second conductivity type; the plurality of well regions of adjacent field-limiting rings are staggered.

4. The terminal structure according to claim 1, characterized in that, The substrate has a first surface and a second surface disposed opposite to each other, and at least one field limiting ring is disposed on the first surface of the substrate; a buffer layer, a collector region and a collector metal layer are sequentially stacked on the second surface of the substrate.

5. The terminal structure according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

6. The terminal structure according to any one of claims 1 to 5, characterized in that, The substrate has a main junction, and multiple main junction regions of a second conductivity type are spaced apart on the main junction within the substrate.

7. The terminal structure according to claim 6, characterized in that, The multiple main junction region well regions and the multiple well regions of the field limiting ring adjacent to the main junction are arranged opposite to each other, or the multiple main junction region well regions and the multiple well regions of the field limiting ring adjacent to the main junction are arranged alternately.

8. A method for preparing a terminal structure, characterized in that, include: Provide a substrate of the first conductivity type; A first mask is formed on a first surface of the substrate. The first mask has at least one field-confined ring diffusion window. Ion implantation is performed on the field-confined ring diffusion window and a sink is formed to form a corresponding field-confined ring of the second conductivity type. A second mask is formed on the first surface of the substrate. The second mask has a plurality of well diffusion windows spaced apart, corresponding to at least one field confinement ring. Ion implantation is performed on the well diffusion windows and well push-in is performed to form well regions of the corresponding second conductivity type. A buffer layer, a collector region, and a collector metal layer are sequentially formed on the second surface of the substrate; the first surface and the second surface are disposed opposite to each other to form a terminal structure.

9. A semiconductor device, characterized in that, The semiconductor device includes an active region and a termination region, the termination region being disposed around the active region, and the termination region including the termination structure according to any one of claims 1 to 7.

10. A vehicle, characterized in that, It includes the terminal structure described in any one of claims 1 to 7, or the semiconductor device described in claim 9.

Images