Semiconductor structure and method of manufacturing the same

Abstract

This application discloses a semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The fabrication method includes: forming a dummy gate, an etch stop layer, and an interlayer dielectric layer on a substrate. Multiple dummy gates are spaced apart. The etch stop layer covers the sidewalls and top surface of the dummy gates. The interlayer dielectric layer covers the etch stop layer and fills the trench between adjacent dummy gates. The interlayer dielectric layer and etch stop layer are ground until the top surface of the dummy gates is exposed, and a depression is formed in the interlayer dielectric layer within the trench. The dummy gates are replaced with gate material, which fills the depression. The gate material is etched using a chemical dry etching process until the inner wall of the depression is exposed. The gate material and interlayer dielectric layer are planarized to form a gate, with the top surface of the gate away from the substrate flush with the top surface of the interlayer dielectric layer away from the substrate. This reduces the risk of short circuits in the semiconductor structure and improves the yield and performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In existing technologies that use metal materials to form metal gates, a chemical mechanical polishing (CMP) process is used to planarize the interlayer dielectric layer and the etch barrier layer to expose the dummy gate covered by the etch barrier layer. Then, the dummy gate is replaced with a metal material to form the metal gate. However, the CMP process polishes the etch barrier layer at a rate that is lower than that of the interlayer dielectric layer, causing surface dishing of the interlayer dielectric layer, which in turn affects the performance of the semiconductor device. Summary of the Invention

[0003] This disclosure provides semiconductor structures and their fabrication methods, which can reduce defects in semiconductor devices and improve their performance.

[0004] A method for fabricating a semiconductor structure, comprising:

[0005] A dummy gate, an etch barrier layer, and an interlayer dielectric layer are formed on a substrate. The number of dummy gates is multiple and they are spaced apart. The etch barrier layer covers the sidewalls and top surface of the dummy gates. The interlayer dielectric layer covers the etch barrier layer and fills the trench between two adjacent dummy gates.

[0006] The interlayer dielectric layer and the etch barrier layer are ground until the top surface of the dummy gate is exposed and a recess is formed in the interlayer dielectric layer within the trench;

[0007] The dummy gate is replaced with a gate material, which fills the depression.

[0008] The gate material is etched using a chemical dry etching process until the inner wall of the recess is exposed;

[0009] The gate material and the interlayer dielectric layer are planarized to form a gate, wherein the top surface of the gate away from the substrate and the top surface of the interlayer dielectric layer away from the substrate are flush.

[0010] In one embodiment, replacing the dummy gate with a gate material includes:

[0011] Remove the dummy gate to form a gate-filled groove;

[0012] The gate material is formed by filling the gate filling groove and the recess.

[0013] In one embodiment, filling the gate filling trench and the recess with the gate material includes:

[0014] A metal material is filled into the gate filling trench and the recess, and the metal material covers the interlayer dielectric layer;

[0015] The metal material is ground until the remaining metal material fills only the gate fill trench and the recess, forming the gate material.

[0016] In one embodiment, prior to filling the gate fill trench and recess with metal material, the method further includes:

[0017] A work function layer is formed on the inner wall of the gate filling trench; the work function layer extends along the inner wall of the gate filling trench to the inner wall of the recess; the metal material covers the work function layer;

[0018] The metal material is ground until the work function layer between the gate filling trench and the recess is exposed.

[0019] In one embodiment, the etching of the gate material using a chemical dry etching process until the inner wall of the recess is exposed includes:

[0020] A chemical dry etching process is used to etch the gate material and the work function layer until the inner wall of the recess is exposed;

[0021] The etching rates of the gate material and the work function layer in the chemical dry etching process are both greater than the etching rate of the interlayer dielectric layer in the chemical dry etching process.

[0022] In one embodiment, a chemical mechanical polishing process is used to polish the metal material until the remaining metal material only fills the gate fill trench and the recess.

[0023] In one embodiment, a chemical mechanical polishing process is used to planarize the gate material and the interlayer dielectric layer to form the gate.

[0024] Wherein, the speed at which the chemical mechanical polishing process polishes the gate material is equal to the speed at which the chemical mechanical polishing process polishes the interlayer dielectric layer.

[0025] In one embodiment, the fabrication method further includes: forming a plurality of gate dielectric layers on a substrate;

[0026] Each of the gate dielectric layers is located between a corresponding gate and the substrate.

[0027] In one embodiment, a dummy gate, an etch barrier layer, and an interlayer dielectric layer are formed on a substrate, including:

[0028] A stacked structure is formed on the substrate, the stacked structure comprising a gate dielectric material and a dummy gate material stacked along a first direction; the first direction is perpendicular to the substrate;

[0029] A trench is formed that penetrates the stacked structure along the first direction to obtain a dummy gate and the gate dielectric layer;

[0030] An etch barrier layer is formed on the inner wall of the trench; the etch barrier layer extends along the sidewall of the trench and covers the dummy gate.

[0031] An interlayer dielectric layer is formed in the trench to contact the etch barrier layer; the interlayer dielectric layer extends along the sidewall of the trench to cover the dummy gate.

[0032] A semiconductor structure is fabricated using the above-described preparation method.

[0033] In the aforementioned semiconductor structure and its fabrication method, the gate material within the recesses of the interlayer dielectric layer is removed using a chemical dry etching process, reducing the risk of short circuits in the semiconductor structure and improving its yield and performance. Then, the gate material and the interlayer dielectric layer are planarized to obtain a gate that meets the required height, improving its uniformity. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in the embodiments of this application;

[0036] Figure 2 This is a schematic diagram of the process of forming a dummy gate, an etch barrier layer and an interlayer dielectric layer on a substrate in an embodiment of this application.

[0037] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the interlayer dielectric layer in the embodiments of this application;

[0038] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the dummy gate is exposed in the embodiments of this application;

[0039] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the metal material is formed in the embodiments of this application;

[0040] Figure 6 This is a schematic cross-sectional view of the semiconductor structure after the gate material is formed in an embodiment of this application;

[0041] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure after the recessed inner wall is exposed in an embodiment of this application;

[0042] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the gate is formed in an embodiment of this application.

[0043] Explanation of reference numerals in the attached figures:

[0044] Substrate 102; dummy gate 104; gate dielectric layer 106; diffusion barrier layer 108; etch barrier layer 110; interlayer dielectric layer 112; gate material 114; gate 116; trench 202; recess 204; gate filling trench 206; metal material 208; work function layer 210. Detailed Implementation

[0045] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0048] It is understood that the terms "first," "second," etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first stacked structure may be referred to as a second stacked structure, and similarly, a second stacked structure may be referred to as a first stacked structure. Both the first and second stacked structures are stacked structures, but they are not the same stacked structure.

[0049] As used herein, the terms “substrate” and “base” refer to and include the base material or structure of the transistor material described in this disclosure. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate comprising layers of semiconductor material.

[0050] In this disclosure, the upper surface of the substrate is the surface on which the device structure or device layer is formed. The lower surface of the substrate is opposite to the upper surface. The upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For structures or layers located within the substrate, the surface parallel to the substrate surface is called the upper surface / top surface / top / top face, and the surface away from the upper surface is called the lower surface / bottom surface / bottom / bottom face. Conversely, for structures or layers located on the substrate, the surface closer to the upper surface is called the lower surface / bottom surface / bottom / bottom face, and the surface away from the upper surface is called the upper surface / top surface / top / top face. For structures, trenches, holes, or layers formed in a semiconductor structure from the substrate surface in a direction away from the substrate, the surface in the direction perpendicular to the substrate is the sidewall of the structure, trench, hole, or layer, and the position where the trench or hole stops is the bottom of the trench or hole; for trenches or holes formed in other directions in a semiconductor structure, the position where the trench or hole stops is the bottom of the trench or hole, and the surface in the direction of the trench or hole is the sidewall of the trench or hole.

[0051] To improve the switching speed of semiconductor structures, polysilicon gates in semiconductor structures are replaced with metal gates. In the process of forming metal gates, chemical mechanical polishing of the interlayer dielectric layer and dummy gate removal are performed before filling with metal material. Then, chemical mechanical polishing is used to remove excess metal material and global surface planarization is performed to obtain a gate that meets the requirements.

[0052] During the chemical mechanical polishing of the interlayer dielectric layer, the interlayer dielectric layer may be excessively removed, forming a "dish-shaped depression". The filling metal material fills the "dish-shaped depression" at the same time. After the height meets the gate, there will be metal material residue in the "dish-shaped depression", which will cause short circuit risk in the semiconductor structure and affect the yield.

[0053] Increasing the removal amount of global surface planarization can remove residual metal material in the recesses and reduce the risk of short circuits. However, this increased removal amount reduces the gate height, making it unable to meet design requirements. While increasing the allowance for the interlayer dielectric layer can eliminate the impact of increased removal amount on gate height, this increases two problems: uneven metal filling rate, with some areas experiencing insufficient or excessive filling, affecting the subsequent gate formation; and metal accumulation at the top edge and thinning on the sides, affecting the uniformity of subsequent chemical mechanical polishing, and consequently impacting the final gate formation. Therefore, finding a solution to remove residual metal in the recesses without compromising gate height is a pressing issue.

[0054] Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure in an embodiment of this application. See also... Figure 1 In this embodiment, a method for fabricating a semiconductor structure is provided, comprising:

[0055] S102, a dummy gate, an etch barrier layer and an interlayer dielectric layer are formed on the substrate.

[0056] As an example, a substrate is provided; dummy gates, an etch stop layer, and an interlayer dielectric layer are formed on the substrate; wherein the number of dummy gates is plurality of, and adjacent dummy gates are spaced apart, with trenches between adjacent dummy gates; the etch stop layer covers the sidewalls of the dummy gates and the top surface away from the substrate. Exemplarily, the etch stop layer and the sidewalls and top surface of the dummy gates are in contact.

[0057] The interlayer dielectric layer covers the etch stop layer and fills the trench between two adjacent dummy gates; that is, the interlayer dielectric layer fills the trench, and the top surface of the interlayer dielectric layer away from the substrate is higher than the top surface of the etch stop layer away from the substrate.

[0058] In some embodiments, the substrate constituent material includes undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. For example, in this embodiment, single-crystal silicon is selected as the substrate constituent material.

[0059] In some embodiments, the interlayer dielectric layer is composed of one or more of silicon nitride, silicon oxide, and silicon oxynitride. As an example, the interlayer dielectric layer is composed of silicon oxide, the dummy gate is composed of polysilicon, and the etch stop layer is composed of silicon nitride.

[0060] S104, grind the interlayer dielectric layer and etch the barrier layer until the top surface of the dummy gate is exposed, and a recess is formed in the interlayer dielectric layer within the trench.

[0061] The interlayer dielectric layer and etch barrier layer are polished to remove the interlayer dielectric layer and etch barrier layer above the dummy gate, exposing the top surface of the dummy gate away from the substrate. The remaining etch barrier layer and the sidewall of the dummy gate are in contact. The top surface of the interlayer dielectric layer in the trench away from the substrate has an arc towards the substrate, forming a recess in the interlayer dielectric layer.

[0062] S106, replace the dummy gate with gate material, and fill the depression with gate material.

[0063] As an example, an etching process and a deposition process are used to replace the dummy gate with a gate material; wherein the gate material fills the recesses in the interlayer dielectric layer.

[0064] S108 uses a chemical dry etching process to etch the gate material until the recessed inner wall is exposed.

[0065] As an example, a chemical dry etching process is used to etch the gate material, remove the gate material in the recess, and expose the inner wall of the recess. The inner wall includes the sidewall and the bottom. By removing the gate material in the recess through the chemical dry etching process, the height of the gate obtained subsequently is not affected, and the residual gate material in the recess is avoided from affecting the performance of the semiconductor structure.

[0066] Compared to dry etching, chemical dry etching does not damage the gate material used as the gate electrode. During the etching process, as the gate material is etched and the inner wall of the recess is exposed, volatile byproducts are extracted from the reaction chamber, preventing residue. Furthermore, after etching the gate material, any remaining etching reagents evaporate, preventing residue from affecting the performance of the semiconductor structure.

[0067] S110, planarize the gate material and the interlayer dielectric layer to form the gate.

[0068] As an example, the remaining gate material and interlayer dielectric layer in the trench after chemical dry etching are planarized to form a gate; wherein, the top surface of the gate away from the substrate and the top surface of the interlayer dielectric layer away from the substrate are flush, that is, after the planarization process, the depression in the interlayer dielectric layer is eliminated, and a flat surface is obtained.

[0069] In the above-described semiconductor structure fabrication method, the gate material within the recesses of the interlayer dielectric layer is removed using a chemical dry etching process, reducing the risk of short circuits in the semiconductor structure and improving its yield and performance. Then, the gate material and the interlayer dielectric layer are planarized to obtain a gate that meets the required height, improving its uniformity.

[0070] In some embodiments, the method for fabricating a semiconductor structure further includes: forming a plurality of gate dielectric layers on a substrate; wherein each gate dielectric layer is located between a corresponding gate and the substrate.

[0071] As an example, the number of gate dielectric layers is the same as the number of gates, and the gate dielectric layers and gates correspond one-to-one. The gate is located on the side of the corresponding gate dielectric layer away from the substrate. A complete semiconductor structure can be obtained by forming gate dielectric layers.

[0072] In some embodiments, the gate dielectric layer is composed of one or more of silicon oxide (SiO2), silicon oxynitride (SiNO), and materials with high dielectric constants. When the gate dielectric layer is a high dielectric constant material, parasitic capacitance can be reduced. High dielectric constant materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide. In preferred embodiments, hafnium oxide, zirconium oxide, and aluminum oxide are used.

[0073] Figure 2 This is a schematic diagram illustrating the process of forming a dummy gate, an etch barrier layer, and an interlayer dielectric layer on the substrate in an embodiment of this application. Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the interlayer dielectric layer in an embodiment of this application. See also: Figure 2 and Figure 3 In some embodiments, a dummy gate, an etch barrier layer, and an interlayer dielectric layer are formed on the substrate, including:

[0074] S202, a stacked structure is formed on the substrate, the stacked structure including gate dielectric material and pseudo gate material stacked along the first direction.

[0075] As an example, a deposition process, such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition, is used to sequentially form a gate dielectric material and a dummy gate material on a substrate 102; wherein, in a first direction perpendicular to the substrate 102, the gate dielectric material and the dummy gate material are stacked, with the dummy gate material located on the side of the gate dielectric material away from the substrate 102; the stacked structure includes the gate dielectric material and the dummy gate material. As an example, the dummy gate material includes polycrystalline silicon.

[0076] As an example, after forming a gate dielectric material on substrate 102 and before forming a dummy gate material on substrate 102, the method for fabricating a semiconductor structure further includes: forming a diffusion barrier material on the top surface of the gate dielectric material away from substrate 102; wherein the dummy gate material is formed on the top surface of the diffusion barrier material away from the gate dielectric material. Exemplarily, the diffusion barrier material includes at least one of titanium, tantalum nitride, and titanium nitride.

[0077] S204, forming a trench that penetrates the stacked structure along the first direction to obtain a pseudo gate and a gate dielectric layer.

[0078] As an example, firstly, a hard mask material is formed on the side of the stacked structure away from the substrate 102; the hard mask material is patterned to form a hard mask layer; wherein the hard mask layer defines the shape and location of the trenches. Exemplarily, the hard mask material includes titanium nitride and silicon oxide.

[0079] Secondly, an etching process, such as wet etching or dry etching, is used to etch the stacked structure exposed by the hard mask layer to form a trench 202 that penetrates the stacked structure along the first direction; thus obtaining a pseudo gate 104 made of the remaining pseudo gate material and a gate dielectric layer 106 made of the remaining gate dielectric material; wherein the bottom of the trench 202 exposes the substrate 102.

[0080] It is understood that when the stacked structure includes a diffusion barrier material, the trench 202 penetrates the diffusion barrier material along the first direction to form a diffusion barrier layer 108 composed of the remaining diffusion barrier material; wherein, the opposite surfaces of the diffusion barrier layer 108 are in contact with the gate dielectric layer 106 and the gate, respectively. The diffusion barrier layer 108 can suppress interfacial reactions, protect the gate dielectric layer 106, improve the adhesion of the subsequently formed gate, prevent gate peeling, adjust the work function, reduce the preset voltage of the semiconductor structure, and optimize the switching performance of the semiconductor structure. Simultaneously, it can prevent the subsequently formed gate from diffusing into the gate dielectric layer 106 and the substrate 102.

[0081] S206, an etch barrier layer is formed on the inner wall of the trench; the etch barrier layer extends along the sidewall of the trench to cover the dummy gate.

[0082] As an example, an etch barrier layer 110 is formed on the inner wall of trench 202 using a deposition process, such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition; wherein the etch barrier layer 110 extends along the sidewall of trench 202 and covers dummy gate 104. Exemplarily, the etch barrier layer 110 and the inner wall of trench 202, and the dummy gate 104, are in contact with the top surface of the substrate 102. Exemplarily, the material of the etch barrier layer 110 includes at least one of silicon nitride and silicon oxynitride.

[0083] During the grinding of the interlayer dielectric layer, the etch stop layer 110 protects the dummy gate 104 from damage. Simultaneously, the etch stop layer 110 defines the grinding endpoint of the interlayer dielectric layer, precisely controlling its thickness to ensure high global consistency and improve planarization quality. Furthermore, during the subsequent removal of the dummy gate 104, the etch stop layer 110 defines the contour of the gate filling trench, providing precise boundaries for subsequent gate material filling.

[0084] S208, an interlayer dielectric layer is formed in the trench to contact the etch barrier layer; the interlayer dielectric layer extends along the sidewall of the trench to cover the dummy gate.

[0085] As an example, a deposition process, such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition, is used to fill trench 202 to form an interlayer dielectric layer 112; wherein the interlayer dielectric layer 112 contacts an etch stop layer and extends along the sidewalls of trench 202 to cover a dummy gate 104. As an example, the material of the interlayer dielectric layer 112 includes silicon oxide.

[0086] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the dummy gate is exposed in an embodiment of this application. See also: Figure 4 A chemical mechanical polishing (CMP) process is used to polish the interlayer dielectric layer 112 and the etch stop layer 110 until the top surface of the dummy gate 104 away from the substrate 102 is exposed. The polishing speed of the interlayer dielectric layer 112 is greater than that of the etch stop layer 110. Therefore, after polishing, the interlayer dielectric layer 112 within the trench 202 is excessively removed, causing the top surface away from the substrate 102 to become concave, forming a depression 204. Polishing the interlayer dielectric layer 112 and the etch stop layer 110 exposes the top surface of the dummy gate 104 away from the substrate 102, preparing it for subsequent removal of the dummy gate 104.

[0087] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the metal material is formed in the embodiments of this application. Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure after the gate material is formed in an embodiment of this application. See also: Figure 5 and Figure 6In some embodiments, replacing the dummy gate 104 with the gate material 114 includes: removing the dummy gate 104 to form a gate filling trench 206; and filling the gate filling trench 206 and the recess 204 with the gate material 114.

[0088] As an example, a wet etching process or a dry etching process is used to remove the exposed dummy gate 104 to form a gate filling trench 206; wherein, the bottom of the gate filling trench 206 exposes a diffusion barrier layer 108. A deposition process is used to fill the gate filling trench 206 and the recess 204 to form a gate material 114; wherein, the gate material 114 completely fills the gate filling trench 206.

[0089] See Figure 5 and Figure 6 In some embodiments, filling the gate filling trench 206 and the recess 204 to form a gate material 114 includes: filling the gate filling trench 206 and the recess 204 with a metal material 208, the metal material 208 covering the interlayer dielectric layer 112; and grinding the metal material 208 until the remaining metal material 208 is only filled in the gate filling trench 206 and the recess 204 to form the gate material 114.

[0090] As an example, a deposition process, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition, is used to fill the gate fill trench 206 and the recess 204 to form a metal material 208. The metal material 208 extends along the sidewall of the gate fill trench 206 and the inner wall of the recess 204 to cover the interlayer dielectric layer 112. The metal material 208 fills the gate fill trench 206 and the recess 204, and the metal material 208 is away from the top surface of the substrate 102 and higher than the top surface of the etch barrier layer 110 away from the substrate 102.

[0091] As an example, a chemical mechanical polishing (CMP) process is used to polish the metal material 208 until the remaining metal material 208 fills only the gate fill trench 206 and the recess 204, forming a gate material 114 composed of the metal material 208 in the gate fill trench 206 and the metal material 208 in the recess 204. It can be understood that the gate material 114 in the gate fill trench 206 and the gate material 114 in the recess 204 are spaced apart. This arrangement reduces the etching time of the chemical dry etching process and lowers costs.

[0092] See Figure 5 and Figure 6In some embodiments, before filling the gate fill trench 206 and the recess 204 with metal material 208, the method further includes: forming a work function layer 210 on the inner wall of the gate fill trench 206; the work function layer 210 extending along the inner wall of the gate fill trench 206 to the inner wall of the recess 204; the metal material 208 covering the work function layer 210; wherein the metal material 208 is ground until the work function layer 210 between the gate fill trench 206 and the recess 204 is exposed. By setting the work function layer 210, the performance of the semiconductor structure can be adjusted.

[0093] As an example, a deposition process, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition, is used to form a work function layer 210 on the inner wall of the gate filling trench 206. The work function layer 210 extends along the inner wall of the gate filling trench 206 to the inner wall of the recess 204. The work function layer 210 extends to cover the top surface of the etch barrier layer 110 away from the substrate 102. Metal material 208 is formed on the surface of the work function layer 210 away from the substrate 102 and is in contact with the work function layer 210.

[0094] As an example, the metal material 208 is ground until the work function layer 210 between the gate filling trench 206 and the recess 204 is exposed, forming the gate material 114. At this point, the top surface of the gate material 114 away from the substrate 102 is flush with the top surface of the work function layer 210 away from the substrate 102. By setting the metal material 208 to expose the work function layer 210 to form the gate material 114, the influence of the different speeds of the metal material 208 and the work function layer 210 on the height of the gate material 114 can be avoided, increasing the surface flatness after grinding the metal material 208.

[0095] As an example, the gate material 114 may be composed of one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), aluminum, or titanium (Ti); the conductive metal nitride may include titanium nitride (TiN); the conductive metal oxide may include iridium oxide (IrO2) or indium tin oxide (ITO); and the metal silicide may include titanium silicide (TiSi). For example, the gate material 114 may be composed of aluminum.

[0096] As an example, the constituent material of the work function layer 210 includes at least one of metallic molybdenum and titanium nitride.

[0097] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure after the recessed inner wall is exposed in an embodiment of this application. See also: Figure 7In some embodiments, a chemical dry etching process is used to etch the gate material 114 until the inner wall of the recess 204 is exposed. This includes: using a chemical dry etching process to etch the gate material 114 and the work function layer 210 until the inner wall of the recess 204 is exposed. At this time, the work function layer 210 on the inner wall of the recess 204 and the work function layer 210 between the gate filling trench 206 and the recess 204 are removed, and there is no gate material 114 in the recess 204, reducing the risk of short circuit.

[0098] Specifically, the etching rate of the gate material 114 using the chemical dry etching process is greater than the etching rate of the interlayer dielectric layer 112 using the same process. Furthermore, the etching rate of the work function layer 210 using the chemical dry etching process is greater than the etching rate of the interlayer dielectric layer 112. This configuration avoids the impact on the thickness of the interlayer dielectric layer 112 caused by removing the gate material 114 and work function layer 210 from the recess 204, and avoids the short-circuit risk caused by insufficient margin in the planarization process window during gate formation, which is crucial for the planarization of the gate material 114 and interlayer dielectric layer 112.

[0099] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the gate is formed in an embodiment of this application. See also: Figure 8 In some embodiments, a chemical mechanical polishing (CMP) process is used to planarize the gate material 114 and the interlayer dielectric layer 112 to form the gate 116. The CMP process grinds the gate material 114 at a rate equal to the CMP process grinds the interlayer dielectric layer 112. By setting the CMP process grinding speed of the gate material 114 to be equal to the CMP process grinding speed of the interlayer dielectric layer 112, the planarization of the gate 116 can be improved, increasing the yield of the semiconductor structure. By combining the chemical polishing process and the chemical dry etching process, the risk of short circuits caused by residual metal material 208 in the recess 204 is avoided, while obtaining a gate 116 with satisfactory height and flatness.

[0100] It should be understood that, although Figure 1 and Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 and Figure 2At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0101] In one embodiment of this application, a semiconductor structure is provided, which is fabricated using the semiconductor structure preparation method described above.

[0102] In one embodiment of this application, an electronic device is also provided, including the semiconductor structure described above. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the described electronic device.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure embodiments, and these modifications and improvements all fall within the protection scope of the present disclosure embodiments.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A dummy gate, an etch barrier layer, and an interlayer dielectric layer are formed on a substrate. The number of dummy gates is multiple and they are spaced apart. The etch barrier layer covers the sidewalls and top surface of the dummy gates. The interlayer dielectric layer covers the etch barrier layer and fills the trench between two adjacent dummy gates. The interlayer dielectric layer and the etch barrier layer are ground until the top surface of the dummy gate is exposed and a recess is formed in the interlayer dielectric layer within the trench; The dummy gate is replaced with a gate material, which fills the depression. The gate material is etched using a chemical dry etching process until the inner wall of the recess is exposed; The gate material and the interlayer dielectric layer are planarized to form a gate, wherein the top surface of the gate away from the substrate and the top surface of the interlayer dielectric layer away from the substrate are flush.

2. The preparation method according to claim 1, characterized in that, The step of replacing the dummy gate with a gate material includes: Remove the dummy gate to form a gate-filled groove; The gate material is formed by filling the gate filling groove and the recess.

3. The preparation method according to claim 2, characterized in that, The process of filling the gate filling trench and the recess to form the gate material includes: A metal material is filled into the gate filling trench and the recess, and the metal material covers the interlayer dielectric layer; The metal material is ground until the remaining metal material fills only the gate fill trench and the recess, forming the gate material.

4. The preparation method according to claim 3, characterized in that, Before filling the gate filling trench and recess with metal material, the method further includes: A work function layer is formed on the inner wall of the gate filling trench; the work function layer extends along the inner wall of the gate filling trench to the inner wall of the recess; the metal material covers the work function layer; The metal material is ground until the work function layer between the gate filling trench and the recess is exposed.

5. The preparation method according to claim 4, characterized in that, The step of etching the gate material using a chemical dry etching process until the inner wall of the recess is exposed includes: A chemical dry etching process is used to etch the gate material and the work function layer until the inner wall of the recess is exposed; The etching rates of the gate material and the work function layer in the chemical dry etching process are both greater than the etching rate of the interlayer dielectric layer in the chemical dry etching process.

6. The preparation method according to claim 3, characterized in that, The metal material is ground using a chemical mechanical polishing process until the remaining metal material only fills the gate fill trench and the recess.

7. The preparation method according to claim 1, characterized in that, The gate is formed by planarizing the gate material and the interlayer dielectric layer using a chemical mechanical polishing process. Wherein, the speed at which the chemical mechanical polishing process polishes the gate material is equal to the speed at which the chemical mechanical polishing process polishes the interlayer dielectric layer.

8. The preparation method according to claim 1, characterized in that, The preparation method further includes: forming multiple gate dielectric layers on a substrate; Each of the gate dielectric layers is located between a corresponding gate and the substrate.

9. The preparation method according to claim 8, characterized in that, Forming a dummy gate, an etch barrier layer, and an interlayer dielectric layer on a substrate, including: A stacked structure is formed on the substrate, the stacked structure comprising a gate dielectric material and a dummy gate material stacked along a first direction; the first direction is perpendicular to the substrate; A trench is formed that penetrates the stacked structure along the first direction to obtain a dummy gate and the gate dielectric layer; An etch barrier layer is formed on the inner wall of the trench; the etch barrier layer extends along the sidewall of the trench and covers the dummy gate. An interlayer dielectric layer is formed in the trench to contact the etch barrier layer; the interlayer dielectric layer extends along the sidewall of the trench to cover the dummy gate.

10. A semiconductor structure, characterized in that, It is prepared by any one of the preparation methods described in claims 1-9.

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