Semiconductor device and forming method thereof

Abstract

The method includes patterning a first opening through a first dielectric layer to expose a first source / drain region; forming a first silicide region on the first source / drain region; depositing a first plurality of polycyclic aromatic hydrocarbons along the surface of the first opening; performing an annealing process to convert the first plurality of polycyclic aromatic hydrocarbons into a first graphene layer; and filling a remaining portion of the first opening with a first metal material. In another embodiment, the method further includes forming a second opening through the first dielectric layer, the second source / drain region, and the third dielectric layer to expose the third source / drain region, where, in a top view, the second source / drain region overlaps the third source / drain region. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers over a semiconductor substrate, and patterning each material layer using photolithography to form electrical circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. As the semiconductor industry continues to advance toward higher densities, higher performance and lower costs, challenges have emerged in manufacturing and design that have resulted in stacked device configurations, such as stacked transistors, including complementary field effect transistors (CFETs). As the minimum feature size is reduced, however, additional components are introduced. SUMMARY

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: patterning a first opening through a first dielectric layer to expose a first source / drain region; forming a first silicide region on the first source / drain region; depositing a first plurality of polycyclic aromatic hydrocarbons along a surface of the first opening; performing an anneal process to convert the first plurality of polycyclic aromatic hydrocarbons to a first graphene layer; and filling a remaining portion of the first opening with a first metallic material.

[0005] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first opening through a plurality of layers to expose a first source / drain region, the plurality of layers comprising: a first dielectric layer disposed above the first source / drain region; a second source / drain region disposed above the first dielectric layer; and a second dielectric layer disposed above the second source / drain region; forming a first metal-semiconductor alloy on a surface of the first source / drain region; forming a second metal-semiconductor alloy on a surface of the second source / drain region; performing thermal evaporation deposition to deposit a first material in the first opening, the first material comprising a plurality of discontinuous sheets; performing an anneal process to convert the first material to a second material, the second material comprising a continuous sheet; and depositing a conductive material to fill the first opening.

[0006] Yet other embodiments of the present application provide a semiconductor device comprising: a first source / drain region; a first silicide region on the first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region overlapping the first source / drain region; a second silicide region on the second source / drain region; a contact plug extending through the second source / drain region to the first source / drain region, the contact plug comprising: a contact liner layer comprising a polycyclic aromatic hydrocarbon; and a metallic material; a second nanostructure adjacent to the second source / drain region; a first gate structure around the first nanostructure; and a second gate structure overlapping the first gate structure and around the second nanostructure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the illustrative embodiments can be best understood with reference to the following detailed description when read with the accompanying drawings in which:

[0008] Figure 1 A perspective view of an exemplary stacked transistor is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B are views of intermediate stages in the manufacture of a stacked transistor in accordance with some embodiments.

[0010] Figure 12 are views of intermediate stages in the manufacture of a stacked transistor in accordance with some embodiments.

[0011] Figures 13 to 16 are views of intermediate stages in the manufacture of a stacked transistor in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] A stacked transistor structure and a method for forming the same are provided. The stacked transistor structure (such as a CFET) and a method for forming the same are provided. The stacked transistor structure includes two transistors vertically stacked and having opposite types (e.g., vertically stacked n-type and p-type transistors). Therefore, the source / drain regions of the vertically stacked transistors can also be vertically stacked. Furthermore, source / drain region contacts to the upper and / or lower source / drain regions can be formed. A patterning step can be used to form openings to the source / drain regions, and the openings to the lower source / drain regions can have a high aspect ratio (e.g., up to 8 to 15). In various embodiments, a thin pad (e.g., less than or equal to) is formed along the surface of the opening. The ultrathin pad is used, and the remaining portion of the opening is filled with a conductive filler material. For example, the thin pad can include polycyclic aromatic hydrocarbons (PAHs), which can be processed before or after the deposition of the conductive filler material and transformed into a graphene pad layer. Due to the thin pad, the conductive filler material can be deposited into the opening (e.g., with a high aspect ratio) without shrinkage or void formation. The source / drain contacts are formed with improved yield and reliability, resulting in higher performance and robustness of the stacked transistors.

[0015] Figure 1 Examples of stacked transistors 10 (including FETs 10U and 10L) according to some embodiments are shown. Figure 1It is a 3D view, and for clarity, some components of the stacked transistors have been omitted.

[0016] The stacked transistor includes multiple vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be adapted to other types of transistors (e.g., finFETs, etc.).

[0017] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 may refer to either a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0018] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor and in the direction of current, for example, between the source / drain regions 62 of the stacked transistor. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and extending through the source / drain regions 62 of the stacked transistor. For clarity, subsequent figures may refer to these reference cross sections.

[0019] Figures 2 to 16 Stacked transistors (such as) according to some embodiments are shown. Figure 1 A cross-sectional view of an intermediate stage in the formation of (illustrated representation). In the following discussion, unless otherwise stated, figures with a number followed by the letter "A" indicate the process along the [symbol / symbol]. Figure 1 A vertical section diagram similar to the vertical reference section A-A' in the diagram. The diagram with a number followed by the letter "B" shows the section along the vertical reference section A-A'. Figure 1A vertical section diagram of a section similar to the vertical reference section B-B' in the diagram. Furthermore, Figure 12 The vertical section B-B' is shown, and Figures 13 to 16 The vertical section A-A' is shown.

[0020] exist Figure 2 The wafer is provided, and the wafer includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, or combinations thereof.

[0021] Semiconductor strips 28 are formed extending upward from semiconductor substrate 20. Each semiconductor strip 28 includes a semiconductor strip 20' (a patterned portion of semiconductor substrate 20, also referred to as semiconductor fin 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes a pseudo-nanostructure 24A, one or more pseudo-nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Pseudo-nanostructures 24A and 24B can be further collectively referred to as pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0022] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the pseudo-semiconductor layer 24B can be removed at a faster rate than the pseudo-semiconductor layer 24A.

[0023] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 24 exhibit high etch selectivity towards the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-nanostructure 24A is formed of or includes silicon-germanium, the semiconductor nanostructure 26 is formed of silicon, and the pseudo-nanostructure 24B can be formed of germanium or silicon-germanium having a higher percentage of germanium atoms than the pseudo-nanostructure 24A.

[0024] The lower semiconductor nanostructure 26L will provide the channel region for the lower nanostructure FET used in the CFET. The upper semiconductor nanostructure 26U will provide the channel region for the upper nanostructure FET used in the CFET. The semiconductor nanostructure 26, located directly above / below (e.g., in contact with) the pseudo-nanostructure 24B, can be used for isolation and may or may not be used as the channel region for the CFET. The pseudo-nanostructure 24B will then be replaced by an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0025] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) can be deposited over the semiconductor substrate 20. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor strip 20', a pseudo-nanostructure 24, and a semiconductor nanostructure 26.

[0026] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual patterning or multi-patterning processes. Typically, dual or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, and the semiconductor substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0027] Similarly, Figure 2 As shown, an isolation region 32, such as a shallow trench isolation (STI) region 32, is formed over the substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric pad and a dielectric material above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof. Forming the STI region 32 may include: depositing a dielectric layer; and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc., to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric layer is then recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0028] After forming the STI region 32, a dummy gate stack 42 can be formed over the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32) and along the sidewalls of the upper portion of the semiconductor strip 28. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or include, for example, silicon oxide, silicon nitride, combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, poly-SiGe, etc. A mask layer 40, including, for example, silicon nitride, silicon oxynitride, etc., is formed over the planarized dummy gate layer 38. Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38, and possibly etch and pattern the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0029] exist Figure 3 In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc. Fin spacers 45 (see...) can also be formed. Figure 4B It is part of forming the gate spacer 44.

[0030] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or flush with the top surface of isolation region 32. During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach the desired depth, a timing etching process can be used to stop the etching of the source / drain recesses 46.

[0031] Figure 4A and Figure 4B The various subsequent processing steps are shown.Figure 4A The A-A' section of the structure is shown, and Figure 4B The B-B' cross-section of the structure is shown. Specifically, an internal spacer 54 and a dielectric isolation layer 56 are formed. Forming the internal spacer 54 and the dielectric isolation layer 56 may include an etching process that laterally etches the pseudo-nanostructure 24A and removes the pseudo-nanostructure 24B. The etching process may be isotropic and selective for the material of the pseudo-nanostructure 24, such that the pseudo-nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective for the material of the pseudo-nanostructure 24B, such that the pseudo-nanostructure 24B is etched at a faster rate than the pseudo-nanostructure 24A. In this way, the pseudo-nanostructure 24B can be completely removed from between the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L) and the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U), without completely removing the pseudo-nanostructure 24A.

[0032] In some embodiments, where the pseudo-nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the pseudo-nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the pseudo-gate stack 42 surrounds the sidewalls of the semiconductor nanostructure 26 (see...), Figure 2 Therefore, the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, preventing it from collapsing when the dummy nanostructure 24B is removed. Furthermore, although the sidewalls of the dummy nanostructure 24A are shown as straight after etching, the sidewalls can be concave or convex.

[0033] An internal spacer 54 is formed on the sidewall of the recessed pseudo-nanostructure 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U) and the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the pseudo-nanostructure 24A will be replaced with the corresponding gate structure. The internal spacer 54 serves as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (such as etching processes for forming the gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26L) from the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0034] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonate, silicon oxycarbonate, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value of less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion retained in the sidewalls of the pseudo-nanostructure 26A (thus forming the internal spacer 54) and a portion retained between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0035] like Figure 4A and Figure 4B As further shown, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. An internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0036] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0037] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0038] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0039] The formation process may include: depositing a conformal CESL layer; depositing material for the first ILD 68; and a subsequent planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0040] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U may be doped in situ with n-type or p-type dopants and / or may be implanted with n-type or p-type dopants. Adjacent upper source / drain regions 62U may remain separated after the epitaxial process, or they may be merged.

[0041] After forming the epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail here. The formation process may include: depositing layers for CESL 70 and ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 (if present) or the dummy gate 38 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or the dummy gate 38 is exposed through the second ILD 124. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, thereby exposing the top surface of the dummy gate 38 through the second ILD 72.

[0042] exist Figure 5A and Figure 5B In this process, a gate replacement process is implemented to replace the pseudo gate stack 42 and the pseudo nanostructure 24A with the gate stack 90. Figure 5A The A-A' section of the structure is shown, and Figure 5BA B-B' cross-section of the structure is shown. The gate replacement process includes first removing the dummy gate stack 42 and the remainder of the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, thereby defining a trench between the gate spacers 44 and exposing the upper portion of the semiconductor strip 28. The remainder of the dummy nanostructure 24A is then removed by etching, such that the trench extends between the semiconductor nanostructures 26. In the etching process, the material of the dummy nanostructure 24A is etched at a rate faster than the material of the semiconductor nanostructure 26, the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0043] Then, a gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric 78 is conformally formed on the exposed surface of the recesses (removed gate stack 42 and pseudo nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 encapsulates all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 may be formed on the top surface of the fin 20'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 26; and the sidewalls of the gate spacers 44. The gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric 78 may include high dielectric constant (high k) materials having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 located above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0044] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L encapsulates the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0045] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0046] The lower gate electrode 80L can be formed by: conformally depositing one or more gate electrode layers; or by recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0047] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0048] Then, an upper gate electrode 80U is formed on the isolation layer (if present) or lower gate electrode 80L described above. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U encapsulates the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0049] Furthermore, a removal process is performed to make the top surfaces of the upper gate electrode 80U and the second ILD 72 flush. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each corresponding pair of gate dielectric 78 and gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 The lower gate structure 90L may also extend along the sidewalls and / or top surface of the semiconductor fin 20'.

[0050] like Figure 5A As further shown, a gate mask 92 is formed over the gate stack 90. ​​The formation process may include: recessing the gate stack 90; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, or combinations thereof; and performing a planarization process to remove excess portions of the dielectric material over the second ILD 72.

[0051] Figures 6A to 10B Source / drain contacts 96 (e.g., contact plugs) are shown formed according to some embodiments to be electrically coupled to upper epitaxial source / drain regions 62U and / or lower epitaxial source / drain regions 62L. Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A The A-A' section of the structure is shown, and Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B The B-B' cross-section of the structure is shown. As described in more detail below, a source / drain contact opening 82 is formed to the source / drain region 62, a source / drain contact pad layer 88 is formed in the source / drain contact opening, and the remainder of the source / drain contact opening 82 is filled with a conductive material 94 to form a source / drain contact 96.

[0052] exist Figure 6A and Figure 6BIn the second ILD 72, source / drain contact openings 82 are formed to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. For example, the upper source / drain contact opening 82U and the lower source / drain contact opening 82L are formed to expose (and optionally extend therein) the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L, respectively. Specifically, the lower source / drain contact opening 82L may extend through the second ILD 72, the second CESL 70, the upper epitaxial source / drain region 62U, the first ILD 68, and / or the first CESL 66 to expose and partially extend into the lower epitaxial source / drain region 62L, and the upper source / drain contact opening 82U extends through the second ILD 72 and the second CESL 70 to expose and partially extend into the upper epitaxial source / drain region 62U. Each of the upper source / drain contact openings 82U may or may not be connected to one of the lower source / drain contact openings 82L. In the region connecting the upper source / drain contact opening 82U and the lower source / drain contact opening 82L, the exposed upper epitaxial source / drain region 62U and lower epitaxial source / drain region 62L can be electrically connected together by source / drain contacts subsequently formed in the connecting upper source / drain contact opening 82U and lower source / drain contact opening 82L (see...). Figure 10A and Figure 10B ).

[0053] For example, the upper source / drain contact opening 82U and the lower source / drain contact opening 82L can be formed by a combination of sequential photolithography and etching processes. In some embodiments, the lower source / drain contact opening 82L can be formed before the upper source / drain contact opening 82U. Optionally, this order can be reversed, and the upper source / drain contact opening 82U can be formed before the lower source / drain contact opening 82L.

[0054] According to various embodiments, the source / drain contact opening 82 can have a high aspect ratio. For example, the aspect ratio of the lower source / drain contact opening 82L can be as high as about 8 to about 15. Furthermore, the width (e.g., diameter) of the source / drain contact opening 82 can be about 4 nm to about 15 nm. Additionally, the lower source / drain contact opening 82L can have a depth ranging from about 32 nm to about 225 nm. For example, an embodiment of the lower source / drain contact opening 82L with a width of about 4 nm can have a depth between about 32 nm and about 60 nm (e.g., an aspect ratio ranging from 8 to 15). Furthermore, an embodiment of the lower source / drain contact opening 82L with a width of about 15 nm can have a depth between about 60 nm and about 225 nm (e.g., an aspect ratio ranging from 8 to 15).

[0055] In some embodiments (see) Figure 12 The formation of the source / drain contact opening 82 may include a widening process to widen the upper portion of the source / drain contact opening 82. For example, over-etching in the upper portion can be used to reduce the aspect ratio of the upper portion of the source / drain contact opening 82. These wider upper portions can improve the gap-filling process during the formation of the source / drain contact 82.

[0056] exist Figure 7A and Figure 7B In this process, a metal-semiconductor alloy region 84 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 84 may be a silicide region formed by metal silicides (e.g., nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), ruthenium silicide (RuSi), zirconium silicide (ZrSi), antimony silicide (SbSi), cobalt silicide (CoSi), etc.), a germanium region formed by metal germanides (e.g., nickel germanide (NiGe), titanium germanide (TiGe), tungsten germanide (WGe), molybdenum germanide (MoGe), ruthenium germanide (RuGe), zirconium germanide (ZrGe), antimony germanide (SbGe), cobalt germanide (CoGe), etc.), or a silicon-germanium region formed by metal silicides and metal germanides, etc. The metal-semiconductor alloy region 84 can be formed prior to the material of the source / drain contact 96 by depositing metal in the opening for the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof.

[0057] Furthermore, the metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings for the source / drain contacts 96 (such as from the surface of the metal-semiconductor alloy region 84). The metal-semiconductor alloy region 84 may include an upper metal-semiconductor alloy region 84U along the exposed surface of the upper source / drain region 62U and a lower metal-semiconductor alloy region 84L along the exposed surface of the lower source / drain region 62L.

[0058] exist Figure 8A and Figure 8BIn this process, a contact pad precursor 86 is formed along the surface of the source / drain contact opening 82. In some embodiments, forming the contact pad precursor 86 includes depositing a variety of polycyclic aromatic hydrocarbons (PAHs) along the surface of the source / drain contact opening 82. PAHs may include, for example, anthracene, pyrene, perylene, benzo[a]benzene, benzo[b]benzene, etc., or any combination thereof. The contact pad precursor 86 may be attached and bonded to the surface without forming a chemical bond. For example, the contact pad precursor 86 may be bonded to the surface by electrostatic interactions, such as hydrogen bonding and / or van der Waals forces. For example, hydrogen bonding may bond the contact pad precursor 86 to a first ILD 68 and a second ILD 72, as well as a first CESL 66 and a second CESL 70, of silicides, oxides, nitrides, etc., via van der Waals forces (e.g., weak electrostatic forces). Therefore, the interface between the contact pad precursor 86 and the surface of the source / drain contact opening 82 (e.g., metal-semiconductor alloy region 84) may be substantially free of chemical bonding.

[0059] The deposition process can be any suitable method, such as thermal evaporation deposition. For example, the precursor material can be evaporated into vapor in a vacuum chamber, the vapor can be sent to a processing chamber via a gas line, and the vapor can be condensed onto a structure (e.g., the surface of the source / drain contact opening 82). In some embodiments, thermal evaporation deposition is performed at a temperature ranging from about 300°C to about 400°C.

[0060] In some embodiments, the contact pad precursor 86 within each source / drain contact opening 82 may be in the form of small pieces (e.g., groups or clusters) that are discontinuous or interconnected with multiple voids. For example, any of the PAHs (etc.) listed above may constitute the contact pad precursor. In some embodiments, some or substantially all of the PAHs may be chemically bonded to each other to form a PAH network along the surface of the respective source / drain contact opening 82. Thus, the contact pad precursor may have a size less than or equal to approximately The thickness, such as less than or equal to approximately

[0061] exist Figure 9A and Figure 9B In this process, a process is performed to transform the contact pad precursor 86 into a contact pad layer 88. In some embodiments, the process may be an annealing process, such as a rapid vacuum pyrolysis (FVP) annealing process. For example, the process may transform the contact pad precursor 86 comprising a PAH into a contact pad layer 88 comprising a graphene sheet (e.g., a two-dimensional (2D) layer following the contour of the source / drain contact opening 82). Thus, the contact pad layer 88 may have a surface area less than or equal to The thickness (e.g., ranging from approximately) to approximately It should be noted that the increase in the aspect ratio of the source / drain contact opening 82 is small enough to facilitate subsequent processes for filling the remaining portion of the source / drain contact opening 82 with conductive filler material.

[0062] According to some embodiments, the FVP annealing process connects different PAH molecules (e.g., groups or flakes) to each other to form a contact pad layer 88 within each source / drain contact opening 82 as a substantially continuous sheet or several large continuous sheets. In embodiments where the contact pad precursor 86 includes a network of interconnected PAHs, the process may further connect the PAHs (e.g., fill voids) to form a graphene sheet. Each graphene sheet of the contact pad layer 88 may have few or virtually no voids. Thus, the contact pad layer 88 comprises a more ordered arrangement of aromatic rings compared to the contact pad precursor 86.

[0063] The FVP annealing process can be carried out at a temperature ranging from about 300°C to about 1100°C and at a pressure ranging from about 1E4 Torr to about 5 Torr for a duration between about 0.1 seconds and about 5 seconds. For example, the FVP annealing process can be carried out at a temperature greater than that used for depositing the contact liner precursor 86.

[0064] Similarly, as discussed above with respect to the contact pad precursor 86, van der Waals forces allow the contact pad layer 88 to adhere to the surface of the source / drain contact opening 82. Therefore, the interface between the contact pad layer 88 and the surface of the source / drain contact opening 82 (e.g., the metal-semiconductor alloy region 84) can remain substantially free of chemical bonding.

[0065] According to some embodiments (not specifically shown), the contact pad layer 88 may have a varying thickness along the source / drain contact opening 82. For example, the contact pad precursor 86 may be deposited with a greater thickness along the metal-semiconductor alloy region 84 than along the dielectric layer (e.g., CESL 66, first ILD 68, CESL 70, and / or second ILD 72). Furthermore, the contact pad precursor 86 may be deposited with a greater thickness over the upward surface than over the sidewall surface. Thus, the contact pad precursor 86 may be deposited with a greater thickness over the lower metal-semiconductor alloy region 84L than over the sidewall surface of the upper metal-semiconductor alloy region 84U. However, the contact pad precursor 86 may be deposited with a maximum thickness over the upward surface of the upper metal-semiconductor alloy region 84U. These relative thickness variations in the contact pad precursor may remain substantially the same after the contact pad layer 88 is formed. In other embodiments, the contact pad precursor 86 may be deposited with a greater thickness over the dielectric layer than over the metal-semiconductor alloy region 84.

[0066] exist Figure 10A and Figure 10BIn the source / drain contact opening 82 and on the contact pad layer 88, a conductive material 94 is formed to electrically couple to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. The source / drain contact 96 includes the contact pad layer 88 and the conductive material 94. The conductive material 94 can be a metal, such as ruthenium, tungsten, molybdenum, cobalt, copper, copper alloys, silver, gold, aluminum, nickel, combinations thereof, etc., and can be formed by plating processes, PVD, CVD, ALD, etc. A removal process can be implemented to remove excess material from the top surface of the gate spacer 44 and the second ILD 72. The remaining contact pad layer 88 and conductive material 94 form the source / drain contact 96 in the source / drain contact opening 82. In some embodiments, planarization processes such as CMP, etch-back processes, combinations thereof are utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD72, and the source / drain contact 96 are substantially coplanar (within process variations).

[0067] The formation of the contact pad layer 88, as described above, improves the process for depositing conductive material 94 in the source / drain contact opening 82. As discussed above, the lower source / drain contact opening 82L can have a high aspect ratio, which can make the deposition of conductive material 94 prone to shrinkage or void formation. Furthermore, the aspect ratio increases after the formation of the contact pad layer 88 by further narrowing the remaining portion of the source / drain contact opening 82. However, the contact pad layer 88 formed according to the disclosed embodiments is a substantially uniform and flat thin graphene sheet. This allows the conductive material 94 to diffuse along the contact pad layer 88 to reach the lower portion of the source / drain contact opening 82, while the upper portion along the sidewalls has less attachment and accumulation. Furthermore, the substantially uniform and flat nature of the conductive material 94 ensures that these attachment portions of the conductive material 94 remain in place and are less likely to slip when partially attached to the contact pad layer 88.

[0068] As discussed above, the aspect ratio of the lower source / drain contact opening 82L can be as high as approximately 8 to approximately 15. Furthermore, the aspect ratio can be approximately... When the contact pad layer 88 is of a certain thickness, the aspect ratio can be increased by 7% to 33% (e.g., reducing the width of the source / drain contact opening 84 by about 1 nm). For example, a lower source / drain contact opening 82L with a width of about 15 nm can be reduced to about 14 nm after the contact pad layer 88 is formed, which can increase the aspect ratio range from 8 to 15 to about 8.5 to about 16. Furthermore, after the contact pad layer 88 is formed, a lower source / drain contact opening 82L with a width of about 4 nm can be reduced to about 3 nm, which can increase the aspect ratio range from 8 to 15 to about 10.5 to about 20. It should be understood that a thicker contact pad layer 88 will result in a greater increase in aspect ratio, which will increase the risk of shrinkage and / or void formation during the deposition of the conductive material 94.

[0069] In some embodiments (not specifically shown), conductive material 94 may be deposited on top of contact pad precursor 86 prior to performing a processing step (e.g., FVP annealing) on ​​contact pad precursor 86. In such embodiments, the annealing process may be performed before or after a removal process to remove excess material and flush the conductive material 94.

[0070] exist Figure 11A and Figure 11B In the process, ESL 104 and third ILD 106 are then formed. In some embodiments, ESL 104 may comprise a dielectric material with high etch selectivity relative to the etching of third ILD 106, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0071] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 108 and the source / drain via 110, openings for the gate contact 108 and the source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately) (such as diffusion barrier layers, adhesive layers, etc.) and conductive material are formed within the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form the gate contact 108 and the source / drain via 110 within the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0072] A front-side interconnect structure 114 is formed on device layer 112. The front-side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0073] Conductive components 118 may include wires and vias, which can be formed using a damascene process. Conductive components 118 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads may also be present above the metal wires and vias and electrically connected to them. In some embodiments, contacts to the lower gate stack 90L and the lower source / drain region 62L may be fabricated via the back side of device layer 112 (e.g., the side opposite the front interconnect structure 114).

[0074] exist Figure 12In various embodiments, contacts to the lower gate stack 90L and the lower epitaxial source / drain region 62L can be fabricated via the back side of device layer 122 (e.g., the side opposite to the front interconnect structure 128). For example, device layer 122 is shown located between the front interconnect structure 128 and the back interconnect structure 134. The back interconnect structure 134 can be substantially similar to the front interconnect structure 128 as described above. It should be noted that the same reference numerals indicate the same elements formed by the same process as described above.

[0075] A contact via 130 is formed having contact spacers 132 disposed on its sidewalls to extend through at least partially through the device layer 122. The contact via 130 and contact spacers 132 can be formed from the same material and using the same process as the upper and lower source / drain vias 110. For example, the opening can be formed by a combination of photolithography and etching processes. The contact spacers 132 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc., and can be formed by conformally depositing an insulating material layer (not explicitly shown) via CVD, ALD, etc. The lateral portions of the insulating material layer can then be etched away using an anisotropic etching process (such as plasma-based dry etching) to form the contact spacers 132. A conductive material, including cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc., is then formed in the opening. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the second ILD 72.

[0076] As shown in the figure, before forming ESL 104 and the third ILD 106, contact via 130 and contact spacer 132 can be formed to pass through the first ESL 66, the first ILD 68, the second ESL 70, and the second ILD 72. Contact via 130 can be electrically connected to the back-side interconnect structure 134, and contact via 130 can also be electrically connected to the front-side interconnect structure 128 (e.g., via the upper source / drain contact 120). In this way, an interconnection between the front-side interconnect structure 128 and the back-side interconnect structure 134 can be achieved.

[0077] As further shown, some of the source / drain contacts 96 can be coupled to the contact via 130. The source / drain contacts 96 can be formed similarly as described above. Figures 6A to 10BImplemented as described. In some embodiments, the third ILD 106 is formed prior to the formation of the source / drain contact 96 or as part of the formation of the source / drain contact 96. Furthermore, the third ILD 106 may include multiple layers to facilitate multiple patterning and etching steps to couple the source / drain contact 96 to the contact via 130 and / or the source / drain region 62. Therefore, the third ILD 106 and ESL 104 may collectively include ESL 104A, third ILD 106A, ESL 104B, and third ILD 106B. Additionally, as discussed above, a widening process can be used to widen the upper portion of the source / drain contact opening 82 (see...). Figure 6A and Figure 6B Over-etching of the upper portion can be used to reduce the aspect ratio of the upper portion for the source / drain contact opening 82, which provides further improvement to the gap filling process (see...). Figures 8A to 10B ).

[0078] Figures 13 to 16 Additional embodiments are shown for forming conductive material 94 over the contact pad layer 88 in the source / drain contact opening 82. It should be noted that these embodiments can be used in conjunction with any other embodiments described above, where appropriate and suitable.

[0079] exist Figure 13 In the figure, a first portion of conductive material 94 is formed in the source / drain contact opening 82. As shown, a first portion of upper conductive material 94U is formed in the upper source / drain contact opening 82U, and a first portion of lower conductive material 94L is formed in the lower source / drain contact opening 82L. In some embodiments, due to the high aspect ratio of the lower source / drain contact opening 82L, the first portion of the lower conductive material 94L may form one or more voids 94V.

[0080] exist Figure 14 In this process, an etching-back process is performed to remove some of the first portion of the conductive material 94. Specifically, the etching-back process is performed until the voids 94V are no longer enclosed within the conductive material 94 (e.g., the lower conductive material 94L). The etching-back process may include anisotropic etching, isotropic etching, or a combination thereof.

[0081] exist Figure 15In this process, a second portion of the conductive material 94 is formed above the first portion of the etched conductive material 94. As shown, the second portion of the upper conductive material 94U is formed to further fill the upper source / drain contact opening 82U, and the second portion of the lower conductive material 94L is formed to fill the lower source / drain contact opening 82L. In some embodiments, due to the high aspect ratio of the lower source / drain contact opening 82L, the second portion of the lower conductive material 94L may form one or more additional voids 94V.

[0082] exist Figure 16 In this process, another etch-back process can be performed to remove the additional voids 94V, and the source / drain contact opening 82 can be filled with a third portion of the conductive material 94. In some embodiments, the steps of depositing the conductive material 94 and etching back the conductive material 94 can be performed any suitable number of times to ensure that the conductive material 94 is substantially free of voids 94V. For example, some embodiments may utilize one etch-back step, and other embodiments may utilize more than two etch-back steps. After the remaining portion of the source / drain contact opening 82 is filled and there are no voids 94V, removal processes and other processing steps can be performed, similarly as described above.

[0083] Each of these advantages is achieved. Some contact openings (such as the lower source / drain contact opening 82L leading to the lower source / drain region 62L of the stacked transistor) can have a high aspect ratio. In particular, the formation of the lower source / drain contact 96L can benefit from the embodiments disclosed herein. For example, the contact pad layer 88 can be deposited as polycyclic aromatic hydrocarbons (PAHs) and processed to transform into an ultrathin graphene sheet. The contact pad layer 88 can be less than or equal to Therefore, after the contact pad layer 88 is formed, the aspect ratio of the lower source / drain contact opening 82L increases only slightly. This allows the conductive material 94 to be deposited with essentially zero voids (or very few voids). Consequently, semiconductor devices utilizing these transistors can operate with improved performance and higher reliability.

[0084] In one embodiment, the method includes: patterning a first opening through a first dielectric layer to expose a first source / drain region; forming a first silicide region on the first source / drain region; depositing a first polycyclic aromatic hydrocarbon (PAH) along the surface of the first opening; performing an annealing process to convert the first PAH into a first graphene layer; and filling the remainder of the first opening with a first metallic material. In another embodiment, the method further includes forming a second opening through the first dielectric layer, a second source / drain region, and a third dielectric layer to expose a third source / drain region, wherein, in a top view, the second source / drain region overlaps with the third source / drain region. In another embodiment, forming the first silicide region includes: forming a second silicide region on the second source / drain region; and forming a third silicide region on the third source / drain region. In another embodiment, the method further includes: depositing a second PAH along the surface of the second opening; performing an annealing process to convert the second PAH into a second graphene layer; and filling the remainder of the second opening with a second metallic material. In another embodiment, filling the remaining portion of the second opening with the second metallic material includes: depositing a first portion of the second metallic material into the second opening; performing an etching process to remove some of the first portion of the second metallic material; and after performing the etching process, depositing a second portion of the second metallic material into the second opening. In another embodiment, there is no chemical bonding at the interface between the first graphene layer and the first silicide region. In another embodiment, a first polycyclic aromatic hydrocarbon is bonded to the first silicide region by van der Waals forces before filling the remaining portion of the first opening. In another embodiment, filling the remaining portion of the first opening with the first metallic material is performed before performing an annealing process to convert the first polycyclic aromatic hydrocarbon into the first graphene layer.

[0085] In one embodiment, the method includes: forming a first opening through a plurality of layers to expose a first source / drain region, the plurality of layers including: a first dielectric layer disposed over the first source / drain region; a second source / drain region disposed over the first dielectric layer; and a second dielectric layer disposed over the second source / drain region; forming a first metal-semiconductor alloy on a surface of the first source / drain region; forming a second metal-semiconductor alloy on a surface of the second source / drain region; performing thermal evaporation deposition to deposit a first material in the first opening, the first material comprising a plurality of discontinuous sheets; performing an annealing process to convert the first material into a second material, the second material comprising continuous sheets; and depositing a conductive material to fill the first opening. In another embodiment, the first material comprises a polycyclic aromatic hydrocarbon. In another embodiment, the second material comprises graphene. In another embodiment, the second material has a density less than or equal to... The thickness. In another embodiment, the annealing process includes rapid vacuum pyrolysis. In another embodiment, the conductive material includes ruthenium.

[0086] In one embodiment, the semiconductor device includes: a first source / drain region; a first silicide region located on the first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region overlapping the first source / drain region; a second silicide region located on the second source / drain region; and a contact plug extending through the second source / drain region to the first source / drain region, the contact plug including: a contact pad layer comprising a polycyclic aromatic hydrocarbon; and a metallic material; a second nanostructure adjacent to the second source / drain region; a first gate structure located around the first nanostructure; and a second gate structure overlapping the first gate structure and located around the second nanostructure. In another embodiment, the contact pad layer comprises a graphene sheet. In another embodiment, the contact pad layer has a density less than or equal to... The thickness. In another embodiment, the contact pad layer comprises a continuous sheet extending between the first silicide region and the second silicide region. In another embodiment, the metallic material comprises ruthenium. In another embodiment, the semiconductor device further comprises: a third source / drain region adjacent to the second nanostructure; and an additional contact plug extending to the third source / drain region, the additional contact plug comprising: an additional contact pad layer comprising a polycyclic aromatic hydrocarbon; and an additional metallic material.

[0087] Some embodiments of this application provide a method for forming a semiconductor device, including: patterning a first opening through a first dielectric layer to expose a first source / drain region; forming a first silicide region on the first source / drain region; depositing a first plurality of polycyclic aromatic hydrocarbons along the surface of the first opening; performing an annealing process to convert the first plurality of polycyclic aromatic hydrocarbons into a first graphene layer; and filling the remaining portion of the first opening with a first metallic material.

[0088] In some embodiments, the method further includes forming a second opening through the first dielectric layer, the second source / drain region, and the third dielectric layer to expose a third source / drain region, wherein, in a top view, the second source / drain region overlaps with the third source / drain region. In some embodiments, forming the first silicide region includes: forming a second silicide region on the second source / drain region; and forming a third silicide region on the third source / drain region. In some embodiments, the method further includes: depositing a second polycyclic aromatic hydrocarbon along the surface of the second opening; performing the annealing process to convert the second polycyclic aromatic hydrocarbon into a second graphene layer; and filling the remaining portion of the second opening with a second metal material. In some embodiments, filling the remaining portion of the second opening with the second metal material includes: depositing a first portion of the second metal material into the second opening; performing an etching process to remove some of the first portion of the second metal material; and after performing the etching process, depositing a second portion of the second metal material into the second opening. In some embodiments, the interface between the first graphene layer and the first silicide region is not chemically bonded. In some embodiments, the first polycyclic aromatic hydrocarbons are bonded to the first silicide region by van der Waals forces before filling the remaining portion of the first opening. In some embodiments, filling the remaining portion of the first opening with the first metallic material is performed before performing the annealing process to convert the first polycyclic aromatic hydrocarbons into the first graphene layer.

[0089] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a first opening through a plurality of layers to expose a first source / drain region, the plurality of layers including: a first dielectric layer disposed over the first source / drain region; a second source / drain region disposed over the first dielectric layer; and a second dielectric layer disposed over the second source / drain region; forming a first metal-semiconductor alloy on a surface of the first source / drain region; forming a second metal-semiconductor alloy on a surface of the second source / drain region; performing thermal evaporation deposition to deposit a first material in the first opening, the first material comprising a plurality of discontinuous sheets; performing an annealing process to convert the first material into a second material, the second material comprising continuous sheets; and depositing a conductive material to fill the first opening. In some embodiments, the first material comprises a polycyclic aromatic hydrocarbon. In some embodiments, the second material comprises graphene. In some embodiments, the second material has a content less than or equal to The thickness. In some embodiments, the annealing process includes rapid vacuum pyrolysis. In some embodiments, the conductive material includes ruthenium.

[0090] Further embodiments of this application provide a semiconductor device including: a first source / drain region; a first silicide region located on the first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region overlapping the first source / drain region; a second silicide region located on the second source / drain region; a contact plug extending through the second source / drain region to the first source / drain region, the contact plug including: a contact pad layer comprising a polycyclic aromatic hydrocarbon; and a metallic material; a second nanostructure adjacent to the second source / drain region; a first gate structure located around the first nanostructure; and a second gate structure overlapping the first gate structure and located around the second nanostructure.

[0091] In some embodiments, the contact pad layer comprises a graphene sheet. In some embodiments, the contact pad layer has a density less than or equal to... The thickness. In some embodiments, the contact pad layer comprises a continuous sheet extending between the first silicide region and the second silicide region. In some embodiments, the metal material comprises ruthenium. In some embodiments, the semiconductor device further comprises: a third source / drain region adjacent to the second nanostructure; and an additional contact plug extending to the third source / drain region, the additional contact plug comprising: an additional contact pad layer comprising the polycyclic aromatic hydrocarbon; and an additional metal material.

[0092] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor device, comprising: patterning a first opening through a first dielectric layer to expose a first source / drain region; forming a first silicide region on the first source / drain region; depositing a first plurality of polycyclic aromatics along a surface of the first opening; implementing an anneal process to convert the first plurality of polycyclic aromatics into a first graphene layer; filling a remaining portion of the first opening with a first metallic material. in a top view, the second source / drain region overlaps the third source / drain region.

2. The method of claim 1, further comprising forming a second opening through the first dielectric layer, the second source / drain region, and the third dielectric layer to expose a third source / drain region, wherein, forming the first silicide region comprises:

3. The method of claim 2, wherein, forming a second silicide region on the second source / drain region; and forming a third silicide region on the third source / drain region.

4. The method of claim 3, further comprising: depositing a second plurality of polycyclic aromatics along a surface of the second opening; implementing the anneal process to convert the second plurality of polycyclic aromatics into a second graphene layer; filling a remaining portion of the second opening with a second metallic material. filling the remaining portion of the second opening with the second metallic material comprises: depositing a first portion of the second metallic material into the second opening; 5. The method of claim 4, wherein, implementing an etch process to remove some of the first portion of the second metallic material; and after implementing the etch process, depositing a second portion of the second metallic material into the second opening. an interface between the first graphene layer and the first silicide region is free of chemical bonding. prior to filling the remaining portion of the first opening, the first plurality of polycyclic aromatics are adhered to the first silicide region by van der Waals forces.

6. The method of claim 1, wherein, filling the remaining portion of the first opening with the first metallic material is implemented prior to implementing the anneal process to convert the first plurality of polycyclic aromatics into the first graphene layer.

7. The method of claim 6, wherein, 9. A method of forming a semiconductor device, comprising:

8. The method of claim 1, wherein, forming a first opening through a plurality of layers to expose a first source / drain region, the plurality of layers comprising: a first dielectric layer disposed above the first source / drain region; a second source / drain region disposed above the first dielectric layer; and a second dielectric layer disposed above the second source / drain region; forming a first metal-semiconductor alloy on a surface of the first source / drain region; forming a second metal-semiconductor alloy on a surface of the second source / drain region; implementing thermal evaporation deposition to deposit a first material in the first opening, the first material comprising a plurality of discontinuous sheets; implementing an anneal process to convert the first material into a second material, the second material comprising a continuous sheet; and depositing a conductive material to fill the first opening.

10. A semiconductor device, comprising: a first source / drain region; a first silicide region on the first source / drain region; a first nanostructure adjacent to the first source / drain region; a second source / drain region overlapping the first source / drain region; a second silicide region on the second source / drain region; ​ ​ a contact plug extending through the second source / drain region to the first source / drain region, the contact plug comprising: a contact liner layer comprising a polycyclic aromatic hydrocarbon; and a metallic material; a second nanostructure adjacent to the second source / drain region; a first gate structure located around the first nanostructure; and a second gate structure overlapping the first gate structure and located around the second nanostructure.

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