A GaN HEMT monolithic integrated complementary inverter and a device manufacturing method thereof

By integrating n-channel and p-channel enhancement-mode devices in GaN HEMTs and utilizing graphene layers and two-dimensional dielectric layers to improve interface quality, the problems of slow switching speed and insufficient hole carrier concentration in GaN HEMTs are solved, achieving efficient signal switching and stable high-frequency performance.

CN121548103BActive Publication Date: 2026-05-05ZHONGKE (SHENZHEN) WIRELESS SEMICON CO LTD
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Patent Information

Application Number
CN202610070620.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-01-20
Publication Date
2026-05-05
Estimated Expiration
2046-01-20

AI Technical Summary

Technical Problem

Existing GaN HEMT switching transistor drive circuits have slow response speeds and large chip areas. The insufficient hole carrier concentration in p-channel enhancement-mode GaN HEMTs leads to poor performance of complementary inverters in high-voltage and high-frequency applications.

Method used

A monolithically integrated n-channel and p-channel enhancement-mode GaN HEMT is adopted. A polarized dipole layer is formed on the P-GaN layer using a graphene layer. The interface defects are improved and the hole injection capability is enhanced by combining the two-dimensional dielectric layer and the graphene layer. Electrical connection is achieved through a metal interconnect layer.

Benefits of technology

It improves signal switching speed, reduces ohmic contact resistance and gate leakage current, enhances the heat dissipation capacity of the device during high-power operation, and improves the stability and matching of device performance.

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Abstract

This invention discloses a monolithically integrated complementary inverter for GaN HEMT and its fabrication method, relating to the field of semiconductor technology. The inverter includes an n-channel and a p-channel enhancement-mode GaN HEMT, both laterally distributed on a common epitaxial layer of the same substrate. A two-dimensional dielectric layer, a graphene layer, and an isolation dielectric layer are sequentially disposed above the epitaxial layer. The source and drain electrodes of the p-channel device are located in grooves after etching the isolation dielectric layer and the graphene layer, with the gate groove etched into the P-GaN layer. The source and drain electrodes of the n-channel device are located in grooves etched from the epitaxial layer to the bottom of the barrier layer, with the gate electrode located above the unetched P-GaN layer. Isolation between devices is achieved through isolation trenches extending into the buffer layer. By introducing a two-dimensional dielectric layer and a graphene layer, this invention induces a two-dimensional hole gas at the P-GaN interface, significantly increasing the hole carrier concentration, solving the performance bottleneck of p-channel devices, and realizing high-speed, low-power monolithically integrated complementary logic.
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