A GaN HEMT monolithic integrated complementary inverter and a device manufacturing method thereof

Abstract

This invention discloses a monolithically integrated complementary inverter for GaN HEMT and its fabrication method, relating to the field of semiconductor technology. The inverter includes an n-channel and a p-channel enhancement-mode GaN HEMT, both laterally distributed on a common epitaxial layer of the same substrate. A two-dimensional dielectric layer, a graphene layer, and an isolation dielectric layer are sequentially disposed above the epitaxial layer. The source and drain electrodes of the p-channel device are located in grooves after etching the isolation dielectric layer and the graphene layer, with the gate groove etched into the P-GaN layer. The source and drain electrodes of the n-channel device are located in grooves etched from the epitaxial layer to the bottom of the barrier layer, with the gate electrode located above the unetched P-GaN layer. Isolation between devices is achieved through isolation trenches extending into the buffer layer. By introducing a two-dimensional dielectric layer and a graphene layer, this invention induces a two-dimensional hole gas at the P-GaN interface, significantly increasing the hole carrier concentration, solving the performance bottleneck of p-channel devices, and realizing high-speed, low-power monolithically integrated complementary logic.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a GaN HEMT monolithically integrated complementary inverter and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a wide-bandgap (3.4 eV) semiconductor material, possesses an extremely high critical electric field (≈3 MV / cm) and excellent thermal conductivity (≈130 W / m·K). High electron mobility transistors (HEMTs) based on GaN utilize the strong polarization effect of the AlGaN / GaN heterojunction to form a two-dimensional electron gas (2DEG). Its high electron mobility (up to 1500 cm² / V·s) enables HEMT devices to achieve low on-resistance, fast switching, and reliable power conversion under high voltage, high frequency, and high temperature environments, and it has been widely used in RF power amplifiers, DC-DC converters, and power management chips. However, current driving circuits for GaN HEMT switches are typically based on Si-based MOSFET devices, whose slow response speed and large chip area contradict the advantages of GaN HEMT devices. Therefore, researchers are attempting to construct transistors using GaN HEMT devices as driving circuits, making GaN HEMT-based inverters a key focus for driving circuit architectures. Complementary inverters (CMOS-style inverters) retain the zero static power consumption of CMOS while also possessing the high breakdown voltage and high-speed switching advantages of GaN. They can achieve a wide operating voltage range (5V-200V) and sub-nanosecond rise / fall times, making them particularly suitable for digital control of power modules and bias circuits in RF front-ends. However, the low hole carrier concentration in p-channel enhancement-mode GaN HEMTs remains a bottleneck restricting the performance of complementary devices. This results in a much higher on-resistance (Ron) for p-channel devices compared to n-channel devices, leading to insufficient pull-up current and consequently, problems such as slow rise time, reduced noise margin, and insufficient saturation of the output high level.

[0003] To increase the hole concentration in P-GaN, various approaches have been proposed, such as introducing a high-Al content AlGaN barrier layer to enhance the polarization electric field and thus improve hole injection, and activating holes by depassivating Mg-doped GaN layers with hydrogen to increase hole concentration. While these methods have achieved some progress in the laboratory, they still face common problems such as large lattice mismatch in the insertion layer, low carrier concentration, threshold instability, and insufficient high-temperature reliability. This makes it difficult to achieve pull-up current matching with n-channel GaN HEMTs in practical power cascade chips. Therefore, it is necessary to find other methods to increase the hole concentration in P-GaN layers to achieve truly symmetrical, low-power GaN complementary inverters. Since p-type two-dimensional material graphene has a suitable work function relative to GaN, and due to the different band structures of the two materials, charge transfer occurs at the contact interface, inducing a hole accumulation layer (i.e., 2DHG) on the nitride surface. This method does not rely on lattice matching, avoiding defects caused by lattice mismatch. However, due to the mismatch between the carbon lattice of graphene and the lattice of GaN, the interface quality is poor. Therefore, improving the interface quality between graphene and GaN is of practical significance for the application of two-dimensional graphene materials in complementary GaN inverters. Summary of the Invention

[0004] The present invention provides a GaN HEMT monolithically integrated complementary inverter and its fabrication method, which can solve the above-mentioned problems.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a GaN HEMT monolithically integrated complementary inverter, comprising an n-channel enhancement-mode GaN HEMT and a p-channel enhancement-mode GaN HEMT; wherein the n-channel enhancement-mode GaN HEMT and the p-channel enhancement-mode GaN HEMT are fabricated on the same substrate and distributed along the lateral direction of the substrate;

[0007] An epitaxial layer shared by the n-channel enhancement-type GaN HEMT and the p-channel enhancement-type GaN HEMT is disposed above one side of the substrate. The epitaxial layer consists of a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-GaN layer from bottom to top. A two-dimensional dielectric layer and a graphene layer are disposed above the epitaxial layer. An isolation dielectric layer is disposed above the graphene layer.

[0008] The source and drain ohmic metals of the p-channel enhancement-type GaN HEMT are disposed in the groove formed after partial etching of the isolation dielectric layer and the graphene layer.

[0009] The p-channel enhancement-mode GaN HEMT has a gate groove etched into the P-GaN layer between its source and drain; a dense dielectric layer is disposed within the gate groove, and a p-channel gate electrode is disposed above the dense dielectric layer.

[0010] The source and drain ohmic metals of the n-channel enhancement GaN HEMT are disposed in the grooves formed by etching the epitaxial layer to the barrier layer; a dense dielectric layer is disposed above the unetched P-GaN layer region between the source and drain of the n-channel enhancement GaN HEMT, and an n-channel gate electrode is disposed above the dense dielectric layer.

[0011] An isolation trench extending into the buffer layer is provided between the n-channel enhancement-mode GaN HEMT and the p-channel enhancement-mode GaN HEMT; the wafer region with the isolation trench is a passive region, and the wafer regions with the n-channel enhancement-mode GaN HEMT and the p-channel enhancement-mode GaN HEMT are active regions. The passive region surrounds the active region to form electrical isolation between the devices in the epitaxial layer.

[0012] Furthermore, the nucleation layer is an AlN material; the buffer layer is a high-resistivity GaN material; the channel layer is an intrinsically GaN material that is not intentionally doped; the barrier layer is an AlxGa(1-x)N material with gradually decreasing Al composition, wherein 0.25≤x≤0.75; and the P-GaN layer is a Mg-doped P-type GaN material.

[0013] Furthermore, the two-dimensional dielectric layer is a hexagonal boron nitride (h-BN) material with a thickness ranging from 2 to 5 nm; the graphene layer is a single-layer or multi-layer structure; and the insulating dielectric layer is an AlN material with a thickness ranging from 2 to 10 nm.

[0014] Furthermore, the source and drain ohmic metals of the p-channel enhancement-type GaN HEMT adopt one or more metal stacking structures selected from Ni, Pt, and Pd metals; the source and drain ohmic metals of the n-channel enhancement-type GaN HEMT adopt one or more metal stacking structures selected from Ti, Al, Ni, Pt, Pd, and W metals.

[0015] Furthermore, the dense dielectric layer is made of Al2O3 or HfO2 material; the p-channel gate electrode and the n-channel gate electrode adopt a stacked structure of one or more metals selected from Ni, Pt, Pd, and W.

[0016] Furthermore, a passivation layer of SiO2 or Si3N4 material is disposed above the active and passive regions of the wafer; by etching the passivation layer above the electrodes of the n-channel enhancement GaN HEMT and p-channel enhancement GaN HEMT, the metal electrodes are exposed, and a metal interconnect layer is obtained by metal deposition process; the metal interconnect layer is Al or Cu metal, and electrical connections between devices are formed by leading out the metal electrodes and in accordance with the circuit connection sequence.

[0017] Furthermore, the device-to-device electrical connections formed by the metal interconnects include: the source of the p-channel enhancement-mode GaN HEMT is connected to the power supply voltage VDD; the gate electrode of the p-channel enhancement-mode GaN HEMT is connected to the gate electrode of the n-channel enhancement-mode GaNHEMT and serves as the input voltage VIN terminal; the drain of the p-channel enhancement-mode GaN HEMT is connected to the drain of the n-channel enhancement-mode GaN HEMT and serves as the output voltage VOUT terminal; and the source of the n-channel enhancement-mode GaN HEMT is connected to the ground electrode GND.

[0018] In a second aspect, the present invention provides a method for fabricating the GaN HEMT monolithically integrated complementary inverter described in the first aspect, comprising:

[0019] A substrate is provided, and a core layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer are sequentially grown on the substrate to complete the epitaxial layer growth;

[0020] Choose a substrate, and grow a graphene layer and a two-dimensional dielectric layer on the substrate;

[0021] The substrate on which the graphene layer and the two-dimensional dielectric layer have been grown is flipped over so that the two-dimensional dielectric layer is bonded to the P-GaN layer of the epitaxial layer, and the substrate is peeled off, thereby successfully transferring the graphene layer and the two-dimensional dielectric layer above the P-GaN layer.

[0022] An isolation dielectric layer is grown on top of the graphene layer;

[0023] The isolation dielectric layer and graphene layer are selectively etched to deposit the source and drain metals of the p-channel enhancement-mode GaNHEMT in the etched grooves;

[0024] Selectively etch the epitaxial layer to the buffer layer to form an isolation trench, and etch the P-GaN layer and part of the barrier layer in the n-channel enhancement GaN HEMT region to deposit the source and drain metals of the n-channel enhancement GaN HEMT;

[0025] Selectively etch the epitaxial layer of the gate region of a p-channel enhancement-type GaN HEMT into the P-GaN layer to form a gate trench;

[0026] A dense dielectric layer is deposited on the side of the epitaxial layer away from the substrate, and a metal gate is fabricated in the gate trench of the p-channel enhancement GaN HEMT and above the unetched P-GaN layer of the n-channel enhancement GaN HEMT.

[0027] A passivation layer is deposited, contact holes are etched, and an interconnect metal layer is deposited to complete device fabrication.

[0028] Furthermore, the method for flipping and bonding a substrate with a graphene layer and a two-dimensional dielectric layer includes: placing the substrate in a bonding machine, applying a certain temperature and pressure to align and bond the two-dimensional dielectric layer with the P-GaN layer, using chemical etching or laser exfoliation to separate the substrate from the graphene layer, and optimizing the bonding interface through low-temperature annealing.

[0029] Furthermore, before growing the isolation medium layer, the epitaxial wafer is subjected to oxygen plasma treatment to activate the graphene layer surface; the growth of the isolation medium layer includes: transferring the epitaxial wafer into an atomic layer deposition (ALD) device to grow AlN material as the isolation medium layer.

[0030] Furthermore, after depositing the source and drain metals of the p-channel enhanced GaN HEMT and the n-channel enhanced GaN HEMT, ohmic contacts are achieved through low-temperature rapid annealing; the dense dielectric layer is prepared by atomic layer deposition; and the passivation layer is surface planarized by chemical mechanical polishing.

[0031] Compared with the prior art, the beneficial effects of the present invention are:

[0032] (1) The inverter designed in this invention adopts monolithically integrated n-channel enhancement-mode and p-channel enhancement-mode GaN HEMT, which has a higher signal switching speed than CMOS inverter. A two-dimensional dielectric layer and a graphene layer are prepared on the P-GaN layer through a one-time transfer method, which passivates the interface defects of the P-GaN layer. In addition, the graphene layer in the p-channel enhancement-mode GaN HEMT forms a polarized dipole layer above the P-GaN layer, which cancels the spontaneous polarization field inside the P-GaN layer, thereby reducing the potential barrier, enhancing hole injection and increasing the hole carrier concentration. This greatly improves the problem of inconsistent current levels and switching speeds between p-channel and n-channel devices caused by insufficient hole concentration inside the P-GaN layer.

[0033] (2) The high conductivity of graphene forms a low-impedance current diffusion layer between the electrodes, which reduces the ohmic contact resistance of the source and drain of the p-channel enhancement GaN HEMT and the gate leakage current of the n-channel enhancement GaN HEMT. In addition, the high thermal conductivity of the graphene layer is beneficial to the heat dissipation of the device when it is operating at high power, and slows down the degradation of device performance such as metal contact failure caused by the rise in device surface temperature.

[0034] (3) The two-dimensional dielectric layer and the graphene layer are prepared on the same substrate, forming a high-quality van der Waals heterojunction with a lower interface defect density than that of the secondary transfer. The lattice constants of the two-dimensional dielectric layer and the P-GaN layer are relatively similar, which can form an atomically flat surface without dangling bonds on the surface of the P-GaN layer. The bonding quality is high and will not significantly affect the crystal quality and hole mobility of the P-GaN layer. As an insulating layer between the P-GaN layer and the graphene, it can provide extremely low tunneling leakage current while maintaining an extremely thin thickness, which can significantly suppress gate leakage current.

[0035] (4) The isolation medium layer above the graphene layer is an AlN hexagonal crystal structure, which matches the graphene regular hexagonal two-dimensional structure, thus forming a high-density AlN isolation layer, which can better isolate the graphene layer from the outside air and improve the stability of device performance.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the cross-sectional structure of a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0039] Figure 2 This is a process flow diagram of the fabrication process of a GaN HEMT monolithic integrated complementary inverter provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the epitaxial layer fabrication of a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0041] Figure 4This is a schematic diagram of graphene fabrication for a GaN HEMT monolithic integrated complementary inverter provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the epitaxial layer and graphene bonding of a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the epitaxial structure of the isolation dielectric layer of a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the source and drain electrode fabrication of a p-channel enhancement-type GaN HEMT, which is a monolithically integrated complementary inverter provided in this embodiment of the invention.

[0045] Figure 8 This is a schematic diagram illustrating the fabrication of an isolation trench for a GaN HEMT monolithically integrated complementary inverter according to an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of the source and drain electrode fabrication of an n-channel enhancement-type GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of the gate recess fabrication of a p-channel enhancement-type GaN HEMT with a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram illustrating the fabrication of a dense dielectric layer in a GaN HEMT monolithically integrated complementary inverter according to an embodiment of the present invention.

[0049] Figure 12 This is a schematic diagram of the gate electrode fabrication of a p-channel and n-channel enhancement-type GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0050] Figure 13 This is a schematic diagram of the metal interconnect layer fabrication of a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention;

[0051] Figure 14 This is a circuit diagram of a GaN HEMT monolithically integrated complementary inverter provided in an embodiment of the present invention.

[0052] Explanation of reference numerals in the attached figures:

[0053] 100 - Monolithic GaN HEMT Complementary Inverter, 101 - Substrate, 102 - Nucleation Layer, 103 - Buffer Layer, 104 - Channel Layer, 105 - Barrier Layer, 106 - P-GaN Layer, 201 - Substrate, 202 - Graphene Layer, 203 - Two-Dimensional Dielectric Layer, 107 - Isolation Dielectric Layer, 108 - P-Channel Enhancement GaN HEMT Source, 109 - P-Channel Enhancement GaN HEMT Drain, 110 - N-Channel Enhancement GaN HEMT Two-Dimensional Electron Gas, 111 - Isolation Trench, 112 - N-Channel Enhancement GaN HEMT Source, 113 - N-Channel Enhancement GaNHEMT Drain, 114 - P-Channel Enhancement GaN HEMT Gate Trench, 115 - Dense Dielectric Layer, 116 - P-Channel Enhancement GaNHEMT Gate Electrode, 117 - N-Channel Enhancement GaN HEMT gate electrode, 118-passivation layer, 119-first metal interconnect, 120-second metal interconnect, 121-third metal interconnect, 122-fourth metal interconnect, 1-GaN HEMT monolithic integrated complementary inverter epitaxial layer, 2-graphene fabrication structure layer, Mp-p channel enhancement GaN HEMT, Mn-n channel enhancement GaN HEMT, 3-metal interconnect layer. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0055] To address the problems of slow switching speed and large chip area in existing CMOS inverters, and insufficient hole carrier concentration in p-type GaNHEMTs in GaN inverters, this invention proposes using a two-dimensional dielectric layer and a graphene layer to improve the surface defect state density and gate leakage of the P-GaN layer, and inducing two-dimensional hole gas at the interface, thereby increasing the carrier concentration and improving the carrier transport channel. To this end, an embodiment of this invention provides a GaN HEMT monolithically integrated complementary inverter 100, see [link to relevant documentation]. Figure 1 The diagram shows a cross-sectional view of an inverter 100 provided in an embodiment of the present invention. The device 100 includes a p-channel enhancement-mode GaN HEMT Mp and an n-channel enhancement-mode GaN HEMT Mn, as well as a metal interconnect layer 3.

[0056] In this embodiment of the invention, devices Mp and Mn share a common substrate 101 and epitaxial layer 1. The substrate 101 can be silicon, sapphire, silicon carbide, gallium nitride, gallium oxide, diamond, etc., with a thickness of 300 μm to 800 μm. The epitaxial layer 1 is fabricated along a lateral extension direction on one side of the substrate, and from bottom to top consists of a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, and a P-GaN layer 106. The nucleation layer 102 is made of AlN material with a thickness ranging from 10 to 50 nm; the buffer layer 103 is intentionally doped high-resistivity GaN material with a thickness ranging from 300 to 1000 nm; the channel layer 104 is unintentionally doped intrinsic GaN material with a thickness ranging from 100 to 300 nm; and the barrier layer 105 is made of Al with gradually decreasing Al content. x Ga (1-x) The material is N (0.25≤x≤0.75) with a thickness ranging from 15 to 30 nm. The P-GaN layer 106 is a P-type GaN layer with a high concentration of Mg ions doped with a thickness ranging from 50 to 100 nm.

[0057] In this embodiment of the invention, the graphene layer 202 is prepared on the transfer substrate 201; wherein the substrate 201 can be a flexible material such as copper foil or platinum foil, or a composite substrate in which a flexible material is attached to a rigid material substrate such as sapphire or silicon; wherein the graphene layer 202 is a single layer or multiple layers of graphene, preferably a single layer of graphene; the two-dimensional dielectric layer 203 is prepared on the graphene layer 202, and is a hexagonal boron nitride (h-BN) material with a thickness ranging from 2 to 5 nm.

[0058] In this embodiment of the invention, a two-dimensional dielectric layer 203 and a graphene layer 202 are transferred on a P-GaN layer 106 by a thin film transfer bonding method, wherein the P-GaN layer 106 is in contact with the two-dimensional dielectric layer 203, and the graphene layer 202 is prepared on top of the epitaxial layer 1.

[0059] In this embodiment of the invention, an AlN isolation medium layer 107 with a thickness ranging from 2 to 10 nm is disposed on the bonded graphene layer 202.

[0060] In this embodiment of the invention, the source 108 and drain 109 of the device Mp are disposed in a groove in which an isolation dielectric layer 107 and a portion of a graphene layer 202 are etched. They adopt a stacked structure of one or more metals such as Ni / Pt / Pd, with a thickness ranging from 100 to 300 nm. After low-temperature rapid annealing, they form ohmic contacts with the graphene layer 202 and the two-dimensional dielectric layer 203 at the bottom of the groove.

[0061] In this embodiment of the invention, the P-GaN layer 106 outside the Mn gate electrode 117 region of the device is removed by selective etching. The channel depletion effect of the P-GaN layer 106 in the device Mn disappears, and a two-dimensional electron gas (2DEG) 110 with high electron mobility is generated at the top interface on one side of the channel layer 104 due to the polarization effect of the barrier layer 105 and the channel layer 104.

[0062] In this embodiment of the invention, the epitaxial layer 1 of the wafer region outside the device Mp and device Mn regions achieves electrical isolation by selectively etching grooves to the buffer layer 103. The etched groove region is called the isolation groove 111, which is used to block the electrical connection between different inverters 100 distributed in the lateral expansion direction of the wafer and between devices Mp and devices Mp.

[0063] In this embodiment of the invention, the source 112 and drain 113 of the device Mn are disposed in the groove where part of the barrier layer 105 has been etched, and adopt one or more metal stacking structures such as Ti / Al / Ni / Pt / Pd / W, with a thickness ranging from 100 to 300 nm, and form an ohmic contact with the top of the channel layer 104 after low-temperature rapid annealing.

[0064] In this embodiment of the invention, a portion of the epitaxial layer between the source 108 and the drain 109 of the device Mp is selectively etched to the P-GaN layer 106 to obtain the gate recess 114 of the device Mp.

[0065] In this embodiment of the invention, a dense dielectric layer 115 is grown on the wafer surface with the etched gate groove 114. The dielectric layer is a high-k dielectric material, such as Al2O3 or HfO2, with a thickness ranging from 2 to 10 nm.

[0066] In this embodiment of the invention, gate electrodes 116 and 117 are respectively fabricated above the gate recess 114 of device Mp covered by dense dielectric layer 115 and above the unetched P-GaN layer 106 of device Mn. The gate electrodes adopt one or more metal stacking structures of metals such as Ni / Pt / Pd / W, with a thickness range of 50~200nm.

[0067] In this embodiment of the invention, after the gate electrodes 116 and 117 are fabricated, a passivation layer 118 is deposited on the wafer surface facing away from the substrate. The passivation layer 118 is made of SiO2 or Si3N4 material and has a thickness ranging from 500 to 1000 nm. The deposited passivation layer 118 is planarized by chemical mechanical polishing (CMP).

[0068] In this embodiment of the invention, the electrode portions of devices Mp and Mn are exposed by etching the passivation layer 118 and the dense dielectric layer 115 above the electrodes of devices Mp and Mn. Electrodes are led out by depositing a metal interconnect layer 3 in the openings using metal deposition or sputtering processes. The source 108 of device Mp is connected to the power supply voltage VDD of the external circuit via a first metal interconnect 119. The gate electrode 116 of device Mp and the gate electrode 117 of device Mn are connected via a second metal interconnect 120 and connected to the input voltage VIN of the external circuit. The drain 109 of device Mp and the drain 112 of device Mn are connected via a third metal interconnect 121 and connected to the output voltage VOUT of the external circuit. The source 113 of device Mn is connected to the ground electrode GND of the external circuit via a fourth metal interconnect 122. The metal interconnect layer 3 is made of Al or Cu metal material.

[0069] This invention also provides a method for fabricating a GaN HEMT monolithically integrated complementary inverter 100, such as... Figure 2 The diagram shown is a flowchart of the fabrication process for inverter 100. The specific fabrication process is as follows: Figures 3 to 13 As shown, the specific steps include the following:

[0070] Step S11, as follows Figure 3 As shown, substrate 101 is selected. Substrate 101 can be any of the following substrates: silicon, sapphire, silicon carbide, gallium nitride, gallium oxide, diamond, etc. In this embodiment, silicon is selected as substrate 101. After organic and inorganic cleaning, substrate 101 is placed in the MOCVD chamber, and an AlN nucleation layer 102 with a thickness of 20 nm, a high-resistivity GaN buffer layer 103 with a thickness of 800 nm, an unintentionally doped intrinsic GaN channel layer 104 with a thickness of 150 nm, and an Al layer with a thickness of 30 nm and a gradually decreasing Al composition are grown sequentially. x Ga (1-x) An N (0.25≤x≤0.75) barrier layer 105 and a Mg-ion heavily doped P-GaN layer 106 with a thickness of 70 nm are used to obtain the epitaxial layer 1 of the inverter 100.

[0071] Step S12, as follows Figure 4As shown, the substrate 201 can be a flexible material such as copper foil or platinum foil, or a composite substrate of a flexible material attached to a rigid material substrate such as sapphire or silicon. In this embodiment, a method of hot-pressing and bonding copper foil onto a sapphire substrate is used to provide a rigid support substrate for the subsequent transfer process. The sapphire substrate 201 with bonded copper foil is transferred to the MOCVD chamber, the temperature is raised to 1000 ℃, and a carbon-containing precursor CH4 is introduced to grow a graphene layer 202 on the surface of the copper foil. Subsequently, a boron and nitrogen-containing precursor borane ammonia NH3BH3 is introduced to directly grow a two-dimensional dielectric layer 203 (hexagonal boron nitride h-BN) on the graphene layer 202, finally obtaining the graphene preparation structure layer 2. The graphene layer 202 is a single layer of graphene, and the thickness of the two-dimensional dielectric layer 203 is 3 nm.

[0072] Step S13, as follows Figure 5 As shown, the graphene-prepared structural layer 2 is flipped onto the epitaxial layer 1 of the inverter 100 and transferred to a bonding machine, so that the two-dimensional dielectric layer 203 comes into contact with the P-GaN layer 106 on top of the epitaxial layer 1. Slight pressure and temperature are applied, and the two-dimensional dielectric layer 203 forms a perfect bonding effect with the P-GaN layer 106 under the action of van der Waals forces. The substrate 201 above the graphene layer 202 is removed by laser exfoliation, completing the transfer process of the two-dimensional dielectric layer 203 and the graphene layer 202.

[0073] Step S14, as follows Figure 6 As shown, the wafers are cleaned by organic and inorganic processes to remove surface contaminants during the transfer process. The cleaned wafers are then transferred to the ALD. First, low-power oxygen plasma is used to activate the surface of the graphene layer 202, generating various oxygen functional groups on the surface of the graphene layer 202. This provides a large number of polar bond sites for the subsequent growth of the AlN isolation dielectric layer 107, increasing the nucleon density of the AlN material on the graphene layer 202, thereby forming a dense and defect-free high-quality AlN isolation dielectric layer 107. After the oxygen plasma treatment, at a low temperature of 250 °C, Al source TMAl and nitrogen source NH3 are introduced into the ALD cavity using an alternating pulse method. By controlling the number of pulse cycles, the atomic-level thickness of the AlN layer is controlled, ultimately obtaining an AlN isolation dielectric layer 107 with a thickness of 5 nm that is in perfect contact with the graphene layer 202.

[0074] Step S15, as follows Figure 7As shown, photolithography is used to coat, expose, and develop the wafer surface, forming a mask in the Mp source / drain area, the Mn channel area, and the isolation trench 111 area. Inductively coupled plasma etching (ICP) is used to etch the isolation dielectric layer 107 in the mask area, exposing the graphene layer 202. The etched wafer is then immersed in a solution of dilute HCl (15%) and ultrapure water diluted at a 1:10 ratio to remove etching residues. The wafer surface is then cleaned with low-power plasma to passivate etching defects. Photolithography is then used again to coat, expose, and develop the wafer surface, forming a mask in the middle area of ​​the etched isolation dielectric layer 107 at the Mp source / drain, the Mn channel area, and the area of ​​the etched isolation dielectric layer 107 in the isolation trench 111. The graphene layer 202 in the mask area is etched using an inductively coupled plasma etching (ICP) device to expose the bottom two-dimensional dielectric layer 203. The etched wafer is then immersed in the dilute HCl solution and the wafer surface is cleaned with low-power oxygen plasma. Finally, the wafer surface is coated, exposed, and developed using photolithography to form a mask for the source and drain trenches etched on the device Mp. Ni / Pd (thickness of 50 / 100nm) metal stack structure is deposited in the trenches using electron beam evaporation (E-beam) process. After metal stripping, the metal is rapidly annealed at 500℃ in a nitrogen atmosphere for 2 minutes to achieve ohmic contact between the metal and the graphene layer 202 and the two-dimensional dielectric layer 203 at the bottom of the trench, resulting in the source 108 and drain 109 of the device Mp.

[0075] Step S16, as follows Figure 8 As shown, photolithography is used to perform spin coating, exposure, and development on the surface of the wafer. A mask is formed in the area where the graphene layer 202 is etched in the Mn channel of the device and the isolation trench 111. ICP etching is used to selectively etch to the top of the barrier layer 105. The etching residue is cleaned with dilute HCl solution and oxygen plasma from step S15. The photolithography process is used again to perform spin coating, exposure, and development on the surface of the wafer. A mask is formed in the area where the barrier layer 105 is etched in the isolation trench 111. ICP etching is used to selectively etch to the buffer layer 103 to obtain the isolation trench 111. This achieves electrical isolation on the epitaxial layer between the inverters 100 arranged in the lateral direction of the wafer and between the devices Mp and Mn.

[0076] Step S17, as follows Figure 9As shown, photolithography is used to perform photoresist homogenization, exposure, and development on the surface of the wafer to form a mask for the barrier layer 105 of the Mn source and drain region of the device. The barrier layer 105 of the mask region is etched to its bottom using ICP. The etching residue is cleaned with dilute HCl solution in step S15. Then, the wafer with the mask photoresist is transferred to the E-beam cavity. A Ti / Al / Ni / Pt metal stack structure (thickness of 20 / 130 / 50 / 100nm) is prepared using metal evaporation. After metal lift-off, it is rapidly annealed at 650 °C in a nitrogen atmosphere for 60s to achieve ohmic contact between the metal and the bottom of the barrier layer 105, resulting in the source 112 and drain 113 of the Mn device.

[0077] Step S18, as follows Figure 10 As shown, photolithography is used to perform photoresist coating, exposure, and development on the surface of the wafer to form a mask for a portion of the isolation dielectric layer 107 between the source 108 and drain 109 of device Mp. The isolation dielectric layer 107, graphene layer 202, two-dimensional dielectric layer 203, and a portion of P-GaN layer 106 in the mask area are etched by ICP. The etching residue is cleaned using dilute HCl solution and oxygen plasma in step S15 to obtain the gate groove 114 of device Mp.

[0078] Step S19, as Figure 11 As shown, the wafer is placed in the ALD cavity, and trimethylaluminum (TMA) and water (H2O) are pulsed through it at 300 °C. By controlling the number of pulse cycles, a high-quality, dense Al2O3 layer of 10 nm is grown as a dense dielectric layer 115.

[0079] Step S20, as follows Figure 12 As shown, photolithography is used to perform photoresist homogenization, exposure, and development on the surface of the wafer. A mask is formed on the gate groove 114 of device Mp and the dense dielectric layer 115 of the unetched P-GaN layer 106 of device Mn. The wafer with the mask photoresist is transferred to the E-beam cavity. A Ni / Pt (thickness of 50 / 100nm) metal stacked structure is prepared by metal evaporation. After metal lift-off, the gate electrode 116 of device Mp and the gate electrode 117 of device Mn are obtained.

[0080] Step S21, as follows Figure 13As shown, a Si3N4 passivation layer 118 with a thickness of 800 nm is deposited on the wafer surface away from the substrate using plasma-enhanced chemical deposition (PECVD). Surface planarization is then performed using chemical mechanical polishing (CMP) to obtain a smooth Si3N4 passivation layer 118. Photolithography is then used to perform photoresist homogenization, exposure, and development on the surface of the passivation layer 118, forming a mask for the electrodes of devices Mp and Mn. ICP etching is then used to etch the passivation layer 118 in the masked area and the dense dielectric layer 115 on some electrodes, exposing the metal electrodes. Residual etching is then cleaned using dilute HCl solution and oxygen plasma as described in step S15. The wafer with the mask photoresist is then transferred to the cavity of a magnetron sputtering equipment for sputtering. Metal Cu with a density of 1000 nm is used to obtain a metal interconnect layer 3 through a metal stripping process. The source 108 of device Mp is led out through the first metal interconnect line 119 to be connected to the power supply voltage VDD of the external circuit. The gate electrode 116 of device Mp and the gate electrode 117 of device Mn are connected through the second metal interconnect line 120 and led out to be connected to the input voltage VIN of the external circuit. The drain 109 of device Mp and the drain 112 of device Mn are connected through the third metal interconnect line 121 and led out to be connected to the output voltage VOUT of the external circuit. The source 113 of device Mn is led out through the fourth metal interconnect line 122 to be connected to the ground electrode GND of the external circuit, thereby completing the fabrication of inverter 100.

[0081] like Figure 14 The diagram shows a circuit schematic of a GaN HEMT monolithically integrated complementary inverter 100 provided in this embodiment. Device Mp is a p-channel enhancement-mode GaN HEMT, and device Mn is an n-channel enhancement-mode GaN HEMT. The source Sp of device Mp is connected to the external power supply voltage VDD. The gate electrodes Gp and Gn of devices Mp and Mn are interconnected and connected to the external gate drive voltage VIN. The drain electrodes Dp and Dn of devices Mp and Mn are interconnected and connected to the external output voltage VOUT. The source Sn of device Mn is connected to the ground electrode GND. When the input voltage VIN is low (0V), device Mp is turned on, device Mn is turned off, and the output voltage VOUT is pulled high to VDD, i.e., the output is high. When the input voltage VIN is high (VDD), device Mp is turned off, device Mn is turned on, and the output voltage VOUT is pulled low to the ground voltage GND, i.e., the output is low. Based on the above analysis, this complementary inverter has only one device conducting in any steady state, so the static power consumption is almost zero. It can also achieve a full swing output from ground voltage 0V to power supply voltage VDD, and can be applied in high-end application fields such as RF modulation circuits, automotive power module protection logic, and aerospace reconfigurable mixed-signal chips.

[0082] In summary, the GaN HEMT monolithically integrated complementary inverter 100 fabricated in this embodiment achieves high-quality two-dimensional material growth by simultaneously growing a graphene layer 202 and a two-dimensional dielectric layer 203 on the intermediate substrate 201. A single-bonding method mitigates the numerous interface defects caused by multiple bonding processes. Furthermore, the low lattice constant difference between the two-dimensional dielectric layer 203 and the P-GaN layer 106 minimizes interface problems caused by thin-film transfer, thus improving leakage current performance. The graphene layer 202 increases the hole carrier concentration above the P-GaN layer 106 and enhances hole injection capability, improving the low hole carrier concentration problem in the P-GaN layer 106. This solves the problem of inconsistent pull-up current levels and switching speeds between devices Mp and Mn due to excessively large differences in carrier concentration. This provides practical reference value for further improving the performance of GaN HEMTs in complementary inverters.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A GaN HEMT monolithically integrated complementary inverter, characterized in that, It includes n-channel enhancement-mode GaN HEMT and p-channel enhancement-mode GaN HEMT; the n-channel enhancement-mode GaN HEMT and p-channel enhancement-mode GaN HEMT are fabricated on the same substrate and distributed along the lateral direction of the substrate; An epitaxial layer shared by the n-channel enhancement-type GaN HEMT and the p-channel enhancement-type GaN HEMT is disposed above one side of the substrate. The epitaxial layer consists of a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-GaN layer from bottom to top. A two-dimensional dielectric layer and a graphene layer are disposed above the epitaxial layer. An isolation dielectric layer is disposed above the graphene layer. The source and drain ohmic metals of the p-channel enhancement-type GaN HEMT are disposed in the groove formed after partial etching of the isolation dielectric layer and the graphene layer. The p-channel enhancement-mode GaN HEMT has a gate groove etched into the P-GaN layer between its source and drain; a dense dielectric layer is disposed within the gate groove, and a p-channel gate electrode is disposed above the dense dielectric layer. The source and drain ohmic metals of the n-channel enhancement-mode GaN HEMT are disposed in grooves formed by etching the epitaxial layer to the bottom of the barrier layer; a dense dielectric layer is disposed above the unetched P-GaN layer region between the source and drain of the n-channel enhancement-mode GaN HEMT, and an n-channel gate electrode is disposed above the dense dielectric layer; the graphene layer of the n-channel enhancement-mode GaN HEMT is etched into the gate region of the n-channel enhancement-mode GaN HEMT; the P-GaN layer outside the gate electrode region of the n-channel enhancement-mode GaN HEMT is removed by selective etching, and the channel depletion effect of the P-GaN layer in the n-channel enhancement-mode GaN HEMT disappears; due to the polarization effect, a two-dimensional electron gas with high electron mobility is generated at the top interface on one side of the channel layer between the barrier layer and the channel layer. An isolation trench extending into the buffer layer is provided between the n-channel enhancement-mode GaN HEMT and the p-channel enhancement-mode GaN HEMT; the wafer region with the isolation trench is a passive region, and the wafer regions with the n-channel enhancement-mode GaN HEMT and the p-channel enhancement-mode GaN HEMT are active regions. The passive region surrounds the active region to form electrical isolation between the devices in the epitaxial layer.

2. The GaN HEMT monolithically integrated complementary inverter according to claim 1, characterized in that, The nucleation layer is made of AlN material; the buffer layer is made of high-resistivity GaN material; the channel layer is made of unintentionally doped intrinsic GaN material; the barrier layer is made of AlxGa(1-x)N material with gradually decreasing Al composition, where 0.25≤x≤0.75; the P-GaN layer is made of Mg ion-doped P-type GaN material; the two-dimensional dielectric layer is made of hexagonal boron nitride (h-BN) material with a thickness ranging from 2 to 5 nm; the graphene layer is a single-layer or multi-layer structure; and the isolation dielectric layer is made of AlN material with a thickness ranging from 2 to 10 nm.

3. The GaN HEMT monolithically integrated complementary inverter according to claim 1, characterized in that, The source and drain ohmic metals of the p-channel enhancement-type GaN HEMT adopt one or more metal stacking structures selected from Ni, Pt, and Pd metals; the source and drain ohmic metals of the n-channel enhancement-type GaN HEMT adopt one or more metal stacking structures selected from Ti, Al, Ni, Pt, Pd, and W metals.

4. The GaN HEMT monolithically integrated complementary inverter according to claim 1, characterized in that, The dense dielectric layer is made of Al2O3 or HfO2 material; the p-channel gate electrode and the n-channel gate electrode adopt one or more metal stacking structures selected from Ni, Pt, Pd and W metals.

5. A GaN HEMT monolithically integrated complementary inverter according to claim 1, characterized in that, A passivation layer of SiO2 or Si3N4 material is also disposed above the active and passive regions; by etching the passivation layer above the electrodes of the n-channel enhancement-mode GaNHEMT and p-channel enhancement-mode GaN HEMT, the metal electrodes are exposed, and a metal interconnect layer is obtained by metal deposition process; the metal interconnect layer is Al or Cu metal, and electrical connections between devices are formed by leading out the metal electrodes and in accordance with the circuit connection sequence.

6. A GaN HEMT monolithically integrated complementary inverter according to claim 1, characterized in that, The source of the p-channel enhancement-mode GaN HEMT is connected to the power supply voltage VDD; the gate electrode of the p-channel enhancement-mode GaN HEMT is connected to the gate electrode of the n-channel enhancement-mode GaN HEMT and serves as the input voltage VIN terminal; the drain of the p-channel enhancement-mode GaN HEMT is connected to the drain of the n-channel enhancement-mode GaN HEMT and serves as the output voltage VOUT terminal; the source of the n-channel enhancement-mode GaN HEMT is connected to the ground electrode GND.

7. A method for fabricating a GaN HEMT monolithically integrated complementary inverter as described in any one of claims 1-6, characterized in that, include: A substrate is provided, and a core layer, a buffer layer, a channel layer, a barrier layer and a P-GaN layer are sequentially grown on the substrate to complete the epitaxial layer growth; Choose a substrate, and grow a graphene layer and a two-dimensional dielectric layer on the substrate; The substrate on which the graphene layer and the two-dimensional dielectric layer have grown is flipped over so that the two-dimensional dielectric layer is bonded to the P-GaN layer of the epitaxial layer, and the substrate is peeled off, thereby transferring the graphene layer and the two-dimensional dielectric layer above the P-GaN layer. An isolation dielectric layer is grown on top of the graphene layer; The isolation dielectric layer and graphene layer are selectively etched to deposit the source and drain metals of the p-channel enhancement GaN HEMT in the etched grooves; Selectively etch the epitaxial layer to the buffer layer to form an isolation trench, and etch the P-GaN layer and part of the barrier layer in the n-channel enhancement GaN HEMT region to deposit the source and drain metals of the n-channel enhancement GaN HEMT; Selectively etch the epitaxial layer of the gate region of a p-channel enhancement-type GaN HEMT into the P-GaN layer to form a gate trench; A dense dielectric layer is deposited on the side of the epitaxial layer away from the substrate, and a metal gate is fabricated in the gate trench of the p-channel enhancement GaN HEMT and above the unetched P-GaN layer of the n-channel enhancement GaN HEMT. A passivation layer is deposited, contact holes are etched, and an interconnect metal layer is deposited to complete device fabrication.

8. The device fabrication method according to claim 7, characterized in that, The method for flipping and bonding a substrate with a graphene layer and a two-dimensional dielectric layer includes: placing the substrate in a bonding machine, aligning and bonding the two-dimensional dielectric layer with the P-GaN layer, separating the substrate from the graphene layer by chemical etching or laser exfoliation, and optimizing the bonding interface by low-temperature annealing.

9. The device fabrication method according to claim 7, characterized in that, Before growing the isolation medium layer, the epitaxial wafer is subjected to oxygen plasma treatment to activate the surface of the graphene layer; the growth of the isolation medium layer includes: transferring the epitaxial wafer to an atomic layer deposition device and growing AlN material as the isolation medium layer.

10. The device fabrication method according to claim 7, characterized in that, After depositing the source and drain metals of the p-channel enhanced GaN HEMT and the n-channel enhanced GaN HEMT, ohmic contacts are achieved by low-temperature rapid annealing. The dense dielectric layer is prepared by atomic layer deposition. The passivation layer is surface planarized by chemical mechanical polishing.

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