Chip, layout design method thereof and electronic equipment

Abstract

The invention provides a chip, a layout design method thereof and electronic equipment, PDIOs in an electrostatic discharge protection circuit corresponding to the chip are divided into N groups, and each group of PDIOs comprises at least one PDIO; nDIOs in the electrostatic discharge protection circuit are divided into N groups, and each group of NDIOs comprises at least one NDIO; and arranging the N groups of PDIOs and the N groups of NDIOs in a staggered manner. And through staggered arrangement, heating areas are sufficiently dispersed during electrostatic discharge, so that the thermal breakdown current capability of PDIO and NDIO is greatly improved, and the possibility of burnout of PDIO and NDIO is reduced.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a chip, a layout design method for the chip, and an electronic device thereof. Background Technology

[0002] Electrostatic discharge (ESD) protection circuits are essential components on the external pins of all integrated circuits, serving to prevent electrostatic breakdown and protect internal circuitry. During ESD, current flows through the P-type diode (PDIO) or N-type diode (NDIO), leading to high power consumption and heat generation. When the current exceeds the breakdown current, the PDIO or NDIO will burn out.

[0003] Improving the thermal breakdown current capability of PDIO or NDIO to reduce the possibility of burnout has become a problem of concern to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a chip, a layout design method therewith, and an electronic device to improve the aforementioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a chip layout design method, the method comprising: The PDIO in the electrostatic discharge protection circuit corresponding to the chip is divided into N groups, and each group of PDIO includes at least 1 PDIO; The NDIO in the electrostatic discharge protection circuit is divided into N groups, and each group of NDIO includes at least one NDIO. The N groups of PDIO and N groups of NDIO are arranged alternately.

[0006] Optionally, the method includes: determining the number of PDIO groups and the number of PDIOs in each PDIO group based on the electrostatic discharge protection level and the total number of PDIOs in the electrostatic discharge protection circuit; and determining the number of NDIO groups and the number of NDIOs in each NDIO group based on the electrostatic discharge protection level and the total number of NDIOs in the electrostatic discharge protection circuit.

[0007] Optionally, each PDIO group includes one PDIO, and each NDIO group includes one NDIO.

[0008] Optionally, each PDIO is provided with one P-type doped region and two N-type doped regions; each NDIO is provided with one N-type doped region and two P-type doped regions.

[0009] Secondly, embodiments of the present invention provide a chip, the chip being provided with an electrostatic discharge protection circuit, the electrostatic discharge protection circuit including N groups of PDIOs and N groups of NDIOs arranged in an alternating manner, each group of PDIOs including at least one PDIO, and each group of NDIOs including at least one NDIO.

[0010] Optionally, each PDIO is provided with one P-type doped region and two N-type doped regions; each NDIO is provided with one N-type doped region and two P-type doped regions.

[0011] Optionally, the P-type doped region of the PDIO is connected to the chip's I / O interface, the N-type doped region of the PDIO is connected to the chip's power supply, the P-type doped region of the NDIO is connected to the chip's ground, and the N-type doped region of the NDIO is connected to the chip's I / O interface.

[0012] Optionally, the electrostatic discharge protection circuit further includes an NMOS transistor and a PMOS transistor; the source of the PMOS transistor is connected to the chip power supply, the drain of the PMOS transistor and the drain of the NMOS transistor are both connected to the chip's I / O interface, and the source of the NMOS transistor is connected to the chip ground.

[0013] Thirdly, embodiments of the present invention provide an electronic device, including the aforementioned chip.

[0014] Compared to existing technologies, the chip and its layout design method and electronic device provided in this invention divide the PDIO in the electrostatic discharge protection circuit of the chip into N groups, each group including at least one PDIO; divide the NDIO in the electrostatic discharge protection circuit into N groups, each group including at least one NDIO; and arrange the N groups of PDIO and N groups of NDIO alternately. This alternating arrangement ensures that the heat-generating areas during electrostatic discharge are sufficiently dispersed, greatly improving the thermal breakdown current capability of the PDIO and NDIO and reducing the possibility of them burning out.

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the connection of the electrostatic discharge protection circuit provided in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of continuous chip layout provided in an embodiment of the present invention.

[0019] Figure 3 This is a flowchart illustrating the chip layout design method provided in an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the staggered chip layout provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] This invention provides an electrostatic discharge protection circuit, please refer to... Figure 1 , Figure 1 This is a schematic diagram of the electrostatic discharge protection circuit provided in an embodiment of the present invention. The electrostatic discharge protection circuit includes a first diode D1, a second diode D2, an NMOS transistor N0, and a PMOS transistor P0. The gates of the NMOS transistor N0 and the PMOS transistor P0 are used to connect to the preceding circuit, which will not be described in detail here.

[0026] The cathode of the first diode D1 and the source of the PMOS transistor P0 are connected to the chip power supply (VDD). The anode of the first diode D1, the cathode of the second diode D2, the drain of the PMOS transistor P0 and the drain of the NMOS transistor N0 are all connected to the chip's I / O interface. The anode of the second diode D2 and the source of the NMOS transistor N0 are connected to the chip ground (VSS).

[0027] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a continuous chip layout provided in an embodiment of the present invention. Figure 2 The example uses 3 PDIOs and 3 NDIOs, but this is not a limitation on their quantity; more or fewer PDIOs and NDIOs can also be used. Figure 2 Multiple PDIOs are continuously distributed in region A on the chip, and multiple NDIOs are continuously distributed in region B on the chip.

[0028] It should be understood that the first diode D1 uses PDIO, and the second diode D2 uses NDIO; the P-type doped region (P+, serving as the positive terminal of the first diode D1) of PDIO is connected to the chip's IO interface, the N-type doped region (N+, serving as the negative terminal of the first diode D1) of PDIO is connected to the chip's power supply (VDD), the P-type doped region (P+, serving as the positive terminal of the second diode D2) of NDIO is connected to the chip's ground (VSS), and the N-type doped region (N+, serving as the negative terminal of the second diode D2) of NDIO is connected to the chip's IO interface.

[0029] The three common discharge models for ESD are: CDM (Charged Device Model), MM (Machine Model), and HBM (Human Body Model). The following explanation will use HBM as an example.

[0030] When HBM is positive, the IO voltage of the IO interface is positive relative to each node of the chip. At this time, current flows into the chip from the IO interface, PDIO is turned on, and NDIO is not turned on. PDIO experiences a large current during the conduction process, resulting in high power consumption and self-heating. When it exceeds the breakdown current, PDIO burns out. When PDIO experiences ESD impact, region A is the center of heat generation, and the size of region A determines the breakdown current of PDIO.

[0031] When the HBM is negative, the IO voltage of the IO interface is negative relative to the nodes of the chip. At this time, current flows out of the chip from the IO interface, NDIO is turned on, and PDIO is not turned on. NDIO experiences a large current during the conduction process, resulting in high power consumption and self-heating. When it exceeds the breakdown current, NDIO burns out. When NDIO experiences ESD impact, region B is the center of heat generation, and the size of region B determines the breakdown current of NDIO.

[0032] Typically, PDIO is continuously and tightly packed in region A, and NDIO is continuously and tightly packed in region B. Since the areas of regions A and B are limited, the metal connecting the P-type doped region (P+) and the N-type doped region (N+) is relatively concentrated (due to limited area), resulting in high parasitic resistance. This leads to a large intrinsic resistance of PDIO / NDIO, which affects ESD current discharge.

[0033] To address the above problems, embodiments of the present invention provide a chip layout design method, which can be applied to, but is not limited to, chip design servers or computers. Please refer to... Figure 3 , Figure 3 This is a schematic flowchart of a chip layout design method provided in an embodiment of the present invention. The chip layout design method includes S10, S20, and S30, which are described in detail below.

[0034] S10 divides the PDIO in the electrostatic discharge protection circuit corresponding to the chip into N groups.

[0035] Each PDIO group includes at least one PDIO, and N is greater than or equal to 2.

[0036] It should be noted that the number of PDIOs in each PDIO group can be the same or different; no specific limitation is made here. A PDIO group can include 1, 2, or 3 PDIOs.

[0037] S20 divides the NDIO in the electrostatic discharge protection circuit into N groups.

[0038] Each group of NDIOs includes at least one NDIO.

[0039] It should be noted that the number of NDIOs in each NDIO group can be the same or different; no specific limitation is made here. One NDIO group can include 1 NDIO, 2 NDIOs, or 3 NDIOs.

[0040] S30, arranges N groups of PDIO and N groups of NDIO in an alternating manner.

[0041] Please refer to Figure 4 , Figure 4This is a schematic diagram of the staggered chip layout provided in an embodiment of the present invention. In this embodiment, each group of PDIOs includes one PDIO and each group of NDIOs includes one NDIO, as an example for illustration. It can be seen that between any two adjacent groups of PDIOs, there is one group of NDIOs, thus achieving the staggered layout effect.

[0042] Taking HBM as an example, analysis shows that: When the positive HBM is present, the ESD current flows through the PDIO, and the heat generation area is concentrated and dispersed in the A1, A2...AN regions. There is no current in the B1, B2...BN regions. The heat generation area is sufficiently dispersed, which greatly improves the thermal breakdown current capability of the PDIO.

[0043] When the HBM is negative, the ESD current flows through the NDIO, and the heating area is dispersed in the B1 region, B2 region...BN region. There is no current in the A1 region, A2 region...AN region. The heating area is sufficiently dispersed, which greatly improves the thermal breakdown current capability of the NDIO.

[0044] like Figure 4 As shown, each PDIO group is located in an NWELL (N-type well), and each NDIO group is located in a P-SUB (P-type substrate).

[0045] Building upon the preceding text, this embodiment of the invention also provides an optional implementation method for determining the number of PDIO groups and NDIO groups. Please refer to the following: S10, dividing the PDIO in the electrostatic discharge protection circuit corresponding to the chip into N groups, including: S101; S20, dividing the NDIO in the electrostatic discharge protection circuit into N groups, including: S201.

[0046] S101, based on the electrostatic discharge protection level and the total number of PDIOs in the electrostatic discharge protection circuit, determine the number of PDIO groups and the number of PDIOs in each PDIO group.

[0047] It should be understood that when the total number of PDIOs in the electrostatic discharge protection circuit is fixed, the higher the electrostatic discharge protection level (the greater the electrostatic discharge current), the lower the number of PDIOs in each group of PDIOs.

[0048] S201, based on the electrostatic discharge protection level and the total number of NDIOs in the electrostatic discharge protection circuit, determine the number of NDIO groups and the number of NDIOs in each NDIO group.

[0049] It should be understood that when the total number of NDIOs in the electrostatic discharge protection circuit is fixed, the higher the electrostatic discharge protection level (the greater the electrostatic discharge current), the lower the number of NDIOs in each group of NDIOs.

[0050] When the total number of NDIO and PDIO in the electrostatic discharge protection circuit is fixed, considering the preciousness of chip layout space, the higher the number of PDIOs in each PDIO group and the higher the number of NDIOs in each NDIO group, the less layout space is occupied; conversely, the lower the number of PDIOs in each PDIO group and the lower the number of NDIOs in each NDIO group, the more space is occupied. That is, the metal area of ​​the chip occupied by PDIO and NDIO is larger, the parasitic resistance is smaller, and the on-resistance of PDIO / NDIO (including intrinsic resistance and parasitic resistance) is smaller, which is conducive to the discharge of ESD current.

[0051] Similarly, under the same electrostatic discharge protection level, the total number of NDIO and PDIO required is reduced, the total occupied area is reduced, the parasitic capacitance is reduced, and the circuit operating speed is higher.

[0052] In one alternative implementation, each PDIO group includes one PDIO, and each NDIO group includes one NDIO.

[0053] In one alternative implementation, each PDIO is provided with one P-type doped region (P+) and two N-type doped regions (N+).

[0054] Each NDIO line has one N-type doped region (N+) and two P-type doped regions (P+).

[0055] In one alternative implementation, the ratio of P-type doped region (P+) to N-type doped region (N+) in each PDIO can also be 1:1 or 2:3, and the ratio of N-type doped region (N+) to P-type doped region (P+) in each NDIO can also be 1:1 or 2:3.

[0056] The electrostatic discharge current flows from P+ to N+. The P-type doped region of PDIO is connected to the chip's IO interface, the N-type doped region of PDIO is connected to the chip's power supply VDD, the P-type doped region of NDIO is connected to the chip's ground VSS, and the N-type doped region of NDIO is connected to the chip's IO interface.

[0057] This invention also provides a chip, which can be manufactured according to the chip layout design method described above. The chip is provided with an electrostatic discharge (ESD) protection circuit, which includes N groups of PDIOs and N groups of NDIOs arranged alternately on the chip. Each group of PDIOs includes at least one PDIO, and each group of NDIOs includes at least one NDIO. Please continue to refer to... Figure 4 , Figure 4 The diagram shows N sets of PDIO and N sets of NDIO arranged in an alternating pattern.

[0058] Optionally, each PDIO is provided with one P-type doped region (P+) and two N-type doped regions (N+).

[0059] Each NDIO line has one N-type doped region (N+) and two P-type doped regions (P+).

[0060] Optionally, the P-type doped region of the PDIO is connected to the chip's I / O interface, the N-type doped region of the PDIO is connected to the chip's power supply (VDD), the P-type doped region of the NDIO is connected to the chip's ground (VSS), and the N-type doped region of the NDIO is connected to the chip's I / O interface.

[0061] Optionally, the electrostatic discharge protection circuit also includes an NMOS transistor and a PMOS transistor; the source of the PMOS transistor is connected to the chip power supply (VDD), the drain of the PMOS transistor and the drain of the NMOS transistor are both connected to the chip's IO interface, and the source of the NMOS transistor is connected to the chip ground (VSS).

[0062] This invention also provides an electronic device, which includes the chip described above. The electronic device can be a mobile phone, computer, tablet, or wearable smart device, etc.

[0063] In summary, the chip and its layout design method and electronic device provided by the embodiments of the present invention divide the PDIO in the electrostatic discharge protection circuit corresponding to the chip into N groups, each group including at least one PDIO; divide the NDIO in the electrostatic discharge protection circuit into N groups, each group including at least one NDIO; and arrange the N groups of PDIO and N groups of NDIO alternately. This alternating arrangement ensures that the heat-generating areas during electrostatic discharge are sufficiently dispersed, greatly improving the thermal breakdown current capability of the PDIO and NDIO and reducing the possibility of them burning out.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0065] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method of chip layout design, characterized by, The method comprises: dividing the PDIO in the electrostatic discharge protection circuit corresponding to the chip into N groups, each group of PDIO including at least one PDIO; dividing the NDIO in the electrostatic discharge protection circuit into N groups, each group of NDIO including at least one NDIO; interleaving the N groups of PDIO and the N groups of NDIO.

2. The chip layout design method of claim 1, wherein, The method comprises: determining the number of groups of PDIO and the number of PDIO in each group of PDIO according to the electrostatic discharge protection level and the total number of PDIO in the electrostatic discharge protection circuit; determining the number of groups of NDIO and the number of NDIO in each group of NDIO according to the electrostatic discharge protection level and the total number of NDIO in the electrostatic discharge protection circuit.

3. The chip layout design method of claim 1, wherein, Each group of PDIO includes one PDIO, and each group of NDIO includes one NDIO.

4. The chip layout design method of claim 1, wherein, Each PDIO is provided with one P-type doped region and two N-type doped regions; Each NDIO is provided with one N-type doped region and two P-type doped regions.

5. A chip, characterized by The chip is provided with an electrostatic discharge protection circuit, the electrostatic discharge protection circuit including interleaved N groups of PDIO and N groups of NDIO, each group of PDIO including at least one PDIO, and each group of NDIO including at least one NDIO.

6. The chip of claim 5, wherein, Each PDIO is provided with one P-type doped region and two N-type doped regions; Each NDIO is provided with one N-type doped region and two P-type doped regions.

7. The chip of claim 5, wherein, The P-type doped region of the PDIO is connected to the IO interface of the chip, the N-type doped region of the PDIO is connected to the power supply of the chip, the P-type doped region of the NDIO is connected to the ground of the chip, and the N-type doped region of the NDIO is connected to the IO interface of the chip.

8. The chip of claim 5, wherein, The electrostatic discharge protection circuit further includes an NMOS tube and a PMOS tube; The source of the PMOS tube is connected to the power supply of the chip, the drain of the PMOS tube and the drain of the NMOS tube are both connected to the IO interface of the chip, and the source of the NMOS tube is connected to the ground of the chip.

9. An electronic device, comprising: It comprises: The chip of any one of claims 5-8.

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