Semiconductor structure and forming method thereof

Abstract

The semiconductor structure includes: a substrate; a dielectric structure including a plurality of dielectric layers; a ring structure disposed in the substrate and the dielectric structure; and a through hole structure extending longitudinally in the vertical direction and located in a region surrounded by the ring structure. The plurality of dielectric layers includes a plurality of front-side dielectric layers disposed on the front side of the substrate and a plurality of back-side dielectric layers disposed on the back side of the substrate. The ring structure includes a metal feature disposed in a plurality of dielectric layers of the dielectric structure. In a top view, the ring structure has a ring pattern, and one of the metal features extends laterally beyond an outer sidewall of the ring pattern to connect to a diode or a conductive via. The conductive via is connected to a first reference voltage. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing ICs. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor structure including: a substrate; a dielectric structure including a plurality of dielectric layers, wherein the plurality of dielectric layers include a plurality of front-side dielectric layers disposed on a front side of the substrate and a plurality of back-side dielectric layers disposed on a back side of the substrate; a ring structure disposed in the substrate and the dielectric structure; and a via structure extending longitudinally in a vertical direction and located in a region surrounded by the ring structure, wherein the ring structure includes metal components disposed in the plurality of dielectric layers of the dielectric structure, wherein, in a top view, the ring structure has a ring pattern, and one of the metal components extends laterally beyond the outer sidewall of the ring pattern to connect to a diode or a conductive via, wherein the conductive via is connected to a first reference voltage.

[0004] Other embodiments of this application provide a semiconductor structure including: a substrate; a front-side dielectric structure disposed above the substrate and including a plurality of front-side dielectric layers; a back-side dielectric structure disposed below the substrate and including a plurality of back-side dielectric layers; and a ring structure including a front-side conductive component, a back-side conductive component, and a front-end process (FEOL) component and a middle-end process (MEOL) component connecting the front-side conductive component and the back-side conductive component, wherein the front-side conductive component is disposed in the front-side dielectric structure, wherein the back-side conductive component is disposed in the back-side dielectric structure, and wherein the ring structure is electrically connected to a reference voltage or electrically connected to a diode through a via.

[0005] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a substrate; forming a front-end process (FEOL) component and a front-side middle process (MEOL) component over the substrate; forming a front-side dielectric structure over the substrate, wherein the front-side dielectric structure includes a front-side dielectric layer; forming a front-side ring conductive component electrically connected to the front-end process component and the front-side middle process component in the front-side dielectric structure; and forming a discharge structure connected to a ring conductive component of the front-side ring conductive component in one of the front-side dielectric layers. A back-side mid-section process component electrically connected to the front-end process component is formed in and beneath the substrate; a back-side dielectric structure is formed beneath the substrate; a back-side ring conductive component electrically connected to the back-side mid-section process component is formed in the back-side dielectric structure, wherein, during the formation of the back-side mid-section process component and the back-side ring conductive component, charge is generated and discharged to the discharge structure; and a via extending in the front-side dielectric structure, the substrate, and the back-side dielectric structure is formed, wherein the via is surrounded by the front-side ring conductive component and the back-side ring conductive component in a top view. Attached Figure Description

[0006] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of embodiments of the present disclosure is shown.

[0008] Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 7 Exemplary semiconductor structures according to one or more aspects of embodiments of this disclosure are shown in Figure 1 Partial cross-sectional views during each manufacturing stage of the method.

[0009] Figure 4A , Figure 4B , Figure 4C , Figure 8A , Figure 8B and Figure 8C Exemplary semiconductor structures according to one or more aspects of embodiments of this disclosure are shown in Figure 1 Partial top views during various manufacturing stages in the method.

[0010] Figure 9 and Figure 10A partial cross-sectional view of an alternative semiconductor structure according to one or more aspects of embodiments of the present disclosure is shown.

[0011] Figure 11 A partial schematic top view of an exemplary semiconductor structure according to one or more aspects of embodiments of the present disclosure is shown.

[0012] Figure 12 A partial schematic cross-sectional view of an exemplary semiconductor structure according to one or more aspects of embodiments of the present disclosure is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact.

[0014] Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments disclosed herein. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following embodiments of the present disclosure, forming a component connected to and / or coupled to another component on another component may include embodiments where the components are formed in direct contact, and may also include embodiments where an additional component is formed between the components, such that the components do not directly contact each other. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the embodiments of the present disclosure. Spatially relative terms are intended to cover different orientations of the device including the component. Moreover, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” etc., as will be understood by those skilled in the art, the term is intended to cover numerical values ​​within a reasonable range that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having numerically related characteristics, the numerical value or range of numerical values ​​encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" can include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is + / - 15%, as is known to those skilled in the art.

[0015] Through-substrate vias (TSVs) are commonly used in three-dimensional integrated circuits (3DICs) because they route electrical signals from one side of the IC's silicon substrate to the other. The formation of TSVs can generate stress around the structure, causing delamination and failure. Protective structures (e.g., guard rings) have been developed to reduce, absorb, or isolate the stress generated by TSVs. While existing protective structures are generally sufficient for their intended purpose, they are not satisfactory in all respects.

[0016] Furthermore, as integrated circuits continue to shrink, so do power rails. This leads to an increased voltage drop across the power rails and increased power consumption of the integrated circuit. One area of ​​interest is the formation of back-side structures, such as power rails and vias on the back side of an IC. Plasma processing (e.g., plasma etching processes) can be used to form back-side power rails and vias, and may cause plasma-induced damage (PID) to occur in previously formed devices, resulting in channel resistance degradation, threshold voltage shift, circuit leakage, failed device yields, and / or reduced device reliability. Therefore, while existing semiconductor structures are generally sufficient for their intended purpose, they are not entirely satisfactory in all respects.

[0017] This disclosure generally relates to structures including a guard ring structure surrounding one or more TSVs. More specifically, this disclosure provides a semiconductor structure including a guard ring structure surrounding a region in a top view. The guard ring structure includes a front-side conductive component, a back-side conductive component, and a front-end process (FEOL) component and a middle-end process (MEOL) component connecting the front-side conductive component and the back-side conductive component. The guard ring structure is connected to a discharge structure, such as a diode, a reference voltage, or a diode connected to a reference voltage. The reference voltage may be a VSS. The semiconductor structure may also include a substrate via (TSV) extending vertically in the region surrounded by the guard ring structure. By connecting the guard ring structure to the discharge structure, charges generated during and after the manufacturing process (e.g., back-side metallization) can be rapidly discharged, avoiding charge accumulation in the guard ring structure and thus mitigating the potential risk of damage to the guard ring structure (e.g., plasma-induced damage (PID)). PID to other devices can also be reduced. By having a guard ring structure surrounding the TSV, TSV noise can be reduced, and TSV performance can be improved. Therefore, the overall performance of the semiconductor structure can be improved.

[0018] Various aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a structure (such as structure 200) according to an embodiment of the present disclosure. The following is in conjunction with... Figures 2 to 8C Description method 100. Figures 2 to 3 and Figures 5 to 7 It is based on Figure 1 Partial cross-sectional views of structure 200 at different manufacturing stages of an embodiment of method 100.

[0019] Figures 4A to 4C and Figures 8A to 8C It shows that according to Figure 1 A partial top view of the structure 200 of an embodiment of method 100 at different manufacturing stages. Figure 9 and Figure 10 Partial cross-sectional views of optional structures 200' and 200" according to embodiments of the present disclosure are shown respectively. Figure 11 and Figure 12 Partial schematic top and cross-sectional views of an exemplary structure 200 according to embodiments of the present disclosure are shown, respectively. Method 100 is merely an example and is not intended to limit the embodiments of the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or moved around for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. Because structure 200 (or 200', 200") will be fabricated as a semiconductor structure or semiconductor device, structure 200 (or 200', 200") may be referred to herein as semiconductor structure 200 (or 200', 200") or semiconductor device 200 (or 200', 200") as the context requires. To avoid doubt, Figures 2 to 12 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout the embodiments of this disclosure. Throughout the embodiments of this disclosure, the same reference numerals denote the same parts unless otherwise stated. That is, the material properties of the various numbered elements described in conjunction with the methods or drawings, and their comparisons, should be applied to the same numbered elements described in conjunction with different methods or different drawings.

[0020] Furthermore, the semiconductor structures disclosed herein may include various other devices and components, such as other types of devices including transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, SRAM, and / or other logic circuits, but simplification has been provided for a better understanding of the inventive concepts of the embodiments of this disclosure. In some embodiments, exemplary devices include multiple interconnectable semiconductor devices (e.g., transistors), including n-type GAA transistors, p-type GAA transistors, PFETs, NFETs, etc.

[0021] refer to Figure 1 and Figure 2Method 100 includes block 102, in which a substrate 202 is provided. Substrate 202 is part of structure 200, which will include further structures as method 100 proceeds. In an embodiment, substrate 202 comprises silicon (Si). Optionally or additionally, substrate 202 may include: another elemental semiconductor, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Optionally, substrate 202 may be a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated using SIMOX, wafer bonding, and / or other suitable methods. Substrate 202 may include various doped regions (not shown), depending on the design requirements of device structure 200. In some embodiments, substrate 202 includes p-type doped regions (e.g., p-type wells) doped with p-type dopants, such as boron (e.g., BF2), indium, other p-type dopants, or combinations thereof. In some embodiments, substrate 202 includes n-type doped regions (e.g., n-type wells) doped with n-type dopants, such as phosphorus (P), arsenic (As), other n-type dopants, or combinations thereof. In some embodiments, substrate 202 includes doped regions formed with a combination of p-type and n-type dopants. The various doped regions may be formed directly on and / or in substrate 202, for example, providing p-well structures, n-well structures, double-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be implemented to form the various doped regions.

[0022] Still referencing Figure 1 and Figure 2 Method 100 includes block 104, wherein front-end process (FEOL) components and front-side middle-end process (MEOL) components are formed over substrate 202. FEOL typically encompasses processes associated with manufacturing IC devices, such as transistors. For example, an FEOL process may include forming FEOL components, such as isolation components, gate structures, and source and drain components (often referred to as source / drain components). MEOL typically encompasses processes associated with MEOL components that manufacture contacts (such as contacts to gate structures and / or source / drain components) for conductive components (or conductive regions) to IC devices. In some embodiments, as depicted, an FEOL component includes a source / drain component 206, and a front-side MEOL component includes a source / drain contact 208 and a source / drain via 210.

[0023] FEOL components may include devices, such as planar transistors or multi-gate transistors, such as fin-field FETs (FinFETs) or gate-all-around (GAA) transistors. GAA transistors may include channel regions of various shapes, including nanowires, nanorods, or nanosheets, which can be collectively referred to as nanostructures. GAA transistors may also be referred to as multi-bridge channel (MBC) transistors or gate-around transistors (SGTs). Devices may include FinFETs, which include a gate structure enclosing the channel regions of a fin structure rising from substrate 202 and source / drain components (e.g., source / drain component 206) disposed above the source / drain regions of the fin structure. The fin structure may be formed from substrate 202 (which may be a silicon (Si) substrate) or from an epitaxial layer formed on substrate 202. In the latter case, the epitaxial layer may include germanium (Ge) or silicon-germanium (SiGe).

[0024] Although not explicitly shown, the gate structure includes an interface layer in contact with the fin structure, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Optionally, the gate dielectric layer may comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0025] The gate electrode layer of the gate structure may comprise a single layer or optionally a multilayer structure, such as a metal layer (power function metal layer) having a selected work function to enhance device performance, a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials, or combinations thereof.

[0026] The source / drain component 206 can be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain component 206 is n-type, it can comprise silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As). When the source / drain component 206 is p-type, it can comprise silicon germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron difluoride (BF2). In some alternative embodiments not explicitly shown in the figures, the source / drain component 206 can comprise multiple layers, such as a lightly doped first epitaxial layer above the finned source / drain region, a heavily doped second epitaxial layer above the lightly doped first epitaxial layer, and a cover epitaxial layer disposed above the heavily doped second epitaxial layer.

[0027] Although Figure 2 Not explicitly shown, but multiple active regions (e.g., fin structures) are formed above substrate 202. The active regions can be isolated from each other by isolation components. In some embodiments, the isolation components can be formed by etching trenches in substrate 202 or an epitaxial layer on the substrate using a dry etching process and filling the trenches with an insulating material using a chemical vapor deposition (CVD) process, a flowable CVD (FCVD) process, or a spin-coating glass process. A chemical mechanical polishing (CMP) process can be performed to remove excess insulating material and to provide a flat surface. The insulating material is then etched back to form the isolation components, thereby allowing the active regions to rise above the isolation components. In some embodiments, the isolation components can include a multilayer structure comprising a pad dielectric layer and a bulk dielectric layer. The isolation components can include silicon oxide, silicon oxynitride, borosilicate glass (BSG), or phosphosilicate glass (PSG).

[0028] The operation in block 104 may include forming an interlayer dielectric (ILD) layer 214 over substrate 202. In the depicted embodiment, a front-side MEOL component is disposed within the ILD layer 214. Figure 2 As shown, source / drain contacts 208 extend within the ILD layer 214 to physically and electrically connect to one of the source / drain components 206. In some embodiments, the ILD layer 214 may comprise silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide such as borosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 214 may comprise multiple layers. The ILD layer 214 may be deposited using PECVD, FCVD, spin coating, or suitable deposition techniques. In some embodiments, structure 200 may be annealed after the formation of the ILD layer 214 to improve the integrity of the ILD layer 214. The source / drain contacts 208 may comprise ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The source / drain contacts 208 may be deposited using CVD, PVD, or suitable methods. Although not shown in the figures, a contact etch stop layer (CESL) may be deposited prior to the deposition of the ILD layer 214, thereby positioning the CESL between the ILD layer 214 and the source / drain component 206. The CESL may comprise silicon nitride or silicon oxynitride and may be deposited using CVD, ALD, or a suitable method. In some embodiments not explicitly shown, the source / drain contact 208 may include a barrier layer to interface with the ILD layer 214. Such a barrier layer may comprise a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride, or nickel nitride. Furthermore, to reduce contact resistance, a silicide component may be positioned between the source / drain contact 208 and the source / drain component 206. The silicide component may comprise titanium silicide. A source / drain via 210 extends within the ILD layer 214 to physically and electrically connect to the source / drain contact 208. The source / drain via 210 may comprise a conductive material, such as Cu, aluminum (Al), Co, Ru, or Ni.

[0029] refer to Figure 1 and Figures 3 to 4C Method 100 includes block 106, wherein a front-side interconnect structure is formed over substrate 202 and ILD layer 214. The front-side interconnect structure includes a front-side dielectric structure 218 and a front-side conductive structure 220. Figure 3 It shows the following: Figure 4A A partial cross-sectional view of structure 200 intercepted by line A-A' in the diagram. Figure 4A A partial top view of structure 200 is shown. Figure 4B and Figure 4C An optional partial top view of a structure 200 according to various embodiments of the present disclosure is shown.

[0030] refer to Figure 3Although not explicitly shown, the front dielectric structure 218 may include multiple dielectric layers (e.g., intermetallic dielectric (IMD) layers and etch stop layers (ESL)). It can be said that ESLs are interleaved with IMD layers, or vice versa. ESLs may share the same composition and may include silicon nitride or silicon oxynitride. IMD layers may share the same composition and may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide such as borosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of low-k dielectric materials include carbon-doped silicon oxide, xylogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide.

[0031] A front conductive structure 220 may be disposed within a front dielectric structure 218. The front conductive structure 220 may include multiple conductive components (e.g., metal wires, metal vias). In some embodiments, the front conductive structure 220 includes metal wires 222 and vias 224, such as... Figure 3 As depicted in the image. The conductive components may each extend continuously around the spacing to form a closed loop in the top view. In other words, the conductive components may each form a ring in the top view. Therefore, the conductive components may be referred to as a ring layer. Figure 4A As shown, the front conductive structure 220 is a closed loop along the XY plane, such that a portion of the front dielectric structure 218 is surrounded by the front conductive structure 220. The front conductive structure 220 can have any suitable shape in the top view, such as a square (e.g., Figure 4A and Figure 4B (middle), circular (e.g., such as) Figure 4C (Medium), rectangular, elliptical, triangular, hexagonal, octagonal or other polygonal shapes. The front conductive structure 220 may completely surround a portion 218a of the front dielectric structure 218, thereby isolating the portion 218a of the front dielectric structure 218 located in the front conductive structure 220 from the rest of the front dielectric structure 218 through the front conductive structure 220.

[0032] exist Figure 3In the depicted embodiment, the front-side interconnect structure includes a metal zero interconnect layer (M0 level), a via zero interconnect layer (V0 level), a metal one interconnect layer (M1 level), a via one interconnect layer (V1 level), ... a metal thirteen interconnect layer (M13 level), a via thirteen interconnect layer (V13 level), and a metal fourteen interconnect layer (M14 level). Each of the M0, V0, M1, V1, ... M13, V13, and M14 levels can be referred to as a metal level. The metal line formed at the M0 level can be referred to as an M0 metal line. Similarly, the vias or metal lines formed at the V0, M1, V1, M2, ... V13, and M14 levels can be referred to as V0 vias, M1 metal lines, V1 vias, M2 metal lines, ... V13 vias, and M14 metal lines, respectively. This disclosure describes front-side interconnect structures with more or fewer interconnect layers (including metal wire interconnect layers and via interconnect layers) and / or levels, e.g., a total number of N interconnect layers in the front-side interconnect structure, where N is an integer ranging from 1 to 40. Each level of the front-side interconnect structure includes conductive components (e.g., metal wires 222, metal vias 224) disposed in one or more dielectric layers (e.g., IMD layers and ESL) of the front-side dielectric structure 218. In some embodiments, the front-side dielectric structure 218 includes one or more dielectric layers (e.g., corresponding to the V14 level as depicted) above the front-side conductive structure 220. The conductive components may each form a closed loop along the XY plane. Viewed from a top view along the Z direction, the conductive components may have substantially the same shape (e.g., the shape of the front-side conductive structure 220 described above). Figures 3 to 4C From the top view, the conductive components can overlap.

[0033] In the depicted embodiment, the source / drain via 210 connects the source / drain contact 208 to the M0 metal line. In some embodiments, the source / drain via 210 may also include a mating contact. The M0 layer includes the M0 metal line disposed in the front dielectric structure 218. The V0 layer includes the V0 via disposed in the front dielectric structure 218, wherein the V0 via connects the M0 metal line to the M1 metal line. Similarly, the Mx layer includes the Mx metal line disposed in the front dielectric structure 218. The Vx layer includes the Vx via disposed in the front dielectric structure 218, wherein the Vx via connects the Mx metal line to the M(x+1) metal line. The M(x+1) layer includes the M(x+1) metal line disposed in the front dielectric structure 218. x is an integer. In the depicted embodiment, x can be from 0 to 13.

[0034] In block 106, the front interconnect structure can be formed layer by layer from bottom to top. In some embodiments, conductive components at the same level (such as the M0 level) of the front conductive structure 220 are formed simultaneously. In some embodiments, the conductive components at the same level of the front conductive structure 220 have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other.

[0035] Forming conductive components (e.g., metal lines 222, vias 224) at a layer level may include: depositing a dielectric layer (e.g., an IMD layer and an ESL) of the front dielectric structure 218 at the layer level; patterning / etching the dielectric layer to form an opening; and forming the conductive component in the opening (e.g., by a damascene process). After forming the conductive component, the same process steps may be repeated to form another metal layer until a set number of metal layers is reached.

[0036] The dielectric layer at the layer level can be deposited using ALD, CVD, FCVD, spin coating, or a suitable deposition method. Patterning the dielectric layer at the layer level may involve multiple processes, such as photolithography, etching, and / or cleaning. For example, at least one hard mask is deposited over the dielectric layer at the layer level using CVD or a suitable process. A photoresist layer is then deposited over the at least one hard mask layer using spin coating. The deposited photoresist layer may undergo a pre-exposure baking process, exposure to radiation reflected or transmitted through the photomask, a post-exposure baking process, and a development process to form a patterned photoresist. The patterned photoresist is then used as an etch mask to etch at least one hard mask layer to form a patterned hard mask. The patterned hard mask is then applied as an etch mask to etch the dielectric layer at the layer level. Etching of the dielectric layer at the layer level can include dry etching processes (e.g., plasma etching), wet etching processes, or combinations thereof. In some instances, different etching processes or different etchant chemicals may be used to etch the dielectric layer at the layer level. After the dielectric layer at the patterned level, residual patterned photoresist can be removed by ashing, stripping, or selective etching.

[0037] After the openings are formed in the dielectric layer at the level, the conductive components at the level can be formed using a damascene process (e.g., single damascene or double damascene). The conductive components in the front conductive structure 220 (e.g., via 224 and metal line 222) can include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), and / or other suitable materials. In one embodiment, they can include copper (Cu). In some embodiments, to prevent electromigration or oxygen diffusion from the front dielectric structure 218 into the metal material, via 224 and metal line 222 may each include a barrier layer to be connected to the front dielectric structure 218. The barrier layer can include titanium nitride (TiN), tantalum nitride (TaN), or cobalt nitride (CoN). In an exemplary process for filling the openings in the dielectric layer at the level, a barrier layer is first deposited over the opening using ALD, PVD, CVD, metal-organic CVD (MOCVD), or a suitable method. A seed layer is then deposited over the barrier layer using ALD, PVD, CVD, MOCVD, or a suitable method. In some instances, the seed layer may comprise titanium or copper. A bulk metal layer may then be deposited over the seed layer using electroplating or electroless plating. In one embodiment, the bulk metal layer may comprise copper. In some alternative embodiments, the seed layer may be omitted, and the openings are filled with titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al) using PVD, CVD, MOCVD, or a suitable method. After filling with the barrier layer, seed layer, and bulk metal layer, structure 200 is planarized using, for example, CMP to form conductive components at the layer level.

[0038] In some embodiments, one of the metal line 222 and the metal via 224 is formed as an extended metal line 226. The extended metal line 226 has a width in the X direction greater than that of the other metal lines 222 and via 224. In the depicted embodiment, the M0 metal line is formed as the extended metal line 226. In addition to the extended metal line 226, lower-level metal lines (e.g., M1 metal line) of the front conductive structure 220 may have a width in the X direction greater than that of higher-level metal lines (e.g., M13 metal line).

[0039] refer to Figures 4A to 4C From a top view, the extended metal wire 226 includes an extension 226' extending beyond the outer wall 220s of the front conductive structure 220. (Reference) Figure 4A The extension 226' may have a width W1 smaller than the width W2 of the front conductive structure 220. W1 and W2 are along the Y direction. (See reference) Figure 4B The extension 226' along the Y direction can have the same width W3 as W2. (See reference) Figure 4CIn some embodiments, the front conductive structure 220 has a circular shape, and the extension 226' may have a width W1 smaller than the diameter D1 of the circle.

[0040] Forming the front conductive structure 220 may include a process for generating charge (e.g., a plasma etching process). The charge can be discharged via a discharge structure 228 (described) electrically connected to the extended metal line 226 and / or via the substrate 202, where the substrate 202 is grounded during this stage. In some embodiments, the substrate 202 is not grounded, and the charge is discharged via the discharge structure 228. Therefore, charge accumulation in the front conductive structure is avoided and / or reduced.

[0041] In some embodiments, the operation in block 106 includes forming a discharge structure 228 connected to the extended metal line 226. The discharge structure 228 may include a diode or conductive component (e.g., a wire) connected to a first reference voltage.

[0042] The conductor connected to the first reference voltage can be disposed in the same metal layer as the extended metal line 226 as depicted. The conductor can be connected to the first reference voltage via other conductive components (e.g., conductive vias 227) in adjacent metal layers. The conductive components (e.g., conductive vias 227) can be located above or below the conductor. The via 227 is depicted as a dashed rectangle because in some embodiments (e.g., when the discharge structure 228 includes a diode), the via 227 can be omitted. The conductor connected to the first reference voltage can have a similar material to the conductive components of the preceding conductive structure 220 and can be formed using a similar method. The extended metal line 226 and the conductor connected to the first reference voltage can be formed simultaneously or separately. When the extended metal line 226 and the conductor connected to the first reference voltage are formed simultaneously, they can be combined into a single continuous metal line. In such an embodiment, the operation in block 106 may include: forming an opening for extending the metal wire 226 and the conductor connected to the first reference voltage; and forming a barrier layer, an optional seed layer, and a bulk metal layer in the opening. In some embodiments, the first reference voltage is VSS (i.e., ground or negative supply voltage). In such an embodiment, the conductor is also referred to as a VSS conductor. The via 227 may be formed similarly to a V0 via.

[0043] In some embodiments, the discharge structure 228 includes a diode. The diode may include a pn junction. The diode can be formed using any suitable method. In an exemplary process, forming the diode includes: forming a diode opening in a dielectric layer of a front-side dielectric structure 218 at a layer level; depositing a semiconductor material (e.g., silicon, germanium, polycrystalline silicon, amorphous silicon) in the diode opening; doping a first portion of the semiconductor material with a p-type dopant (such as boron (B) or boron difluoride (BF2)); and doping a second portion of the semiconductor material with an n-type dopant (such as phosphorus (P) or arsenic (As)). In some embodiments, the first and second portions are in direct contact. In some other embodiments, the diode also includes an undoped semiconductor component (e.g., a third portion of the semiconductor material) located between the first and second portions. The undoped semiconductor component is also referred to as an intrinsic component. In some embodiments, the diode is electrically connected to a second reference voltage via a via 227. The second reference voltage may be VSS (i.e., ground or a negative supply voltage).

[0044] It should be pointed out that, Figures 3 to 4C The dimensions, shape, and location of the discharge structure 228 are for illustrative purposes only. From a top view, the discharge structure 228 can have any suitable size and / or shape, such as a square, circle, rectangle, ellipse, triangle, hexagon, octagon, or other polygonal shape. The discharge structure 228 can be located in any suitable position, such as... Figure 4B In the dashed square, the discharge structure 228 is connected to the extension 226'.

[0045] Still referencing Figure 1 and Figures 3 to 4C Method 100 includes block 108, wherein a top metal line 230 is formed over a front conductive structure 220. In some embodiments, the top metal line 230 may not be a closed loop in a top view. The top metal line 230 may comprise a material similar to the metal line 222 described above and is formed using a method similar to that described above. Forming the top metal line 230 may include forming an additional dielectric layer 229 (e.g., an IMD layer and an ESL) over a front dielectric structure 218. The top metal line 230 is isolated from the front conductive structure 220 by a portion of the front dielectric structure 218. The ILD layer 214, the front dielectric structure 218, and the additional dielectric layer 229 may be collectively referred to as the combined front dielectric structure 231.

[0046] refer to Figure 1 and Figure 5Method 100 includes block 110, wherein a back-side MEOL component and a back-side dielectric layer 232 are formed beneath a substrate 202. The FEOL component, front-side MEOL component, and back-side MEOL component may be collectively referred to as device layer structure 236. The front-side MEOL component and the back-side MEOL component may be collectively referred to as MEOL component. The back-side MEOL component is electrically connected to the FEOL component. The back-side MEOL component may extend through the substrate 202 and the back-side dielectric layer 232. In the depicted embodiment, the back-side MEOL component includes a back-side contact 234. The back-side contact 234 extends in the back-side dielectric layer 232 to be electrically connected to one of the source / drain components 206.

[0047] The back-side dielectric layer 232 may comprise a material similar to that of the ILD layer 214 and is formed using a method similar to that of the ILD layer 214. Prior to forming the back-side dielectric layer 232, a CESL may be formed under the substrate 202. The back-side contact 234 may comprise a material similar to that of the source / drain contact 208 described above and is formed using a method similar to that of the source / drain contact 208 described above. A back-side silicide component similar to the silicide component described above may be disposed between the back-side contact 234 and the source / drain component 206.

[0048] Still referencing Figure 1 and Figure 5 Method 100 includes a frame 112, wherein a back-side interconnect structure is formed beneath a substrate 202 and a back-side dielectric layer 232. The back-side interconnect structure includes a back-side dielectric structure 238 and a back-side conductive structure 240. A front-side conductive structure 220, a device layer structure 236, and a back-side conductive structure 240 together form a guard ring structure 254. The back-side conductive structure 240 is connected to a back-side MEOL component via a back-side MEOL component.

[0049] The back-side dielectric structure 238 may include multiple dielectric layers (e.g., IMD layers and ESL) similar to the front-side dielectric structure 218. A back-side conductive structure 240 may be disposed within the back-side dielectric structure 238. The back-side conductive structure 240 may include back-side conductive components (e.g., back-side metal lines, back-side metal vias) similar to the conductive components of the front-side conductive structure 220. In some embodiments, the back-side conductive structure 240 includes a back-side metal line 250 and a back-side via 252, such as... Figure 5 As depicted in the figure. From a top view, the back metal line 250 and the back via 252 may include structures (e.g., barrier layers, seed layers, and bulk metal layers) similar to those of the metal line 222 and the via 224, materials, and shapes, and may be formed using methods similar to those used for the metal line 222 and the via 224.

[0050] exist Figure 5In the depicted embodiments, the back-side interconnect structure includes a back-side metal zero interconnect layer (BM0 level), a back-side via zero interconnect layer (BV0 level), a back-side metal first interconnect layer (BM1 level), a back-side via first interconnect layer (BV1 level), a back-side metal second interconnect layer (BM2 level), a back-side via second interconnect layer (BV2 level), and a back-side metal third interconnect layer (BM3 level). Each of the BM0, BV0, BM1, BV1, BM2, BV2, and BM3 levels can be referred to as a metal level. The metal line formed at the BM0 level can be referred to as a BM0 metal line. Similarly, the vias or metal lines formed at the BV0, BM1, BV1, BM2, BV2, and BM3 levels can be referred to as BV0 vias, BM1 metal lines, BV1 vias, BM2 metal lines, BV2 vias, and BM3 metal lines, respectively. This disclosure considers back-side interconnect structures having more or fewer interconnect layers (including metal wire interconnect layers and via interconnect layers) and / or levels, for example, the total number of Q interconnect layers (levels) of the back-side interconnect structure, where Q is an integer ranging from 1 to 40. Each level of the back-side interconnect structure includes back-side conductive components (e.g., back-side metal wires, back-side metal vias) disposed in one or more dielectric layers (e.g., IMD layers and ESL) of the back-side dielectric structure 238. In some embodiments, the back-side dielectric structure 238 includes one or more dielectric layers (e.g., corresponding to the BV3 level as depicted) below the back-side conductive structure 240.

[0051] In the depicted embodiment, back-side contact 234 connects source / drain component 206 to the BMO metal line. The BMO layer includes the BMO metal line disposed in the back-side dielectric structure 238. The BV0 layer includes a BV0 via disposed in the back-side dielectric structure 238, wherein the BV0 via connects the BMO metal line to the BM1 metal line. Similarly, the BMy layer includes the BMy metal line disposed in the back-side dielectric structure 238. The BVy layer includes a BVy via disposed in the back-side dielectric structure 238, wherein the BVy via connects the BMy metal line to the BM(y+1) metal line. The BM(y+1) layer includes the BM(y+1) metal line disposed in the back-side dielectric structure 238. y is an integer. In the depicted embodiment, y can range from 0 to 2.

[0052] The back-side conductive components can each form a closed loop along the XY plane. Viewed from a top view along the Z direction, the back-side conductive components can have substantially the same shape (e.g., the shape of the front-side conductive structure 220 described above). Viewed from a top view, the back-side conductive components can overlap. Figures 4A to 4C A partial top view of structure 200 in block 112 according to various embodiments of the present disclosure may be shown.

[0053] refer to Figure 5 Along the X direction, the lower-level (e.g., BM3 level) metal lines of the back-side conductive structure 240 may have a width greater than the width of the higher-level (e.g., BM0 level) metal lines. Along the X direction, the lower-level (e.g., BV2 level) vias of the back-side conductive structure 240 may have a width greater than the width of the higher-level (e.g., BV0 level) vias. The bottommost metal line and bottommost via of the back-side conductive structure 240 may, along the horizontal direction (e.g., the X or Y direction), have widths greater than those of the metal lines 222 and vias 224 (excluding the extending metal line 226) of the front-side conductive structure 220. The width differences described above can be applied to the radial width in embodiments where the guard ring structure 254 has a circular shape. Figure 4A and Figure 4B The dashed square in the middle and Figure 4C The dashed circle in the diagram represents the inner sidewall 240s of the back-side conductive structure 240. A wider width in a lower-level conductive component (or back-side conductive component) can provide more mechanical support to the structure above it (e.g., conductive components and / or back-side conductive components), thus improving the integrity of the protective ring structure 254. In the depicted embodiment, the outer sidewalls of the metal wires of the back-side conductive structure 240 and the front-side conductive structure 220 are substantially aligned. Therefore, Figures 4A to 4C The width W2 and diameter D1 in the middle are also the width and diameter of the protective ring structure 254, respectively.

[0054] refer to Figures 4A to 4C In some embodiments, in a top view, the protective ring structure 254 has a ring pattern between the outer sidewall 220s and the inner sidewall 240s. An extension 226' extends laterally beyond the outer sidewall 220s to connect to the discharge structure 228. In the depicted embodiment, the discharge structure 228 is located outside and spaced apart from the outer sidewall 220s.

[0055] Forming the back-side interconnect structure can be done using a method similar to that used for forming the front-side interconnect structure as described above. In block 112, the differences from the operations in block 106 include the following: The back-side interconnect structure is formed layer by layer from top to bottom. In some embodiments, the operations in block 112 (e.g., deposition, patterning, etching) can be performed from the back side of structure 200. Structure 200 can be flipped for access to its back side. Forming back-side conductive components (e.g., metal lines 250, vias 252) at the layer level can include: depositing dielectric layers (e.g., IMD layers and ESL layers) of the back-side dielectric structure 238 at the layer level; patterning / etching the dielectric layers to form openings; and forming back-side conductive components in the openings (e.g., via a single damascene or double damascene process). After forming the back-side conductive components, the same process steps can be repeated to form another metal layer until a predetermined number of metal layers is reached.

[0056] Forming the back-side conductive structure 240 and the back-side contact 234 may include a charge-generating process (e.g., a plasma etching process). During these stages, the substrate 202 may not be grounded. Charge can be discharged through the device layer structure 236, the front-side conductive structure 220 including the extended metal line 226, and the discharge structure 228. Therefore, charge accumulation in the guard ring structure 254 is avoided and / or reduced. This reduces the potential risk of damage to the guard ring structure 254 (e.g., PID) and protects other devices in the structure 200 (e.g., devices located on the substrate 202 and adjacent to the device layer structure 236) from PID.

[0057] refer to Figure 1 and Figures 6 to 8C Method 100 includes a frame 114 in which a substrate via (TSV) 256 is formed. Figure 7 As shown Figure 8A A partial cross-sectional view of structure 200 in the diagram. Figure 8A A partial top view of structure 200 is shown. Figure 8B and Figure 8C An optional partial top view of structure 200 is shown. Figures 8A to 8C They represent respectively by Figures 4A to 4C The structure shown is the result of manufacturing the structure. The operations in block 114 may include forming the TSV trench 258. Figure 6 (as shown); and filling TSV trench 258 with TSV 256 (as shown); Figures 7 to 8C (as shown in the image).

[0058] refer to Figure 6A TSV trench 258 can be formed in the front dielectric structure 218, the back dielectric structure 238, the substrate 202, the ILD layer 214, and the back dielectric layer 232. In some embodiments, forming the TSV trench 258 includes: forming a patterned mask layer 260 in which an opening is formed having an opening in a region exposed by a guard ring structure 254 surrounding the back dielectric structure 238; and using the patterned mask layer 260 as an etching mask to etch the back dielectric structure 238 and subsequently etch the back dielectric layer 232, the substrate 202, the ILD layer 214, and the front dielectric structure 218. The patterned mask layer 260 can be formed using a photolithography process that may include resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, resist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. In some embodiments, the patterned mask layer 260 is a patterned hard mask layer (e.g., a silicon nitride layer). In some embodiments, the patterned mask layer 260 is a patterned resist layer. Etching can be a dry etching process, a wet etching process, other etching processes, or a combination thereof. In some embodiments, the etching process is isotropic dry etching. In some embodiments, a Bosch process is implemented to extend the TSV trench 258 through the back-side dielectric structure 238, the back-side dielectric layer 232, the substrate 202, the ILD layer 214, and the front-side dielectric structure 218. The Bosch process generally refers to a high aspect ratio plasma etching process involving alternating etch and deposition stages, wherein the cycle includes etch and deposition stages, and the cycle is repeated until the top metal line 230 is exposed.

[0059] refer to Figures 7 to 8C The fabrication process continues by filling the TSV trench 258 with TSV 256. TSV 256 may include conductive plugs and barrier layers and pads disposed on the top surface and sidewalls of the conductive plugs. In some embodiments, TSV 256 is formed by: depositing pads (e.g., silicon oxide, silicon nitride) and barrier materials (e.g., TiN or TaN) on the top surface and sidewalls of the TSV trench 258 (such that the pads and barrier materials partially fill the TSV trench 258); depositing bulk conductive material (e.g., Cu) to fill the remaining portion of the TSV trench 258; and performing a planarization process (e.g., CMP) to remove excess barrier material and excess bulk conductive material from the structure 200.

[0060] TSV 256 extends through the front dielectric structure 218, substrate 202, back dielectric structure 238, ILD layer 214, and back dielectric layer 232. TSV 256 may be surrounded by a guard ring structure 254, such as... Figures 8A to 8C As depicted in the illustration. In some embodiments, more than one TSV 256 is formed, surrounded by a protective ring structure 254. The TSV 256 may be physically and electrically connected to the top metal wire 230.

[0061] The protective ring structure 254 provides a structural barrier around the TSV 256 to prevent moisture from corroding the metallic materials within the TSV 256. Furthermore, the protective ring structure 254 provides an electrical barrier to isolate electrical interference between nearby components and the TSV 256. Because charge accumulation in the protective ring structure 240 is reduced, noise in the TSV 256 can be reduced or avoided. Therefore, the performance of the TSV structure 256 can be improved, and the overall performance of the structure 200 can be enhanced.

[0062] Still referencing Figure 1 and Figures 7 to 8C Method 100 includes block 116, in which a bottom metal line 260 is formed. The bottom metal line 260 may be physically and electrically connected to the TSV 256. In some embodiments, the bottom metal line 260 may not be a closed loop in a top view. The bottom metal line 260 may comprise a material similar to the top metal line 230 described above and is formed using a method similar to that described above for the top metal line 230. Forming the bottom metal line 260 may include forming an additional back-side dielectric layer 262 (e.g., an IMD layer and an ESL) beneath the TSV 256 and the back-side dielectric structure 238. The back-side dielectric layer 232, the back-side dielectric structure 238, and the additional back-side dielectric layer 262 may be collectively referred to as the combined back-side dielectric structure 264. The bottom metal line 260 is isolated from the guard ring structure 254 by a portion of the back-side dielectric structure 238. The semiconductor structure 200 may undergo further processing to form various components and regions known in the art. For example, the semiconductor structure 200 may be packaged as a component of a 3DIC.

[0063] refer to Figure 9 A partial cross-sectional view of an optional structure 200' manufactured by method 100 is provided. The structure differs from the structure 200 described above as follows. As depicted, the extended metal line 226 of structure 200' is an M1 metal line. The extended metal line 226 can be connected to the discharge structure 228 via a V0 via 266. The V0 via 266 can be formed simultaneously with other V0 vias using a method similar to that used for other V0 vias. In such an embodiment, the extended metal line 226 overlaps with the discharge structure 228 in the top view. In some embodiments, the discharge structure 228 is further connected to vias (e.g., V0 vias other than V0 via 266). The vias can be connected to the VSS voltage.

[0064] refer to Figure 10A partial cross-sectional view of an optional structure 200” manufactured by method 100 is provided. The differences from structure 200 described above are as follows. As depicted, the extending metal line 226 of structure 200” is a BMO metal line, and the discharge structure 228 can be disposed in a BMO layer. The extending metal line 226 can be in direct contact with the discharge structure 228. In the depicted embodiment, a conductive via 227 is located below the discharge structure 228. The extending metal line 226 and the discharge structure 228 can be formed during the operation in block 112. The discharge structure 228 of structure 200” can be formed similarly to the discharge structure 228 of structure 200 as described above, except for the different location.

[0065] Figure 11 A schematic partial top view of structure 200 or an optional structure (e.g., 200', 200") is shown. Figure 12 It shows the following: Figure 11 A schematic partial cross-sectional view of structure 200 or an optional structure (e.g., 200', 200") taken along line A-A'. In some embodiments, the guard ring structure 254 disclosed herein is electrically connected to the discharge structure 228 via path 268 or path 270. Path 268 can connect the discharge structure 228 to the front conductive structure 220. For example, Figure 7 The direct contact between the extended metal line 226 and the discharge structure 228 corresponds to path 268. In another example, Figure 9 The V0 via 266 corresponds to path 268. Path 270 can connect the discharge structure to the back-side conductive structure 240. For example, Figure 10 The direct contact between the extended metal line 226 and the discharge structure 228 corresponds to path 270. The discharge structure 228 can be located in any suitable location, such as the substrate 202, ILD layer 214, back-side dielectric layer 232, and any level of interconnect layers (e.g., M0, V0, M1, ... BM2, BV2, and BM3 levels) of the front and back interconnect structures. The discharge structure 228 can extend in more than one interconnect layer. The discharge structure 228 can be located in the substrate 202. The extended metal line 226 can be a metal line or via at any level. Path 268 (or path 270) connects the extended metal line 226 and the discharge structure 228 and can be located between them. In addition to TSV 256, structure 200 may include additional components (e.g., metal lines, vias, devices) surrounded by a guard ring structure 254.

[0066] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits to semiconductor devices. For example, embodiments of this disclosure avoid charge accumulation in the guard ring structure. Therefore, potential damage to the guard ring structure (e.g., PID) and PID to other devices can be avoided or reduced. Furthermore, TSV noise can be reduced, and TSV performance can be improved. Thus, the overall performance of the semiconductor device can be improved.

[0067] In one exemplary aspect, embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes: a substrate; a dielectric structure including a plurality of dielectric layers; a ring structure disposed in the substrate and the dielectric structure; and a via structure extending longitudinally in a vertical direction and located in a region surrounded by the ring structure. The plurality of dielectric layers include a plurality of front-side dielectric layers disposed on a front side of the substrate and a plurality of back-side dielectric layers disposed on a back side of the substrate. The ring structure includes metal components disposed in the plurality of dielectric layers of the dielectric structure. In a top view, the ring structure has a ring pattern, and one of the metal components extends laterally beyond the outer wall of the ring pattern to connect to a diode or a conductive via. The conductive via is connected to a first reference voltage.

[0068] In some embodiments, the first reference voltage is ground or a negative supply voltage. In some embodiments, the diode is connected to a second reference voltage via a via. In some embodiments, the second reference voltage is ground or a negative supply voltage. In some embodiments, the metal component includes a front metal component disposed in a plurality of front dielectric layers and a back metal component disposed in a plurality of back dielectric layers, the front metal components being vertically stacked and the back metal components being vertically stacked, and the ring structure further includes a front-end process (FEOL) component and a middle-end process (MEOL) component connecting the front metal component and the back metal component. In some embodiments, the diode is disposed in the same dielectric layer as one of the metal components. In some embodiments, one of the metal components is disposed in a first dielectric layer of the plurality of dielectric layers, and the diode is disposed in a second dielectric layer of the plurality of dielectric layers, the second dielectric layer being closer to the substrate than the first dielectric layer. In some embodiments, the semiconductor structure further includes a via connecting one of the metal components and the diode. In some embodiments, the semiconductor structure further includes a top metal line disposed in the dielectric structure and above the ring structure and the via structure, the top metal line being connected to the via structure and spaced apart from the ring structure.

[0069] In another exemplary aspect, embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes: a substrate; a front-side dielectric structure disposed above the substrate and including a plurality of front-side dielectric layers; a back-side dielectric structure disposed below the substrate and including a plurality of back-side dielectric layers; and a ring structure including a front-side conductive component, a back-side conductive component, and a front-end process (FEOL) component and a middle-end process (MEOL) component connecting the front-side conductive component and the back-side conductive component. The front-side conductive component is disposed in the front-side dielectric structure. The back-side conductive component is disposed in the back-side dielectric structure. The ring structure is electrically connected to a reference voltage or electrically connected to a diode via a via.

[0070] In some embodiments, the diode is disposed in the substrate, in the front dielectric structure, or in the back dielectric structure. In some embodiments, the diode is also connected to ground or a negative supply voltage. In some embodiments, the reference voltage is ground or a negative supply voltage, and the ring structure is electrically connected to the reference voltage through a via and a metal line disposed in the front dielectric structure or the back dielectric structure. In some embodiments, the semiconductor structure further includes a via structure extending in the front dielectric structure, the substrate, and the back dielectric structure in the region surrounded by the ring structure in a top view. In some embodiments, the semiconductor structure further includes a bottom metal line disposed in the back dielectric structure and below the ring structure and the via structure, the bottom metal line being connected to the via structure and spaced apart from the ring structure. In some embodiments, in a cross-sectional view, one of the front conductive members has a first width greater than the width of the other front conductive members, and one front conductive member is connected to the diode or the reference voltage.

[0071] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes: receiving a substrate; forming a front-end process (FEOL) component and a front-side middle process (MEOL) component over the substrate; and forming a front-side dielectric structure over the substrate. The front-side dielectric structure includes a front-side dielectric layer. The method further includes: forming a front-side ring conductive component electrically connected to the FEOL component and the front-side MEOL component in the front-side dielectric structure; forming a discharge structure connected to one of the front-side ring conductive components in one of the front-side dielectric layers; forming a back-side MEOL component electrically connected to the FEOL component in and under the substrate; forming a back-side dielectric structure under the substrate; forming a back-side ring conductive component electrically connected to the back-side MEOL component in the back-side dielectric structure; and forming a via extending in the front-side dielectric structure, the substrate, and the back-side dielectric structure. During the formation of the back-side MEOL component and the back-side ring conductive component, charge is generated and discharged to the discharge structure. The via is surrounded by the front-side ring conductive component and the back-side ring conductive component in a top view.

[0072] In some embodiments, the discharge structure includes a diode, a wire connected to ground or a negative supply voltage, or both. In some embodiments, the method further includes: forming a top metal line in the front dielectric structure and above the front ring conductive member before forming the back dielectric structure; and forming a bottom metal line in the back dielectric structure and below the back ring conductive member after forming the via. The via connects to the top metal line and the bottom metal line. In some embodiments, the front ring conductive member and the back ring conductive member overlap in a top view.

[0073] Some embodiments of this application provide a semiconductor structure including: a substrate; a dielectric structure including a plurality of dielectric layers, wherein the plurality of dielectric layers include a plurality of front-side dielectric layers disposed on a front side of the substrate and a plurality of back-side dielectric layers disposed on a back side of the substrate; a ring structure disposed in the substrate and the dielectric structure; and a via structure extending longitudinally in a vertical direction and located in a region surrounded by the ring structure, wherein the ring structure includes metal components disposed in the plurality of dielectric layers of the dielectric structure, wherein, in a top view, the ring structure has a ring pattern, and one of the metal components extends laterally beyond the outer sidewall of the ring pattern to connect to a diode or a conductive via, wherein the conductive via is connected to a first reference voltage.

[0074] In some embodiments, the first reference voltage is ground or a negative supply voltage. In some embodiments, the diode is connected to a second reference voltage via a via. In some embodiments, the second reference voltage is ground or a negative supply voltage. In some embodiments, the metal component includes a front metal component disposed in the plurality of front dielectric layers and a back metal component disposed in the plurality of back dielectric layers, wherein the front metal components are vertically stacked, wherein the back metal components are vertically stacked, and wherein the ring structure further includes a front-end process (FEOL) component and a middle-end process (MEOL) component connecting the front metal component and the back metal component. In some embodiments, the diode is disposed in the same dielectric layer as one of the metal components. In some embodiments, one of the metal components is disposed in a first dielectric layer of the plurality of dielectric layers, wherein the diode is disposed in a second dielectric layer of the plurality of dielectric layers, the second dielectric layer being closer to the substrate than the first dielectric layer. In some embodiments, the semiconductor structure further includes a via connecting one of the metal components and the diode. In some embodiments, the semiconductor structure further includes a top metal line disposed in the dielectric structure and above the ring structure and the via structure, wherein the top metal line is connected to the via structure and spaced apart from the ring structure.

[0075] Other embodiments of this application provide a semiconductor structure including: a substrate; a front-side dielectric structure disposed above the substrate and including a plurality of front-side dielectric layers; a back-side dielectric structure disposed below the substrate and including a plurality of back-side dielectric layers; and a ring structure including a front-side conductive component, a back-side conductive component, and a front-end process (FEOL) component and a middle-end process (MEOL) component connecting the front-side conductive component and the back-side conductive component, wherein the front-side conductive component is disposed in the front-side dielectric structure, wherein the back-side conductive component is disposed in the back-side dielectric structure, and wherein the ring structure is electrically connected to a reference voltage or electrically connected to a diode through a via.

[0076] In some embodiments, the diode is disposed in the substrate, the front dielectric structure, or the back dielectric structure. In some embodiments, the diode is also connected to ground or a negative supply voltage. In some embodiments, the reference voltage is ground or a negative supply voltage, and wherein the ring structure is electrically connected to the reference voltage through the via and a metal line disposed in the front dielectric structure or the back dielectric structure. In some embodiments, the semiconductor structure further includes via structures extending in the front dielectric structure, the substrate, and the back dielectric structure in the region surrounded by the ring structure in a top view. In some embodiments, the semiconductor structure further includes a bottom metal line disposed in the back dielectric structure and below the ring structure and the via structure, wherein the bottom metal line is connected to the via structure and spaced apart from the ring structure. In some embodiments, in a cross-sectional view, one of the front conductive members has a first width greater than the width of the other front conductive members, and wherein the one front conductive member is connected to the diode or the reference voltage.

[0077] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a substrate; forming a front-end process (FEOL) component and a front-side middle process (MEOL) component over the substrate; forming a front-side dielectric structure over the substrate, wherein the front-side dielectric structure includes a front-side dielectric layer; forming a front-side ring conductive component electrically connected to the front-end process component and the front-side middle process component in the front-side dielectric structure; and forming a discharge structure connected to a ring conductive component of the front-side ring conductive component in one of the front-side dielectric layers. A back-side mid-section process component electrically connected to the front-end process component is formed in and beneath the substrate; a back-side dielectric structure is formed beneath the substrate; a back-side ring conductive component electrically connected to the back-side mid-section process component is formed in the back-side dielectric structure, wherein, during the formation of the back-side mid-section process component and the back-side ring conductive component, charge is generated and discharged to the discharge structure; and a via extending in the front-side dielectric structure, the substrate, and the back-side dielectric structure is formed, wherein the via is surrounded by the front-side ring conductive component and the back-side ring conductive component in a top view.

[0078] In some embodiments, the discharge structure includes a diode, a wire connected to ground or a negative supply voltage, or both. In some embodiments, the method further includes: forming a top metal line in the front dielectric structure and above the front ring conductive member before forming the back dielectric structure; and forming a bottom metal line in the back dielectric structure and below the back ring conductive member after forming the via, wherein the via connects to the top metal line and the bottom metal line. In some embodiments, the front ring conductive member and the back ring conductive member overlap in the top view.

[0079] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: a substrate; a dielectric structure comprising a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a plurality of front-side dielectric layers disposed on a front-side of the substrate and a plurality of back-side dielectric layers disposed on a back-side of the substrate; a ring structure disposed in the substrate and the dielectric structure; and a via structure extending longitudinally in a vertical direction and located in an area surrounded by the ring structure, wherein the ring structure comprises a metal component disposed in the plurality of dielectric layers of the dielectric structure, wherein, in a top view, the ring structure has a ring pattern and one of the metal components extends laterally beyond an outer sidewall of the ring pattern to connect to a diode or a conductive via, wherein the conductive via connects to a first reference voltage.

2. The semiconductor structure of claim 1, wherein, The first reference voltage is a ground or a negative supply voltage.

3. The semiconductor structure of claim 1, wherein, The diode connects to a second reference voltage through a via.

4. The semiconductor structure of claim 3, wherein, The second reference voltage is a ground or a negative supply voltage.

5. The semiconductor structure of claim 1, wherein, The metal components comprise front-side metal components disposed in the plurality of front-side dielectric layers and back-side metal components disposed in the plurality of back-side dielectric layers, wherein the front-side metal components are vertically stacked, wherein the back-side metal components are vertically stacked, wherein the ring structure further comprises a front-end-of-line (FEOL) component and a middle-end-of-line (MEOL) component connecting the front-side metal components and the back-side metal components.

6. The semiconductor structure of claim 1, wherein, The diode is disposed in a same dielectric layer as one of the metal components.

7. The semiconductor structure of claim 1, wherein, One of the metal components is disposed in a first dielectric layer of the plurality of dielectric layers, wherein the diode is disposed in a second dielectric layer of the plurality of dielectric layers, the second dielectric layer being closer to the substrate than the first dielectric layer.

8. The semiconductor structure of claim 7, further comprising a via connecting one of the metal components and the diode.

9. A semiconductor structure, comprising: a substrate; a front-side dielectric structure disposed above the substrate and comprising a plurality of front-side dielectric layers; a back-side dielectric structure disposed below the substrate and comprising a plurality of back-side dielectric layers; and a ring structure comprising a front-side conductive component, a back-side conductive component, and a front-end-of-line (FEOL) component and a middle-end-of-line (MEOL) component connecting the front-side conductive component and the back-side conductive component, wherein the front-side conductive component is disposed in the front-side dielectric structure, wherein the back-side conductive component is disposed in the back-side dielectric structure, and wherein the ring structure is electrically connected to a reference voltage or to a diode through a via.

10. A method of forming a semiconductor structure, comprising: receiving a substrate; forming a front-end-of-line (FEOL) component and a front-side middle-end-of-line (MEOL) component above the substrate; forming a front-side dielectric structure above the substrate, wherein the front-side dielectric structure comprises front-side dielectric layers; forming front-side ring conductive components in the front-side dielectric structure that are electrically connected to the FEOL component and the front-side MEOL component; forming a discharge structure in one of the front-side dielectric layers that is connected to one of the front-side ring conductive components; ​ forming a backside middle-of-line component electrically connected to the frontside middle-of-line component in and below the substrate; forming a backside dielectric structure below the substrate; forming a backside ring conductive component electrically connected to the backside middle-of-line component in the backside dielectric structure, wherein during forming the backside middle-of-line component and the backside ring conductive component, electrical charges are generated and discharged to the discharge structure; and forming a via extending in the frontside dielectric structure, the substrate, and the backside dielectric structure, wherein the via is surrounded by the frontside ring conductive component and the backside ring conductive component in a top view.

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