Semiconductor device, lead frame, system, and related manufacturing method

Abstract

A semiconductor device includes a first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface. A first semiconductor chip is mounted on the first mounting surface. The semiconductor device also includes a second die pad, the second die pad including a second mounting surface. A second semiconductor chip is mounted on the second mounting surface and includes electrical contacts arranged on a top surface of the second semiconductor chip facing away from the second mounting surface. The semiconductor device also includes a first electrical connection element electrically connecting the electrical contact of the second semiconductor chip and the first raised portion of the first die pad.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, lead frames, systems, and related manufacturing methods. Background Technology

[0002] The development of semiconductor devices is moving towards smaller dimensions. In this context, various problems can arise due to the lack of space within semiconductor devices. For example, in the fabrication of semiconductor devices, there may not be enough space to properly mount the semiconductor chip onto the die pads or to effectively use bonding tools. Furthermore, due to the lack of mounting space, the semiconductor chip may dangle from the die pads, or solder runoff may occur, potentially causing damage.

[0003] In view of the above problems, it may be desirable to provide a smaller-sized semiconductor device that at least partially solves the aforementioned problems. Additionally, it may be desirable to provide a simple and cost-effective method for manufacturing such a semiconductor device. Summary of the Invention

[0004] One aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a first die pad, the first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface. The semiconductor device also includes a first semiconductor chip mounted on the first mounting surface. The semiconductor device further includes a second die pad, the second die pad including a second mounting surface. The semiconductor device also includes a second semiconductor chip mounted on the second mounting surface and including electrical contacts disposed on a top surface of the second semiconductor chip opposite to the second mounting surface. The semiconductor device further includes a first electrical connection element electrically connecting the electrical contacts of the second semiconductor chip and the first raised portion of the first die pad.

[0005] Another aspect of this disclosure relates to a method for manufacturing a semiconductor device. The method includes the step of providing a first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface. The method further includes the step of mounting a first semiconductor chip on the first mounting surface. The method further includes the step of providing a second die pad including a second mounting surface. The method further includes the step of mounting a second semiconductor chip on the second mounting surface, wherein the second semiconductor chip includes electrical contacts disposed on a top surface of the second semiconductor chip facing away from the second mounting surface. The method further includes the step of electrically connecting the electrical contacts of the second semiconductor chip and the first raised portion of the first die pad via a first electrical connection element.

[0006] Another aspect of this disclosure relates to a leadframe. The leadframe includes a first die pad, the first die pad including a first mounting surface and a first raised portion that rises relative to the first mounting surface. The leadframe also includes a second die pad, the second die pad including a second mounting surface. The first raised portion is disposed at the periphery of the first mounting surface opposite the second die pad. Attached Figure Description

[0007] The methods and devices according to this disclosure will now be described in more detail based on the accompanying drawings. Elements in the drawings are not necessarily to scale. Similar reference numerals may designate corresponding similar parts. Technical features of the various examples shown may be combined unless they exclude each other and / or may be selectively omitted where not necessarily required.

[0008] Figure 1A and 1B The schematic diagram shows a top view and a perspective view of the lead frame 100 according to the present disclosure.

[0009] Figure 2A and 2B A perspective view and a cross-sectional side view of a semiconductor device 200 according to this disclosure are schematically shown.

[0010] Figures 3A to 3C The schematic diagram shows a perspective view, a top view, and a cross-sectional side view of a semiconductor device 300 according to the present disclosure.

[0011] Figure 4 A schematic cross-sectional side view of a semiconductor device 400 according to the present disclosure is shown.

[0012] Figure 5 A schematic cross-sectional side view of a semiconductor device 500 according to the present disclosure is shown.

[0013] Figure 6A and Figure 6B The schematic diagram shows a top view and a cross-sectional side view of a semiconductor device 600 according to the present disclosure.

[0014] Figure 7 A schematic cross-sectional side view of a semiconductor device 700 according to the present disclosure is shown.

[0015] Figure 8 The circuit diagram of the half-bridge circuit 800 is shown.

[0016] Figure 9 A schematic top view of the system 900 according to this disclosure is shown.

[0017] Figure 10 A perspective view of the lead frame 1000 according to this disclosure is shown schematically.

[0018] Figure 11 A perspective view of the lead frame 1100 according to this disclosure is shown schematically.

[0019] Figure 12 A flowchart of a method for manufacturing a semiconductor device according to the present disclosure is shown.

[0020] Figure 13 Exemplary method steps of a method for manufacturing a semiconductor device according to the present disclosure are shown.

[0021] Figure 14 Exemplary method steps of a method for manufacturing a semiconductor device according to the present disclosure are shown.

[0022] Figure 15A and 15B A perspective bottom view and a cross-sectional side view of the semiconductor device 1500 according to the present disclosure are schematically shown.

[0023] Figure 16A and 16B The schematic diagram shows a perspective bottom view and a cross-sectional side view of the semiconductor device 1500 according to the present disclosure. Detailed Implementation

[0024] In the following detailed description, reference is made to the accompanying drawings, which illustrate specific aspects of this disclosure by way of illustration. In this regard, directional terms such as “top,” “bottom,” “front,” and “back” may be used with reference to the orientation of the described drawings. Since components of the described device can be positioned in several different orientations, the directional terms are for illustrative purposes and are by no means limiting. Other aspects may be utilized, and structural or logical changes may be made without departing from the concept of this disclosure. Therefore, the following detailed description should not be considered limiting, and the concept of this disclosure is defined by the appended claims.

[0025] Now for reference Figure 1A and 1B The diagram shows different views of a leadframe 100 according to the present disclosure. The leadframe 100 may include a first die pad 2A having a first mounting surface 4A and a second die pad 2B having a second mounting surface 4B. The first die pad 2A may include a raised portion 6 that is raised relative to the first mounting surface 4A. The leadframe 100 may also include a plurality of leads (or lead fingers or pins) 8 that may be arranged at the periphery of the die pads 2A and 2B.

[0026] The lead frame 100 (i.e., the die pads 2A, 2B and the lead 8) may comprise or be made of metal or metal alloy. For example, the lead frame 100 may comprise a core material, which includes at least one of copper, copper alloys, aluminum, aluminum alloys, etc. Optionally, the lead frame 100 may be plated with at least one plating material, which may include, for example, at least one of nickel, nickel-phosphorus, nickel-nickel-phosphorus, copper, silver, etc. The plating material may cover the entire lead frame 100 (or its core material) or only a selected portion thereof. It should be understood that the core material and plating material of the lead frame 100 may depend on the type of semiconductor chip to be mounted on the die pads 2A, 2B and / or the material of the electrical connection elements (e.g., wires, strips, clamps, etc.) to be connected to the die pads 2A, 2B and / or the lead 8.

[0027] In the example, the raised portion 6 may be plated with a first plating material configured to provide the raised portion 6 with bonding capability for electrical connection elements connected to the raised portion 6. In a first case where the electrical connection element is implemented as a copper and / or gold conductor, the first plating material may include or correspond to a strip or spot silver plating. In a second case where the electrical connection element is implemented as an aluminum conductor, the first plating material may include or correspond to a strip or spot NiNiP plating. In a third case where the electrical connection element is implemented as a copper conductor, the first plating material may include or correspond to at least one of a copper strip plating or a rough copper plating.

[0028] Additionally or alternatively, the first mounting surface 4A of the first die pad 2A may be plated with a second plating material, which may be different from the first plating material. Specifically, the second plating material may provide bonding capability of the first mounting surface 4A to the semiconductor chip to be attached to it. Typically, the die attachment material may include at least one of diffused solder material, soft solder material (which can be applied by dispensing and / or printing), DAF (die attachment film) tape, or materials suitable for soldering processes. In a particular example, the semiconductor chip may be soldered to the first mounting surface 4A using a soldering material. It should be understood that the preceding considerations can be similarly applied to the plating material applied to the second mounting surface 4B of the second die pad 2B.

[0029] The raised portion 6 of the first die pad 2A can be arranged on the outer periphery of the first mounting surface 4A opposite to the second die pad 2B. Figure 1AIn the exemplary top view, the raised portion 6 may extend along the first mounting surface 4A in the y-direction and be arranged facing the right side of the second die pad 2B. In the illustrated case, the raised portion 6 may extend along the entire right side of the mounting surface 4A. In another example, the raised portion 6 may extend only a portion of the right side of the mounting surface 4A, i.e., the size of the raised portion 6 as measured in the y-direction may be reduced.

[0030] The top surface 10 of the raised portion 6 may be substantially parallel to the first mounting surface 4A. Both surfaces may extend, exemplarily, in the xy-plane. In the illustrated example, the surface area of ​​the top surface 10 of the raised portion 6 may be smaller than the surface area of ​​the first mounting surface 4A. However, in other examples, the surface area of ​​the top surface 10 of the raised portion 6 may be greater than or equal to the surface area of ​​the first mounting surface 4A.

[0031] The first mounting surface 4A and the raised portion 6 of the first die pad 2A may form at least one step at the periphery of the first mounting surface 4A. In the example shown, the single step formed may be rectangular, i.e., the portion 12 of the first die 2A connecting the first mounting surface 4A and the raised portion 6 may be substantially perpendicular to the top surface 10 of the first mounting surface 4A and the raised portion 6. The angle between the first mounting surface 4A and the portion 12 may be approximately 90 degrees. In other examples, this angle may be different and may be less than or greater than 90 degrees.

[0032] The bottom surface 20A of the first die pad 2A, opposite to the first mounting surface 4A, may include a recess 22 opposite to the top surface 10 of the raised portion 6. The recess 22 may be formed by a step created by the first mounting surface 4A and the raised portion 6. In this context, when measured in the z-direction, the portion of the first die pad 2A including the first mounting surface 4A and the portion of the first die pad 2A including the raised portion 6 may have similar (or equal) thicknesses. However, in another example, the bottom surface 20A of the first die pad 2A opposite to the first mounting surface 4A and the bottom surface 24 of the raised portion 6 opposite to the top surface 10 may be coplanar, i.e., arranged in a common plane. In this case, when measured in the z-direction, the thickness of the portion of the first die pad 2A including the first mounting surface 4A may be less than the thickness of the portion of the first die pad 2A including the raised portion 6.

[0033] The raised portion 6 may optionally include at least one opening 14 extending from its top surface 10 through the raised portion 6 to its bottom surface 24. In the illustrated example, an exemplary number of three openings 14 are shown, which may differ in other examples. As will become apparent later, encapsulating material may extend through at least one opening 14, thereby providing an interlocking feature.

[0034] Leads 8 may be arranged, for example, on opposite sides of lead frame 100. In the illustrated example, lead frame 100 may include three single leads 8A to 8C arranged on a first side of lead frame 100 and a first plurality of leads 8D and a second plurality of leads 8E arranged on an opposite second side of lead frame 100. It should be understood that the number of leads 8 may vary in other examples and may depend particularly on the specific design of the semiconductor device including lead frame 100. Some leads 8 may be connected to die pads 2A, 2B, while other leads 8 may be separate from die pads 2A, 2B.

[0035] exist Figure 1A-1B In the example, only a single lead frame 100 is shown for illustrative purposes. It should be understood that semiconductor devices can be manufactured in batch processes based on lead frame panels (or lead frame strips) comprising one or more rows of lead frames, with the number of lead frames in a single row potentially reaching dozens or more. For example, the individual lead frames of the lead frame panel can be mechanically connected by tie rods. After the batch process steps are performed, the processing apparatus including the lead frame panel can be divided into multiple semiconductor devices (or semiconductor packages) by cutting tie rods.

[0036] Now for reference Figure 2A and Figure 2B Different views of the semiconductor device 200 according to this disclosure are shown. Figure 2B A cross-sectional side view of the semiconductor device 200 along the cross-sectional plane is shown, wherein it is not in Figure 2A All components shown in the perspective view Figure 2B The semiconductor device 200 may be visible. The lead frame 100 may include some or all of the features of the lead frame 100 of FIG. 1, which are referenced herein. Figure 1A-1B The semiconductor device 200 may also include a lead frame 100. The semiconductor device 200 may further include a first semiconductor chip 16A mounted on a first mounting surface 4A of a first die pad 2A and a second semiconductor chip 16B mounted on a second mounting surface 4B of a second die pad 2B. Furthermore, the semiconductor device 200 may include a plurality of electrical connection elements 18, which will be described later.

[0037] Typically, the semiconductor chips described herein can be fabricated from elemental semiconductor materials (e.g., Si) or from wide-bandgap semiconductor materials or compound semiconductor materials (e.g., SiC, GaN, SiGe, GaAs). Semiconductor chips can be of any type and can include integrated circuits with active and / or passive electronic components. Integrated circuits can be designed as logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, power integrated circuits, memory circuits, integrated passive circuits, etc. It should be noted that the terms "chip," "semiconductor chip," "die," and "semiconductor die" are used interchangeably throughout this specification.

[0038] Specifically, semiconductor chips 16A and 16B can be power semiconductor chips. In this context, the term "power semiconductor chip" can refer to a semiconductor chip that provides at least one of high voltage blocking or high current carrying capacity. Power semiconductor chips can be configured to handle high currents, having a maximum current value of several amperes (e.g., 10A) or a maximum current value of up to or exceeding 100A. Similarly, the voltage associated with such current values ​​can range from several volts to tens or hundreds or even thousands of volts, such as about 1200V, about 1600V, about 2400V, etc. Power semiconductor chips can be used in any kind of power application, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), half-bridge circuits, power modules including gate drivers, etc. For example, a power semiconductor chip can include or be part of a power device (e.g., a power MOSFET, an LV (Low Voltage) power MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a superjunction power MOSFET, etc.).

[0039] The first semiconductor chip 16A may include at least one first electrical contact 26A and at least one second electrical contact 28A disposed on the top surface of the first semiconductor chip 16A facing away from the first mounting surface 4A. Additionally, the first semiconductor chip 16A may include at least one third electrical contact (not shown) disposed on the bottom surface of the first semiconductor chip 16A facing the first mounting surface 4A. In the illustrated example, the first semiconductor chip 16A may include or correspond to a vertical power chip. The vertical power chip may be manufactured from an elemental semiconductor material (particularly silicon) or from a wide-bandgap semiconductor material or a compound semiconductor material (particularly SiC).

[0040] In the example shown, the first semiconductor chip 16A may correspond to a power transistor chip such as a power MOSFET chip or a power IGBT chip. In the case of a power MOSFET, at least one first electrical contact 26A may be a source contact, at least one second electrical contact 28A may be a gate contact, and at least one third electrical contact may be a drain contact of the power MOSFET. In the case of a power IGBT, the electrical contacts in question may represent the base, collector, and emitter of the power IGBT. The second semiconductor chip 16B may be at least partially similar to the first semiconductor chip 16A and may similarly include electrical contacts 26B, 28B disposed on its top and bottom surfaces, as previously described. In a specific but non-limiting example, each of the semiconductor chips 16A and 16B may be based on or include silicon carbide.

[0041] The plurality of electrical connection elements 18 of the semiconductor device 200 can be configured to electrically interconnect the device components previously described, such as... Figure 2A-2B As shown and described below, at least one first electrical connection element 18A can electrically connect lead 8B and first electrical contact 26A of first semiconductor chip 16A. In the illustrated example, the first electrical connection element 18A may include an exemplary number of two thick wires.

[0042] At least one second electrical connection element 18B can electrically connect at least one of the leads 8D to a second electrical contact 28A of the first semiconductor chip 16A. In the illustrated example, the second electrical connection element 18B can exemplary comprise a single thin wire. A third electrical contact disposed on the bottom surface of the first semiconductor chip 16A can be electrically connected to the lead 8A via a first die pad 2A. In this context, the lead 8A and the first die pad 2A can be formed as a single piece. Due to the described electrical interconnects, the electrical contacts of the first semiconductor chip 16A can be electrically reached via leads 8A, 8B, and 8D. In the case of a power MOSFET chip, lead 8A can be referred to as a drain lead, lead 8B can be referred to as a source lead, and lead 8D can be referred to as a gate lead. As will be discussed later, in the case where the semiconductor device 200 includes a half-bridge circuit, lead 8A can represent a switching node of the half-bridge circuit.

[0043] At least one third electrical connection element 18C can electrically connect the electrical contacts 26B of the second semiconductor chip 16B to the top surface 10 of the first raised portion 6 of the first die pad 2A. In the illustrated example, the third electrical connection element 18B may include an exemplary number of three thick wires. The electrical contacts of the first semiconductor chip 16A, disposed on the bottom surface of the first semiconductor chip 16A, can be electrically connected to the electrical contacts 26B of the second semiconductor chip 16B via the first mounting surface 4A of the first die pad 2A, the first raised portion 6, and the third electrical connection element 18C. In the case of two power MOSFET chips, the third electrical connection element 18C can connect the drain contacts of the first semiconductor chip 16A and the source contacts of the second semiconductor chip 16B. In this context, the first semiconductor chip 16A and the second semiconductor chip 16B can form part of the low-side switch and high-side switch of a half-bridge circuit. In particular, the first semiconductor chip 16A can form part of the low-side switch, and the second semiconductor chip 16B can form part of the high-side switch.

[0044] At least one fourth electrical connection element 18D can electrically connect at least one of the leads 8E to the second electrical contact 28B of the second semiconductor chip 16B. A third electrical contact disposed on the bottom surface of the second semiconductor chip 16B can be electrically connected to the lead 8C via the second die pad 2B. In this respect, the lead 8C and the second die pad 2B can be formed as a single piece. Due to the described electrical interconnection, the electrical contacts of the second semiconductor chip 16B can be electrically reached via leads 8C and 8E. Lead 8C can be referred to as the drain lead, and lead 8E can be referred to as the gate lead.

[0045] Semiconductor device 200 may include packaging material 30, which is only used in... Figure 2B Shown in the cross-sectional side view, but not in Figure 2A The perspective diagram shows, in order to avoid confusion Figure 2A The encapsulation material 30 may include or be made of at least one of epoxy resin, filled epoxy resin, glass fiber filled epoxy resin, imide, thermoplastic, thermosetting polymer, polymer blend, laminate, molding compound, etc. Various techniques (e.g., at least one of compression molding, injection molding, powder molding, liquid molding, map molding, lamination, etc.) may be used for encapsulating components in the encapsulation material 30.

[0046] Encapsulation material 30 may at least partially encapsulate the first die pad 2A, the second die pad 2B, the first semiconductor chip 16A, and the second semiconductor chip 16B. Leads 8 of the semiconductor device 200 may at least partially protrude from the encapsulation material 30, allowing electrical contacts of the semiconductor chips 16A and 16B connected to the corresponding leads 8 to be accessible from outside the encapsulation material 30. Therefore, the semiconductor device 200 may be referred to as a leaded package (as opposed to a leadless package). Similarly, at least a portion of the bottom surface 20B of the second die pad 2B and the bottom surface 20A of the first die pad 2A may be uncovered by the encapsulation material 30, allowing electrical contacts disposed on the bottom surfaces of the semiconductor chips 16A and 16B and connected to the die pads 2A and 2B to be accessible from outside the encapsulation material 30. In the illustrated example, the bottom surface 24 of the raised portion 6 may be at least partially covered by the encapsulation material 30. However, in other examples, the bottom surface 24 of the raised portion 6 may be at least partially uncovered by the encapsulation material 30. The encapsulation material 30 may extend at least partially through the opening 14, providing interlocking between the encapsulation material 30 and the first die pad 2A. This prevents separation of the encapsulation material 30.

[0047] Typically, leads 8A to 8C can be referred to as power supply leads of semiconductor device 200, while leads 8D and 8E can be referred to as logic leads of semiconductor device 200. Power leads can be associated with high current and / or high voltage related to the function of the connected semiconductor chip and / or can be configured to handle high current and / or high voltage. That is, power supply leads can be associated with the high power domain of the device. For example, a drain lead or source lead connected to a power MOSFET can be referred to as a power supply lead. Logic leads can be associated with control signals, communication signals, status information signals, etc., associated with the connected semiconductor chip and / or can be configured to handle said control signals, communication signals, status information signals, etc. For example, a gate lead connected to a power MOSFET can be referred to as a logic lead. Generally, compared to power supply leads, logic leads can operate at lower power levels (e.g., typically standard digital or analog signal levels). Logic leads can be associated with the low power domain of the device.

[0048] The power supply terminals of the first semiconductor chip 16A and the second semiconductor chip 16B can be electrically connected only to leads arranged on one side of the semiconductor device 200. In the illustrated case, the source and drain terminals of semiconductor chips 16A and 16B can be connected to power leads 8A to 8C arranged on the right side of the semiconductor device 200. The logic terminals of the first semiconductor chip 16A and the second semiconductor chip 16B can be electrically connected only to leads arranged on opposite sides of the semiconductor device 200. In the illustrated case, the gate terminals of semiconductor chips 16A and 16B can be connected to logic leads 8D and 8E arranged on the left side of the semiconductor device 200. As a result, the power supply leads and logic leads can be arranged on opposite sides of the semiconductor device 200, which can provide improved electrical isolation between the high-power and low-power domains of the semiconductor device 200.

[0049] In the example shown, semiconductor device 200 may include a half-bridge circuit. Figure 8 An exemplary circuit diagram of a half-bridge circuit 800 is shown. The half-bridge circuit 800 can be arranged between two terminals 50A and 50B. The half-bridge circuit 800 may include two switches 52A and 52B connected in series. Switch 52A may be the low-side switch of the half-bridge circuit, while switch 52B may be the high-side switch of the half-bridge circuit. A constant potential can be applied to terminals 50A and 50B. For example, a high potential such as about 10V, about 50V, about 100V, about 200V, about 500V, or about 1000V, or any other potential, can be applied to terminal 50B, and a low potential (e.g., about 0V) can be applied to terminal 50A. Switches 52A and 52B can switch at frequencies ranging from about 1 kHz to about 100 MHz, but the switching frequency can also be outside this range. This means that during operation of the half-bridge circuit 800, a changing potential can be applied to terminal 50C arranged between switches 52A and 52B. Terminal 50C may be referred to as a switching node. The potential of terminal 50C can vary between low and high potential.

[0050] For example, a half-bridge circuit 800 can be implemented in electronic circuitry used to convert DC voltage (a so-called DC-DC converter). A DC-DC converter can be used to convert a DC input voltage provided by a battery or rechargeable battery into a DC output voltage that matches the needs of downstream connected electronic circuitry. A DC-DC converter can be embodied, for example, as a buck converter, where the output voltage can be less than the input voltage, or it can be embodied, for example, as a boost converter, where the output voltage can be greater than the input voltage. Frequency of several MHz or higher can be applied to a DC-DC converter. Furthermore, currents up to about 50 A or even higher can flow through a DC-DC converter.

[0051] Return to reference Figure 2A For example, the first semiconductor chip 16A and the second semiconductor chip 16B can form part of the low-side switch 52A and the high-side switch 52B of the half-bridge circuit. More specifically, the first semiconductor chip 16A can form part of the low-side switch 52A, and the second semiconductor chip 16B can form part of the high-side switch 52B.

[0052] Power lead 8B can be electrically connected to the power terminal of the first semiconductor chip 16A, while power lead 8C can be electrically connected to the power terminal of the second semiconductor chip 16B. In the example shown, power lead 8B can be electrically connected to the source (or low-side switch) of the first semiconductor chip 16A, while power lead 8C can be electrically connected to the drain (or high-side switch) of the second semiconductor chip 16B. It should be noted that power leads 8B and 8C can be arranged on the same first side of the semiconductor device 200. Further note that power leads 8B and 8C can be arranged directly adjacent to each other.

[0053] Power lead 8C can be configured to receive power and / or voltage from the power supply. In the example shown, power lead 8C can be the DC+ (or Vcc) terminal of a half-bridge circuit. Power lead 8B can be configured to output current. In the example shown, power lead 8B can be the DC- terminal of a half-bridge circuit. For example, power lead 8B can be connected to ground.

[0054] Power lead 8A can be electrically connected to the first semiconductor chip 16A and the second semiconductor chip 16B. In the example shown, power lead 8A can be electrically connected to the drain of the first semiconductor chip 16A and the source of the second semiconductor chip 16B. Power lead 8A can also be electrically connected to the switching node of the half-bridge circuit (see...). Figure 8 (50C in the example). Power lead 8A can be configured to output power and / or signals. It should be noted that power lead 8A can be arranged on the same side of semiconductor device 200 adjacent to power leads 8B and 8C. That is, the DC terminals DC+ and DC-, as well as the switching nodes of the half-bridge circuit, are arranged on the same side of semiconductor device 200. Specifically, the DC+ terminal can be directly arranged adjacent to the DC- terminal.

[0055] According to the semiconductor device disclosed herein (e.g., Figure 2A-2B The semiconductor device 200 can be part of the system. In this connection, now refer to... Figure 9The example schematically illustrates a top view of a system 900 according to the present disclosure. System 900 may include a printed circuit board (PCB) 54 on which semiconductor devices 200 may be disposed. It should be noted that only a portion of PCB 54 is shown, and any number of additional components may be disposed on PCB 54. In the example shown, surfaces 20A and 20B of dies 2A and 2B may face away from the mounting surfaces of PCB 54. Leads 8A to 8E of semiconductor devices 200 may be electrically and mechanically connected to conductive traces 56 of PCB 54. In this respect, power lead 8B may be electrically connected to a first conductive trace 56B of PCB 54, and power lead 8C may be electrically connected to a second conductive trace 56C of PCB 54.

[0056] System 900 may also include at least one capacitor 58 electrically connected between the first conductive trace 56B and the second conductive trace 56C. In the illustrated example, an exemplary number of two capacitors 58A, 58B may be connected between conductive traces 56B, 56C, and thus between the two DC terminals DC+ and DC- of semiconductor device 200. The use of a capacitor connected between DC terminals DC+ and DC-, utilizing the half-bridge configuration as described above, can be particularly advantageous for high-frequency switching applications. It should be noted that the simple and efficient arrangement of the capacitor 58 between the DC terminals is facilitated and made possible by the adjacent arrangement of DC leads 8B and 8C on the same side of semiconductor device 200. In contrast, conventional semiconductor devices may have DC terminals arranged on opposite sides of the respective devices, making proper capacitor arrangement difficult. Therefore, semiconductor device 200 and the associated system can exceed conventional solutions.

[0057] Furthermore, semiconductor device 200 can outperform conventional semiconductor devices in various other ways. In this context, the following views should not be considered exhaustive. It should be understood that, according to this disclosure, the following views can also be applied to all other semiconductor devices.

[0058] Compared to conventional semiconductor devices, semiconductor device 200 can provide an increased first mounting surface 4A, meaning a larger semiconductor chip can be mounted on the first die pad 2A. For example... Figure 2A As shown in the example, electrical connection element 18C can be connected to the top surface 10 of the raised portion 6. In contrast, conventional semiconductor devices may not include the raised portion 6, making it possible for electrical connection element 8C to be connected to the first mounting surface 4A instead. This connection may naturally require a portion of the first mounting surface 4A, reducing the available area for mounting the semiconductor chip 16A on the first mounting surface 4A. For example, this could cause the mounted semiconductor chip 16A to protrude beyond the contour of the first die pad 2A in an undesirable manner.

[0059] Compared to conventional semiconductor devices, semiconductor device 200 avoids dicing tool marks on the first semiconductor chip 16A. In a conventional semiconductor device excluding the raised portion 6, the electrical connection element 18C may need to be connected to the first mounting surface 4A. Here, when the electrical connection element 18C is cut due to space constraints, the dicing tool may impact the first semiconductor chip 16A. As a result, undesirable dicing tool marks may remain on the first semiconductor chip 16A. In contrast, in semiconductor device 200, the electrical connection element 18C can be bonded to the raised portion 6, thereby avoiding mechanical contact between the first semiconductor chip 16A and the dicing tool.

[0060] Furthermore, the raised portion 6 of the first die pad 2A can be configured as a solder flow barrier for attaching the first semiconductor chip 16A to the first mounting surface 4A. In this context, the distance between the first semiconductor chip 16A and the raised portion 6 can be less than the distance between the first semiconductor chip 16A and the opposite edges of the first die pad 2A to the edge of the raised portion 6. Because the raised portion 6 is configured as a solder flow barrier, the first semiconductor chip 16A can be arranged closer to the raised portion 6, thereby increasing the distance to the opposite edge of the first die pad 2A. This may be beneficial in mitigating solder flow problems.

[0061] Compared to conventional semiconductor devices, the use of the additional raised portion 6 can provide increased metal density (especially copper density) in the semiconductor device 200, thereby increasing heat dissipation in the semiconductor device 200. In other words, the additional metal material of the raised portion 6 can help reduce the operating temperature of the semiconductor device 200.

[0062] Furthermore, the upper surface 10 of the raised portion 6 is not limited to serving solely as a connection point for the electrical connection element 18C. Additionally, the upper surface 10 can provide an additional area where additional electronic components (e.g., another semiconductor chip) can be mounted. In some examples, a third semiconductor chip (not shown) can be mounted on the raised portion 6. Specifically, such a third semiconductor chip can be a logic semiconductor chip (or a driver semiconductor chip) configured to control (or drive) at least one of the first semiconductor chip 16A or the second semiconductor chip 16.

[0063] Now for reference Figures 3A to 3C Different views of a semiconductor device 300 according to this disclosure are shown. The semiconductor device 300 may include... Figure 2A-2BThe semiconductor device 300 may include some or all of the features of the semiconductor device 200. The semiconductor device 300 may include a first semiconductor chip 16A, a first driver chip 32A, and a controller chip 34 mounted above a first mounting surface 4A of a first die pad 2A, and a second semiconductor chip 16B and a second driver chip 32B mounted above a second mounting surface 4B of a second die pad 2B. Furthermore, the semiconductor device 300 may include a plurality of electrical connection elements 18, which will be described later. The semiconductor device 300 may include features similar to... Figure 2A-2B The packaging material, for illustrative purposes, is in Figures 3A-3C The example is not shown.

[0064] In the example shown, the second die pad 2A of the lead frame 100 may include a second raised portion 6B that is raised relative to the second mounting surface 4B. Figure 3A The raised portions 6A and 6B can be similar to the raised portions described in conjunction with the previous examples. The first raised portion 6A of the first die pad 2A can be arranged on the outer periphery of the first mounting surface 4A opposite to the second die pad 2B, and the second raised portion 6B of the second die pad 2B can be arranged on the outer periphery of the second mounting surface 4B opposite to the first raised portion 6A of the first die pad 2A. Note that... Figure 3A The second raised section 6B shown in Figure 1 and Figure 2A-2B In the example.

[0065] from Figure 3C As can be seen from the cross-sectional side view, the bottom surfaces 20A and 20B of the cores 2A and 2B may include recesses 22A and 22B opposite to the first raised portions 6A and 6B. That is, in the example shown, neither of the bottom surfaces 20A and 20B can be flat. Similar to... Figure 2A-2B In a previous example, semiconductor device 300 may include an encapsulation material (not shown), wherein the bottom surface of the encapsulation material and the bottom surfaces 20A, 20B of the die pads 2A, 2B may be coplanar. Furthermore, the bottom surfaces 20A, 20B of the die pads 2A, 2B may not be covered by the encapsulation material. Because the recesses 22A, 22B are filled with encapsulation material, the creepage distance between the uncovered die pads 2A, 2B along the surface of the encapsulation material can be increased compared to semiconductor devices including die pads with flat bottom surfaces.

[0066] Figure 3A Semiconductor chips 16A and 16B can specifically correspond to power chips and can be configured to provide and combine Figure 2A-2B Similar electronic functions are described. With Figure 2A-2B compared to, Figure 3ASemiconductor chips 16A and 16B can correspond to lateral power chips. That is, although semiconductor chips 16A and 16B can have the same characteristics as... Figure 2A-2B The electrical contacts described are similar or identical, but these contacts can be arranged on the top surface of the corresponding semiconductor chip. Lateral power chips can be fabricated from elemental semiconductor materials (especially silicon), wide-bandgap semiconductor materials, or compound semiconductor materials (especially GaN).

[0067] In the example shown, the first semiconductor chip 16A may correspond to a power transistor chip, such as a power MOSFET chip or a power IGBT chip. In the case of a power MOSFET, the electrical contacts disposed on the top surface of the first semiconductor chip 16A may include or correspond to the gate contact, drain contact, and source contact of the power MOSFET. In the case of a power IGBT, the electrical contacts of the first semiconductor chip 16A discussed may represent the base, collector, and emitter of the power IGBT. The second semiconductor chip 16B may be at least partially similar to the first semiconductor chip 16A and may include similar electrical contacts disposed on its top surface, as previously described.

[0068] Semiconductor chips 16A and 16B can be interconnected in the following manner. An electrical contact 26A disposed on the top surface of the first semiconductor chip 16A can be electrically connected to the second raised portion 6B of the second die pad 2B via at least one electrical connection element 18C. Similarly, an electrical contact 26B disposed on the top surface of the second semiconductor chip 16B can be electrically connected to the second raised portion 6B via at least one electrical connection element 18E. In the example shown, electrical connection elements 18C and 18E may include or correspond to multiple wires. Therefore, the electrical contact 26A of the first semiconductor chip 16A can be electrically connected to the electrical contact 26B of the second semiconductor chip 16B via electrical connection element 18C, the second raised portion 6B, and the second electrical connection element 18E. In the case of two power MOSFET chips, the source contact of the first semiconductor chip 16A and the drain contact of the second semiconductor chip 16B can be electrically connected via electrical connection element 18C, the second raised portion 6B, and the second electrical connection element 18E. For example, the first semiconductor chip 16A and the second semiconductor chip 16B can form part of the low-side switch and the high-side switch of a half-bridge circuit.

[0069] The first driver chip 32A and the second driver chip 32B may include driver circuitry configured to drive the first semiconductor chip 16A and the second semiconductor chip 16B, respectively. The driver circuitry may be configured to drive one or more electronic components, such as high-power transistors that may be included in the device. The driven components may be voltage-driven or current-driven. For example, power MOSFETs, IGBTs, etc., may be voltage-driven switches because their insulated gates may behave specifically like capacitors. Conversely, switches such as triacs (transistors for AC), thyristors, bipolar transistors, PN diodes, etc., may be current-driven. In one example, driving a component including a gate electrode may include applying different voltages to the gate electrode, for example, in the form of on and off switching waveforms. In another example, the driver circuitry may be used to drive directly driven circuitry.

[0070] The controller chip 34 may include control circuitry configured to control one or more of the driver chips 32A and 32B. In one example, the control circuitry can simultaneously control drivers of multiple direct drive circuits. For example, a half-bridge circuit including two direct drive circuits can therefore be controlled by the controller chip 34. Note that, as Figure 3A The driver chips 32A, 32B and controller chip 34 shown can also be included Figure 2A-2B Among the semiconductor devices 200.

[0071] Now for reference Figure 4 This image shows a cross-sectional side view of a semiconductor device 400 according to the present disclosure. The semiconductor device 400 may include some or all of the features of the previously described semiconductor devices. Figures 3A-3C Compared to the previous example, when measured in the x-direction, the dimensions of the bottom surfaces 24A and 24B of the raised portions 6A and 6B can be increased. This may result in an increased creepage distance between the die pads 2A and 2B along the surface of the encapsulation material (not shown).

[0072] Now for reference Figure 5 This figure shows a cross-sectional side view of a semiconductor device 500 according to the present disclosure. The semiconductor device 500 may include some or all of the features of the previously described semiconductor devices. In the example shown, for simplicity, several device components as previously described in conjunction with other examples are omitted. The semiconductor device 500 may include a recess 36 formed in the main surface 38 of the encapsulation material 30. In particular, the recess 36 may be arranged between the uncovered bottom surfaces 20A, 20B of the die pads 2A, 2B and may be configured to increase the creepage distance between the uncovered bottom surfaces 20A, 20B. It should be understood that the features of the recess 36 may also be implemented in any other semiconductor device including an encapsulation material according to the present disclosure.

[0073] Now for reference Figure 6A and Figure 6B The diagram illustrates different views of a semiconductor device 600 according to the present disclosure. The semiconductor device 600 may include some or all of the features of the previously described semiconductor devices. The semiconductor device 600 may include two lateral power semiconductor chips 16A, 16B forming a portion of a low-side switch and a high-side switch of a half-bridge circuit. In the example shown, semiconductor chips 16A, 16B may correspond to power MOSFET chips. Figure 6B The cross-sectional side view is specifically intended to illustrate the source and drain connections in semiconductor device 600.

[0074] One or more of the first plurality of leads 8A can be drain leads electrically connected to drain contacts disposed on the top surface of the first semiconductor chip 16A via first plurality of wires 18A. The source contacts disposed on the top surface of the first semiconductor chip 16A can be electrically connected to the top surface of the first raised portion 6A of the first die pad 2A via second plurality of wires 18B. The drain contacts disposed on the top surface of the second semiconductor chip 16B can be electrically connected to the top surface of the first raised portion 6A via third plurality of wires 18C. Therefore, the source contacts of the first semiconductor chip 16A can be electrically connected to the drain contacts of the second semiconductor chip 16B via wires 18B, 18C, and the first raised portion 6A. Furthermore, the source contacts disposed on the top surface of the second semiconductor chip 16B can be electrically connected to one or more source leads of the second plurality of leads 8B via fourth plurality of wires 18D. Additionally, the source contacts of the second semiconductor chip 16B can be electrically connected to the top surface of the second die pad 2B via fifth plurality of wires 18E.

[0075] Now for reference Figure 7 The diagram shows a cross-sectional side view of a semiconductor device 700 according to the present disclosure. The semiconductor device 700 may be similar to the semiconductor device 600 of FIG. 6. Compared to the example in FIG. 6, Figure 7 The second die pad 2B may include an additional third raised portion 6C and a third recess 22C formed in the bottom surface of the second die pad 2B. In the example shown, a fifth plurality of conductors 18E may be connected to the top surface of the third raised portion 6C. The source and drain connections in the semiconductor device 700 may be similar to... Figure 6B .

[0076] Now for reference Figure 10 This illustration shows another lead frame 1000 according to the present disclosure. Lead frame 1000 may include some or all of the features of the other lead frames described herein. In particular, lead frame 1000 may be at least partially similar to... Figure 2A-2B The lead frame included in the semiconductor device 200. Similar to... Figure 2A-2B For example, the lead frame 1000 may include power leads 8A to 8C, which can be configured to electrically connect to semiconductor chips (not shown) disposed on mounting surfaces 4A, 4B of die pads 2A, 2B. Specifically, power lead 8C can be configured to electrically connect to a power terminal of the semiconductor chip that can be mounted on mounting surface 4B, while power lead 8B can be configured to electrically connect to a power terminal of the semiconductor chip that can be mounted on mounting surface 4A. When two semiconductor chips are disposed on die pads 2A, 2B and form a half-bridge circuit, power lead 8C may correspond to a DC+ terminal, and power lead 8B may correspond to a DC- terminal, as previously described. Figure 2A-2B As described in the example. It should be noted that power leads 8B and 8C can be arranged on the same side of the lead frame 1000, allowing for configuration similar to... Figure 9 In the system 900, one or more capacitors are advantageously arranged. The power lead 8A can be configured to be electrically connected to the switching node of the half-bridge circuit.

[0077] In the example shown, the first die pad 2A may include a first raised portion 6A that is elevated relative to the first mounting surface 4A. The first raised portion 6A may extend only a portion along one side of the first mounting surface 4A. This can be related to... Figure 2A-2B The example where the raised portion 6 can extend along the entire side of the mounting surface 4A forms a contrast. Figure 10 In the exemplary view, the first raised portion 6A may be substantially disposed in the middle of the left side of the first mounting surface 4A. Typically, the length of the first raised portion 6A along one side of the first mounting surface 4A may be less than about 50% (or about 40%, about 30%, or about 20%) of the length of one side of the first mounting surface 4A.

[0078] Similarly, the second die pad 2B may include a second raised portion 6B that is raised relative to the second mounting surface 4B. The second raised portion 6B may be arranged on the periphery of the second mounting surface 4B opposite to the first raised portion 6A of the first die pad 2A. In other words, raised portions 6A and 6B may be arranged opposite each other or facing each other. In the illustrated case, the second raised portion 6B may have a shape similar to the first raised portion 6A. In other examples, the shapes of the raised portions 6A and 6B may vary depending on the application considered.

[0079] The first die pad 2A may include one or more pull rods 60A disposed on the side of the first die pad 2A opposite to the first raised portion 6A. In the illustrated case, an exemplary number of two pull rods 60A are shown. Similarly, the second die pad 2B may include one or more pull rods 60B disposed on the side of the second die pad 2B opposite to the second raised portion 6B. It should be noted that die pads 2A and 2B do not necessarily include pull rods on the side where the raised portions 6A and 6B are arranged. That is, during the molding process using molding tools, these die pad sides without pull rods may not be mechanically fixed using pull rods, but may be floating or unadjusted, which may result in so-called "molding flash" at the bottom surface of the die pads 2A and 2B. However, as will be discussed later... Figure 13 and 14 As explained, retractable pins can be used for mechanical fixation of die pads during the molding process to avoid unwanted molding flash.

[0080] Figure 11 Another example of a lead frame 1100 according to this disclosure is shown. The first die pad 2A may include another raised portion 6A' raised relative to the first mounting surface 4A and arranged opposite to the raised portion 6A, as previously described. Figure 10 As illustrated in the example. Similarly, the second die pad 2B may include two raised portions 6B, 6B' disposed on opposite sides of the second die pad 2B. Figure 10 In contrast, the die pads 2A and 2B of the lead frame 1100 do not necessarily include tie rods. This may be due to the fact that the die pads 2A and 2B can be mechanically fixed to both sides during the molding process, as combined with Figure 14 As described.

[0081] Now for reference Figure 12 A flowchart of a method according to this disclosure is shown. The method is described in a general manner to qualitatively specify aspects of this disclosure. The method can be used to manufacture a semiconductor device according to this disclosure as described herein. The method can be extended by one or more other aspects, such as any aspect described in conjunction with other examples discussed herein. It should be understood that the timing order of the method steps discussed may be interchanged or changed if it is technically possible and meaningful.

[0082] At position 40, a first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface can be provided. At position 42, a first semiconductor chip can be mounted on the first mounting surface. At position 44, a second die pad including a second mounting surface can be provided. At position 46, a second semiconductor chip can be mounted on the second mounting surface. The second semiconductor chip may include electrical contacts disposed on a top surface of the second semiconductor chip facing away from the second mounting surface. At position 48, the electrical contacts of the second semiconductor chip and the first raised portion of the first die pad can be electrically connected by a first electrical connection element.

[0083] It should be understood that Figure 12 The method may include one or more additional steps. For example, a first power lead may be electrically connected to a power terminal of a first semiconductor chip, and a second power lead may be electrically connected to a power terminal of a second semiconductor chip. Here, the first power lead and the second power lead may be arranged on the same side of the semiconductor device. Return to Reference Figure 2A For example, power leads 8B and 8C can be electrically connected to semiconductor chips 16A and 16B as previously described.

[0084] Now combine Figure 13 Further optional steps of the method for manufacturing a semiconductor device according to this disclosure are described. In the example shown, die pads 2A, 2B can be arranged in an encapsulation tool or molding tool (not shown). For example, die pads 2A, 2B can be similar to Figure 10 This is a part of the lead frame 1000. It should be noted that semiconductor chips can be arranged on the mounting surfaces 4A, 4B of die pads 2A, 2B, which can be interconnected as described in the previous examples. However, for simplicity, in Figure 13 Such a semiconductor chip and its associated electrical interconnects are not shown.

[0085] The first die 2A can be pressed against the surface of the encapsulation tool by means of the first retractable pin 62A. In the example shown, the first die pad 2A can be pushed downward so that the bottom surface 20A of the first die pad 2A can press against the surface of the encapsulation tool, thereby mechanically securing the first die pad 2A. More specifically, the first retractable pin 62A can press against the first raised portion 6A of the first die pad 2A. In a similar manner, the second die pad 2B can be pressed against the surface of the encapsulation tool by means of the second retractable pin 62B. Here, the second retractable pin 62B can press against the second raised portion 6B of the second die pad 2B.

[0086] In the next step, die pads 2A and 2B and retractable pins 62A and 62B are encapsulated by placing encapsulating material 30 in the encapsulation tool. For example, molding material can be injected into the volume of the molding tool containing die pads 2A and 2B. Since the die pads 2A and 2B can be firmly pressed against the inner wall of the encapsulation tool by means of the retractable pins 62A and 62B, no encapsulating material can reach the space between the bottom surfaces 20A and 20B of the die pads 2A and 2B and the tool. In the case of a molding process, undesirable molding flash can therefore be avoided.

[0087] After the device is embedded in the encapsulation material 30, the retractable pins 62A and 62B can be removed (specifically pulled back), wherein recesses can be formed in the main surface 64 of the encapsulation material 30. A first recess can be disposed above a first die pad 2A, and a second recess can be disposed above a second die pad 2B. More specifically, the first recess and the first raised portion 6A can at least partially overlap in a top view of the first die pad 2A (i.e., when viewed in the z-direction). Similarly, the second recess and the second raised portion 6B can at least partially overlap in a top view of the second die pad 2B. (See attached diagram) Figures 15A-15B Exemplary semiconductor devices including recesses formed in an encapsulating material, as discussed in 16A-16B, are disclosed in accordance with this disclosure.

[0088] Figure 14 Other exemplary steps of a method for manufacturing a semiconductor device according to this disclosure are shown. The method steps may be at least partially similar to... Figure 13 The method steps are as follows. In the case shown, die pads 2A and 2B can be similar to... Figure 11 This is part of the lead frame of the lead frame 1100. That is, each die pad 2A, 2B may include two raised portions arranged on opposite sides of the respective die pad. The first die pad 2A can be engaged with the lead frame by pressing a retractable pin 62A against the first raised portion 6A. Figure 13 Similarly, mechanical fastening is used, but now the additional retractable pin 62A' can press against another raised portion 6A' located on the opposite side of the first die pad 2A. In a similar manner, the second die pad 2B can be mechanically fastened by means of two retractable pins 62B, 62B' pressing against the two raised portions 62B, 62B' of the second die pad 2B.

[0089] Now for reference Figure 15A and Figure 15B The diagram shows a perspective bottom view and a cross-sectional side view of a semiconductor device 1500 according to the present disclosure. For example, the semiconductor device 1500 may include a device similar to... Figure 10The lead frame 1000 is a lead frame. In the illustrated case, the die pads 2A and 2B of the lead frame and the semiconductor chip (not shown) disposed thereon can be bonded using the previously described method. Figure 13 The described retractable pin is encapsulated in encapsulating material 30. Therefore, a first recess 66A can be formed in the main surface 64 of the encapsulating material 30, wherein the first recess 66A can be disposed above the first die pad 2A. More specifically, the first recess 66A and the first raised portion 6A can at least partially overlap in a top view of the first die pad 2A (i.e., when viewed in the z-direction). Similarly, a second recess 66B can be formed in the main surface 64 of the encapsulating material 30 above the second die pad 2B. In some non-limiting examples, each of the recesses 66A and 66B can have a depth ranging from about 0.5 μm to about 3 μm.

[0090] Now for reference Figure 16A and Figure 16B The diagram shows a perspective bottom view and a cross-sectional side view of a semiconductor device 1600 according to the present disclosure. For example, the semiconductor device 1600 may include a device similar to... Figure 11 The lead frame of the lead frame 1100. Since the two retractable pins may press against the raised portions 6A, 6A' of the first die pad 2A, the main surface 64 of the encapsulation material 30 may include two recesses 66A, 66A' respectively disposed above the raised portions 6A, 6A'. Similarly, two additional recesses 66B, 66B' can be formed in the main surface 64 of the encapsulation material 30 above the two raised portions 6B, 6B' of the second die pad 2B.

[0091] Example

[0092] In the following description, semiconductor devices, lead frames, systems, and associated manufacturing methods according to the present invention are described by way of example.

[0093] Example 1 is a semiconductor device comprising: a first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface; a first semiconductor chip mounted on the first mounting surface; a second die pad including a second mounting surface; a second semiconductor chip mounted on the second mounting surface and including electrical contacts disposed on a top surface of the second semiconductor chip facing away from the second mounting surface; and a first electrical connection element electrically connecting the electrical contacts of the second semiconductor chip and the first raised portion of the first die pad.

[0094] Example 2 is a semiconductor device according to Example 1, further comprising: a first power lead electrically connected to a power terminal of the first semiconductor chip; and a second power lead electrically connected to a power terminal of the second semiconductor chip, wherein the first power lead and the second power lead are arranged on the same first side of the semiconductor device.

[0095] Example 3 is a semiconductor device according to Example 2, wherein the first power lead and the second power lead are arranged to be directly adjacent to each other.

[0096] Example 4 is a semiconductor device according to Example 2 or 3, wherein one of the first power lead and the second power lead is configured to receive power and / or power voltage, and the other of the first power lead and the second power lead is configured to output current.

[0097] Example 5 is a semiconductor device according to any one of Examples 2-4, further comprising: a third power lead electrically connected to the first semiconductor chip and the second semiconductor chip, wherein the third power lead is disposed adjacent to the first power lead and the second power lead at the first side of the semiconductor device.

[0098] Example 6 is a semiconductor device according to Example 5, wherein the third power supply lead is configured to output power and / or signal.

[0099] Example 7 is a semiconductor device according to any of the foregoing examples, wherein the first semiconductor chip and the second semiconductor chip form part of the low-side switch and the high-side switch of a half-bridge circuit.

[0100] Example 8 is a semiconductor device according to Example 7, wherein: the first power supply lead is electrically connected to the low-side switch, and the second power supply lead is electrically connected to the high-side switch.

[0101] Example 9 is a semiconductor device according to any one of Examples 2, 7-8, wherein each of the first power supply lead and the second power supply lead is a DC terminal of the half-bridge circuit.

[0102] Example 10 is a semiconductor device according to any one of Examples 5, 7-9, wherein the third power supply lead is electrically connected to the switching node of the half-bridge circuit.

[0103] Example 11 is a semiconductor device according to any one of the foregoing examples, wherein: the power supply terminals of the first semiconductor chip and the power supply terminals of the second semiconductor chip are electrically connected only to leads disposed on one side of the semiconductor device, and the logic terminals of the first semiconductor chip and the logic terminals of the second semiconductor chip are electrically connected only to leads disposed on opposite sides of the semiconductor device.

[0104] Example 12 is a semiconductor device according to any one of the foregoing examples, further comprising: an encapsulation material that at least partially encapsulates the first die pad, the second die pad, the first semiconductor chip, and the second semiconductor chip; and a recess formed in the surface of the encapsulation material, wherein the recess is disposed above the first die pad.

[0105] Example 13 is a semiconductor device according to Example 12, wherein the recess and the first raised portion at least partially overlap in a top view of the first die pad.

[0106] Example 14 is a semiconductor device according to any of the foregoing examples, wherein the first raised portion extends along the entire side of the first mounting surface.

[0107] Example 15 is a semiconductor device according to any one of Examples 1-13, wherein the first raised portion extends along a portion of one side of the first mounting surface, wherein the length of the first raised portion along said side of the mounting surface is less than 50% of the length of said side of the mounting surface.

[0108] Example 16 is a semiconductor device according to any one of the preceding examples, wherein: the first die pad includes another raised portion that is raised relative to the first mounting surface, and the first raised portion is disposed on a first side of the first mounting surface, and the other raised portion is disposed on a second side of the first mounting surface opposite to the first side.

[0109] Example 17 is a semiconductor device according to any one of the foregoing examples, further comprising: a third semiconductor chip mounted on the first raised portion.

[0110] Example 18 is a semiconductor device according to Example 17, wherein the third semiconductor chip is a logic semiconductor chip configured to control at least one of the first semiconductor chip or the second semiconductor chip.

[0111] Example 19 is a semiconductor device according to any one of the foregoing examples, wherein each of the first semiconductor chip and the second semiconductor chip is based on silicon carbide.

[0112] Example 20 is a semiconductor device according to any of the preceding examples, wherein the bottom surface of the first die pad opposite to the first mounting surface and the bottom surface of the first raised portion are coplanar.

[0113] Example 21 is a semiconductor device according to any of the preceding examples, wherein: the second die pad includes a second raised portion that is raised relative to the second mounting surface, and the second raised portion is disposed on the periphery of the second mounting surface opposite to the first raised portion of the first die pad.

[0114] Example 22 is a method for manufacturing a semiconductor device, comprising: providing a first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface; mounting a first semiconductor chip on the first mounting surface; providing a second die pad including a second mounting surface; mounting a second semiconductor chip on the second mounting surface, wherein the second semiconductor chip includes electrical contacts disposed on a top surface of the second semiconductor chip facing away from the second mounting surface; and electrically connecting the electrical contacts of the second semiconductor chip and the first raised portion of the first die pad via a first electrical connection element.

[0115] Example 23 is the method according to Example 22, further comprising: electrically connecting a first power lead to a power terminal of the first semiconductor chip; and electrically connecting a second power lead to a power terminal of the second semiconductor chip, wherein the first power lead and the second power lead are arranged on the same side of the semiconductor device.

[0116] Example 24 is a method according to Example 22 or 23, further comprising: arranging the first die pad and the second die pad in an encapsulation tool; pressing the first die pad against the surface of the encapsulation tool by means of a retractable pin; encapsulating the first die pad, the second die pad, and the retractable pin by arranging encapsulation material in the encapsulation tool; and removing the retractable pin, wherein a recess is formed in the surface of the encapsulation material, wherein the recess is arranged above the first die pad.

[0117] Example 25 is the method according to Example 24, wherein: the retractable pin presses against the first raised portion, and the recess and the first raised portion at least partially overlap in a top view of the first die pad.

[0118] Example 26 is a lead frame comprising: a first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface; and a second die pad including a second mounting surface, wherein the first raised portion is disposed on the periphery of the first mounting surface opposite to the second die pad.

[0119] Example 27 is a lead frame according to Example 26, further comprising: a first power lead configured to be electrically connected to a power terminal of a first semiconductor chip mounted on the first mounting surface; and a second power lead configured to be electrically connected to a power terminal of a second semiconductor chip mounted on the second mounting surface, wherein the first power lead and the second power lead are arranged on the same side of the lead frame.

[0120] Example 28 is a lead frame according to Example 26 or 27, wherein: the second die pad includes a second raised portion that is raised relative to the second mounting surface, and the second raised portion is arranged on the periphery of the second mounting surface opposite to the first raised portion of the first die pad.

[0121] Example 29 is a lead frame according to any one of Examples 26-28, wherein the first die pad further includes one or more pull rods arranged on the side of the first die pad opposite to the first raised portion.

[0122] Example 30 is a system comprising: a semiconductor device according to any one of Examples 2-21; a printed circuit board, wherein the semiconductor device is disposed on the printed circuit board, wherein a first power lead is electrically connected to a first conductive trace of the printed circuit board, wherein a second power lead is electrically connected to a second conductive trace of the printed circuit board; and at least one capacitor electrically connected between the first conductive trace and the second conductive trace.

[0123] As used in this specification, the terms “connection,” “coupling,” “electrical connection,” and / or “electrical coupling” do not necessarily mean that the components must be directly connected or coupled together. Intermediate elements may be provided between components that are “connected,” “coupled,” “electrically connected,” or “electrically coupled.”

[0124] Furthermore, the terms "on" or "on" a material layer, for example, formed or located "above" or "on" a surface of an object, can be used herein to mean that the material layer may be directly located (e.g., formed, deposited, etc.) on it, for example, in direct contact with the indicated surface. The terms "on" and "on" a material layer, for example, formed or positioned "on" or "on" a surface, can also be used herein to mean that the material layer may be "indirectly" placed (e.g., formed, deposited, etc.) on the indicated surface, for example, one or more additional layers are arranged between the indicated surface and the material layer.

[0125] Furthermore, with regard to the use of the terms “having,” “comprising,” “including,” “possessing,” or variations thereof in the specific embodiments or claims, these terms are intended to be included in a manner similar to the term “comprising.” That is, as used herein, the terms “having,” “comprising,” “including,” “possessing,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles “a,” “an,” and “the” are intended to include both plural and singular forms.

[0126] Furthermore, the word “exemplary” is used herein to mean as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as superior to other aspects or designs. Rather, the use of the word “exemplary” is intended to present the concept in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated, “X adopts A or B” is intended to indicate any natural inclusive substitution, as is clear from the context. That is, “X adopts A or B” is satisfied in any of the foregoing instances if X adopts A; X adopts B; or X adopts both A and B. Furthermore, the articles “a” and “an” as used in this application and the appended claims can generally be interpreted as meaning “one or more” unless otherwise stated or clearly pointed to from the context in the singular form. In addition, at least one of A and B generally means A or B or both A and B.

[0127] This document describes a device and a method for manufacturing the device. Comments made in connection with the described device may also apply to the corresponding method, and vice versa. For example, if a particular component of the device is described, the corresponding method for manufacturing the device may include the step of providing said component in a suitable manner, even if such a step is not explicitly described or illustrated in the accompanying drawings.

[0128] Although this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art, at least in part, based on a reading and understanding of the description and drawings. This disclosure includes all such modifications and changes and is limited only by the concept of the appended claims. In particular, with respect to the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe such components is intended to correspond to any component that performs the specified function of the described component (e.g., functionally equivalent), even if the disclosed structure is not structurally equivalent to the function performed in the exemplary embodiments of this disclosure described herein. Furthermore, while certain features of this disclosure may have been disclosed with respect to only one of multiple embodiments, such features may be combined with one or more other features of other embodiments, as may be desired and advantageous for any given or particular application.

Claims

1. A semiconductor device, comprising: A first die pad, the first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface; A first semiconductor chip, the first semiconductor chip being mounted on the first mounting surface; The second die pad includes a second mounting surface; A second semiconductor chip is mounted on the second mounting surface and includes electrical contacts disposed on a top surface of the second semiconductor chip facing away from the second mounting surface. as well as A first electrical connection element is electrically connected to the electrical contact of the second semiconductor chip and the first raised portion of the first die pad.

2. The semiconductor device according to claim 1, further comprising: A first power lead is electrically connected to the power terminal of the first semiconductor chip. as well as The second power lead is electrically connected to the power terminal of the second semiconductor chip; The first power lead and the second power lead are arranged on the same first side of the semiconductor device.

3. The semiconductor device according to claim 2, wherein, The first power lead and the second power lead are arranged to be directly adjacent to each other.

4. The semiconductor device according to claim 2 or 3, wherein, One of the first power lead and the second power lead is configured to receive power and / or voltage, and the other of the first power lead and the second power lead is configured to output current.

5. The semiconductor device according to any one of claims 2-4, further comprising: A third power lead is electrically connected to the first semiconductor chip and the second semiconductor chip, wherein the third power lead is arranged on the first side of the semiconductor device adjacent to the first power lead and the second power lead.

6. The semiconductor device according to claim 5, wherein, The third power lead is configured to output power and / or signal.

7. The semiconductor device according to any one of the preceding claims, wherein, The first semiconductor chip and the second semiconductor chip form part of the low-side switch and high-side switch of the half-bridge circuit.

8. The semiconductor device according to claim 7, wherein: The first power lead is electrically connected to the low-side switch; and The second power lead is electrically connected to the high-side switch.

9. The semiconductor device according to any one of claims 7-8, wherein, Each of the first power lead and the second power lead is a DC terminal of the half-bridge circuit.

10. The semiconductor device according to any one of claims 7-9, wherein, The third power supply lead is electrically connected to the switching node of the half-bridge circuit.

11. The semiconductor device according to any one of the preceding claims, wherein: The power supply terminals of the first semiconductor chip and the second semiconductor chip are electrically connected only to leads disposed on one side of the semiconductor device, and The logic terminals of the first semiconductor chip and the logic terminals of the second semiconductor chip are electrically connected only to leads arranged on opposite sides of the semiconductor device.

12. The semiconductor device according to any one of the preceding claims further comprises: Encapsulation material, said encapsulation material at least partially encapsulates the first die pad, the second die pad, the first semiconductor chip, and the second semiconductor chip; as well as A recess is formed in the surface of the encapsulating material, wherein the recess is arranged above the first die pad.

13. The semiconductor device according to claim 12, wherein, The recess and the first raised portion at least partially overlap in a top view of the first die pad.

14. The semiconductor device according to any one of the preceding claims, wherein, The first raised portion extends along the entire side of the first mounting surface.

15. The semiconductor device according to any one of claims 1-13, wherein, The first raised portion extends along a portion of one side of the first mounting surface, wherein the length of the first raised portion along the side of the mounting surface is less than 50% of the length of the side of the mounting surface.

16. The semiconductor device according to any one of the preceding claims, wherein: The first die pad includes another raised portion that is elevated relative to the first mounting surface, and The first raised portion is disposed on the first side of the first mounting surface, and The other raised portion is arranged on the second side of the first mounting surface opposite to the first side.

17. The semiconductor device according to any one of the preceding claims, further comprising: A third semiconductor chip is mounted on the first raised portion.

18. The semiconductor device according to claim 17, wherein, The third semiconductor chip is a logic semiconductor chip configured to control at least one of the first semiconductor chip or the second semiconductor chip.

19. The semiconductor device according to any one of the preceding claims, wherein, Each of the first semiconductor chip and the second semiconductor chip is based on silicon carbide.

20. The semiconductor device according to any one of the preceding claims, wherein, The bottom surface of the first die pad opposite to the first mounting surface and the bottom surface of the first raised portion are coplanar.

21. The semiconductor device according to any one of the preceding claims, wherein: The second die pad includes a second raised portion that is elevated relative to the second mounting surface, and The second raised portion is arranged on the periphery of the second mounting surface opposite to the first raised portion of the first die pad.

22. A method for manufacturing a semiconductor device, comprising: A first die pad is provided, comprising a first mounting surface and a first raised portion that is raised relative to the first mounting surface; A first semiconductor chip is mounted on the first mounting surface; Provides a second die pad including a second mounting surface; A second semiconductor chip is mounted on the second mounting surface, wherein the second semiconductor chip includes electrical contacts disposed on a top surface of the second semiconductor chip facing away from the second mounting surface; as well as The electrical contacts of the second semiconductor chip and the first raised portion of the first die pad are electrically connected via a first electrical connection element.

23. The method of claim 22, further comprising: Connect the first power lead to the power terminal of the first semiconductor chip; as well as Connect the second power supply lead to the power supply terminal of the second semiconductor chip. The first power lead and the second power lead are arranged on the same side of the semiconductor device.

24. The method according to claim 22 or 23, further comprising: The first die pad and the second die pad are arranged in the encapsulation tool; The first die pad is pressed against the surface of the encapsulation tool by means of retractable pins; The first die pad, the second die pad, and the retractable pin are encapsulated by placing encapsulation material in the encapsulation tool; Remove the retractable pin, wherein a recess is formed in the surface of the encapsulation material, wherein the recess is arranged above the first die pad.

25. The method of claim 24, wherein: The retractable pin presses against the first raised portion, and The recess and the first raised portion at least partially overlap in a top view of the first die pad.

26. A lead frame, comprising: A first die pad, the first die pad including a first mounting surface and a first raised portion raised relative to the first mounting surface; as well as The second die pad includes a second mounting surface. The first raised portion is arranged on the periphery of the first mounting surface opposite to the second die pad.

27. The lead frame according to claim 26, further comprising: A first power lead is configured to be electrically connected to a power terminal of a first semiconductor chip mounted on the first mounting surface. A second power lead is configured to be electrically connected to a power terminal of a second semiconductor chip mounted on the second mounting surface. The first power lead and the second power lead are arranged on the same side of the lead frame.

28. The lead frame according to claim 26 or 27, wherein: The second die pad includes a second raised portion that is elevated relative to the second mounting surface, and The second raised portion is arranged on the periphery of the second mounting surface opposite to the first raised portion of the first die pad.

29. The lead frame according to any one of claims 26-28, wherein, The first die pad also includes one or more pull rods arranged on the side of the first die pad opposite to the first raised portion.

30. A system comprising: The semiconductor device according to any one of claims 2-21; A printed circuit board, wherein the semiconductor device is disposed on the printed circuit board; The first power lead is electrically connected to the first conductive trace on the printed circuit board. Wherein, the second power lead is electrically connected to the second conductive trace of the printed circuit board; and At least one capacitor is electrically connected between the first conductive trace and the second conductive trace.

Images