Semiconductor device, semiconductor module, and electronic apparatus

Abstract

A semiconductor device includes a field effect transistor having: a semiconductor; a bonded body containing a transition metal element provided on the semiconductor; and a gate electrode provided on the semiconductor with the bonded body interposed therebetween.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, semiconductor modules, and electronic devices. Background Technology

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes a field-effect transistor (FET). The FET includes a nitride semiconductor layer, an insulating film partially formed on the upper surface of the nitride semiconductor layer, and a gate electrode formed in contact with the exposed upper surface of the nitride semiconductor layer not covered by the insulating film. The insulating film is formed in side contact with the gate electrode. Furthermore, a transition metal is mixed into the insulating film.

[0003] In semiconductor devices constructed in this way, the transition metal mixed in the insulating film forms surface defects and energy levels at the interface between the nitride semiconductor device and the insulating film, as well as in the insulating film near this interface. Holes or electrons are trapped in the surface defects and energy levels. This allows for a reduction in the gate leakage current of the field-effect transistor.

[0004] Reference List

[0005] Patent documents

[0006] Patent Document 1: International Publication No. WO 2019 / 008658 A1 Summary of the Invention

[0007] Incidentally, for semiconductor devices, there is a desire to develop a field-effect transistor that can effectively suppress characteristic changes such as threshold voltage or drain hysteresis in the on-state and effectively suppress gate leakage current (turn-off leakage) in the off-state.

[0008] It is also hoped that semiconductor modules and electronic devices that include such semiconductor devices will be developed.

[0009] The semiconductor device according to a first aspect of this disclosure includes a field-effect transistor. The field-effect transistor includes: a semiconductor; a junction disposed on the semiconductor and including a transition metal element; and a gate electrode disposed on the semiconductor via the junction.

[0010] The semiconductor device according to the second aspect of this disclosure, which is a semiconductor device according to the first aspect, further includes: a main electrode disposed on the semiconductor at a position spaced apart from the gate electrode in the gate length direction; and a passivation film disposed on the semiconductor between the gate electrode and the main electrode. The passivation film comprises a transition metal element.

[0011] Furthermore, in the semiconductor device according to the second aspect, the bonding body and the passivation film each comprise the same transition metal element.

[0012] Furthermore, in the semiconductor device according to the second aspect, the content of the transition metal element included in the bonding body is lower than the content of the transition metal element included in the passivation film.

[0013] A semiconductor module according to a third aspect of this disclosure includes a semiconductor device. The semiconductor device includes a field-effect transistor (FET), the FET comprising: a semiconductor; a junction disposed on the semiconductor and including a transition metal element; and a gate electrode disposed on the semiconductor across the junction.

[0014] An electronic device according to a fourth aspect of this disclosure includes a semiconductor device. The semiconductor device includes a field-effect transistor (FET), the FET comprising: a semiconductor; a junction disposed on the semiconductor and including a transition metal element; and a gate electrode disposed on the semiconductor via the junction. Attached Figure Description

[0015] [ Figure 1 ] Figure 1 This is a vertical cross-sectional view of the main portion of a semiconductor device according to a first embodiment of the present disclosure (along... Figure 2 The cross-section diagram shown in the figure is taken by the cutting line AA.

[0016] [ Figure 2 ] Figure 2 It is a diagram. Figure 1 The diagram shows a plan view of the main components of a semiconductor device.

[0017] [ Figure 3 ] Figure 3 It corresponds to Figure 1 The illustration is a cross-sectional view of the first process of the semiconductor device manufacturing method according to the first embodiment.

[0018] [ Figure 4 ] Figure 4 This is a cross-sectional view of the second process.

[0019] [ Figure 5 ] Figure 5 This is a cross-sectional view of the third process.

[0020] [ Figure 6 ] Figure 6 This is a cross-sectional view of the fourth process.

[0021] [ Figure 7 ] Figure 7 This is a cross-sectional view of the fifth process.

[0022] [ Figure 8 ] Figure 8It is a graph illustrating the relationship between the on / off ratio and the gate voltage in a field-effect transistor mounted on a semiconductor device according to the first embodiment and in a field-effect transistor according to a comparative example.

[0023] [ Figure 9 ] Figure 9 It is a graph illustrating the relationship between the on / off ratio of a field-effect transistor mounted on a semiconductor device according to the first embodiment and the thickness of the junction.

[0024] [ Figure 10 ] Figure 10 This is a table illustrating the atomic composition ratio of the content of transition metal elements in the junction of a field-effect transistor mounted on a semiconductor device according to the first embodiment to the content of transition metal elements in the passivation film.

[0025] [ Figure 11 ] Figure 11 The diagram corresponds to Figure 1 A vertical cross-sectional view of the main part of a semiconductor device according to a second embodiment of the present disclosure.

[0026] [ Figure 12 ] Figure 12 This is a perspective view of a semiconductor module according to a third embodiment of the present disclosure.

[0027] [ Figure 13 ] Figure 13 This is a block diagram illustrating an electronic device according to a fourth embodiment of the present disclosure. Detailed Implementation

[0028] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Note that the description will be given in the following order.

[0029] 1. First Embodiment

[0030] The first embodiment is a first example in which the present technology is applied to a field-effect transistor mounted on a semiconductor device. Here, the planar structure, vertical cross-section structure, and manufacturing method of the field-effect transistor will be described.

[0031] 2. Second Embodiment

[0032] The second embodiment is a second example in which the structure of the gate electrode in the field-effect transistor of the semiconductor device according to the first embodiment is modified.

[0033] 3. Third Embodiment

[0034] The third embodiment is a third example of a semiconductor module equipped with a semiconductor device according to the first or second embodiment.

[0035] 4. Fourth Embodiment

[0036] The fourth embodiment is a fourth example of an electronic device illustrated with a semiconductor device according to the first or second embodiment.

[0037] 5. Other embodiments

[0038] <1. First Embodiment>

[0039] Reference Figures 1 to 10 A semiconductor device 1 and a method of manufacturing the same according to a first embodiment of the present disclosure are described.

[0040] Here, for convenience, the arrow X direction appropriately illustrated in the accompanying drawings represents one planar direction of the semiconductor device 1 placed on a plane. The arrow Y direction represents another planar direction orthogonal to the arrow X direction. Furthermore, the arrow Z direction represents an upward direction orthogonal to both the arrow X and arrow Y directions. That is, the arrow X, arrow Y, and arrow Z directions are aligned only with the X-axis, Y-axis, and Z-axis directions of the three-dimensional coordinate system, respectively.

[0041] Note that each of the above directions is illustrated to aid understanding of the description and does not limit the direction of this technique.

[0042] [Construction of semiconductor device 1 and field-effect transistor 2]

[0043] Figure 1 An example of the cross-sectional structure of a semiconductor device 1 and a field-effect transistor 2 mounted on the semiconductor device 1 according to the first embodiment is illustrated. The cross-sectional structure is as seen in the direction of arrow Y (hereinafter referred to as "in the side view"). Figure 2 The illustration shows an example of a planar configuration of semiconductor device 1 and field-effect transistor 2. The planar configuration is the planar configuration viewed from the direction of arrow Z (hereinafter referred to as "in the planar view").

[0044] (1) Schematic overall structure of semiconductor device 1 and field-effect transistor 2

[0045] like Figure 1 and Figure 2 As illustrated, the semiconductor device 1 according to the first embodiment is constructed using a substrate 3 as a base. Furthermore, the semiconductor device 1 includes a field-effect transistor 2 on the substrate 3. Although a detailed construction will be described later, in the first embodiment, the field-effect transistor 2 is a Schottky junction (Schottky barrier junction) high electron mobility transistor (HEMT).

[0046] The field-effect transistor 2 includes a semiconductor 4, a gate electrode 6, and a pair of main electrodes 7, which are to be used as source and drain electrodes, as shown in the side and plan views. Each component of the field-effect transistor 2 will be described in detail below.

[0047] (2) Structure of substrate 3

[0048] In the first embodiment, the substrate 3 comprises a semiconductor material. Specifically, for example, a semi-insulating single-crystal GaN, which is a group III-V compound semiconductor material, is used as the substrate 3.

[0049] Note that the lattice constant between the substrate 3 and the channel layer 42 can be controlled by using the buffer layer 41 included in the semiconductor 4, which will be described later. In this case, the substrate 3 can be constructed using a material having a lattice constant different from that of the channel layer 42, such as materials like SiC, sapphire, or Si. Alternatively, the substrate 3 can include materials such as SCAM (ScAlMgO4), Ga2O3, AlN, or diamond.

[0050] (3) Structure of semiconductor 4

[0051] like Figure 1 As illustrated, semiconductor 4 is disposed on substrate 3. In the side view, semiconductor 4 is formed by sequentially stacking each of buffer layer 41, channel layer 42, spacer layer 44, barrier layer 45 and cap layer 46 from the surface of substrate 3 toward the direction of arrow Z.

[0052] (3-1) Construction of buffer layer 41

[0053] The buffer layer 41 includes, for example, a compound semiconductor layer. The compound semiconductor layer is formed on the substrate 3 by an epitaxial growth method.

[0054] When the lattice constants of the substrate 3 and the channel layer 42 are different, the lattice constants can be controlled by the buffer layer 41. This allows for improvement in the crystal quality of the channel layer 42. Furthermore, warpage of the substrate 3 after the formation of the channel layer 42 during manufacturing can be controlled. Here, the warpage of the substrate 3 corresponds to the warpage of the semiconductor wafer before the dicing step in the manufacturing process.

[0055] In the case where the substrate 3 comprises single-crystal Si and the channel layer 42 comprises GaN, in the first embodiment, one or more compound semiconductor materials selected from AlN, AlGaN and GaN can be used, for example, for the buffer layer 41.

[0056] In other words, the buffer layer 41 can be formed as a single layer, or can be formed by stacking the above-mentioned various compound semiconductor materials. Additionally, when the buffer layer 41 includes a ternary compound semiconductor material, the buffer layer 41 can be formed in such a manner that the composition ratio gradually changes in the film formation direction.

[0057] Furthermore, the buffer layer 41 can be appropriately doped with impurities such as C or Fe. Doping with impurities enables reduction of buffer leakage and suppression of current collapse.

[0058] Structure of the channel layer 42 (3-2)

[0059] The channel layer 42 includes, for example, a compound semiconductor layer. The compound semiconductor layer is formed on the buffer layer 41 by an epitaxial growth method.

[0060] The channel layer 42 forms a part of the current path between a pair of main electrodes 7. More specifically, a two-dimensional electron gas (2DEG) 43 in which carriers are accumulated is formed in the channel layer 42 due to the difference in the amount of polarized charges between the channel layer 42 and the barrier layer 45 provided on the channel layer 42. Here, the carriers are electrons.

[0061] The channel layer 42 includes, for example, GaN as the compound semiconductor material. GaN can be formed of undoped GaN (u-GaN) without adding impurities. In this case, impurity scattering of carriers in the channel layer 42 can be suppressed and high carrier mobility can be achieved.

[0062] Structure of the spacer layer 44 (3-3)

[0063] The spacer layer 44 includes, for example, a compound semiconductor layer having a bandgap larger than that of the channel layer 42. The compound semiconductor layer is formed on the channel layer 42 by an epitaxial growth method.

[0064] The spacer layer 44 includes, for example, a nitride semiconductor material including AlN. This will be described in detail. In the first embodiment, the spacer layer 44 includes, for example, Al x1 In y1 Ga [1-x1-y1] N (0 < x1 ≤ 1, 0 ≤ y1 < 1, 0 < x1 + y1 ≤ 1). That is, the spacer layer 44 can be formed using AlN as a binary nitride semiconductor material, AlGaN as a ternary nitride semiconductor material, or AlGaInN as a quaternary nitride semiconductor material.

[0065] In the first embodiment, AlN, a binary compound semiconductor material, is formed as a spacer layer 44 in semiconductor 4, located between channel layer 42 and barrier layer 45. According to the field-effect transistor 2 constructed in this manner, the carriers (two-dimensional electron gas 43) induced at the interface between spacer layer 44 and channel layer 42 are less affected by alloy scattering from the barrier layer 45, which includes a ternary compound semiconductor material. In other words, high carrier mobility can be achieved in the field-effect transistor 2.

[0066] (3-4) Construction of barrier layer 45

[0067] Barrier layer 45 includes a compound semiconductor layer that allows charge carriers to accumulate in channel layer 42 through polarization between barrier layer 45 and channel layer 42. The compound semiconductor layer is formed on spacer layer 44 by epitaxial growth.

[0068] The barrier layer 45 comprises a nitride semiconductor material having a band gap larger than that of the channel layer 42. This will be described in detail. The barrier layer 45 comprises, for example, a nitride semiconductor material Al. x In 1-x N (0≤x<1).

[0069] As a compound semiconductor material to be used in barrier layer 45, Al can also be used, for example. 1-x-y In x Ga y N (0≤x<1, 0≤y<1, x+y≤1) is required as long as the compound semiconductor material allows carriers to accumulate at the interface between the channel layer 42 and the spacer layer 44 due to the difference in polarization charge between the barrier layer 45 and the channel layer 42.

[0070] In addition, u-Al without added impurities can be produced. 1-x-y In x Ga y N is used for barrier layer 45. In this case, impurity scattering of carriers in channel layer 42 can be suppressed, thereby enabling high carrier mobility.

[0071] (3-5) Construction of cap layer 46

[0072] A cap layer 46 is stacked on the barrier layer 45. The cap layer 46 is formed, for example, a monolayer of GaN or SiN, or a composite layer obtained by stacking SiN on GaN. In addition, the cap layer 46 may include, for example, a material whose constituent element concentration changes in the thickness direction although it is a monolayer.

[0073] In addition, the cap layer 46 may include, for example, a compound semiconductor material Al. 1-z-w In z Ga wN (0≤z≤1, 0≤w≤1, z+w≤1). In this case, the wafer surface with the epitaxial layer can be protected from the effects of processing or processing history.

[0074] It should be noted that from the perspective of the final expected device characteristics and mass production, a cap layer 46 is not necessarily required.

[0075] (4) Construction of gate electrode 6

[0076] like Figure 1 and Figure 2 As illustrated, a passivation film 5 is disposed on a cap layer 46 of the semiconductor 4, and a gate opening 5H1 penetrating in the thickness direction (arrow Z direction) is provided in the passivation film 5. A gate electrode 6 is disposed on the cap layer 46 of the semiconductor 4, at least in the gate opening 5H1. A portion of the gate electrode 6 extends around the gate opening 5H1 and extends on the passivation film 5.

[0077] In the first embodiment, the gate electrode 6 is formed as a composite layer obtained by sequentially stacking each of Ni and Au from the semiconductor 4 side toward the direction of arrow Z. Note that the gate electrode material of the gate electrode 6 is not limited to this example.

[0078] (5) Construction of main electrode 7

[0079] Each of the main electrodes 7 is disposed on the semiconductor 4 at a position spaced apart from the gate electrode 6 in the gate length direction through a main electrode opening 5H2 formed in the passivation film 5. A pair of main electrodes 7 are disposed around the gate electrode 6 on both sides in the gate length direction. The main electrodes 7 are ohmic electrodes that make ohmic contact with the semiconductor 4. That is, the connection between the main electrodes 7 and the two-dimensional electron gas 43 provides low resistance.

[0080] The main electrode 7 is formed as a composite layer obtained by sequentially stacking each of Ti, Al, Ni and Au from semiconductor 4 toward arrow Z.

[0081] Furthermore, each of the main electrodes 7 is coupled to the two-dimensional electron gas 43 via a high impurity density region 9. The high impurity density region 9 extends from the cap layer 46 to the channel layer 42. In the plan and side views, the high impurity density region 9 is a semiconductor region disposed at the location where the channel layer 42 overlaps with the main electrode 7, having the same conductivity type as the charge carriers flowing through the channel layer 42 and having a higher impurity density than the channel layer 42. In the first embodiment, since electrons flow through the two-dimensional electron gas 43 as charge carriers as described above, the high impurity density region 9 includes an n-type semiconductor region.

[0082] Due to the high impurity density region 9, the connection between the main electrode 7 and the two-dimensional electron gas 43 provides low resistance.

[0083] (6) Construction of active region 10 and component isolation region 11

[0084] like Figure 1 and Figure 2 As illustrated in the side view and plan view, the field-effect transistor 2 is disposed in the active region 10, and the element isolation region 11 is disposed around the side of the field-effect transistor 2.

[0085] The component isolation region 11 is disposed around the side of the active region 10 from the cap layer 46 to the channel layer 42, extending to a position closer to the substrate 3 than the two-dimensional electron gas (2DEG) 43.

[0086] In the first embodiment, the element isolation region 11 is a region with insulating properties provided, for example, by introducing an impurity such as B. For example, ion implantation is used to introduce the impurity.

[0087] (7) Structure of passivation film 5

[0088] In the first embodiment, the passivation film 5 includes a first passivation film 51 disposed on the semiconductor 4 and a second passivation film 52 disposed on the first passivation film 51. Because the gate opening 5H1 and the main electrode opening 5H2 are formed in the passivation film 5, the passivation film 5 is effectively disposed between the gate electrode 6 and the main electrode 7.

[0089] The first passivation film 51 is disposed in contact with the surface of the cap layer 46 of the semiconductor 4. The first passivation film 51 comprises one or more transition metal elements from group III to group XI.

[0090] In the first embodiment, the first passivation film 51 comprises HfOx (x = 2), which contains Hf as a transition metal element. HfO2 is formed with stoichiometry. The first passivation film 51 constructed in this way has insulating properties. Therefore, the first passivation film 51 serves as an interlayer insulator disposed between electrodes, between electrodes and wiring, or between wirings. Furthermore, the first passivation film 51 effectively suppresses or prevents the diffusion of elements included in the second passivation film 52 into the semiconductor 4.

[0091] The first passivation film 51 is formed, for example, greater than or equal to 0.5 nm and less than 7.0 nm.

[0092] It should be noted that as long as the first passivation film 51 has insulating properties, it does not necessarily have a complete stoichiometric composition.

[0093] The second passivation film 52 is stacked on the first passivation film 51. The second passivation film 52 serves as an interlayer insulator disposed between electrodes, between electrodes and wiring, or between wiring.

[0094] The second passivation film 52 may include one or more insulating materials selected from, for example, SiN, Al2O3, and SiO2. The second passivation film 52 is formed as a single layer or composite layer of the selected (one or more) of the above-mentioned insulating materials. The second passivation film 52 is formed, for example, greater than or equal to 10 nm and less than or equal to 200 nm.

[0095] (8) Construction of the joint 8

[0096] In the field-effect transistor 2 constructed in this manner, the gate electrode 6 is disposed on the semiconductor 4 through a bonding body 8 in the gate opening 5H1. In other words, the bonding body 8 is disposed between the cap layer 46 of the semiconductor 4 and the gate electrode 6. Here, this technology includes both the case where the bonding body 8 is disposed at a portion of the interface between the cap layer 46 and the gate electrode 6 and the case where the bonding body 8 is disposed at the entire interface. Note that a portion of the bonding body 8 may be formed to be recessed into the surface portion of the cap layer 46.

[0097] Similar to the first passivation film 51, the junction 8 comprises one or more transition metal elements from Group III to Group XI. In a first embodiment, the junction 8 comprises Hf, a transition metal element similar to that included in the first passivation film 51, and includes HfOx (x≠2). The HfOx is formed with a non-stoichiometric composition (non-stoichiometric). That is, the junction 8 is formed as a conductor rather than an insulator and is bonded to the cap layer 46 of the semiconductor 4 via a Schottky junction. In other words, the gate electrode is bonded to the cap layer 46 of the semiconductor 4 via the Schottky junction through the junction 8. Furthermore, the Schottky junction can be a combination of both.

[0098] In the first embodiment, the junction 8 further includes a transition metal element different from Hf. Here, Ni is included as a transition metal element. Since Ni is included on the junction 8 side of the gate electrode 6 as described above, a portion of this Ni diffuses into the junction 8. Note that no gate electrode material may diffuse into the junction 8.

[0099] Additionally, the conjugate 8 includes pseudomorphic regions and amorphous or non-crystalline regions at the interface with the cap layer 46 of the semiconductor 4. The pseudomorphic and amorphous regions are each included in the interface direction or the thickness direction of the conjugate 8.

[0100] Here, the pseudo-lattice-matched region is used to represent a portion of the junction 8 having a lattice constant that matches the lattice constant of the crystallization of the cap layer 46 within the range of reaching the critical film thickness.

[0101] Furthermore, in the region overlapping with the gate electrode 6, the junction may be formed with a non-uniform thickness compared to the thickness of the cap layer 46 or the barrier layer 45 of the surface layer on the junction side of the semiconductor 4.

[0102] The joint 8 constructed in this way is formed with a thickness of, for example, less than 7 nm. Preferably, the thickness of the joint 8 is less than or equal to 5 nm. More preferably, the thickness of the joint 8 is less than or equal to 3 nm.

[0103] If the thickness of the junction 8 is greater than or equal to 7 nm, the threshold voltage will vary significantly during the operation of the field-effect transistor 2. In cases where the semiconductor device 1 according to the first embodiment is used as, for example, a power amplifier in a mobile terminal, such a variation in threshold voltage is unsuitable for this type of device.

[0104] Furthermore, since the bonding body 8 can be formed with a non-uniform thickness as described above, in the region overlapping with the gate electrode 6, the bonding body 8 can be formed with an average thickness of, for example, greater than or equal to one atomic layer. When described numerically, depending on the selected transition metal element, the thickness of the bonding body 8 of greater than or equal to one atomic layer is, for example, greater than or equal to 0.25 nm.

[0105] [Manufacturing method of semiconductor device 1 and field-effect transistor 2]

[0106] Next, a method for manufacturing the semiconductor device 1 and the field-effect transistor 2 according to the first embodiment will be described. Figures 3 to 7 The illustration shows an example of a process cross-section describing the manufacturing method for each process.

[0107] First, prepare substrate 3 (see Figure 3 As substrate 3, for example, single-crystal Si is used. Although simply referred to as substrate 3, in practice substrate 3 is a semiconductor wafer that includes the formation regions of multiple semiconductor devices 1 before the dicing process.

[0108] like Figure 3 As illustrated, semiconductor 4 is formed on substrate 3. Semiconductor 4 is formed by sequentially stacking each of the following layers from the substrate 3 side toward the direction of arrow Z: buffer layer 41, channel layer 42, spacer layer 44, barrier layer 45, and cap layer 46. Each layer of semiconductor 4 will be described in detail.

[0109] A buffer layer 41 is formed on substrate 3 by an epitaxial growth method. The buffer layer 41 is formed using one or more compound semiconductor layers selected from, for example, AlN, AlGaN, and GaN.

[0110] A channel layer 42 is formed on the buffer layer 41 using an epitaxial growth method. For example, GaN is used as a compound semiconductor layer to form the channel layer 42.

[0111] Spacer layer 44 is formed on channel layer 42 by epitaxial growth method. Spacer layer 44 is formed using a nitride semiconductor material including AlN as a compound semiconductor layer.

[0112] A barrier layer 45 is formed on spacer layer 44 by epitaxial growth. A nitride semiconductor material, for example, is used as a compound semiconductor layer to form barrier layer 45.

[0113] Alternatively, the cap layer 46 is formed by a deposition method selected from epitaxial growth, ALD (atomic layer deposition), and CVD (chemical vapor deposition), the deposition method corresponding to the material to be deposited. For example, in the case where the cap layer 46 is formed using GaN as a compound semiconductor layer, the cap layer 46 is formed by an epitaxial growth method.

[0114] Subsequently, in semiconductor 4, an element isolation region 11 is formed around the active region 10 where the field-effect transistor 2 is to be formed (see [reference]). Figure 4 As described above, insulating properties are provided by selectively introducing materials such as B into the semiconductor 4, for example, through ion implantation, thereby forming the device isolation region 11. When the device isolation region 11 is formed, the active region 10 is formed in a mesa shape.

[0115] like Figure 4 As illustrated in the figure, in the active region 10, a pair of high impurity concentration regions 9 are formed as the source region and the drain region.

[0116] High impurity density regions are formed, for example, through regeneration growth methods.

[0117] Note that a high impurity density region 9 can be formed after the gate electrode 6 is formed.

[0118] like Figure 5 As illustrated, the passivation film 5 is formed over the entire area of ​​the semiconductor 4, including the active region 10 and the device isolation region 11. As described above, the passivation film 5 is formed by sequentially stacking each of the first passivation film 51 and the second passivation film 52.

[0119] A first passivation film 51 is formed on the cap layer 46 using an ALD or CVD method. The first passivation film 51 is formed using, for example, HfO2 comprising transition metal elements. The first passivation film 51 is formed with a thickness of, for example, greater than or equal to 0.5 nm.

[0120] The second passivation film 52 is formed on the first passivation film 51 by ALD or CVD. The second passivation film 52 is formed by using a single layer or composite layer of an insulating material such as SiN.

[0121] like Figure 6As illustrated, in the region where the gate electrode 6 is formed, a portion of the gate opening 5H1 is formed in the second passivation film 52 of the passivation film 5. When a portion of the gate opening 5H1 is formed, the surface of the first passivation film 51, which acts as a substrate, is exposed. The gate opening 5H1 is formed by etching, for example, using a mask 55 formed by photolithography. As an etching method, an anisotropic dry etching or wet etching method is used to effectively suppress the expansion of the opening size.

[0122] Furthermore, because the first passivation film 51 has an etch selectivity ratio relative to the second passivation film 52, the first passivation film 51 also serves as an etch stop layer. That is, when a portion of the gate opening 5H1 is formed in the second passivation film 52, the first passivation film 51 effectively suppresses or prevents etch damage to the surface of the semiconductor 4.

[0123] Subsequently, as Figure 7 As illustrated, a portion of the first passivation film 51 in the thickness direction is etched using an etching method, employing a mask 55 and a portion of the gate opening 5H1 as a mask. Either dry etching or wet etching is used as the etching method.

[0124] When the thickness of the first passivation film 51 decreases from the initial film formation thickness and the effect of etching history is additionally applied, the insulating properties of the first passivation film 51 disappear, and the first passivation film 51 is formed into a conductive bond 8. When the thickness of the first passivation film 51 decreases from the initial film formation thickness by, for example, more than 10%, the insulating properties significantly disappear. As a result, the bond 8 changes into a conductor comprising transition metal elements and having a non-stoichiometric composition.

[0125] Additionally, in forming the bond body 8, a portion of the gate opening 5H1 (the second passivation film 52) serves as a mask. Therefore, the bond body 8 is formed relative to the gate opening 5H1 through self-alignment (self-alignment).

[0126] Note that when the joint body 8 is formed, another part of the gate opening 5H1 that communicates with a part of the gate opening 5H1 is formed, and the gate opening 5H1 is completed.

[0127] After forming the joint 8, the mask 55 is peeled off.

[0128] Subsequently, as described above Figure 1 and Figure 2 As illustrated, a gate electrode 6 is formed. A portion of the gate electrode 6 is electrically coupled and mechanically bonded to the bonding body 8 through a gate opening 5H1. Another portion of the gate electrode 6 extends on the passivation film 5.

[0129] The gate electrode 6 is formed, for example, by mask deposition. In the first embodiment, the gate electrode 6 is formed by sequentially stacking each of Ni and Au. Thus, in the junction 8, although Hf is already included as a transition metal element, Ni of the gate electrode 6 is diffused and further included. Ni is a transition metal element.

[0130] Subsequently, in the region of high impurity density 9, a main electrode opening 5H2 is formed in the passivation film 5 (see...). Figure 1 ). After that, as described above Figure 1 and Figure 2 As illustrated, a pair of main electrodes 7 are formed to be used as source and drain electrodes. The main electrodes 7 are electrically coupled and mechanically bonded to the high impurity density region 9 through the main electrode opening 5H2.

[0131] The main electrode 7 is formed, for example, by sequentially depositing each of Ti, Al, Ni and Au using a mask deposition method.

[0132] When these series of manufacturing processes are completed, the manufacturing method of the semiconductor device 1 and the field-effect transistor 2 according to the first embodiment is finished.

[0133] [Functions and Effects]

[0134] As described above, the semiconductor device 1 according to the first embodiment includes a field-effect transistor 2. The field-effect transistor 2 includes a semiconductor 4 and a junction 8, and further includes a gate electrode 6. The junction 8 is disposed on the semiconductor 4 and includes a transition metal element. The gate electrode 6 is disposed on the semiconductor 4 across the junction 8. In other words, the junction 8 is disposed between the semiconductor 4 and the gate electrode 6.

[0135] The junction 8 is configured to protect the surface of the semiconductor 4, which forms a Schottky contact with the gate electrode 6. This will be described in detail. In the manufacturing method... Figure 6 and Figure 7 In the process of forming a portion of the gate opening 5H1 in the passivation film 5, as illustrated in the figure, the first passivation film 51, which will later be formed as the bonding body 8, effectively suppresses or prevents the diffusion of elements included in the second passivation film 52 into the semiconductor 4. In addition, the first passivation film 51 effectively suppresses or prevents etch damage to the semiconductor 4 caused by the etching used to form a portion of the gate opening 5H1.

[0136] After a portion of the gate opening 5H1 is formed in the second passivation film 52, that is, after effectively suppressing or preventing the diffusion and etching damage of the aforementioned elements, the bonding body 8 is formed from the first passivation film 51 by losing the insulating properties of the first passivation film 51.

[0137] In the Schottky junction HEMT according to the comparative example, during dry etching to form the gate opening, elements included in the passivation film and elements included in the etching gas are incorporated into the semiconductor. The elements incorporated into the semiconductor cause leakage current generated during turn-off operation.

[0138] Furthermore, in the Schottky junction HEMT according to the comparative example, the gate opening is formed by completely removing the passivation film and exposing the semiconductor surface. That is, etching damage occurs on the semiconductor surface, and the Schottky junction HEMT exhibits characteristic changes such as variations in the threshold voltage.

[0139] In the field-effect transistor 2 according to the first embodiment, since the gate electrode 6 is disposed on the semiconductor 4 with the junction 8 in between, the turn-off leakage current can be effectively suppressed.

[0140] Figure 8 This diagram illustrates an example of the relationship between the on / off ratio of a field-effect transistor (FET) and its gate voltage. The horizontal axis represents the gate voltage applied to the gate electrode of the FET. The vertical axis represents the on / off ratio of the FET. The on / off ratio is the ratio between the minimum current value (turn-off current value) and the maximum current value (turn-on current value) flowing through the two-dimensional electron gas 43 controlled by the gate. Additionally, the vertical axis is normalized to the maximum current.

[0141] As from Figure 8 It is clear that the on-off ratio of the field-effect transistor 2 (represented by reference numeral A) according to the first embodiment is about three to four orders of magnitude smaller than that of the Schottky junction HEMT (represented by reference numeral B) according to the comparative example.

[0142] also, Figure 9 The illustration shows an example of the relationship between the on / off ratio of the field-effect transistor 2 and the thickness of the first passivation film 51 formed before the bonding body 8 is formed. The horizontal axis represents the thickness of the first passivation film 51 during its formation. The vertical axis represents the on / off ratio of the field-effect transistor 2 after the bonding body 8 is formed from the first passivation film 51. Here, the on / off ratio is the current in the off state / the current in the on state.

[0143] like Figure 9 As illustrated, when the thickness of the first passivation film 51 during its formation is, for example, 0.5 nm, the on / off ratio of the field-effect transistor 2, including the junction 8 formed from the first passivation film 51, is 10. -5 .

[0144] When the thickness of the first passivation film 51 during its formation is, for example, 1.0 nm, the on / off ratio of the field-effect transistor 2, including the junction 8 formed from the first passivation film 51, is 10. -6 .

[0145] When the thickness of the first passivation film 51 during its formation is, for example, 2.0 nm, the on / off ratio of the field-effect transistor 2, including the junction 8 formed from the first passivation film 51, is 10. -8 .

[0146] For example, when the semiconductor device 1 including the field-effect transistor 2 is used as a power amplifier of a mobile terminal, the power amplifier of the mobile terminal is required to have a strength greater than or equal to 10. -6 The on / off ratio is thus achieved. Therefore, in the semiconductor device 1 to be installed on a mobile terminal, when the first passivation film 51 is formed with a thickness of, for example, 1.0 nm, the field-effect transistor 2 including the junction 8 formed from the first passivation film 51 can achieve the desired on / off ratio.

[0147] In addition, such as Figure 1 As illustrated, field-effect transistor 2 is constructed as a Schottky junction HEMT. That is, junction 8 is not an insulator, and field-effect transistor 2 does not act as a MIS (metal-insulator-semiconductor) HEMT. Therefore, field-effect transistor 2 does not exhibit characteristic variations such as the threshold voltage changes that occur in MIS HEMTs.

[0148] Furthermore, in field-effect transistor 2, such as Figure 1 As illustrated, the junction 8 is formed with a thickness of less than 7 nm. This allows for effective suppression or prevention of threshold voltage variations during operation of the field-effect transistor 2. Therefore, a semiconductor device 1 suitable for a mobile terminal device can be constructed.

[0149] Furthermore, in field-effect transistor 2, such as Figure 1 As illustrated, the thickness of the bonding body 8 is non-uniform compared to the thickness of the surface layer of the semiconductor 4 on the side of the bonding body 8 (i.e., the thickness of the cap layer 46). Furthermore, in the region overlapping with the gate electrode 6, the bonding body 8 is formed with an average thickness greater than or equal to one atomic layer.

[0150] Therefore, even if the thickness of the junction 8 is non-uniform, a field-effect transistor 2 can still be provided, as long as the junction 8 is formed to be greater than or equal to one atomic layer, the above-mentioned functions and effects can be achieved.

[0151] Furthermore, in field-effect transistor 2, such as Figure 1 As illustrated, the junction 8 comprises one or more transition metal elements from Group III to Group XI. Furthermore, the junction 8 comprises a non-stoichiometric composition. In a first embodiment, the junction 8 comprises at least Hf as a transition metal element. Additionally, the junction 8 comprises HfOx (x≠2).

[0152] The aforementioned functions and effects can be achieved using the field-effect transistor 2 constructed in this manner.

[0153] Furthermore, in field-effect transistor 2, such as Figure 1 As illustrated, the gate electrode 6 comprises a transition metal element, and the junction 8 comprises the transition metal element included in the gate electrode 6. In a first embodiment, the gate electrode 6 comprises Ni, and the junction 8 comprises Hf and Ni.

[0154] The aforementioned functions and effects can be achieved using the field-effect transistor 2 constructed in this manner.

[0155] Furthermore, in the semiconductor device 1 according to the first embodiment, such as Figure 1 and Figure 2 As illustrated, the field-effect transistor 2 includes a main electrode 7. The main electrode 7 is disposed on the semiconductor 4 at a position spaced apart from the gate electrode 6 in the gate length direction. Here, a pair of main electrodes 7 are disposed. Furthermore, a passivation film 5 is disposed on the semiconductor 4 between the gate electrode 6 and the main electrodes 7.

[0156] Here, in the first embodiment, the passivation film 5 is formed by sequentially stacking each of the first passivation film 51 and the second passivation film 52. The first passivation film 51 comprises a transition metal element. The transition metal element included in the bonding body 8 is the same as the transition metal element included in the first passivation film 51.

[0157] According to the semiconductor device 1 constructed in this manner, such as the manufacturing method Figures 5 to 7 As illustrated, the first passivation film 51 is formed as an insulator, but the junction 8 can be formed using the first passivation film 51. This allows the field-effect transistor 2 to achieve the aforementioned functions and effects to be constructed with a simple structure.

[0158] Furthermore, from the viewpoint of manufacturing method, since the bonding body 8 is formed using the previously formed first passivation film 51, the number of manufacturing steps can be reduced compared to the case where the bonding body 8 and the first passivation film 51 are formed separately.

[0159] Note that the first passivation film 51 corresponds to the "passivation film" according to the present technology.

[0160] Furthermore, in semiconductor device 1, such as Figure 1 As illustrated, the content (a) of transition metal elements included in the junction 8 of the field-effect transistor 2 is lower than the content (b) of transition metal elements included in the first passivation film 51.

[0161] Figure 10An example of the relationship between the on / off ratio and the content of transition metal elements included in the junction 8 (a) and the content of transition metal elements included in the first passivation film 51 (b) ((b) / (a)) is illustrated.

[0162] The figure here illustrates the ratio of Group III elements to transition metal elements present on the surface of semiconductor 4. This atomic composition ratio was measured using scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDX). The Noran System 7, available from Thermo Fisher Scientific Inc., was used as the analyzer and analysis software.

[0163] In addition, group III elements include, for example, Ga included in the cap layer 46, or Al or In included in the barrier layer 45.

[0164] like Figure 10 As illustrated in the diagram, for Al, a group III element, for example, if the atomic composition ratio of content (a) to content (b) is 1.60, then the turn-on / turn-off ratio is 10. -6 Below. In contrast, if the atomic composition ratio is 2.69, the turn-on / turn-off ratio exceeds 10. -6 The following is not suitable for mobile terminal devices.

[0165] Furthermore, for In, which is a Group III element, for example, if the atomic composition ratio of content (a) to content (b) is 1.84, then the turn-on / turn-off ratio is 10. -6 Below. In contrast, if the atomic composition ratio is 2.69, the turn-on / turn-off ratio exceeds 10. -6 The following are similarly unsuitable for mobile terminal devices.

[0166] In other words, the atomic composition ratio of the content (a) of the transition metal element included in the conjugate 8 to the content (b) of the transition metal element included in the first passivation film 51 is set to be less than 2.7.

[0167] Based on the semiconductor device 1 constructed in this way, a field-effect transistor 2 that achieves the above-mentioned functions and effects can be constructed.

[0168] Furthermore, in semiconductor device 1, such as the manufacturing method Figure 1 or Figure 6 and Figure 7As illustrated, the thickness of the junction 8 from the semiconductor 4 is more than 10% thinner than the thickness of the first passivation film 51 from the semiconductor 4.

[0169] By thinning the first passivation film 51, the insulating properties disappear. Therefore, the bonding body 8 can be easily formed from the first passivation film 51.

[0170] <2. Second Embodiment>

[0171] Reference Figure 11 The semiconductor device 1 and the field-effect transistor 2 according to a second embodiment of the present disclosure are described.

[0172] Note that in the second embodiment and the following description, components that are the same or substantially the same as those in the first embodiment are indicated by the same reference numerals, and redundant descriptions are omitted.

[0173] [Construction of semiconductor device 1 and field-effect transistor 2]

[0174] Figure 11 An example of the cross-sectional structure of a semiconductor device 1 and a field-effect transistor 2 mounted on the semiconductor device 1 according to a second embodiment is illustrated.

[0175] like Figure 11 As illustrated, the field-effect transistor 2 also includes a junction formation layer 80 between the gate electrode 6 and the junction 8. The junction formation layer 80 absorbs some of the elements included in the first passivation film 51 and forms the junction 8, which includes a non-stoichiometric composition, from the first passivation film 51.

[0176] This will be described in detail. In the second embodiment, the bonding layer 80 comprises, for example, Ti. Furthermore, the first passivation film 51 comprises, for example, HfO2, as in the first passivation film 51 according to the first embodiment.

[0177] As in the manufacturing method according to the first embodiment Figure 6 As illustrated in the diagram, after forming the gate opening 5H1 and exposing the first passivation film 51 through the gate opening 5H1, a bonding layer 80 is formed on the first passivation film 51. Subsequently, a gate electrode 6 is formed on the first passivation film 51 through the bonding layer 80. After this, an annealing process and a sintering process are performed.

[0178] When such a manufacturing method is used, the Ti of the bond formation layer 80 absorbs oxygen from the first passivation film 51. Therefore, the first passivation film 51, disposed in the region overlapping with the gate opening 5H1, is formed as a bond 8 comprising a non-stoichiometric composition. That is, in the second embodiment, the dry etching process according to the manufacturing method of the first embodiment is not required.

[0179] The bonding layer 80 is not limited to Ti, as long as it has a similar function. For example, Zn, Bi, Co, Cr, Mn, etc. can be used as the bonding layer 80.

[0180] Since the components other than those described above are the same or substantially the same as the components of the semiconductor device 1 and the field-effect transistor 2 according to the first embodiment described above, their description is omitted here.

[0181] [Functions and Effects]

[0182] The semiconductor device 1 and field-effect transistor 2 according to the second embodiment enable the realization of similar functions and effects as those achieved by the semiconductor device 1 and field-effect transistor 2 according to the first embodiment described above.

[0183] In addition, such as Figure 11 As illustrated, the field-effect transistor 2 also includes a junction formation layer 80 between the gate electrode 6 and the junction 8. The junction formation layer 80 absorbs some of the elements included in the first passivation film 51 and forms the junction 8, which includes a non-stoichiometric composition, from the first passivation film 51.

[0184] Therefore, the dry etching process in the manufacturing method of the field-effect transistor 2 can be reduced, which can improve manufacturing yield.

[0185] <3. Third Embodiment>

[0186] Reference Figure 12 A semiconductor module 100 according to a third embodiment of the present disclosure is described. Figure 12 The illustration shows a schematic structure of a semiconductor module 100 according to a third embodiment.

[0187] [Structure of Semiconductor Module 100]

[0188] The semiconductor module 100 according to the third embodiment is an antenna integration module, including, for example, an edge antenna 101 arranged in an array and a front-end assembly, both of which are mounted as a single module on a substrate 110. The front-end assembly includes, for example, a switch 102, a low-noise amplifier 103, a bandpass filter 104, and a power amplifier 105. The semiconductor module 100 can be used as, for example, a communication transceiver.

[0189] The semiconductor module 100 includes a semiconductor device 1 according to either the first embodiment or the second embodiment, such as a transistor included in a switch 102, a low-noise amplifier 103 or a power amplifier 105.

[0190] [Functions and Effects]

[0191] In the semiconductor module 100 according to the third embodiment, shutdown leakage in wireless communication can be effectively suppressed because it includes the semiconductor device 1.

[0192] <4. Fourth Embodiment>

[0193] Reference Figure 13 A wireless communication device (electronic device) 300 according to a fourth embodiment of the present disclosure is described. Figure 13 The illustration shows a schematic block diagram of the wireless communication device 300 according to the fourth embodiment.

[0194] [Structure of wireless communication device 300]

[0195] The wireless communication device 300 according to the fourth embodiment includes an antenna ANT, an antenna switch circuit 301, a high-power amplifier HPA, a radio frequency integrated circuit (RFIC), a baseband unit BB, a voice output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F includes, for example, wireless LAN (W-LAN: wireless local area network), Bluetooth (registered trademark), etc. The wireless communication device 300 is, for example, a mobile phone system having many functions such as voice or data communication or LAN connection.

[0196] The wireless communication device 300 includes a semiconductor device 1 according to either the first embodiment or the second embodiment, such as an antenna switch circuit 301, a high power amplifier HPA, a radio frequency integrated circuit RFIC, or a transistor included in the baseband section BB.

[0197] [Work and Results]

[0198] In the wireless communication device 300 according to the fourth embodiment, shutdown leakage in wireless communication can be effectively suppressed because it includes the semiconductor device 1.

[0199] <5. Other Embodiments>

[0200] This technology is not limited to the above embodiments, and various modifications can be made to this technology without departing from its spirit.

[0201] For example, in the above embodiments, the semiconductor includes a GaN-based compound semiconductor material. In this technology, the semiconductor may include a GaAs-based compound semiconductor material.

[0202] As described above, the semiconductor device according to the first aspect of this disclosure includes a field-effect transistor. The field-effect transistor includes: a semiconductor; a junction disposed on the semiconductor and including a transition metal element; and a gate electrode disposed on the semiconductor across the junction.

[0203] Semiconductor devices constructed in this way can effectively suppress turn-off leakage of field-effect transistors.

[0204] The semiconductor device according to the second aspect of this disclosure, which is a semiconductor device according to the first aspect, further includes: a main electrode disposed on the semiconductor at a position spaced apart from the gate electrode in the gate length direction; and a passivation film disposed on the semiconductor between the gate electrode and the main electrode. The passivation film comprises a transition metal element.

[0205] Furthermore, in the semiconductor device according to the second aspect, the bonding body and the passivation film each comprise the same transition metal element.

[0206] Furthermore, in the semiconductor device according to the second aspect, the content of the transition metal element included in the bonding body is lower than the content of the transition metal element included in the passivation film.

[0207] Based on the semiconductor device constructed in this way, junctions can be easily formed and turn-off leakage of field-effect transistors can be effectively suppressed.

[0208] A semiconductor module according to a third aspect of this disclosure includes a semiconductor device. The semiconductor device includes a field-effect transistor (FET), the FET comprising: a semiconductor; a junction disposed on the semiconductor and including a transition metal element; and a gate electrode disposed on the semiconductor across the junction.

[0209] Therefore, field-effect transistors that can effectively suppress turn-off leakage can be used to construct semiconductor modules.

[0210] An electronic device according to a fourth aspect of this disclosure includes a semiconductor device. The semiconductor device includes a field-effect transistor (FET), the FET comprising: a semiconductor; a junction disposed on the semiconductor and including a transition metal element; and a gate electrode disposed on the semiconductor via the junction.

[0211] Therefore, field-effect transistors that can effectively suppress turn-off leakage can be used to construct electronic devices.

[0212] <Construction of this technology>

[0213] This technology includes the following structure. According to this technology having the following structure, turn-off leakage of field-effect transistors in semiconductor devices, semiconductor modules, and electronic devices can be effectively suppressed. (1)

[0215] A semiconductor device, including a field-effect transistor,

[0216] The field-effect transistor includes:

[0217] semiconductor;

[0218] A bonding agent disposed on a semiconductor and comprising a transition metal element; and

[0219] The gate electrode is disposed on the semiconductor via a junction. (2)

[0221] According to the semiconductor device described in (1), wherein

[0222] The junction is bonded to the semiconductor via a Schottky junction, or

[0223] The gate electrode is bonded to the semiconductor via a Schottky junction through a junction body. (3)

[0225] The semiconductor device according to (1) or (2) wherein the thickness of the junction from the semiconductor is less than 7 nm. (4)

[0227] According to the semiconductor device of (3), in the region overlapping with the gate electrode, the average thickness of the junction is greater than or equal to one atomic layer. (5)

[0229] According to the semiconductor device described in (4), in the region overlapping with the gate electrode, the thickness of the junction is not uniform compared to the thickness of the surface layer on the junction side of the semiconductor. (6)

[0231] The semiconductor device according to any one of (1) to (5), wherein the junction comprises a non-stoichiometric composition. (7)

[0233] The semiconductor device according to any one of (1) to (6), wherein the junction comprises one or more transition metal elements from Group III to Group XI. (8)

[0235] The semiconductor device according to any one of (1) to (7) wherein the junction comprises one or more transition metal elements selected from Hf and Ni. (9)

[0237] According to the semiconductor device of (8), the junction comprises HfOx (where x≠2). (10)

[0239] The semiconductor device according to any one of (1) to (9), wherein

[0240] The gate electrode includes transition metal elements, and

[0241] The junction includes the transition metal element included in the gate electrode. (11)

[0243] The semiconductor device according to any one of (1) to (10) wherein the junction includes a pseudo-lattice matching region and an amorphous region at the interface with the semiconductor in the interface direction or in the thickness direction of the junction. (12)

[0245] The semiconductor device according to any one of (1) to (11), wherein

[0246] Semiconductors include III-V compound semiconductors, and

[0247] Field-effect transistors include Schottky junction high electron mobility transistors. (13)

[0249] The semiconductor device according to any one of (1) to (12) further includes:

[0250] The main electrode is disposed on the semiconductor at a position spaced apart from the gate electrode along the gate length direction; and

[0251] A passivation film is disposed on the semiconductor between the gate electrode and the main electrode, wherein...

[0252] The passivation film includes transition metal elements. (14)

[0254] According to the semiconductor device described in (13), the bonding body and the passivation film each comprise the same transition metal element. (15)

[0256] According to the semiconductor device of (14), the content of the transition metal element included in the junction is lower than the content of the transition metal element included in the passivation film. (16)

[0258] According to the semiconductor device described in (15), wherein,

[0259] The semiconductor includes group III elements, and

[0260] For Group III elements, the atomic ratio of the transition metal content in the conjugate to the transition metal content in the passivation film is less than 2.7. (17)

[0262] The semiconductor device according to any one of (13)-(16) wherein the thickness of the junction from the semiconductor is more than 10% thinner than the thickness of the passivation film from the semiconductor. (18)

[0264] The semiconductor device according to any one of (1) to (17) further includes:

[0265] A bonding layer is formed between the gate electrode and the bonding body, wherein...

[0266] The bonding layer absorbs a portion of the elements contained in the passivation film, and the passivation film forms a bonding layer comprising a non-stoichiometric composition. (19)

[0268] A semiconductor module includes a semiconductor device.

[0269] The semiconductor device includes a field-effect transistor, which includes:

[0270] semiconductor;

[0271] A bonding agent, disposed on the semiconductor and comprising a transition metal element; and

[0272] The gate electrode is disposed on the semiconductor via a junction. (20)

[0274] An electronic device, including a semiconductor device,

[0275] The semiconductor device includes a field-effect transistor, which includes:

[0276] semiconductor;

[0277] A bonding agent, disposed on the semiconductor and comprising a transition metal element; and

[0278] The gate electrode is disposed on the semiconductor via the junction.

[0279] This application claims the benefit of Japanese priority patent application JP2023-123546, filed with the Japan Patent Office on July 28, 2023, the entire contents of which are incorporated herein by reference.

[0280] Those skilled in the art will understand that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A semiconductor device, comprising a field-effect transistor, The field-effect transistor includes: semiconductor; A bonding assembly disposed on the semiconductor and comprising a transition metal element; as well as A gate electrode is disposed on the semiconductor via the junction.

2. The semiconductor device according to claim 1, wherein, The junction is bonded to the semiconductor via a Schottky junction, or The gate electrode is bonded to the semiconductor via a Schottky junction, with the junction body in between.

3. The semiconductor device according to claim 1, wherein, The thickness of the junction from the semiconductor is less than 7 nm.

4. The semiconductor device according to claim 3, wherein, In the region overlapping with the gate electrode, the average thickness of the junction is greater than or equal to one atomic layer.

5. The semiconductor device according to claim 4, wherein, In the region overlapping with the gate electrode, the thickness of the junction is not uniform compared to the thickness of the surface layer on the junction side of the semiconductor.

6. The semiconductor device according to claim 1, wherein, The conjugate comprises a non-stoichiometric composition.

7. The semiconductor device according to claim 1, wherein, The conjugate comprises one or more transition metal elements from Group III to Group XI.

8. The semiconductor device according to claim 1, wherein, The bonding body includes one or more transition metal elements selected from Hf and Ni.

9. The semiconductor device according to claim 8, wherein, The conjugate comprises HfOx, where x ≠ 2.

10. The semiconductor device according to claim 7, wherein, The gate electrode comprises a transition metal element, and The junction comprises a transition metal element contained in the gate electrode.

11. The semiconductor device according to claim 1, wherein, The junction includes a pseudo-lattice matching region and an amorphous region at the interface with the semiconductor in the interface direction or in the thickness direction of the junction.

12. The semiconductor device according to claim 1, wherein, The semiconductor includes III-V compound semiconductors, and The field-effect transistor includes a Schottky junction high electron mobility transistor.

13. The semiconductor device according to claim 1, further comprising: The main electrode is disposed on the semiconductor at a position spaced apart from the gate electrode in the gate length direction; as well as A passivation film is disposed on the semiconductor between the gate electrode and the main electrode, wherein... The passivation film comprises transition metal elements.

14. The semiconductor device according to claim 13, wherein, The bonding body and the passivation film each comprise the same transition metal element.

15. The semiconductor device according to claim 14, wherein, The content of transition metal elements contained in the bonding body is lower than the content of transition metal elements contained in the passivation film.

16. The semiconductor device according to claim 15, wherein, The semiconductor includes group III elements, and For the group III elements, the atomic ratio of the transition metal element content in the conjugate to the transition metal element content in the passivation film is less than 2.

7.

17. The semiconductor device according to claim 13, wherein, The thickness of the bonding body from the semiconductor is more than 10% thinner than the thickness of the passivation film from the semiconductor.

18. The semiconductor device of claim 13, further comprising: A bonding layer is formed between the gate electrode and the bonding body, wherein... The bonding layer absorbs a portion of the elements contained in the passivation film, and the passivation film forms the bonding layer comprising a non-stoichiometric composition.

19. A semiconductor module, comprising a semiconductor device, The semiconductor device includes a field-effect transistor, the field-effect transistor comprising: semiconductor; A bonding assembly disposed on the semiconductor and comprising a transition metal element; as well as A gate electrode is disposed on the semiconductor via the junction.

20. An electronic device, comprising a semiconductor device, The semiconductor device includes a field-effect transistor, the field-effect transistor comprising: semiconductor; A bonding assembly disposed on the semiconductor and comprising a transition metal element; as well as A gate electrode is disposed on the semiconductor via the junction.

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