Answer signal collector suitable for TACAN signal test
By designing a response signal acquisition device suitable for TACAN signal testing, and utilizing the collaborative operation of multiple circuits to automatically switch test logic and provide clean signal input, the problems of cumbersome instrument combinations and human error in traditional TACAN signal testing are solved, thus achieving efficient and accurate TACAN equipment testing.
Patent Information
- Application Number
- CN202511812425.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-04
- Publication Date
- 2026-02-24
AI Technical Summary
In traditional TACAN signal testing, the response signal acquisition unit needs to be used in conjunction with a frequency meter, which makes the instrument combination cumbersome and the setup process complicated. Operators need to manually adjust parameters and record data, resulting in low testing efficiency and susceptibility to human error.
Design a response signal acquisition device suitable for TACAN signal testing, including a mode selection circuit, a main reference synchronization circuit, an auxiliary reference synchronization circuit, an interrogation pulse circuit, a half-amplitude pulse circuit, a detector pulse circuit, a response pulse circuit, and an MCU main control circuit. Through the coordinated work of these circuits, the test logic is automatically switched to provide a clean signal input and ensure the accuracy and reliability of pulse counting.
It has achieved automation and efficiency in TACAN equipment testing, reduced manual intervention, improved test quality and reliability, and ensured the accuracy of signal counting and the portability of the equipment.
Smart Images
Figure CN121558072A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal testing technology, and in particular to a response signal acquisition device suitable for TACAN signal testing. Background Technology
[0002] As a core device in the field of aviation navigation, the accurate testing of the TACAN system's receiver parameters directly affects navigation accuracy and flight safety. In traditional TACAN receiver parameter testing, the response signal acquisition unit needs to be used in conjunction with a frequency counter to complete the output signal counting. This results in cumbersome instrument combinations and complex setup procedures. Operators need to debug the acquisition unit and frequency counter parameters separately and manually record and verify the data, which not only leads to low testing efficiency but also makes the reliability of the results susceptible to human error. Summary of the Invention
[0003] The technical problem to be solved by this invention is to provide a response signal acquisition device suitable for TACAN signal testing, thereby improving the quality and reliability of TACAN equipment testing.
[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A response signal acquisition device suitable for TACAN signal testing includes a mode selection circuit, a main reference synchronization circuit, an auxiliary reference synchronization circuit, an interrogation pulse circuit, a half-amplitude pulse circuit, a detection pulse circuit, a response pulse circuit, a signal acquisition circuit, and an MCU main control circuit. The MCU main control circuit is electrically connected to the mode selection circuit, half-amplitude pulse circuit, main reference synchronization circuit, auxiliary reference synchronization circuit, response pulse circuit and signal acquisition circuit respectively. The signal acquisition circuit is electrically connected to the main reference synchronization circuit, auxiliary reference synchronization circuit, interrogation pulse circuit, detection pulse circuit and response pulse circuit respectively.
[0005] The beneficial effects of this invention are as follows: This solution uses a mode selection circuit as a switch to change the test scenario. It receives mode commands from the operator and transmits them to the MCU main control circuit, providing a direct basis for the MCU main control circuit to determine the test logic to be executed, avoiding the cumbersome manual switching of multiple instrument modes in traditional testing. The main reference synchronization circuit and the auxiliary reference synchronization circuit respectively receive and transmit the main and auxiliary reference synchronization signals from the TACAN system. After filtering out line interference, the signals are input to the signal acquisition circuit, providing a clean signal source for the MCU main control circuit to count the main reference pulse count and the auxiliary reference pulse count. Simultaneously, in the pulse test scenario, in conjunction with the signal output from the detector pulse circuit, it helps the MCU main control circuit to accurately count the detector pulse count, the main reference pulse count, and the auxiliary reference pulse count, realizing the pulse test function. The interrogation pulse circuit directionally transmits external interrogation pulse signals, ensuring no amplitude attenuation or waveform distortion, providing a stable trigger signal for the MCU main control circuit. In the receiving index test scenario, this interrogation pulse works in conjunction with the detector signal output from the detector pulse circuit, becoming the MCU main control circuit's method for selecting response pulses and counting interrogation and response pulses. The core triggering mechanism consists of: a half-amplitude pulse circuit that specifically receives and transmits half-amplitude pulse signals to ensure amplitude stability; a half-amplitude pulse circuit that, in receiver component testing scenarios, works in conjunction with the output signal of the interrogation pulse circuit to provide reliable input for the MCU main control circuit to count interrogation pulses and the corresponding number of half-amplitude pulses, meeting component testing requirements; a detection pulse circuit that serves as the basic signal channel for all scenarios, receiving and initially filtering the detection pulse signal output by the TACAN system, providing detection pulse signals for pulse testing scenarios and a clean original signal source for the MCU main control circuit to screen response pulses in receiver performance testing scenarios, reducing interference from noise; a response pulse circuit that initially separates response pulses from mixed signals, suppressing non-response pulse interference, reducing the processing load of the signal acquisition circuit, and providing a preliminary guarantee for the MCU main control circuit to accurately identify response pulses; and a signal acquisition circuit that serves as the signal processing center, amplifying, shaping, and performing logical operations on the signals input from each circuit, transmitting the processed digital signals to the MCU main control circuit, ensuring that the signals acquired by the MCU main control circuit meet the counting and logical judgment requirements. The data acquisition unit designed in this scheme integrates screening and counting functions through deep collaboration between various functional circuits and the MCU main control circuit. The MCU main control circuit automatically switches the test logic according to the mode command without manual intervention. At the same time, each circuit provides a clean and stable signal input to the MCU main control circuit, ensuring the accuracy of the screening response pulses and the precision of various pulse counts, thereby significantly improving the quality and reliability of TACAN equipment testing. Attached Figure Description
[0006] Figure 1 This is a connection block diagram of the response signal acquisition device for TACAN signal testing according to the present invention; Figure 2The circuit diagram shows the signal acquisition circuit, interrogation pulse circuit, and detection pulse circuit of the response signal acquisition device for TACAN signal testing according to the present invention. Figure 3 The circuit diagram shows the signal acquisition circuit, main reference synchronization circuit, auxiliary reference synchronization circuit, and response pulse circuit of the response signal acquisition device for TACAN signal testing according to the present invention. Figure 4 The circuit diagram shows the detection pulse circuit of the response signal acquisition device for TACAN signal testing according to the present invention. Figure 5 The circuit diagram shows the MCU main control circuit of the response signal acquisition device for TACAN signal testing according to the present invention. Figure 6 The circuit diagram shows the power supply circuit of the response signal acquisition device for TACAN signal testing according to the present invention. Figure 7 This is a circuit diagram of the display circuit of the response signal acquisition device for TACAN signal testing according to the present invention; Label Explanation: 1. Mode selection circuit; 2. Main reference synchronization circuit; 3. Auxiliary reference synchronization circuit; 4. Interrogation pulse circuit; 5. Half-amplitude pulse circuit; 6. Detection pulse circuit; 7. Response pulse circuit; 8. Signal acquisition circuit; 9. MCU main control circuit; 10. Display circuit; 11. Power supply circuit. Detailed Implementation
[0007] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0008] Please refer to Figure 1 A response signal acquisition device suitable for TACAN signal testing includes a mode selection circuit 1, a main reference synchronization circuit 2, an auxiliary reference synchronization circuit 3, an interrogation pulse circuit 4, a half-amplitude pulse circuit 5, a detection pulse circuit 6, a response pulse circuit 7, a signal acquisition circuit 8, and an MCU main control circuit 9. The MCU main control circuit 9 is electrically connected to the mode selection circuit 1, the half-amplitude pulse circuit 5, the main reference synchronization circuit 2, the auxiliary reference synchronization circuit 3, the response pulse circuit 7, and the signal acquisition circuit 8, respectively. The signal acquisition circuit 8 is electrically connected to the main reference synchronization circuit 2, the auxiliary reference synchronization circuit 3, the interrogation pulse circuit 4, the detection pulse circuit 6, and the response pulse circuit 7, respectively.
[0009] As can be seen from the above description, the beneficial effects of the present invention are as follows: This solution uses mode selection circuit 1 as a test scenario switch, receiving mode commands from the operator and transmitting them to the MCU main control circuit 9. This provides a direct basis for the MCU main control circuit 9 to determine the test logic to be executed, avoiding the cumbersome manual switching of multiple instrument modes in traditional testing. The main reference synchronization circuit 2 and auxiliary reference synchronization circuit 3 respectively receive and transmit the main and auxiliary reference synchronization signals from the TACAN system. After filtering out line interference, the signals are input to the signal acquisition circuit 8, providing a clean signal source for the MCU main control circuit 9 to count the main and auxiliary reference pulse counts. Simultaneously, in the pulse test scenario, in conjunction with the signal output from the detector pulse circuit 6, it assists the MCU main control circuit 9 in accurately counting the detector pulse count, main reference pulse count, and auxiliary reference pulse count, thus realizing the pulse test function. The interrogation pulse circuit 4 directionally transmits external interrogation pulse signals, ensuring no amplitude attenuation or waveform distortion, providing a stable trigger signal for the MCU main control circuit 9. In the receiving index test scenario, this interrogation pulse works in conjunction with the detector signal output from the detector pulse circuit 6 to help the MCU main control circuit 9 filter response pulses and count interrogation and response pulses. The core triggering basis; the half-amplitude pulse circuit 5 is dedicated to receiving and transmitting half-amplitude pulse signals to ensure their amplitude stability. In the receiver component test scenario, it works in conjunction with the signal output by the interrogation pulse circuit 4 to provide reliable input for the MCU main control circuit 9 to count the interrogation pulses and the corresponding number of half-amplitude pulses, meeting the component test requirements; the detection pulse circuit 6 serves as the basic signal channel for the entire scenario, receiving the detection pulse signal output by the TACAN system and performing preliminary filtering. It provides detection pulse signals for the pulse test scenario and provides a pure original signal source for the MCU main control circuit 9 to screen the response pulses in the receiver index test scenario, reducing the interference of noise on signal recognition; the response pulse circuit 7 initially separates the response pulses from the mixed signal, suppresses non-response pulse interference, reduces the processing load of the signal acquisition circuit 8, and provides a preliminary guarantee for the MCU main control circuit 9 to accurately identify the response pulses; the signal acquisition circuit 8 serves as the signal processing center, amplifying, shaping, and performing logical operations on the signals input by each circuit, and transmitting the processed digital signals to the MCU main control circuit 9 to ensure that the signals acquired by the MCU main control circuit 9 meet the counting and logical judgment requirements. The data acquisition unit designed in this scheme integrates screening and counting functions through deep collaboration between various functional circuits and the MCU main control circuit 9. The MCU main control circuit 9 automatically switches the test logic according to the mode command without manual intervention. At the same time, each circuit provides a clean and stable signal input to the MCU main control circuit 9, ensuring the accuracy of the screening response pulse and the precision of various pulse counting, thereby significantly improving the quality and reliability of TACAN equipment testing.
[0010] For further details, please refer to Figure 2 and Figure 3The signal acquisition circuit 8 includes operational amplifier U2A, operational amplifier U2B, comparator U22, AND gate chip U5, AND gate chip U4 and AND gate chip U3, and the AND gate chip U5, AND gate chip U4 and AND gate chip U3 are all model 74LVC1G08; The non-inverting input of operational amplifier U2A is electrically connected to the detector pulse circuit 6. The inverting input of operational amplifier U2A is connected to the output of operational amplifier U2A, and one end of the connection is electrically connected to the non-inverting input of operational amplifier U2B. The output of operational amplifier U2B is electrically connected to one non-inverting input of comparator U22. The other non-inverting input of comparator U22 is electrically connected to the interrogation pulse circuit 4. One output of comparator U22 is electrically connected to the MCU main control circuit 9, the second pin of AND gate chip U5, the second pin of AND gate chip U4, the second pin of AND gate chip U3, and the response pulse circuit 7. The other output of comparator U22 is electrically connected to the MCU main control circuit 9.
[0011] As described above, operational amplifiers U2A and U2B are used for signal amplification, comparator U22 performs waveform shaping, and three 74LVC1G08 AND gate chips are used for logic operations. Specifically, the non-inverting input of operational amplifier U2A receives the signal from the detector pulse circuit 6, and the inverting input and output of operational amplifier U2A are shorted to form a voltage follower (this ensures distortion-free signal transmission), which is then further amplified by operational amplifier U2B. One non-inverting input of comparator U22 receives the amplified signal output from operational amplifier U2B, and the other non-inverting input receives the signal from the interrogation pulse circuit 4. The outputs are connected to the MCU main control circuit 9, the three AND gate chips, and the response pulse circuit 7, respectively. The 74LVC1G08 AND gate chip features low power consumption and high anti-interference capabilities. It can accurately perform logical AND operations on "detector signal and reference synchronization signal" and "delayed interrogation pulse and detector signal", ensuring the accuracy of effective signal selection. Through the combination of operational amplifier and comparator, it provides stable input for the accurate counting of MCU main control circuit 9, improving the test accuracy.
[0012] For further details, please refer to Figure 2 The signal acquisition circuit 8 also includes a capacitor C7 and a resistor R9; One end of capacitor C7 is electrically connected to one end of resistor R9 and the non-inverting input of operational amplifier U2A, the other end of capacitor C7 is electrically connected to detector pulse circuit 6, and the other end of resistor R9 is grounded.
[0013] As described above, adding capacitor C7 and resistor R9 to the signal acquisition circuit 8 forms an RC low-pass filter network. The original signal output from the detection pulse circuit 6 is prone to carrying high-frequency noise (such as circuit interference and external electromagnetic radiation). This RC low-pass filter network can filter out noise signals with frequencies higher than the cutoff frequency. Capacitor C7 presents low impedance to high-frequency signals, bypassing high-frequency noise to ground, while resistor R9 limits the attenuation of low-frequency useful signals, ensuring the purity of the detection pulse signal input to the operational amplifier U2A. This structure can reduce comparator false triggering caused by noise, making subsequent square wave shaping more accurate, thereby reducing the counting error of the MCU main control circuit 9 and improving pulse positioning accuracy.
[0014] For further details, please refer to Figure 2 The signal acquisition circuit 8 also includes capacitor C5, resistor R7, sliding rheostat R8, capacitor C6, and resistor R6; One end of capacitor C5 is electrically connected to the inverting input terminal and the output terminal of operational amplifier U2A, respectively. The other end of capacitor C5 is electrically connected to the non-inverting input terminal of operational amplifier U2B. One end of resistor R7 is electrically connected to the inverting input terminal of operational amplifier U2B and one fixed terminal of sliding rheostat R8, respectively. The other end of resistor R7 is grounded. One end of capacitor C6 is electrically connected to the output terminal of operational amplifier U2B, the other fixed terminal of sliding rheostat R8, and the sliding terminal of sliding rheostat R8, respectively. The other end of capacitor C6 is electrically connected to one end of resistor R6 and one non-inverting input terminal of comparator U22, respectively. The other end of resistor R6 is grounded.
[0015] As described above, by setting capacitor C5, resistor R7, variable resistor R8, capacitor C6, and resistor R6 to optimize the signal amplification and transmission link, one end of capacitor C5 is connected to the inverting input and output of operational amplifier U2A, and the other end of capacitor C5 is connected to the non-inverting input of operational amplifier U2B, thus achieving signal coupling between operational amplifiers U2A and U2B and isolating DC interference; one end of resistor R7 is grounded, and the other end of resistor R7 is connected to the inverting input of operational amplifier U2B and the fixed end of variable resistor R8, forming a voltage divider circuit, which can stabilize the operational amplifier. The potential of the inverting input terminal of the operational amplifier U2B is adjusted; the two ends of the sliding rheostat R8 are connected to the inverting input terminal and the output terminal of the operational amplifier U2B respectively, which can adjust the amplification factor of the operational amplifier U2B; one end of the capacitor C6 is connected to the output terminal of the operational amplifier U2B and the sliding end of the sliding rheostat R8, and the other end of the capacitor C6 is connected to the resistor R6 and the non-inverting input terminal of the comparator U22, which can filter out the ripple of the output signal of the operational amplifier U2B; one end of the resistor R6 is grounded, and the other end of the resistor R6 is connected to the capacitor C6 and the comparator U22, which can limit the current input to the comparator U22 and protect the device.
[0016] The core advantage of this design lies in its adjustable amplification factor and multi-stage filtering. The sliding rheostat R8 can flexibly adjust the amplification factor according to the actual amplitude of the detector pulse, ensuring the stability of the signal amplitude output to comparator U22. The multi-stage filtering of capacitors C5 and C6 further reduces signal interference, avoids distortion of the square wave output of comparator U22 due to signal amplitude fluctuations, and ensures the accuracy of subsequent counting.
[0017] For further details, please refer to Figure 2 The signal acquisition circuit 8 also includes a sliding rheostat R3, a sliding rheostat R4, a resistor R1, and a resistor R2; One fixed terminal of the sliding rheostat R4 is grounded, and the other fixed terminal of the sliding rheostat R4 is connected to a preset power supply. The sliding terminal of the sliding rheostat R4 is electrically connected to an inverting input terminal of the comparator U22. One end of the resistor R2 is connected to the preset power supply, and the other end of the resistor R2 is electrically connected to an output terminal of the comparator U22 and the MCU main control circuit 9, respectively. One fixed terminal of the sliding rheostat R3 is grounded, and the other fixed terminal of the sliding rheostat R3 is connected to a preset power supply. The sliding terminal of the sliding rheostat R3 is electrically connected to the other inverting input terminal of the comparator U22. One end of the resistor R1 is connected to the preset power supply, and the other end of the resistor R1 is electrically connected to the other output terminal of the comparator U22 and the MCU main control circuit 9, respectively.
[0018] As described above, a reference voltage adjustment circuit for the comparator is constructed using sliding rheostats R3 and R4, resistors R1 and R2. One fixed terminal of the sliding rheostat R4 is grounded, and the other fixed terminal of the sliding rheostat R4 is connected to a preset power supply. The sliding terminal of the sliding rheostat R4 is connected to an inverting input terminal of the comparator U22, thus allowing adjustment of the reference voltage at the inverting input terminal. One end of the resistor R2 is connected to the preset power supply, and the other end of the resistor R2 is connected to the corresponding output terminal of the comparator U22 and the MCU main control circuit 9, providing current limiting protection to prevent excessive output current from damaging the pins of the main control chip in the MCU main control circuit 9. One fixed terminal of the sliding rheostat R3 is grounded, and the other fixed terminal of the sliding rheostat R3 is connected to the preset power supply. The sliding terminal of the sliding rheostat R3 is connected to the other inverting input terminal of the comparator U22, which can adjust the other reference voltage. One end of the resistor R1 is connected to the preset power supply, and the other end of the resistor R1 is connected to the other output terminal of the comparator U22 and the MCU main control circuit 9, which serves as current limiting protection and can prevent the output current from being too large and damaging the pins of the MCU main control circuit 9. In this circuit, the sliding rheostats R3 and R4 can respectively adjust the reference voltage of the two inverting inputs of comparator U22 to the detection comparison level or other preset values, ensuring that comparator U22 only outputs a high level when the input signal exceeds the reference voltage, avoiding false judgments triggered by low-amplitude interference signals; at the same time, the current limiting function of resistors R1 and R2 can protect the I / O pins of the main control chip in the MCU main control circuit 9, preventing the instantaneous high voltage at the output of comparator U22 from damaging the main control chip, and improving the reliability of the circuit.
[0019] For further details, please refer to Figure 5 The MCU main control circuit 9 includes a chip U1, which is an STM32F103C8T6. The 29th pin of the chip U1 is electrically connected to the response pulse circuit 7. The 37th and 38th pins of the chip U1 are both electrically connected to the signal acquisition circuit 8. The 26th pin of the chip U1 is electrically connected to the half-amplitude pulse circuit 5. The 27th pin of the chip U1 is electrically connected to the main reference synchronization circuit 2. The 28th pin of the chip U1 is electrically connected to the auxiliary reference synchronization circuit 3.
[0020] As described above, the STM32F103C8T6 chip features a high-performance ARM Cortex-M3 core, abundant I / O interfaces, and timer resources. It can simultaneously process the counting and logic judgment of multiple signals. Compared with traditional 8-bit main control chips, it has a faster processing speed and can complete the synchronous counting of query pulses and response pulses within 1ms, avoiding counting omissions caused by processing delays. At the same time, the chip's low power consumption characteristics are suitable for USB power supply scenarios, extending the device's battery life and improving portability.
[0021] For further details, please refer to Figure 5 The mode selection circuit 1 includes a switch S2. The stationary terminal of the switch S2 is electrically connected to the MCU main control circuit 9. One moving terminal of the switch S2 is connected to a preset power supply, and the other moving terminal of the switch S2 is grounded.
[0022] As described above, the mode selection circuit 1 uses switch S2 (i.e., a single-pole double-throw switch), whose stationary terminal is connected to the MCU main control circuit 9 for transmitting mode control signals. This design directly switches the level state via a mechanical switch: when switch S2 is connected to a preset power supply, the MCU main control circuit 9 receives a high-level signal and switches to "X mode" (e.g., TACAN receiver performance test mode); when switch S2 is grounded, the MCU main control circuit 9 receives a low-level signal and switches to "Y mode" (e.g., receiver component test mode). No software debugging is required; operators can quickly switch modes using the switch, meeting the convenience requirements of on-site testing.
[0023] For further details, please refer to Figure 5The mode selection circuit 1 further includes a resistor R14, and one moving terminal of the switch S2 is connected to a preset power supply through the resistor R14.
[0024] As described above, in mode selection circuit 1, the power supply terminal (i.e., one of the moving terminals) of switch S2 is connected in series with resistor R14. When switch S2 is switched to the power supply terminal, if the mode control pin of MCU main control circuit 9 is in a low-level state, a direct connection will generate a large instantaneous current. Resistor R14 can limit the current, keeping it within the current tolerance standard of the pin of the main control chip in MCU main control circuit 9, thus avoiding damage to the pin of the main control chip in MCU main control circuit 9. At the same time, resistor R14 can also suppress electromagnetic interference in the circuit, ensure stable mode signal transmission, and reduce mode switching errors caused by interference.
[0025] For further details, please refer to Figure 1 The above-mentioned response signal acquisition device for TACAN signal testing also includes a display circuit 10, which is electrically connected to the MCU main control circuit 9.
[0026] As described above, a display circuit 10 is added and connected to the MCU main control circuit 9. This display circuit 10 can automatically switch interfaces according to the control signals of the MCU main control circuit 9: when no interrogation signal is received, it displays the detector pulse count, main reference pulse count, and auxiliary reference pulse count; when an interrogation signal is received, it automatically switches to the half-amplitude pulse count, response pulse count, and interrogation pulse count. Operators do not need additional instruments and can directly read real-time data through the LCD screen, reducing data recording errors and shortening the testing process.
[0027] For further details, please refer to Figure 1 The above-mentioned response signal acquisition device for TACAN signal testing also includes a power supply circuit 11, which is electrically connected to the mode selection circuit 1, the main reference synchronization circuit 2, the auxiliary reference synchronization circuit 3, the interrogation pulse circuit 4, the half-amplitude pulse circuit 5, the detection pulse circuit 6, the response pulse circuit 7, and the signal acquisition circuit 8.
[0028] As described above, the integrated power supply circuit 11 supplies power to all functional circuits, achieving an integrated power supply design. This eliminates the need for separate power supplies for each circuit, simplifying the power supply process. Furthermore, unified power conversion and filtering ensure the stability of the operating voltage of each active chip, preventing equipment malfunctions or testing errors caused by voltage fluctuations.
[0029] Please refer to Figures 1 to 7 As shown, Embodiment 1 of the present invention is as follows: Please refer to Figure 1A response signal acquisition device suitable for TACAN signal testing includes a mode selection circuit 1, a main reference synchronization circuit 2, an auxiliary reference synchronization circuit 3, an interrogation pulse circuit 4, a half-amplitude pulse circuit 5, a detection pulse circuit 6, a response pulse circuit 7, a signal acquisition circuit 8, and an MCU main control circuit 9. The MCU main control circuit 9 is electrically connected to the mode selection circuit 1, the half-amplitude pulse circuit 5, the main reference synchronization circuit 2, the auxiliary reference synchronization circuit 3, the response pulse circuit 7, and the signal acquisition circuit 8, respectively. The signal acquisition circuit 8 is electrically connected to the main reference synchronization circuit 2, the auxiliary reference synchronization circuit 3, the interrogation pulse circuit 4, the detection pulse circuit 6, and the response pulse circuit 7, respectively.
[0030] Please refer to Figure 2 and Figure 3 The signal acquisition circuit 8 includes operational amplifier U2A, operational amplifier U2B, comparator U22, AND gate chip U5, AND gate chip U4 and AND gate chip U3, and the AND gate chip U5, AND gate chip U4 and AND gate chip U3 are all model 74LVC1G08; The non-inverting input of operational amplifier U2A is electrically connected to the detector pulse circuit 6. The inverting input of operational amplifier U2A is connected to the output of operational amplifier U2A, and one end of the connection is electrically connected to the non-inverting input of operational amplifier U2B. The output of operational amplifier U2B is electrically connected to one non-inverting input of comparator U22. The other non-inverting input of comparator U22 is electrically connected to the interrogation pulse circuit 4. One output of comparator U22 is electrically connected to the MCU main control circuit 9, the second pin of AND gate chip U5, the second pin of AND gate chip U4, the second pin of AND gate chip U3, and the response pulse circuit 7. The other output of comparator U22 is electrically connected to the MCU main control circuit 9.
[0031] Please refer to Figure 2 The signal acquisition circuit 8 further includes a capacitor C7 and a resistor R9; one end of the capacitor C7 is electrically connected to one end of the resistor R9 and the non-inverting input terminal of the operational amplifier U2A, the other end of the capacitor C7 is electrically connected to the detection pulse circuit 6, and the other end of the resistor R9 is grounded.
[0032] The signal acquisition circuit 8 further includes capacitor C5, resistor R7, sliding rheostat R8, capacitor C6, and resistor R6. One end of capacitor C5 is electrically connected to the inverting input terminal and the output terminal of operational amplifier U2A, respectively, and the other end of capacitor C5 is electrically connected to the non-inverting input terminal of operational amplifier U2B. One end of resistor R7 is electrically connected to the inverting input terminal of operational amplifier U2B and one fixed terminal of sliding rheostat R8, respectively, and the other end of resistor R7 is grounded. One end of capacitor C6 is electrically connected to the output terminal of operational amplifier U2B, the other fixed terminal of sliding rheostat R8, and the sliding terminal of sliding rheostat R8, respectively, and the other end of capacitor C6 is electrically connected to one end of resistor R6 and one non-inverting input terminal of comparator U22, respectively, and the other end of resistor R6 is grounded.
[0033] The signal acquisition circuit 8 also includes a sliding rheostat R3, a sliding rheostat R4, a resistor R1, and a resistor R2; one fixed end of the sliding rheostat R4 is grounded, the other fixed end of the sliding rheostat R4 is connected to a preset power supply, the sliding end of the sliding rheostat R4 is electrically connected to an inverting input terminal of the comparator U22, one end of the resistor R2 is connected to the preset power supply, and the other end of the resistor R2 is electrically connected to an output terminal of the comparator U22 and the MCU main control circuit 9 respectively. One fixed terminal of the sliding rheostat R3 is grounded, and the other fixed terminal of the sliding rheostat R3 is connected to a preset power supply. The sliding terminal of the sliding rheostat R3 is electrically connected to the other inverting input terminal of the comparator U22. One end of the resistor R1 is connected to the preset power supply, and the other end of the resistor R1 is electrically connected to the other output terminal of the comparator U22 and the MCU main control circuit 9, respectively.
[0034] Please refer to Figure 5 The MCU main control circuit 9 includes a chip U1, which is an STM32F103C8T6. The 29th pin of the chip U1 is electrically connected to the response pulse circuit 7. The 37th and 38th pins of the chip U1 are both electrically connected to the signal acquisition circuit 8. The 26th pin of the chip U1 is electrically connected to the half-amplitude pulse circuit 5. The 27th pin of the chip U1 is electrically connected to the main reference synchronization circuit 2. The 28th pin of the chip U1 is electrically connected to the auxiliary reference synchronization circuit 3.
[0035] The MCU main control circuit 9 also includes capacitor C9, crystal oscillator G1, capacitors C14, C17, C10, C11, C12, C15, C16, resistors R13 and R11, and resistors R14 and R15. For the specific connection relationships between these components, please refer to [reference needed]. Figure 5Crystal oscillator G1 provides the reference clock for the MCU main control circuit 9. Capacitors C9 and C14 are its load capacitors, ensuring that the crystal oscillator output signal can be efficiently and stably output to the MCU main control circuit 9. Capacitors C17, C10, C11, C12, C15, C16, and C13 are all filter capacitors. Resistors R13 and R11 are current-limiting resistors.
[0036] Please refer to Figure 5 The mode selection circuit 1 includes a switch S2. The stationary terminal of the switch S2 is electrically connected to the MCU main control circuit 9. One moving terminal of the switch S2 is connected to a preset power supply, and the other moving terminal of the switch S2 is grounded.
[0037] The mode selection circuit 1 also includes a resistor R14 (a current-limiting resistor), and one moving terminal of the switch S2 is connected to a preset power supply through the resistor R14.
[0038] Please refer to Figure 1 The aforementioned response signal acquisition device also includes a display circuit 10, which is electrically connected to the MCU main control circuit 9.
[0039] Please refer to Figure 7 The display circuit 10 includes a liquid crystal screen XS1 and a resistor R10.
[0040] Please refer to Figure 1 The aforementioned response signal acquisition device also includes a power supply circuit 11, which is electrically connected to the mode selection circuit 1, the main reference synchronization circuit 2, the auxiliary reference synchronization circuit 3, the interrogation pulse circuit 4, the half-amplitude pulse circuit 5, the detection pulse circuit 6, the response pulse circuit 7, and the signal acquisition circuit 8.
[0041] The power supply circuit 11 includes capacitor C1, capacitor C2, chip U11, capacitor C3, and capacitor C4. For the specific connection relationships between these components, please refer to [reference needed]. Figure 6 Capacitors C1 and C2 are input capacitors, which stabilize voltage, filter high-frequency noise, provide instantaneous current, and ensure the reliability of the chip's power supply. Capacitors C3 and C4 are output capacitors, which filter, regulate voltage, store energy, and improve transient response, providing a stable and clean DC voltage to the load.
[0042] It also includes a USB power supply interface, which is electrically connected to the MCU main control circuit 9.
[0043] Please refer to Figure 3 The main reference synchronization circuit 2 includes a main reference synchronization interface X5, and the first pin of the main reference synchronization interface X5 is electrically connected to the first pin of the AND gate chip U5.
[0044] The auxiliary reference synchronization circuit 3 includes an auxiliary reference synchronization interface X4, and the first pin of the auxiliary reference synchronization interface X4 is electrically connected to the first pin of the AND gate chip U4.
[0045] Please refer to Figure 2 The interrogation pulse circuit 4 includes an interrogation pulse interface X1, and the first pin of the interrogation pulse interface X1 is electrically connected to the signal acquisition circuit 8.
[0046] Please refer to Figure 4 The half-amplitude pulse circuit 5 includes a half-amplitude pulse interface X6, and the first pin of the half-amplitude pulse interface X6 is electrically connected to the MCU main control circuit 9.
[0047] Please refer to Figure 2 The detection pulse circuit 6 includes a detection pulse interface X2, and the first pin of the detection pulse interface X2 is electrically connected to the MCU main control circuit 9.
[0048] Please refer to Figure 3 The response pulse circuit 7 includes a response pulse interface X3, and the first pin of the response pulse interface X3 is electrically connected to the fourth pin of the AND gate chip U3.
[0049] The working principle of the response signal acquisition device applicable to TACAN signal testing described above is as follows: This data acquisition unit uses the STM32F103C8T6 main control chip (i.e., chip U1) as its core. Through a fully integrated design of "signal input → processing → counting → display", it realizes automated testing of TACAN signals. The specific workflow is as follows: 1. Power supply startup phase: The USB power supply interface inputs +5V power, which is converted into a stable +3.3V power supply by the DC-DC chip (i.e. chip U11) of the power supply circuit 11. At the same time, capacitors C1 and C2 can filter out the ripple of the input power supply, and capacitors C3 and C4 can stabilize the output voltage, providing reliable power supply for all circuits. After the MCU main control circuit 9 is powered on, it initializes and completes the parameter configuration of the display circuit 10, timer, and I / O interface.
[0050] 2. Mode Selection Stage: The operator switches the test mode via switch S2 of mode selection circuit 1. When switch S2 is connected to a +3.3V power supply, the mode pin of chip U1 receives a high level, which is determined to be "X mode" (one of the working modes of TACAN equipment). When switch S2 is grounded, the mode pin of chip U1 receives a low level, which is determined to be "Y mode" (another working mode of TACAN equipment). Based on the mode signal, chip U1 configures the timer's counting parameters (such as counting period and trigger threshold) and the parameter type of the display interface.
[0051] 3. Signal Acquisition and Processing Stage: (1) Processing of detection pulse and interrogation pulse: The signal of the detection pulse circuit 6 is filtered by capacitor C7 and resistor R9 and then input to operational amplifier U2A, and then amplified by operational amplifier U2B, and then input to the non-inverting input of comparator U22; the signal of the interrogation pulse circuit 4 is directly input to the other non-inverting input of comparator U22; the inverting input of comparator U22 is adjusted to the reference voltage through sliding rheostat R3 and sliding rheostat R4, and the input bell pulse is shaped into a standard square wave, and then output to MCU main control circuit 9 and three AND gate chips.
[0052] (2) Reference synchronization signal processing: The signal input of the main reference synchronization circuit 2 is the first pin of the AND gate chip U4, and the signal input of the auxiliary reference synchronization circuit 3 is the first pin of the AND gate chip U3; the second pins of the AND gate chip U4 and the AND gate chip U3 both receive the detected square wave signal output by the comparator U22. After logical AND operation, the valid main reference synchronization signal and the valid auxiliary reference synchronization signal are output to the MCU main control circuit 9.
[0053] (3) Half-amplitude pulse processing: The signal input of the half-amplitude pulse circuit 5 is to the first pin of the AND gate chip U5. The MCU main control circuit 9 will delay the received query pulse signal by the system (the delay parameter is determined by the mode) and then output it to the second pin of the AND gate chip U5. After AND operation, the effective half-amplitude pulse signal is output to the MCU main control circuit 9.
[0054] 4. Signal Counting and Interface Control Stage: The MCU main control circuit 9 counts the valid input signals using a timer. When the MCU detects an "interrogation pulse" signal, it counts the number of interrogation pulses, response pulses, and half-amplitude pulses. When there is no interrogation pulse signal, it counts the number of detector pulses, main reference pulses, and auxiliary reference pulses. Simultaneously, based on the counting results, the MCU main control circuit 9 controls the LCD screen in the display circuit 10 to automatically switch interfaces and display the corresponding parameters in real time.
[0055] 5. Test completion stage: After the operator reads the data from the XS1 LCD screen, disconnect the power supply from the USB power interface, and the device will stop working; if it is necessary to switch test modes, stages 2 to 4 above can be repeated.
[0056] The entire process requires no additional frequency meter, achieving integrated "acquisition-processing-counting-display". At the same time, through precise signal filtering, amplification, and shaping design, it ensures test accuracy and meets the efficiency, portability, and reliability requirements of TACAN equipment testing.
[0057] In summary, this invention provides a response signal acquisition device suitable for TACAN signal testing. A mode selection circuit acts as a switch for changing test scenarios, receiving mode commands from the operator and transmitting them to the MCU main control circuit. This provides a direct basis for the MCU main control circuit to determine the test logic to be executed, avoiding the cumbersome manual switching of multiple instrument modes in traditional testing. The main reference synchronization circuit and the auxiliary reference synchronization circuit respectively receive and transmit the main and auxiliary reference synchronization signals of the TACAN system. After filtering out line interference, the signals are input to the signal acquisition circuit, providing a clean signal source for the MCU main control circuit to count the main reference pulse count and the auxiliary reference pulse count. Simultaneously, in the pulse test scenario, in conjunction with the signal output from the detector pulse circuit, it assists the MCU main control circuit in accurately counting the detector pulse count, the main reference pulse count, and the auxiliary reference pulse count, thus realizing the pulse test function. The interrogation pulse circuit directionally transmits external interrogation pulse signals, ensuring no amplitude attenuation or waveform distortion, providing a stable trigger signal for the MCU main control circuit. In the reception index test scenario, this interrogation pulse, together with the detector signal output from the detector pulse circuit, becomes the MCU main control circuit for screening response pulses. The core triggering basis for the interrogation pulse and response pulse is the half-amplitude pulse circuit, which specifically receives and transmits the half-amplitude pulse signal to ensure its amplitude stability. In receiver component testing scenarios, it works in conjunction with the signal output from the interrogation pulse circuit to provide reliable input for the MCU main control circuit to count the interrogation pulse and the corresponding half-amplitude pulse quantity, meeting the component testing requirements. The detector pulse circuit serves as the basic signal channel for all scenarios, receiving and initially filtering the detector pulse signal output from the TACAN system. It provides detector pulse signals for pulse testing scenarios and a clean original signal source for the MCU main control circuit to screen response pulses in receiver performance testing scenarios, reducing interference from noise to signal recognition. The response pulse circuit initially separates the response pulse from the mixed signal, suppresses non-response pulse interference, reduces the processing load of the signal acquisition circuit, and provides a preliminary guarantee for the MCU main control circuit to accurately identify the response pulse. The signal acquisition circuit, as the signal processing center, amplifies, shapes, and performs logical operations on the signals input from each circuit, and transmits the processed digital signal to the MCU main control circuit to ensure that the signal acquired by the MCU main control circuit meets the counting and logical judgment requirements. The data acquisition unit designed in this scheme integrates screening and counting functions through deep collaboration between various functional circuits and the MCU main control circuit. The MCU main control circuit automatically switches the test logic according to the mode command without manual intervention. At the same time, each circuit provides a clean and stable signal input to the MCU main control circuit, ensuring the accuracy of the screening response pulses and the precision of various pulse counts, thereby significantly improving the quality and reliability of TACAN equipment testing.
[0058] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A response signal acquisition device suitable for TACAN signal testing, characterized in that, It includes a mode selection circuit, a main reference synchronization circuit, an auxiliary reference synchronization circuit, an interrogation pulse circuit, a half-amplitude pulse circuit, a detection pulse circuit, an answer pulse circuit, a signal acquisition circuit, and an MCU main control circuit; The MCU main control circuit is electrically connected to the mode selection circuit, half-amplitude pulse circuit, main reference synchronization circuit, auxiliary reference synchronization circuit, response pulse circuit and signal acquisition circuit respectively. The signal acquisition circuit is electrically connected to the main reference synchronization circuit, auxiliary reference synchronization circuit, interrogation pulse circuit, detection pulse circuit and response pulse circuit respectively.
2. The response signal acquisition device for TACAN signal testing according to claim 1, characterized in that, The signal acquisition circuit includes operational amplifier U2A, operational amplifier U2B, comparator U22, AND gate chip U5, AND gate chip U4 and AND gate chip U3, wherein the model of AND gate chip U5, AND gate chip U4 and AND gate chip U3 is 74LVC1G08. The non-inverting input of operational amplifier U2A is electrically connected to the detector pulse circuit. One end of the inverting input of operational amplifier U2A connected to the output of operational amplifier U2A is electrically connected to the non-inverting input of operational amplifier U2B. The output of operational amplifier U2B is electrically connected to one non-inverting input of comparator U22. The other non-inverting input of comparator U22 is electrically connected to the interrogation pulse circuit. One output of comparator U22 is electrically connected to the MCU main control circuit, the second pin of AND gate chip U5, the second pin of AND gate chip U4, the second pin of AND gate chip U3, and the response pulse circuit. The other output of comparator U22 is electrically connected to the MCU main control circuit.
3. The response signal acquisition device for TACAN signal testing according to claim 2, characterized in that, The signal acquisition circuit also includes capacitor C7 and resistor R9; One end of capacitor C7 is electrically connected to one end of resistor R9 and the non-inverting input terminal of operational amplifier U2A, the other end of capacitor C7 is electrically connected to the detection pulse circuit, and the other end of resistor R9 is grounded.
4. The response signal acquisition device for TACAN signal testing according to claim 2, characterized in that, The signal acquisition circuit also includes capacitor C5, resistor R7, sliding rheostat R8, capacitor C6, and resistor R6. One end of capacitor C5 is electrically connected to the inverting input terminal and the output terminal of operational amplifier U2A, respectively. The other end of capacitor C5 is electrically connected to the non-inverting input terminal of operational amplifier U2B. One end of resistor R7 is electrically connected to the inverting input terminal of operational amplifier U2B and one fixed terminal of sliding rheostat R8, respectively. The other end of resistor R7 is grounded. One end of capacitor C6 is electrically connected to the output terminal of operational amplifier U2B, the other fixed terminal of sliding rheostat R8, and the sliding terminal of sliding rheostat R8, respectively. The other end of capacitor C6 is electrically connected to one end of resistor R6 and one non-inverting input terminal of comparator U22, respectively. The other end of resistor R6 is grounded.
5. The response signal acquisition device for TACAN signal testing according to claim 2, characterized in that, The signal acquisition circuit also includes a sliding rheostat R3, a sliding rheostat R4, a resistor R1, and a resistor R2; One fixed terminal of the sliding rheostat R4 is grounded, and the other fixed terminal of the sliding rheostat R4 is connected to a preset power supply. The sliding terminal of the sliding rheostat R4 is electrically connected to an inverting input terminal of the comparator U22. One end of the resistor R2 is connected to the preset power supply, and the other end of the resistor R2 is electrically connected to an output terminal of the comparator U22 and the MCU main control circuit, respectively. One fixed terminal of the sliding rheostat R3 is grounded, and the other fixed terminal of the sliding rheostat R3 is connected to a preset power supply. The sliding terminal of the sliding rheostat R3 is electrically connected to the other inverting input terminal of the comparator U22. One end of the resistor R1 is connected to the preset power supply, and the other end of the resistor R1 is electrically connected to the other output terminal of the comparator U22 and the MCU main control circuit, respectively.
6. The response signal acquisition device for TACAN signal testing according to claim 1, characterized in that, The MCU main control circuit includes chip U1, which is an STM32F103C8T6. The 29th pin of chip U1 is electrically connected to the response pulse circuit. The 37th and 38th pins of chip U1 are both electrically connected to the signal acquisition circuit. The 26th pin of chip U1 is electrically connected to the half-amplitude pulse circuit. The 27th pin of chip U1 is electrically connected to the main reference synchronization circuit. The 28th pin of chip U1 is electrically connected to the auxiliary reference synchronization circuit.
7. The response signal acquisition device for TACAN signal testing according to claim 1, characterized in that, The mode selection circuit includes a switch S2. The stationary terminal of the switch S2 is electrically connected to the MCU main control circuit. One moving terminal of the switch S2 is connected to a preset power supply, and the other moving terminal of the switch S2 is grounded.
8. The response signal acquisition device for TACAN signal testing according to claim 7, characterized in that, The mode selection circuit also includes a resistor R14, and one moving terminal of the switch S2 is connected to a preset power supply through the resistor R14.
9. The response signal acquisition device for TACAN signal testing according to claim 1, characterized in that, It also includes a display circuit, which is electrically connected to the MCU main control circuit.
10. The response signal acquisition device for TACAN signal testing according to claim 1, characterized in that, It also includes a power supply circuit, which is electrically connected to the mode selection circuit, the main reference synchronization circuit, the auxiliary reference synchronization circuit, the interrogation pulse circuit, the half-amplitude pulse circuit, the detector pulse circuit, the response pulse circuit, and the signal acquisition circuit.