Time synchronization circuit based on double-SOC chip architecture and vehicle

Abstract

The embodiment of the invention provides a time synchronization circuit based on a double-SOC chip architecture and a vehicle, and belongs to the technical field of vehicle controllers. The circuit comprises a first SOC, a second SOC, a PPSOUT module and a PPSIN module, wherein the PPSOUT module and the PPSIN module are connected through an external wire harness; the first SOC is connected with the PPSIN module, the first SOC is further connected with the PPSOUT module, and the PPSOUT module is used for converting a target output signal output by the first SOC into a target level signal and outputting the target level signal to the PPSIN module through the external wire harness; and the second SOC is also connected with the PPSIN module, and the PPSIN module is used for converting the received target level signal into a target input signal and outputting the target input signal to the second SOC. According to the embodiment of the invention, time synchronization and function linkage between the two SOCs are realized, and the realization effect of multi-domain fusion control of the intelligent driving system is improved.

Description

Technical Field

[0001] This application relates to the field of vehicle controller technology, and in particular to a time synchronization circuit and vehicle based on a dual SOC chip architecture. Background Technology

[0002] In related technologies, with the development of intelligent driving technology for automobiles, in order to meet the high computing power and multi-domain fusion control requirements brought about by the complexity and diversification of intelligent driving system functions, the selection of controller main chips tends to be a dual-SOC architecture. This architecture supports the parallel execution of multiple tasks such as perception, decision-making, planning and control in the intelligent driving system by coordinating the processing capabilities of two SOCs.

[0003] However, in systems where dual SOCs work together, the accuracy of time synchronization and the real-time communication mechanism are technical challenges that affect the uniformity of function scheduling and the real-time performance of system response, thus limiting the effectiveness of multi-domain fusion control in intelligent driving systems.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a time synchronization circuit and vehicle based on a dual-SOC chip architecture, aiming to achieve time synchronization and functional linkage between the two SOCs and improve the implementation effect of multi-domain fusion control of intelligent driving system.

[0006] To achieve the above objectives, one aspect of this application provides a time synchronization circuit based on a dual-SOC chip architecture. The circuit includes: a first SOC, a second SOC, a PPS_OUT module, and a PPS_IN module, wherein the PPS_OUT module and the PPS_IN module are connected by an external wiring harness. The first SOC is also connected to the PPS_OUT module, which is used to convert the target output signal output by the first SOC into a target level signal and output the target level signal to the PPS_IN module through the external wiring harness. The second SOC is also connected to the PPS_IN module, which is used to convert the received target level signal into a target input signal and output the target input signal to the second SOC.

[0007] In some embodiments, the PPS_OUT module includes a first switching unit, a second switching unit, a first resistor, a second resistor, a first capacitor, a first diode, and a first TVS diode; The output terminal of the first SOC is connected to the first switching unit. The first switching unit is also connected to the ground terminal, the first resistor, and the second switching unit. The other end of the first resistor is connected to the first voltage input terminal. The second switching unit is also connected to the ground terminal, the positive terminal of the first diode, and the second resistor. The other end of the second resistor is connected to the second voltage input terminal and the first capacitor. The negative terminal of the first diode is connected to the first TVS diode. The other end of the first capacitor and the other end of the first TVS diode are both connected to the ground terminal. The negative terminal of the first diode is set as the output terminal of the PPS_OUT module. The second voltage input terminal is set to input the same level as the target level signal; the PPS_OUT module is used to turn off the first switching unit and turn on the second switching unit under the drive of the target output signal, so as to control the output of the target level signal.

[0008] In some embodiments, the first switching unit includes a third resistor, a fourth resistor, and a first NPN transistor; The output terminal of the first SOC is connected to the third resistor, the other end of the third resistor is connected to the base of the first NPN transistor, the collector of the first NPN transistor is connected to the first resistor and the second switching unit respectively, the fourth resistor is connected between the base and emitter of the first NPN transistor, and the emitter of the first NPN transistor is also connected to the ground terminal.

[0009] In some embodiments, the third resistor is set to a 10K resistor and the fourth resistor is set to a 47K resistor.

[0010] In some embodiments, the second switching unit includes a fifth resistor, a sixth resistor, and a second NPN transistor; The fifth resistor is connected to the first switching unit, and the other end of the fifth resistor is connected to the base of the second NPN transistor. The collector of the second NPN transistor is connected to the anode of the first diode and the second resistor, respectively. The sixth resistor is connected between the base and emitter of the second NPN transistor, and the emitter of the second NPN transistor is also connected to the ground terminal.

[0011] In some embodiments, the PPS_IN module includes a third switching unit, a fourth switching unit, a seventh resistor, an eighth resistor, a second capacitor, a second diode, and a second TVS diode; The positive terminal of the second diode is set as the input terminal of the PPS_IN module. The positive terminal of the second diode is also connected to the second TVS diode. The negative terminal of the second diode is connected to the third switching unit. The third switching unit is also connected to the ground terminal, the seventh resistor, and the fourth switching unit. The other end of the seventh resistor is connected to the first voltage input terminal. The fourth switching unit is also connected to the ground terminal and the eighth resistor. The other end of the eighth resistor is connected to the third voltage input terminal and the second capacitor. The other ends of the second TVS diode and the second capacitor are both connected to the ground terminal. The connection terminal between the fourth switching unit and the eighth resistor is set as the output terminal of the PPS_IN module. The PPS_IN module is used to turn off the third switch unit and turn on the fourth switch unit under the drive of the target level signal, so as to control the output of the target input signal.

[0012] In some embodiments, the third switching unit includes a ninth resistor, a tenth resistor, and a third NPN transistor; The negative terminal of the second diode is connected to the ninth resistor, the other end of the ninth resistor is connected to the base of the third NPN transistor, the collector of the third NPN transistor is connected to the seventh resistor and the fourth switching unit, the tenth resistor is connected between the base and emitter of the third NPN transistor, and the emitter of the third NPN transistor is also connected to the ground terminal.

[0013] In some embodiments, the ninth resistor is set to a 10K resistor and the tenth resistor is set to a 47K resistor.

[0014] In some embodiments, the fourth switching unit includes an eleventh resistor, a twelfth resistor, and a fourth NPN transistor; The eleventh resistor is connected to the third switching unit, and the other end of the eleventh resistor is connected to the base of the fourth NPN transistor. The collector of the fourth NPN transistor is connected to the eighth resistor. The twelfth resistor is connected between the base and emitter of the fourth NPN transistor. The emitter of the fourth NPN transistor is also connected to the ground terminal.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes a vehicle equipped with a time synchronization circuit based on a dual-SOC chip architecture as described in any of the preceding claims.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides a time synchronization circuit and vehicle based on a dual-SOC chip architecture. The solution includes a first SOC, a second SOC, a PPS_OUT module, and a PPS_IN module. The PPS_OUT module and the PPS_IN module are connected via an external wiring harness. The first SOC is connected to the PPS_OUT module, which converts the target output signal from the first SOC to a target level signal and outputs the target level signal to the PPS_IN module via the external wiring harness. The second SOC is connected to the PPS_IN module, which converts the target level signal to a target input signal and outputs the target input signal to the second SOC. Compared to the dual-SOC architecture, which is constrained by time synchronization accuracy and real-time communication mechanisms, the method of this application, by combining the PPS_OUT module and the PPS_IN module and performing two level conversions respectively, forms a communication link between the first SOC and the second SOC, realizing time synchronization and functional linkage between the two SOCs, and improving the multi-domain fusion control effect of the intelligent driving system. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a time synchronization circuit based on a dual-SOC chip architecture provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the PPS_OUT module in an embodiment of this application; Figure 3 This is a schematic diagram of another embodiment of the PPS_OUT module in this application; Figure 4 This is a schematic diagram of the structure of the PPS_IN module in an embodiment of this application; Figure 5 This is a schematic diagram of another embodiment of the PPS_IN module in this application.

[0018] In the diagram: First SOC 100, PPS_OUT module 200, PPS_IN module 300, Second SOC 400, First switch unit 210, Second switch unit 220, Third switch unit 230, Fourth switch unit 240, First voltage input terminal VIN1, Second voltage input terminal VIN2, Third voltage input terminal VIN3, First resistor R1, Second resistor R2, Third resistor R3, Fourth resistor R4, Fifth resistor R5, Sixth resistor R6, Seventh resistor R7, Eighth resistor R8, Ninth resistor R9, Tenth resistor R10, Eleventh resistor R11, Twelfth resistor R12, First capacitor C1, Second capacitor C2, First diode D1, Second diode D2, First NPN transistor Q1, Second NPN transistor Q2, Third NPN transistor Q3, Fourth NPN transistor Q4, First TVS transistor TVS1, Second TVS transistor TVS2. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0020] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0021] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] In related technologies, with the development of intelligent driving technology for automobiles, in order to meet the high computing power and multi-domain fusion control requirements brought about by the complexity and diversification of intelligent driving system functions, the selection of controller main chips tends to be a dual-SOC architecture. This architecture supports the parallel execution of multiple tasks such as perception, decision-making, planning and control in the intelligent driving system by coordinating the processing capabilities of two SOCs.

[0024] However, in systems where dual SOCs work together, the accuracy of time synchronization and the real-time communication mechanism are technical challenges that affect the uniformity of function scheduling and the real-time performance of system response, thus limiting the effectiveness of multi-domain fusion control in intelligent driving systems.

[0025] In view of this, this application provides a time synchronization circuit and vehicle based on a dual-SOC chip architecture. The solution includes a first SOC 100, a second SOC 400, a PPS_OUT module 200, and a PPS_IN module 300. The PPS_OUT module 200 and the PPS_IN module 300 are connected via an external wiring harness. The first SOC 100 is connected to the PPS_OUT module 200, which converts the target output signal output by the first SOC 100 into a target level signal and outputs the target level signal to the PPS_IN module 300 via the external wiring harness. The second SOC 400 is connected to the PPS_IN module 300, which converts the target level signal into a target input signal and outputs the target input signal to the second SOC 400. Compared with the dual SOC architecture, which is constrained by time synchronization accuracy and real-time communication mechanism, the method of this application combines the PPS_OUT module 200 and the PPS_IN module 300 to perform two level conversions respectively, forming a communication link between the first SOC 100 and the second SOC 400. This solves the constraints of time synchronization accuracy and real-time communication mechanism of the dual SOC architecture and improves the realization effect of multi-domain fusion control of intelligent driving system.

[0026] Figure 1 This is a schematic diagram of an optional structure of the time synchronization circuit based on a dual-SOC chip architecture provided in an embodiment of this application. Figure 1 The circuitry may include, but is not limited to: a first SOC 100, a second SOC 400, a PPS_OUT module 200 and a PPS_IN module 300, which are connected to each other via an external wiring harness. The first SOC 100 is also connected to the PPS_OUT module 200, which is used to convert the target output signal output by the first SOC 100 into a target level signal and output the target level signal to the PPS_IN module 300 through an external wiring harness. The second SOC 400 is also connected to the PPS_IN module 300, which is used to convert the received target level signal into a target input signal and output the target input signal to the second SOC 400.

[0027] Specifically, both the PPS_OUT module 200 and the PPS_IN module 300 are dedicated peripheral interface circuits for the SOC, specifically used to achieve time synchronization and functional linkage between the two SOCs. The PPS_OUT module 200 interfaces with the first SOC 100, processes the signal output from the first SOC 100, and defines it as the target output signal. The PPS_IN module 300 interfaces with the second SOC 400, processes and obtains the signal that is finally input into the second SOC 400, and defines it as the target input signal.

[0028] The PPS_OUT module 200 and PPS_IN module 300 perform level conversion operations to facilitate signal transmission between the first SOC 100 and the second SOC 400. The PPS_OUT module 200 and PPS_IN module 300 are connected via an external wiring harness, and the converted target level signal is transmitted through this harness.

[0029] The circuit shown in this embodiment combines the PPS_OUT module 200 and the PPS_IN module 300 to perform two level conversions, forming a communication link between the first SOC 100 and the second SOC 400, thereby realizing time synchronization and functional linkage between the two SOCs and improving the implementation effect of multi-domain fusion control of the intelligent driving system.

[0030] refer to Figure 2 In some embodiments, the PPS_OUT module 200 includes a first switching unit 210, a second switching unit 220, a first resistor R1, a second resistor R2, a first capacitor C1, a first diode D1, and a first TVS transistor TVS1. The output terminal of the first SOC 100 is connected to the first switching unit 210. The first switching unit 210 is also connected to the ground terminal, the first resistor R1, and the second switching unit 220. The other end of the first resistor R1 is connected to the first voltage input terminal. The second switching unit 220 is also connected to the ground terminal, the positive terminal of the first diode D1, and the second resistor R2. The other end of the second resistor R2 is connected to the second voltage input terminal and the first capacitor C1. The negative terminal of the first diode D1 is connected to the first TVS transistor TVS1. The other end of the first capacitor C1 and the other end of the first TVS transistor TVS1 are both connected to the ground terminal. The negative terminal of the first diode D1 is set as the output terminal of the PPS_OUT module 200. The second voltage input terminal is set to the same level as the target level signal; the PPS_OUT module 200 is used to turn off the first switch unit 210 and turn on the second switch unit 220 under the drive of the target output signal, so as to control the output target level signal.

[0031] Based on the design of the first switch unit 210, the second switch unit 220, and other devices, under the drive of the target output signal, the first switch unit 210 of the PPS_OUT module 200 is turned off, the second switch unit 220 is turned on, and the second resistor R2 acts as a pull-up resistor to pull the level of the output terminal of the PPS_OUT module 200 up to the level of the second voltage input terminal. The second voltage input terminal can be set to 12V. Finally, the low-level target output signal output by the first SOC 100 is converted into a high-level target level signal through the PPS_OUT module 200.

[0032] In addition, the first voltage input terminal can be set to 3.3V, the first resistor R1 can be set to a 10K resistor, the second resistor R2 can be set to a 47K resistor, and the first capacitor C1 can be set to a 100n 50V capacitor.

[0033] refer to Figure 3 In some embodiments, the first switching unit 210 includes a third resistor R3, a fourth resistor R4, and a first NPN transistor Q1; The output terminal of the first SOC 100 is connected to the third resistor R3. The other end of the third resistor R3 is connected to the base of the first NPN transistor Q1. The collector of the first NPN transistor Q1 is connected to the first resistor R1 and the second switching unit 220 respectively. The fourth resistor R4 is connected between the base and emitter of the first NPN transistor Q1. The emitter of the first NPN transistor Q1 is also connected to the ground terminal.

[0034] Optionally, the first switching unit 210 can be configured as a switching unit based on an NPN transistor, and the fourth resistor R4 is used to adjust the voltage drop between the base and emitter of the first NPN transistor Q1 to control its conduction, thereby enabling the PPS_OUT module 200 to convert the low-level target output signal output by the first SOC 100 into a high-level target level signal.

[0035] Furthermore, the base of the first NPN transistor Q1 is actually connected to the GPIO of the first SOC 100. When the first SOC 100 is powered on and initialized, the GPIO is also powered on internally. In this state, short-term spike voltage noise is easily generated, which can cause circuit malfunctions. To address this, setting the third resistor R3 can effectively reduce the impact of spike voltage noise and improve the accuracy of circuit operation control.

[0036] In some embodiments, the third resistor R3 is set to a 10K resistor and the fourth resistor R4 is set to a 47K resistor.

[0037] Specifically, the third resistor R3 is set to 10K and the fourth resistor R4 is set to 47K. The target output signal is 1.67V. Based on the resistance values ​​of the third resistor R3 and the fourth resistor R4, the voltage drop between the base and emitter of the first NPN transistor Q1 can be greater than its turn-on threshold of 0.7V, thereby controlling the first switching unit 210 to conduct.

[0038] refer to Figure 3 In some embodiments, the second switching unit 220 includes a fifth resistor R5, a sixth resistor R6, and a second NPN transistor Q2; The fifth resistor R5 is connected to the first switching unit 210. The other end of the fifth resistor R5 is connected to the base of the second NPN transistor Q2. The collector of the second NPN transistor Q2 is connected to the anode of the first diode D1 and the second resistor R2. The sixth resistor R6 is connected between the base and emitter of the second NPN transistor Q2. The emitter of the second NPN transistor Q2 is also connected to the ground terminal.

[0039] Optionally, the second switching unit 220 can be configured as a switching unit based on an NPN transistor. When the first switching unit 210 is turned on, the fifth resistor R5 is actually connected to the ground terminal, resulting in no voltage drop between the base and emitter of the second NPN transistor Q2 that is greater than its turn-on threshold, thereby controlling its turn-off and supporting the PPS_OUT module 200 to convert the low-level target output signal output by the first SOC 100 into a high-level target level signal.

[0040] In addition, the fifth resistor R5 can be set to a 10K resistor, and the sixth resistor R6 can be set to a 47K resistor.

[0041] refer to Figure 4In some embodiments, the PPS_IN module 300 includes a third switching unit 230, a fourth switching unit 240, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a second diode D2, and a second TVS transistor TVS2. The positive terminal of the second diode D2 is set as the input terminal of the PPS_IN module 300. The positive terminal of the second diode D2 is also connected to the second TVS transistor TVS2. The negative terminal of the second diode D2 is connected to the third switching unit 230. The third switching unit 230 is also connected to the ground terminal, the seventh resistor R7 and the fourth switching unit 240 respectively. The other end of the seventh resistor R7 is connected to the first voltage input terminal. The fourth switching unit 240 is also connected to the ground terminal and the eighth resistor R8 respectively. The other end of the eighth resistor R8 is connected to the third voltage input terminal and the second capacitor C2 respectively. The other end of the second TVS transistor TVS2 and the other end of the second capacitor C2 are both connected to the ground terminal. The connection terminal of the fourth switching unit 240 and the eighth resistor R8 is set as the output terminal of the PPS_IN module 300. The PPS_IN module 300 is used to turn off the third switch unit 230 and turn on the fourth switch unit 240 under the drive of the target level signal, so as to control the output target input signal.

[0042] Based on the design of the third switch unit 230, the fourth switch unit 240, and other devices, under the drive of the target level signal, the third switch unit 230 of the PPS_IN module 300 is turned off, the fourth switch unit 240 is turned on, and the eighth resistor R8 acts as a pull-up resistor to pull the level of the output terminal of the PPS_IN module 300 up to the level of the third voltage input terminal. The third voltage input terminal can be set to 1.8V. Finally, the PPS_IN module 300 converts the high-level target level signal transmitted in the middle into a low-level target input signal that can be input into the second SOC 400.

[0043] In addition, the first voltage input terminal can be set to 3.3V, the seventh resistor R7 can be set to a 10K resistor, the eighth resistor R8 can be set to a 47K resistor, and the second capacitor C2 can be set to a 100n 16V capacitor.

[0044] refer to Figure 5 In some embodiments, the third switching unit 230 includes a ninth resistor R9, a tenth resistor R10, and a third NPN transistor Q3; The negative terminal of the second diode D2 is connected to the ninth resistor R9. The other end of the ninth resistor R9 is connected to the base of the third NPN transistor Q3. The collector of the third NPN transistor Q3 is connected to the seventh resistor R7 and the fourth switch unit 240 respectively. The tenth resistor R10 is connected between the base and emitter of the third NPN transistor Q3. The emitter of the third NPN transistor Q3 is also connected to the ground terminal.

[0045] Optionally, the third switching unit 230 can be configured as a switching unit based on an NPN transistor. The ninth resistor R9 is used to adjust the voltage drop between the base and emitter of the third NPN transistor Q3 to control its conduction, thereby enabling the PPS_IN module 300 to convert the intermediate high-level target level signal into a low-level target input signal that can be input into the second SOC 400.

[0046] In some embodiments, the ninth resistor R9 is set to a 10K resistor and the tenth resistor R10 is set to a 47K resistor.

[0047] Specifically, the ninth resistor R9 is set to a 10K resistor, and the tenth resistor R10 is set to a 47K resistor. The target level signal is 12V. Based on the resistance values ​​of the ninth resistor R9 and the tenth resistor R10, the voltage drop between the base and emitter of the third NPN transistor Q3 can be greater than its turn-on threshold of 0.7V, thereby controlling the third switching unit 230 to conduct.

[0048] refer to Figure 5 In some embodiments, the fourth switching unit 240 includes an eleventh resistor R11, a twelfth resistor R12, and a fourth NPN transistor Q4; The eleventh resistor R11 is connected to the third switch unit 230. The other end of the eleventh resistor R11 is connected to the base of the fourth NPN transistor Q4. The collector of the fourth NPN transistor Q4 is connected to the eighth resistor R8. The twelfth resistor R12 is connected between the base and emitter of the fourth NPN transistor Q4. The emitter of the fourth NPN transistor Q4 is also connected to the ground terminal.

[0049] Optionally, the fourth switching unit 240 can be configured as a switching unit based on an NPN transistor. When the fourth switching unit 240 is turned on, the eleventh resistor R11 is actually connected to the ground terminal, resulting in no voltage drop between the base and emitter of the fourth NPN transistor Q4 that is greater than its turn-on threshold, thereby controlling its turn-off. This enables the PPS_IN module 300 to convert the intermediate high-level target level signal into a low-level target input signal that can be input into the second SOC 400.

[0050] In addition, the eleventh resistor R11 can be set to a 10K resistor, and the twelfth resistor R12 can be set to a 47K resistor.

[0051] The following is a detailed description and explanation of the solutions in the embodiments of the present invention, using specific application examples: In this embodiment of the application, a time synchronization circuit based on a dual-SOC chip architecture is provided. This solution can be applied to vehicle controllers configured with a dual-SOC architecture.

[0052] The circuit includes: a first SOC 100, a second SOC 400, a PPS_OUT module 200 and a PPS_IN module 300, which are connected by an external wiring harness.

[0053] The first SOC 100 is also connected to the PPS_OUT module 200. The PPS_OUT module 200 includes a first resistor R1, a second resistor R2, a first capacitor C1, a first diode D1, a first TVS transistor TVS1, a third resistor R3, a fourth resistor R4, a first NPN transistor Q1, a fifth resistor R5, a sixth resistor R6, and a second NPN transistor Q2. The third resistor R3 is set to 10KΩ, and the fourth resistor R4 is set to 47KΩ. The output terminal of the first SOC 100 is connected to the third resistor R3. The other end of the third resistor R3 is connected to the base of the first NPN transistor Q1. The collector of the first NPN transistor Q1 is connected to both the first resistor R1 and the fifth resistor R5. The fourth resistor R4 is connected between the base and emitter of the first NPN transistor Q1. The emitter of the first NPN transistor Q1 is also connected to ground. The other end of the first resistor R1 is connected to the first voltage input terminal. The other end of the fifth resistor R5 is connected to the base of the second NPN transistor Q2. The collector of the second NPN transistor Q2 is connected to the first... The positive terminal of diode D1 is connected to the second resistor R2. The sixth resistor R6 is connected between the base and emitter of the second NPN transistor Q2. The emitter of the second NPN transistor Q2 is also connected to the ground terminal. The other end of the second resistor R2 is connected to the second voltage input terminal and the first capacitor C1. The negative terminal of the first diode D1 is connected to the first TVS transistor TVS1. The other end of the first capacitor C1 and the other end of the first TVS transistor TVS1 are both connected to the ground terminal. The negative terminal of the first diode D1 is set as the output terminal of the PPS_OUT module 200.

[0054] The second voltage input terminal is set to the same level as the target level signal; the PPS_OUT module 200 is used to turn off the first NPN transistor Q1 and turn on the second NPN transistor Q2 under the drive of the target output signal, convert the target output signal output by the first SOC 100 to the target level signal, and output the target level signal to the PPS_IN module 300 through the external wiring harness.

[0055] The second SOC 400 is also connected to the PPS_IN module 300, which includes a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a second diode D2, a second TVS transistor TVS2, a ninth resistor R9, a tenth resistor R10, a third NPN transistor Q3, an eleventh resistor R11, a twelfth resistor R12, and a fourth NPN transistor Q4. The ninth resistor R9 is set to a 10K resistor, and the tenth resistor R10 is set to a 47K resistor. The positive terminal of the second diode D2 is set as the input terminal of the PPS_IN module 300. The positive terminal of the second diode D2 is also connected to the second TVS transistor TVS2. The negative terminal of the second diode D2 is connected to the ninth resistor R9. The other end of the ninth resistor R9 is connected to the base of the third NPN transistor Q3. The collector of the third NPN transistor Q3 is connected to the seventh resistor R7 and the eleventh resistor R11. The tenth resistor R10 is connected between the base and emitter of the third NPN transistor Q3. The emitter of the third NPN transistor Q3 is also connected to the ground terminal. The other end of the seventh resistor R7 is connected to the first voltage input terminal. The eleventh resistor R11 is connected to... The third switch unit 230 is connected, the other end of the eleventh resistor R11 is connected to the base of the fourth NPN transistor Q4, the collector of the fourth NPN transistor Q4 is connected to the eighth resistor R8, the twelfth resistor R12 is connected between the base and emitter of the fourth NPN transistor Q4, the emitter of the fourth NPN transistor Q4 is also connected to the ground terminal, the other end of the eighth resistor R8 is connected to the third voltage input terminal and the second capacitor C2 respectively, the other end of the second TVS transistor TVS2 and the other end of the second capacitor C2 are both connected to the ground terminal, and the connection terminal of the fourth switch unit 240 and the eighth resistor R8 is set as the output terminal of the PPS_IN module 300.

[0056] The PPS_IN module 300 is used to turn off the third NPN transistor Q3 and turn on the fourth NPN transistor Q4 under the drive of the target level signal, convert the received target level signal into a target input signal, and output the target input signal to the second SOC400.

[0057] This embodiment combines the PPS_OUT module 200 and the PPS_IN module 300 to perform two level conversions, forming a communication link between the first SOC 100 and the second SOC 400, thereby achieving time synchronization and functional linkage between the two SOCs and improving the implementation effect of multi-domain fusion control of the intelligent driving system.

[0058] This invention also provides a vehicle including a time synchronization circuit based on a dual-SOC chip architecture as described in the above embodiments.

[0059] The vehicle can be a private car, such as a sedan, SUV, MPV, or pickup truck. It can also be a commercial vehicle, such as a van, bus, small truck, or large semi-trailer. The vehicle must have an electric motor capable of outputting power or acting as a generator to store mechanical energy. When the vehicle is a new energy vehicle, it can be a hybrid or a pure electric vehicle.

[0060] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0061] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0062] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0063] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0064] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0065] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0067] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0069] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A time synchronization circuit based on a dual-SoC chip architecture, characterized in that, The circuit includes: a first SOC, a second SOC, a PPS_OUT module and a PPS_IN module, wherein the PPS_OUT module and the PPS_IN module are connected by an external wiring harness; The first SOC is also connected to the PPS_OUT module, which is used to convert the target output signal output by the first SOC into a target level signal and output the target level signal to the PPS_IN module through the external wiring harness. The second SOC is also connected to the PPS_IN module, which is used to convert the received target level signal into a target input signal and output the target input signal to the second SOC.

2. The circuit according to claim 1, characterized in that, The PPS_OUT module includes a first switching unit, a second switching unit, a first resistor, a second resistor, a first capacitor, a first diode, and a first TVS diode; The output terminal of the first SOC is connected to the first switching unit. The first switching unit is also connected to the ground terminal, the first resistor, and the second switching unit. The other end of the first resistor is connected to the first voltage input terminal. The second switching unit is also connected to the ground terminal, the positive terminal of the first diode, and the second resistor. The other end of the second resistor is connected to the second voltage input terminal and the first capacitor. The negative terminal of the first diode is connected to the first TVS diode. The other end of the first capacitor and the other end of the first TVS diode are both connected to the ground terminal. The negative terminal of the first diode is set as the output terminal of the PPS_OUT module. The second voltage input terminal is set to input the same level as the target level signal; the PPS_OUT module is used to turn off the first switching unit and turn on the second switching unit under the drive of the target output signal, so as to control the output of the target level signal.

3. The circuit according to claim 2, characterized in that, The first switching unit includes a third resistor, a fourth resistor, and a first NPN transistor; The output terminal of the first SOC is connected to the third resistor, the other end of the third resistor is connected to the base of the first NPN transistor, the collector of the first NPN transistor is connected to the first resistor and the second switching unit respectively, the fourth resistor is connected between the base and emitter of the first NPN transistor, and the emitter of the first NPN transistor is also connected to the ground terminal.

4. The circuit according to claim 3, characterized in that, The third resistor is set to a 10K resistor, and the fourth resistor is set to a 47K resistor.

5. The circuit according to claim 2, characterized in that, The second switching unit includes a fifth resistor, a sixth resistor, and a second NPN transistor; The fifth resistor is connected to the first switching unit, and the other end of the fifth resistor is connected to the base of the second NPN transistor. The collector of the second NPN transistor is connected to the anode of the first diode and the second resistor, respectively. The sixth resistor is connected between the base and emitter of the second NPN transistor, and the emitter of the second NPN transistor is also connected to the ground terminal.

6. The circuit according to claim 1, characterized in that, The PPS_IN module includes a third switching unit, a fourth switching unit, a seventh resistor, an eighth resistor, a second capacitor, a second diode, and a second TVS diode; The positive terminal of the second diode is set as the input terminal of the PPS_IN module. The positive terminal of the second diode is also connected to the second TVS diode. The negative terminal of the second diode is connected to the third switching unit. The third switching unit is also connected to the ground terminal, the seventh resistor, and the fourth switching unit. The other end of the seventh resistor is connected to the first voltage input terminal. The fourth switching unit is also connected to the ground terminal and the eighth resistor. The other end of the eighth resistor is connected to the third voltage input terminal and the second capacitor. The other ends of the second TVS diode and the second capacitor are both connected to the ground terminal. The connection terminal between the fourth switching unit and the eighth resistor is set as the output terminal of the PPS_IN module. The PPS_IN module is used to turn off the third switch unit and turn on the fourth switch unit under the drive of the target level signal, so as to control the output of the target input signal.

7. The circuit according to claim 6, characterized in that, The third switching unit includes a ninth resistor, a tenth resistor, and a third NPN transistor; The negative terminal of the second diode is connected to the ninth resistor, the other end of the ninth resistor is connected to the base of the third NPN transistor, the collector of the third NPN transistor is connected to the seventh resistor and the fourth switching unit, the tenth resistor is connected between the base and emitter of the third NPN transistor, and the emitter of the third NPN transistor is also connected to the ground terminal.

8. The circuit according to claim 7, characterized in that, The ninth resistor is set to a 10K resistor, and the tenth resistor is set to a 47K resistor.

9. The circuit according to claim 6, characterized in that, The fourth switching unit includes an eleventh resistor, a twelfth resistor, and a fourth NPN transistor; The eleventh resistor is connected to the third switching unit, and the other end of the eleventh resistor is connected to the base of the fourth NPN transistor. The collector of the fourth NPN transistor is connected to the eighth resistor. The twelfth resistor is connected between the base and emitter of the fourth NPN transistor. The emitter of the fourth NPN transistor is also connected to the ground terminal.

10. A vehicle, the vehicle being equipped with a time synchronization circuit based on a dual-SoC chip architecture as described in any one of claims 1 to 9.

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