SP application optimization method and device based on multi-core NUMA architecture

Abstract

The invention relates to an SP application optimization method and device based on a multi-core NUMA architecture. The method comprises the following steps of: in a compiling stage, performing compiling optimization based on a multi-core NUMA (Non Uniform Memory Access) architecture, and performing memory management by adopting a memory allocator perceived by the NUMA; in the initialization stage, an MPI process is bound to a specific NUMA node, an OpenMP thread in the MPI process is bound to a physical core of the node, and a memory area in charge of the MPI process is initialized in parallel through the thread so as to achieve data locality; in the execution stage, a NEON instruction is adopted to carry out vectorization optimization on the step of calculating the residual vector local sum. By adopting the method, the memory access delay across the NUMA nodes can be remarkably reduced through multi-level collaborative optimization, and the instruction execution efficiency and the floating point operation throughput rate are improved, so that the execution performance and the parallel expandability of an SP reference program on a multi-core NUMA architecture server are effectively improved.

Description

Technical Field

[0001] This application relates to the field of high-performance computing technology, and in particular to a method and apparatus for optimizing SP applications based on a multi-core NUMA architecture. Background Technology

[0002] With the widespread application of multi-core ARMv8 architecture servers in high-performance computing (HPC), their performance potential in numerical simulation and scientific computing has attracted widespread attention. The SP benchmark program is an important part of NASA's Parallel Benchmarks (NPB) set. It can simulate a class of simplified Navier-Stokes equations in compressible fluid dynamics and solve scalar partial differential equation problems with pentagonal matrix structures. It is widely used in scientific computing scenarios such as turbulence simulation, aerodynamic design, and combustion simulation.

[0003] SP programs typically employ a hybrid programming model combining MPI and OpenMP, solving problems across multiple spatial dimensions using an implicit method with alternating directions. However, on multi-core NUMA architecture servers, due to the complexity of the NUMA topology and the unevenness of memory access latency, traditional SP applications often face limitations in computational performance and low parallel efficiency. Specifically, this manifests as: significantly higher latency for remote memory access across NUMA nodes compared to local access, leading to data access bottlenecks; intense contention for the default memory allocator in multi-threaded environments, causing lock contention and memory fragmentation; compiler options failing to fully utilize the specific instruction set of the ARMv8 architecture; and low computational density for local sums of residual vectors.

[0004] Therefore, existing technologies suffer from technical problems such as low efficiency, low resource utilization, and poor scalability when SP applications run on multi-core NUMA architecture servers. Summary of the Invention

[0005] Therefore, it is necessary to provide an optimization method and apparatus that can significantly improve the execution efficiency and scalability of SP applications on multi-core NUMA architecture servers, addressing the aforementioned technical problems.

[0006] A method for optimizing SP applications based on a multi-core NUMA architecture is proposed. The SP benchmark program to be optimized adopts a hybrid programming model of MPI and OpenMP, and solves a system of partial differential equations in multiple spatial dimensions through an implicit method with alternating directions. The method includes: During the compilation phase, compilation optimization is performed based on a multi-core NUMA architecture, and a NUMA-aware memory allocator is used for memory management. During the initialization phase, the MPI process is bound to a specific NUMA node in the multi-core NUMA architecture, and the OpenMP thread inside the MPI process is bound to the physical core of the specific NUMA node.

[0007] During the execution phase, the step of calculating the local sum of the residual vector during the iteration process of the SP benchmark program is optimized using NEON instructions for vectorization. Specifically, multiple double-precision floating-point numbers are loaded at once using vector loading instructions, parallel operations are performed using vector multiply-accumulate instructions, and multiple NEON vector registers are used as independent accumulators.

[0008] In one embodiment, compilation optimization based on a multi-core NUMA architecture includes: Select the ACfL compiler and set the optimization level to -O3; Specify the target architecture as -mcpu=native, and enable the -ffast-math and -ftree-vectorize options to support fast floating-point calculations and automatic vectorization; Optimize -flto when linking is enabled.

[0009] In one embodiment, memory management using a NUMA-aware memory allocator includes: Use the jemalloc memory allocator instead of the system default allocator; By setting environment variables, jemalloc enables local memory pools for each CPU core, achieving memory allocation by core partitioning.

[0010] In one embodiment, binding the MPI process to a specific NUMA node in a multi-core NUMA architecture, and binding the OpenMP thread within the MPI process to the physical core of the specific NUMA node, includes: Using the numactl tool, the --cpubind and --membind parameters are used to bind each MPI process to a different NUMA node in a multi-core NUMA architecture; By setting the OpenMP environment variables OMP_PROC_BIND=close and OMP_PLACES=cores, the OpenMP threads within each MPI process are bound to the physical core of the NUMA node to which the MPI process belongs.

[0011] Using the first-touch strategy, before the parallel region begins, the threads that will use the corresponding data blocks initialize their respective memory regions in parallel.

[0012] In one embodiment, vectorization optimization using NEON instructions further includes: Multiple vector accumulator registers are used inside the loop to eliminate data dependencies; After the loop ends, the values ​​in multiple vector accumulators are horizontally summed to obtain the final local sum and scalar.

[0013] In one embodiment, the system of partial differential equations solved by the SP benchmark program is: ; in, These are vectors of conserved variables, where A, B, and C are flux Jacobian matrices representing the influence of the convection terms. These are source terms and diffusion terms; The alternating direction implicit method solves a system of five diagonal linear equations in each spatial direction. ,in and It is a lower triangular and upper triangular matrix. For the solution vector This is the right-hand term.

[0014] In one embodiment, the initialization phase further includes a thread-to-data-block binding step: The iterative computation space is divided into contiguous data blocks, and each data block is statically bound to a specific OpenMP thread; the OpenMP thread is fixed to a physical core that shares the same level of cache.

[0015] An SP application optimization apparatus for implementing the above-mentioned SP application optimization method based on multi-core NUMA architecture, the apparatus comprising: The basic optimization module is used to perform compilation optimization based on multi-core NUMA architecture during the compilation phase and to manage memory using a NUMA-aware memory allocator. The data locality optimization module is used to bind the MPI process to a specific NUMA node during the initialization phase, and bind the OpenMP thread inside the MPI process to the physical core of the specific NUMA node. The OpenMP thread initializes the memory region it is responsible for in parallel, so that the core data is located on the local NUMA node. The computation acceleration module is used to perform NEON vectorization optimization on the step of calculating the local sum of the residual vector in the SP benchmark program during the execution phase. It uses vector loading instructions to load multiple double-precision floating-point numbers at once, vector multiply-accumulate instructions for parallel operation, and multiple NEON vector registers as independent accumulators.

[0016] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program performing the following steps: During the compilation phase, compilation optimization is performed based on a multi-core NUMA architecture, and a NUMA-aware memory allocator is used for memory management. During the initialization phase, the MPI process is bound to a specific NUMA node in the multi-core NUMA architecture, and the OpenMP thread inside the MPI process is bound to the physical core of the specific NUMA node.

[0017] During the execution phase, the step of calculating the local sum of the residual vector during the iteration process of the SP benchmark program is optimized using NEON instructions for vectorization. Specifically, multiple double-precision floating-point numbers are loaded at once using vector loading instructions, parallel operations are performed using vector multiply-accumulate instructions, and multiple NEON vector registers are used as independent accumulators.

[0018] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor: During the compilation phase, compilation optimization is performed based on a multi-core NUMA architecture, and a NUMA-aware memory allocator is used for memory management. During the initialization phase, the MPI process is bound to a specific NUMA node in the multi-core NUMA architecture, and the OpenMP thread inside the MPI process is bound to the physical core of the specific NUMA node.

[0019] During the execution phase, the step of calculating the local sum of the residual vector during the iteration process of the SP benchmark program is optimized using NEON instructions for vectorization. Specifically, multiple double-precision floating-point numbers are loaded at once using vector loading instructions, parallel operations are performed using vector multiply-accumulate instructions, and multiple NEON vector registers are used as independent accumulators.

[0020] The aforementioned SP application optimization method and device based on multi-core NUMA architecture achieves performance breakthroughs across multiple dimensions, including compilation optimization, memory management, NUMA topology, and NEON vectorization reduction, through a systematic, multi-level collaborative optimization strategy. During the compilation phase, selecting a targeted compiler and configuring advanced optimization options significantly improves instruction execution efficiency and code quality, laying a solid foundation for subsequent optimizations. At the memory management level, the NUMA-aware jemalloc high-performance memory allocator effectively reduces lock contention and memory fragmentation issues in multi-threaded environments, improving memory access efficiency. Regarding NUMA topology optimization, a refined process and thread binding strategy, combined with a NUMA-aware method for data initialization, ensures tight coupling between computational tasks and memory resources, significantly reducing latency overhead from cross-node memory access. Furthermore, dividing the iterative computation space into contiguous data blocks and statically binding them to threads further enhances CPU cache utilization, reducing cache misses and memory bandwidth pressure. During the execution phase, NEON vectorization optimization is applied to key computational steps, fully utilizing the parallel computing capabilities of modern processors and significantly improving floating-point throughput. These optimization measures work together to solve the performance bottleneck problem faced by SP applications on multi-core NUMA architectures, enabling them to achieve significant speed improvements and excellent parallel scalability while maintaining numerical accuracy. This provides a reliable technical guarantee for the efficient operation of scientific computing applications in complex hardware environments. Attached Figure Description

[0021] Figure 1 This is an application scenario diagram of an SP application optimization method based on a multi-core NUMA architecture in one embodiment; Figure 2 This is a flowchart illustrating a SP application optimization method based on a multi-core NUMA architecture in one embodiment. Figure 3 This is a structural block diagram of an SP application optimization device based on a multi-core NUMA architecture in one embodiment; Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] The SP application optimization method based on multi-core NUMA architecture provided in this application can be applied to applications such as... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. Server 104 can be a multi-core NUMA architecture server. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0024] In one embodiment, such as Figure 2 As shown, a method for optimizing SP applications based on a multi-core NUMA architecture is provided, and this method is applied to... Figure 1 Taking the server in the example, the following steps are included: Step 202: During the compilation phase, compilation optimization is performed based on a multi-core NUMA architecture, and a NUMA-aware memory allocator is used for memory management.

[0025] Specifically, through meticulous compilation optimization for the target platform, it can be ensured that the generated machine code fully utilizes the features of the ARMv8 architecture, especially the NEON vector instruction unit and pipelined parallelism. Simultaneously, employing a NUMA-aware memory allocator effectively reduces lock contention and cross-node memory access in multi-threaded environments, laying the foundation for subsequent optimizations.

[0026] Step 204: During the initialization phase, the MPI process is bound to a specific NUMA node in the multi-core NUMA architecture, and the OpenMP thread inside the MPI process is bound to the physical core of the specific NUMA node. The memory region responsible for the OpenMP thread is initialized in parallel by the OpenMP thread so that the multidimensional array data corresponding to the conservation variable vector and residual vector required by the SP benchmark program are located on the local NUMA node of the OpenMP thread.

[0027] Specifically, by binding processes and threads to specific NUMA nodes and cores, and using a first-touch strategy to allow threads to initialize the memory regions they are responsible for in parallel, it can be ensured that the operating system's virtual memory manager allocates physical memory pages on the NUMA node where the thread accessing it for the first time resides, thereby maximizing the proportion of local memory accesses and significantly reducing memory access latency.

[0028] Step 206 involves using NEON instructions to vectorize and optimize the step of calculating the local sum of the residual vector during the iteration process of the SP benchmark program, and using multiple NEON vector registers as independent accumulators.

[0029] Multiple double-precision floating-point numbers are loaded at once using vector loading instructions, and parallel operations are performed using vector multiply-accumulate instructions.

[0030] Specifically, after each iteration's boundary exchange, the SP application requires residual calculation and a global MPIAllreduce operation to determine convergence. This operation is a global synchronization point, and its performance is crucial. The local sum calculations in the original code are typically implemented using scalar loops, which are computationally inefficient. By optimizing this with NEON vectorization, multiple data elements can be processed simultaneously, fully utilizing the data-level parallelism capabilities of modern processors, significantly improving computational throughput, and thus accelerating the entire global synchronization operation.

[0031] The aforementioned SP application optimization method based on a multi-core NUMA architecture achieves performance breakthroughs across multiple dimensions, including compilation optimization, memory management, NUMA topology, and NEON vectorization reduction, through a systematic, multi-level collaborative optimization strategy. During the compilation phase, selecting a targeted compiler and configuring advanced optimization options significantly improves instruction execution efficiency and code quality, laying a solid foundation for subsequent optimizations. At the memory management level, employing a NUMA-aware high-performance memory allocator effectively reduces lock contention and memory fragmentation issues in multi-threaded environments, improving memory access efficiency. Regarding NUMA topology optimization, a refined process and thread binding strategy, combined with a NUMA-aware method for data initialization, ensures tight coupling between computational tasks and memory resources, significantly reducing latency overhead from cross-node memory access. Furthermore, dividing the iterative computation space into contiguous data blocks and statically binding them to threads further enhances CPU cache utilization, reducing cache misses and memory bandwidth pressure. During the execution phase, NEON vectorization optimization is applied to key computational steps, fully utilizing the parallel computing capabilities of modern processors and significantly improving floating-point throughput. These optimization measures work together to solve the performance bottleneck problem faced by SP applications on multi-core NUMA architectures, enabling them to achieve significant speed improvements and excellent parallel scalability while maintaining numerical accuracy. This provides a reliable technical guarantee for the efficient operation of scientific computing applications in complex hardware environments.

[0032] In one embodiment, compilation optimization based on a multi-core NUMA architecture includes: selecting the ACfL compiler and setting the optimization level to -O3; specifying the target architecture as -mcpu=native and enabling the -ffast-math and -ftree-vectorize options to support fast floating-point calculations and automatic vectorization; and enabling linker optimization -flto.

[0033] In practice, the ACfL compiler was chosen as the compilation tool. Experience has shown that the ACfL compiler typically generates better code for the ARM architecture. The optimization level was set to -O3, which allows for aggressive inter-process and loop optimizations, including function inlining, loop unrolling, and register allocation optimization. The target architecture was specified as -mcpu=native, allowing the compiler to automatically detect the microarchitectural characteristics of the current CPU (such as Neoverse N1 / N2) and generate the optimal instruction sequence. Fast floating-point model and NEON vectorization were enabled using the -ffast-math and -ftree-vectorize options. -ffast-math breaks strict standard compliance, allowing the compiler to perform more aggressive floating-point optimizations, which is crucial for improving the performance of scientific computing applications. Simultaneously, link-time optimization -flto was enabled, allowing the compiler to perform global optimizations across source file boundaries during the linking stage, such as inlining functions defined in another source file and eliminating dead code across files. This is particularly effective for large applications such as SPs composed of multiple source files.

[0034] In one embodiment, memory management using a NUMA-aware memory allocator includes: replacing the system default allocator with the jemalloc memory allocator; and configuring jemalloc to use a memory pool partition local to each CPU core for memory allocation via environment variables.

[0035] In practice, the jemalloc memory allocator is used instead of the system's default glibc malloc. jemalloc is renowned for its excellent multi-threaded scalability, low fragmentation, and NUMA awareness. jemalloc is configured via environment variables, such as setting MALLOC_CONF=percpu_arena:percpu, to allocate memory using the local arena of each CPU core whenever possible. This configuration significantly reduces lock contention during memory allocation in multi-threaded environments, while ensuring that allocated memory resides on the NUMA node where the requesting thread resides, thus avoiding unnecessary remote memory accesses. In NUMA systems, the default glibc malloc presents a bottleneck, especially under intense multi-threaded contention; using a NUMA-aware memory allocator effectively reduces remote memory accesses.

[0036] In one embodiment, binding an MPI process to a specific NUMA node in a multi-core NUMA architecture and binding the OpenMP thread within the MPI process to the physical core of the specific NUMA node includes: using the numactl tool to bind each MPI process to a different NUMA node in the multi-core NUMA architecture using the --cpubind and --membind parameters; and binding the OpenMP thread within each MPI process to the physical core of the NUMA node to which the MPI process belongs by setting the OpenMP environment variables OMP_PROC_BIND=close and OMP_PLACES=cores.

[0037] In practice, the numactl tool is used, with the --cpubind and --membind parameters to bind each MPI process to a different NUMA node. For example, running the command "numactl --cpubind=0 --membind=0 . / sp.Ax" binds the process to NUMA node 0, ensuring that the process's memory allocation and computational tasks are primarily concentrated on node 0. By setting the OpenMP environment variables OMP_PROC_BIND=close and OMP_PLACES=cores, the OpenMP threads within each MPI process are bound to the physical cores of the NUMA node to which the MPI process belongs. OMP_PROC_BIND=close indicates that the thread is bound to a contiguous core close to the main thread, and OMP_PLACES=cores explicitly specifies that the binding location is a physical core rather than a hyperthread. This binding strategy can increase the cache hit rate because frequent switching between multiple CPUs by threads can easily invalidate the cache of the CPU on which the thread was originally running. Binding threads to CPUs sharing the same level of cache can make full use of reused data. At the same time, this binding method reduces the overhead of thread scheduling, because switching threads between CPUs requires overhead, and specifying that a thread runs on a specific CPU can reduce this overhead.

[0038] In one embodiment, the vectorization optimization using NEON instructions further includes: using multiple vector accumulator registers inside the loop to eliminate data dependencies; and after the loop ends, horizontally summing the values ​​in the multiple vector accumulators to obtain the final local sum scalar.

[0039] In practical implementation, multiple vector accumulator registers are used within the loop to eliminate data dependencies. Traditional scalar accumulation forms long dependency chains, limiting the processor pipeline's performance. Using multiple independent accumulator registers breaks this dependency and improves instruction-level parallelism. After the loop ends, the values ​​in the multiple vector accumulators are horizontally summed to obtain a final scalar sum. NEON technology is an advanced 64-bit or 128-bit mixed fixed-vector-length SIMD instruction architecture extension in ARM Cortex-A and Cortex-R series processors. NEON technology uses 32 64-bit or 128-bit vector registers containing elements of the same data type, allowing simultaneous operations on multiple data elements and supporting both integer and floating-point operands. Scalar operations that originally required four operations can be completed in a single operation under NEON instructions. In the implementation, intrinsic functions such as `vld1q_f64` load multiple double-precision floating-point numbers from memory into the NEON register at once. Parallel computation is then performed using the `vmlaq_f64` multiply-accumulate instruction or the `vmulq_f64` multiplication instruction and the `vaddq_f64` addition instruction. It is ensured that the number of loop iterations is an integer multiple of the SIMD width (2 for double-precision floating-point numbers), or that the remaining part is processed using remainder operations. Loop unrolling can further improve performance.

[0040] In one embodiment, the system of partial differential equations solved by the SP benchmark program is: ; in, These are vectors of conserved variables, where A, B, and C are flux Jacobian matrices representing the influence of the convection terms. These are source terms and diffusion terms; The alternating direction implicit method solves a system of five diagonal linear equations in each spatial direction. ,in and It is a lower triangular and upper triangular matrix. For the solution vector This is the right-hand term.

[0041] In its implementation, the SP benchmark program solves a set of nonlinear partial differential equations, whose mathematical form describes the physical processes in compressible fluid dynamics. This set of equations is solved using an implicit method in alternating directions to solve a pentagonal linear system in each spatial direction. Specifically, the algorithm solves the pentagonal linear system in each direction using the ADI method, with each time step including steps such as calculating the right-hand side, solving the pentagonal equations in the x / y / z directions, and updating the solution vector. While this numerical method ensures computational stability, it places high demands on memory access patterns and computational efficiency, highlighting the necessity of the optimization measures in this application.

[0042] In one embodiment, the initialization phase further includes a thread-to-data-block binding step: The iterative computation space is divided into contiguous data blocks, and each data block is statically bound to a specific OpenMP thread; the OpenMP thread is fixed to a physical core that shares the same level of cache.

[0043] In practice, the `omp_get_thread_num()` function of OpenMP is called to obtain the thread number of each thread. All data is divided into n equal parts, and then bound to the n threads in order of thread number. OpenMP threads are fixed to physical cores sharing the same level of cache. Before binding, only one iteration of computation can be allocated to a thread sequentially. After binding, each thread can be allocated consecutive iteration blocks. Specifically, the first thread is allocated (block-1) consecutive iterations, the second to the penultimate thread are allocated (block) consecutive iterations, and the remaining iterations are allocated to the last thread. This method ensures that each thread is allocated consecutive iteration blocks, increases the spatial locality of data, and enables effective data reuse among cores sharing the same cache. Its code overhead is slightly less than static scheduling and it can be flexibly bound according to the characteristics of different applications, better utilizing the local reuse characteristics of data, thereby achieving better performance.

[0044] To ensure NUMA awareness during data initialization, the memory regions handled by the OpenMP thread are initialized in parallel by the OpenMP thread, including: A "first-touch" strategy is employed. Before the parallel region begins, the threads that will use the data block initialize their respective memory regions in parallel (e.g., a simple write operation). This ensures that the operating system's virtual memory manager allocates physical memory pages on the NUMA node where the thread accessing it for the first time resides. Even if threads are core-bound, if the main process initializes all data on node 0, threads on other nodes will trigger numerous page faults on their first access to the data, causing pages to be migrated from node 0 to their local memory, resulting in performance jitter in the initial stage. The "first-touch" strategy effectively avoids this problem.

[0045] To evaluate the practical effect of the multi-level optimization strategy proposed in this application, the experiment was conducted on a Phytium S5000C server. The test platform ran the Kylin V10 operating system to ensure that the overall software and hardware environment adopted the domestic ecosystem. The server uses a dual-socket ARMv8 architecture processor, with each processor containing 64 computing cores, totaling 128 cores, and a main frequency of 2.1 GHz, which can provide sufficient computing power for large-scale parallel computing.

[0046] The experiments tested the performance of the SP application on datasets of different sizes (S, W, B, D) and with varying numbers of enabled cores (from single-core to 128 cores). The data in the table shows the execution time difference between the original and optimized versions under the same runtime environment. The optimized implementation comprehensively applies multiple performance improvement techniques, including compiler-level optimizations, NUMA topology-aware thread and memory binding, improved memory allocation, and vectorized reduction processing in the computation kernel. Through these optimizations, the performance of the SP application is significantly improved when running on multiple cores and across NUMA nodes.

[0047] Table 1. Time (seconds) for different datasets under different OMP threads in a 1MPI process.

[0048] Table 2. Time (seconds) for different datasets under different OMP threads in the 2MPI process.

[0049] Table 3. Time (seconds) for different datasets under different OMP threads in the 4MPI process.

[0050] Table 4. Time (seconds) for different datasets under different OMP threads in an 8MPI process.

[0051] Table 5. Time (seconds) of 16MPI process with different OMP threads on different datasets

[0052] The size information of the datasets (S, W, B, D) is shown in Table 6.

[0053] Table 6 Different Dataset Sizes

[0054] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0055] In one embodiment, such as Figure 3 As shown, an SP application optimization device is provided for implementing the above-mentioned SP application optimization method based on a multi-core NUMA architecture, including: a basic optimization module 302, a data locality optimization module 304, and a computation acceleration module 306, wherein: The basic optimization module 302 performs compilation optimization based on a multi-core NUMA architecture during the compilation phase and uses a NUMA-aware memory allocator for memory management.

[0056] The data locality optimization module 304 is used to bind the MPI process to a specific NUMA node during the initialization phase, and bind the OpenMP thread inside the MPI process to the physical core of the specific NUMA node. The OpenMP thread initializes the memory region it is responsible for in parallel, so that the core data is located on the local NUMA node.

[0057] The computation acceleration module 306 is used to perform NEON vectorization optimization on the step of calculating the local sum of the residual vector in the SP benchmark program during the execution phase; wherein, multiple double-precision floating-point numbers are loaded at once using vector loading instructions, and parallel operations are performed using vector multiply-accumulate instructions.

[0058] In one embodiment, the basic optimization module 302 is further configured to select the LLVM / Clang compiler or ARMCompiler for Linux and set the optimization level to -O3; specify the target architecture as -mcpu=native and enable the -ffast-math and -ftree-vectorize options to support fast floating-point calculation and automatic vectorization; and enable link-time optimization -flto.

[0059] In one embodiment, the basic optimization module 302 is further configured to perform memory management using a NUMA-aware memory allocator, including: replacing the system default allocator with the jemalloc memory allocator; and configuring jemalloc to use a memory pool partition local to each CPU core for memory allocation via environment variables.

[0060] In one embodiment, the data locality optimization module 304 is further configured to bind the MPI process to a specific NUMA node in a multi-core NUMA architecture, and to bind the OpenMP thread within the MPI process to the physical core of the specific NUMA node. This includes: using the numactl tool, binding each MPI process to a different NUMA node in the multi-core NUMA architecture using the --cpubind and --membind parameters; and binding the OpenMP thread within each MPI process to the physical core of the NUMA node to which the MPI process belongs by setting the OpenMP environment variables OMP_PROC_BIND=close and OMP_PLACES=cores.

[0061] In one embodiment, the computation acceleration module 306 is further configured to perform vectorization optimization using NEON instructions, and includes: using multiple vector accumulator registers inside the loop to eliminate data dependencies; and after the loop ends, horizontally summing the values ​​in the multiple vector accumulators to obtain the final local sum scalar.

[0062] In one embodiment, the computation acceleration module 306 is also used for solving the partial differential equations in the SP benchmark program, which are: ; in, These are vectors of conserved variables, where A, B, and C are flux Jacobian matrices representing the influence of the convection terms. These are the source and diffusion terms; the alternating direction implicit method solves the five diagonal linear equations in each spatial direction. ,in and It is a lower triangular and upper triangular matrix. For the solution vector This is the right-hand term.

[0063] In one embodiment, the data locality optimization module 304 is further configured to divide the iterative computation space into contiguous data blocks and statically bind each data block to a specific OpenMP thread; the OpenMP thread is fixed to a physical core sharing the same level of cache.

[0064] Specific limitations regarding the SP application optimization device can be found in the limitations of the SP application optimization method described above, and will not be repeated here. Each module in the aforementioned SP application optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0065] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores input / output data and performance metrics of the SP program. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements an SP application optimization method.

[0066] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0067] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described above.

[0068] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0069] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for optimizing SP applications based on a multi-core NUMA architecture, characterized in that, The SP benchmark program to be optimized adopts a hybrid programming model of MPI and OpenMP, and solves a system of partial differential equations in multiple spatial dimensions through an implicit method of alternating directions. The method includes: During the compilation phase, compilation optimization is performed based on a multi-core NUMA architecture, and a NUMA-aware memory allocator is used for memory management. During the initialization phase, the MPI process is bound to a specific NUMA node in the multi-core NUMA architecture, and the OpenMP thread inside the MPI process is bound to the physical core of the specific NUMA node. During the execution phase, the step of calculating the local sum of the residual vector during the iteration process of the SP benchmark program is optimized using NEON instructions for vectorization. Specifically, multiple double-precision floating-point numbers are loaded at once using vector loading instructions, parallel operations are performed using vector multiply-accumulate instructions, and multiple NEON vector registers are used as independent accumulators.

2. The method according to claim 1, characterized in that, Compilation optimizations based on multi-core NUMA architecture include: Select the ACfL compiler and set the optimization level to -O3; Specify the target architecture as -mcpu=native, and enable the -ffast-math and -ftree-vectorize options to support fast floating-point calculations and automatic vectorization; Optimize -flto when linking is enabled.

3. The method according to claim 1, characterized in that, Memory management using a NUMA-aware memory allocator includes: Use the jemalloc memory allocator instead of the system default allocator; By setting environment variables, jemalloc enables local memory pools for each CPU core, achieving memory allocation by core partitioning.

4. The method according to claim 1, characterized in that, Binding the MPI process to a specific NUMA node in a multi-core NUMA architecture, and binding the OpenMP thread within the MPI process to the physical core of the specific NUMA node, includes: Using the numactl tool, the --cpubind and --membind parameters are used to bind each MPI process to a different NUMA node in a multi-core NUMA architecture; By setting the OpenMP environment variables OMP_PROC_BIND=close and OMP_PLACES=cores, the OpenMP threads within each MPI process are bound to the physical core of the NUMA node to which the MPI process belongs. Using the first-touch strategy, before the parallel region begins, the threads that will use the corresponding data blocks initialize their respective memory regions in parallel.

5. The method according to claim 1, characterized in that, Vectorization optimization using NEON instructions also includes: Multiple vector accumulator registers are used inside the loop to eliminate data dependencies; After the loop ends, the values ​​in multiple vector accumulators are horizontally summed to obtain the final local sum and scalar.

6. The method according to claim 1, characterized in that, The system of partial differential equations solved by the SP benchmark program is as follows: in, These are vectors of conserved variables, where A, B, and C are flux Jacobian matrices representing the influence of the convection terms. These are source terms and diffusion terms; The alternating direction implicit method solves a system of five diagonal linear equations in each spatial direction. ,in and It is a lower triangular and upper triangular matrix. For the solution vector This is the right-hand term.

7. The method according to any one of claims 1 to 6, characterized in that, The initialization phase also includes a thread-to-data-block binding step: The iterative computation space is divided into contiguous data blocks, and each data block is statically bound to a specific OpenMP thread; the OpenMP thread is fixed to a physical core that shares the same level of cache.

8. An SP application optimization apparatus, used to implement the SP application optimization method based on a multi-core NUMA architecture as described in any one of claims 1 to 7, characterized in that, The device includes: The basic optimization module is used to perform compilation optimization based on multi-core NUMA architecture during the compilation phase and to manage memory using a NUMA-aware memory allocator. The data locality optimization module is used to bind the MPI process to a specific NUMA node during the initialization phase, and bind the OpenMP thread inside the MPI process to the physical core of the specific NUMA node. The OpenMP thread initializes the memory region it is responsible for in parallel, so that the core data is located on the local NUMA node. The computation acceleration module is used to perform NEON vectorization optimization on the step of calculating the local sum of the residual vector in the SP benchmark program during the execution phase. It uses vector loading instructions to load multiple double-precision floating-point numbers at once, vector multiply-accumulate instructions for parallel operation, and multiple NEON vector registers as independent accumulators.

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