A memory chip compatibility test method, device and medium

Abstract

The application discloses a kind of storage chip compatibility test method, equipment and medium, it is related to chip compatibility test technical field, including, the multiple-source heterogeneous data generated when the running preset inducing test load of the storage chip to be measured is collected, and fusion is carried out, generates multidimensional time series data set;Based on multidimensional time series data set calculation multiscale entropy feature vector, from the compatibility fault feature knowledge base pre-constructed, obtain reference fault mode feature vector, combine multiscale entropy feature vector and reference fault mode feature vector to generate chip health state feature vector;Migration meta-learning model is constructed, and chip health state feature vector is input into migration meta-learning model, and risk probability score and fault root cause classification result are generated by forward inference calculation.The application generates multidimensional time series data set by collecting multiple-source heterogeneous data, realizes the collaborative collection and integration of the multiple physical parameters of storage chip.

Description

Technical Field

[0001] This invention relates to the field of chip compatibility testing technology, and in particular to a method, equipment and storage medium for testing the compatibility of memory chips. Background Technology

[0002] As the interface speed and power consumption requirements of memory chips continue to increase, compatibility testing methods have gradually shifted from basic functional verification to multi-dimensional performance evaluation. Early testing schemes mainly relied on electrical parameter comparison and protocol consistency checks to determine compatibility. In recent years, timing waveform analysis and power consumption monitoring have been used to assist in fault location by collecting data such as signal integrity and power supply noise. Modern test networks can collect multi-source data such as signal eye diagrams, power supply ripple, and junction temperature changes, thereby improving test coverage through comprehensive evaluation.

[0003] Current memory chip compatibility testing methods have shortcomings. Test data is not fully utilized; heterogeneous data such as voltage, current, and temperature are often processed in isolation during analysis, lacking cross-modal correlation mechanisms. This makes it difficult to effectively capture the comprehensive fault characteristics under multi-physics coupling, resulting in low sensitivity for detecting intermittent faults and concurrent anomalies. Furthermore, diagnostic models have limited generalization ability; static threshold rules or single machine learning models struggle to adapt to parameter differences across different chip platforms and cannot simultaneously achieve risk quantification assessment and root cause localization, thus limiting the applicability of test conclusions in engineering practice. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a memory chip compatibility testing method to address the problems of insufficient utilization of multi-source heterogeneous data and insufficient generalization ability of diagnostic models.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a method for testing the compatibility of memory chips, comprising: collecting multi-source heterogeneous data generated when the memory chip under test runs a preset induced test load, and fusing the data to generate a multi-dimensional time series dataset; calculating a multi-scale entropy feature vector based on the multi-dimensional time series dataset, obtaining a baseline fault mode feature vector from a pre-constructed compatibility fault feature knowledge base, and combining the multi-scale entropy feature vector with the baseline fault mode feature vector to generate a chip health status feature vector; constructing a transfer meta-learning model, inputting the chip health status feature vector into the transfer meta-learning model, and generating a risk probability score and fault root cause classification result through forward inference calculation; and performing multi-dimensional structured integration and deep analysis on the risk probability score and fault root cause classification result to generate a compatibility deep diagnostic summary.

[0008] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the steps of collecting multi-source heterogeneous data generated when the memory chip under test runs a preset induced test load, and fusing the data to generate a multi-dimensional time series dataset are as follows.

[0009] The preset induced test load is converted into an electrical signal sequence through protocol programming and applied to the memory chip under test, so that the memory chip under test is in the operating state.

[0010] Collect multi-source heterogeneous data generated by the memory chip under test during operation, perform data cleaning and time synchronization on the multi-source heterogeneous data, and generate preprocessed multi-source data;

[0011] Preprocessed multi-source data are aligned and stitched together along the time dimension to generate a multidimensional time series dataset.

[0012] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the specific steps for calculating the multi-scale entropy feature vector based on the multi-dimensional time series dataset are as follows:

[0013] The multidimensional time series dataset was normalized using the Max-Min method;

[0014] Calculate the sample entropy values ​​of the normalized multidimensional time series dataset, and combine all the sample entropy values ​​to generate a multi-scale entropy feature vector.

[0015] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the specific steps for generating a chip health status feature vector by combining the multi-scale entropy feature vector with the baseline fault mode feature vector are as follows:

[0016] Historical test data is extracted from a pre-set test database, and a compatibility fault feature knowledge base is built based on the historical test data;

[0017] Input the multi-scale entropy feature vector into the compatibility fault feature knowledge base to match historical fault features;

[0018] Historical fault features are weighted and fused to generate a baseline fault mode feature vector.

[0019] The multi-scale entropy feature vector is concatenated and fused with the baseline fault mode feature vector to generate the chip health status feature vector.

[0020] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the specific steps for constructing the transfer meta-learning model are as follows:

[0021] A feature encoding layer is constructed based on the ReLU activation function, a risk probability scoring layer is constructed based on the Sigmoid activation function, and a fault root cause classification layer is constructed based on the Softmax activation function.

[0022] A transfer meta-learning model is constructed based on the feature encoding layer, risk probability scoring layer, and fault root cause classification layer.

[0023] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the specific steps for generating risk probability scores and fault root cause classification results through forward inference calculation are as follows:

[0024] The chip health status feature vector is input into the transfer meta-learning model, and the feature encoding layer performs a nonlinear transformation on the chip health status feature vector to generate abstract features.

[0025] The abstract features are forward-computed through a risk probability scoring layer and a fault root cause classification layer to generate risk probability scores and fault root cause classification results.

[0026] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the steps for multi-dimensional structured integration and in-depth analysis of the risk probability score and fault root cause classification results to generate a compatibility in-depth diagnostic summary are as follows.

[0027] Risk probability scores are converted into risk level identifiers using predefined risk level mapping rules;

[0028] From the root cause classification results, the root cause category with the highest probability value is extracted as the primary root cause.

[0029] The risk probability score, risk level identifier, primary root cause of failure and corresponding root cause category probability value are integrated through a predefined summary format specification to generate a compatibility-deep diagnostic summary.

[0030] As a preferred embodiment of the memory chip compatibility testing method of the present invention, the predefined summary format specification stipulates the field names, data types, arrangement order and output format of risk probability score, risk level identifier, primary root cause of failure and corresponding root cause category probability value in the compatibility depth diagnostic summary.

[0031] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements any step of the memory chip compatibility testing method as described in the first aspect of the present invention.

[0032] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the memory chip compatibility testing method as described in the first aspect of the present invention.

[0033] The beneficial effects of this invention are as follows: By collecting multi-source heterogeneous data and using a cross-modal fusion algorithm to generate a multi-dimensional time series dataset, the collaborative collection and integration of various physical parameters during the operation of memory chips is realized, solving the problem of isolated data analysis and improving data utilization efficiency and the comprehensiveness of fault detection; by combining and generating chip health status feature vectors, multi-scale and cross-dimensional feature extraction of chip status is realized, which can capture latent fault modes and complex time series features, enhancing the accuracy and reliability of fault diagnosis; by integrating and generating compatibility deep diagnostic summaries, automated and intelligent compatibility assessment is realized, reducing manual intervention, improving testing efficiency and interpretability, and improving the accuracy, generalization ability and engineering applicability of memory chip compatibility testing. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of a memory chip compatibility testing method.

[0036] Figure 2 A flowchart for generating a multidimensional time series dataset.

[0037] Figure 3 A flowchart for generating risk probability scores and root cause classification results.

[0038] Figure 4 A flowchart for generating a deep compatibility diagnostic summary. Detailed Implementation

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0041] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0042] Reference Figures 1-4 This is one embodiment of the present invention, which provides a memory chip compatibility testing method, including the following steps:

[0043] S1. Collect multi-source heterogeneous data generated when the memory chip under test runs a preset induced test load, and fuse them to generate a multi-dimensional time series dataset;

[0044] S1.1. The preset induced test load is converted into an electrical signal sequence through protocol programming and applied to the memory chip under test, so that the memory chip under test is in the running state.

[0045] It should be noted that by analyzing the specifications and common compatibility issues of memory chips, targeted test instructions and data modes are defined in advance. These test instructions and data modes are the induced test loads. Specifically, they include read and write operations, stress tests, error injection, and boundary value checks under different frequency, voltage, and timing conditions to ensure coverage of various operating states and potential failure scenarios of the chip.

[0046] By controlling the digital signal processing components and digital-to-analog converters inside the test equipment, the test instructions and data patterns contained in the induced test load are converted into electrical signal sequences with precise voltage amplitude, specific waveform characteristics, and strict time relationships, according to parameters such as voltage values, signal rise / fall times, clock cycles, and setup and hold times specified by the memory chip communication standard. The electrical signal sequence is then loaded onto the corresponding pins of the memory chip under test using the high-speed interface of the test equipment, driving the memory chip under test to start normal operation and perform test tasks.

[0047] The memory chip communication standard refers to the interface definition specification that regulates the data exchange between memory chips and external controllers; it defines the electrical characteristics of the physical interface (such as signal voltage values, setup and hold times in timing parameters, and clock frequency range), logic instruction set (such as read and write control commands, status query commands, and power management commands), and data transmission protocol (such as differential signal topology and data packet verification method) to ensure that memory chips and controllers from different manufacturers can achieve interoperability.

[0048] S1.2. Collect multi-source heterogeneous data generated by the memory chip under test during operation through a multi-source sensor array; perform data cleaning and time synchronization on the multi-source heterogeneous data to generate preprocessed multi-source data;

[0049] It should be noted that by using physical measurement devices such as voltage probes, current clamps, temperature sensors, high-speed oscilloscope channels, and logic analyzer probes deployed around the memory chip under test and on the test circuit, different types of multi-source heterogeneous data such as power ripple, dynamic power consumption current, junction temperature changes, and signal eye diagram waveforms generated by the memory chip under test during operation are collected.

[0050] Remove abrupt data points that exceed the range of electrical parameters from multi-source heterogeneous data; use a sliding window mean filtering algorithm to calculate the arithmetic mean of multiple adjacent data points within the sliding window to replace the center point value, thereby smoothing random fluctuations and suppressing high-frequency noise, thus completing noise filtering;

[0051] The electrical parameter range is the absolute maximum rated value defined based on the datasheet and interface standard specifications of the memory chip under test; the electrical parameter ranges are also different for different memory chips under test.

[0052] A unified high-precision clock signal is sent to all physical measurement devices through an external precision clock source, so that all physical measurement devices sample based on the high-precision clock signal and mark each acquired data point with a precise timestamp, so that all multi-source heterogeneous data have a common time reference when they are acquired; the multi-source heterogeneous data that has completed outlier removal, noise filtering and time synchronization is called preprocessed multi-source data.

[0053] S1.3 Align and stitch the preprocessed multi-source data along the time dimension to generate a multidimensional time series dataset.

[0054] It should be noted that by using a linear interpolation algorithm, all preprocessed multi-source data with different acquisition frequencies are forcibly matched to the same time point determined by a unified timestamp sequence, so that the voltage value, current value, temperature value and signal waveform amplitude have a completely consistent time scale at every moment.

[0055] By selecting the earliest time point among all preprocessed multi-source data as the starting point and the latest time point as the ending point, and using the interval corresponding to the highest sampling frequency among all preprocessed multi-source data as the benchmark step size, a unified timestamp sequence continuously distributed from the starting point to the ending point at fixed time intervals is generated.

[0056] The aligned preprocessed multi-source data are arranged at each same time point in a fixed order of voltage, current, temperature and signal waveform amplitude to form a data point set; the data point sets corresponding to all time points are arranged vertically in chronological order to form a multidimensional time series dataset with rows representing time points and columns representing parameter types.

[0057] It should also be noted that the fixed order of voltage, current, temperature and signal waveform is defined based on signal dependence and data processing efficiency; voltage is the most basic parameter of the circuit, current change depends on voltage drive, temperature is a derivative effect of current and power consumption, and signal waveform is the continuous trajectory of voltage and current change over time, including the amplitude, the slope of rising and falling edges, whether there is overshoot or ringing, and whether the level is in a stable state, etc.

[0058] S2. Calculate the multi-scale entropy feature vector based on the multi-dimensional time series dataset, obtain the benchmark fault mode feature vector from the pre-built compatibility fault feature knowledge base, and combine the multi-scale entropy feature vector with the benchmark fault mode feature vector to generate the chip health status feature vector.

[0059] S2.1 Normalize the multidimensional time series dataset using the Max-Min method; calculate the sample entropy value of the normalized multidimensional time series dataset, and combine all the sample entropy values ​​to generate a multi-scale entropy feature vector;

[0060] It should be noted that the normalization process involves iterating through all data values ​​of the parameter columns in the multidimensional time series dataset, extracting the global minimum and global maximum values ​​of the parameter columns at all time points using a comparison algorithm, and using the difference between each data value of the parameter column and the global minimum value of the corresponding parameter type as the parameter difference, and the difference between the global maximum value and the global minimum value of the corresponding parameter type as the global difference. The ratio of the parameter difference to the global difference is calculated to scale all values ​​of each parameter type to the range of 0 to 1, thus completing the normalization process of the multidimensional time series dataset.

[0061] Define a set of scaling factor sequences: based on the theoretical framework of multi-scale entropy analysis and the characteristic definition of the signal to be analyzed, the values ​​range from 1 to 10; scaling factor 1 is used to retain the complete details of the parameter series, and scaling factors 2 to 10 are used to progressively extract the medium- and long-term correlation features of the parameter series; the scaling factor is not less than 1 because the subsequent data window needs to contain an integer number of data points; the scaling factor is not greater than 10 because it is limited by the length of the parameter series. When the scaling factor is too large, the length of the subsequent coarse-grained sequence will be shortened, which will lead to a decrease in the statistical reliability of multi-scale entropy.

[0062] The normalized parameter column is divided into continuous non-overlapping data windows. Each data window contains continuous data points of a certain scale factor. For example, the first scale factor is 1, and each data window contains only one continuous data point. The second scale factor is 2, and each data window contains two continuous data points. This process continues until all scale factors have been used to process the parameter column.

[0063] Calculate the arithmetic mean of all continuous data points within each data window, and arrange the arithmetic mean calculated for each data window in chronological order to form a new time series, which is the coarse-grained series under the current scale factor.

[0064] The sample entropy value of each coarse-grained sequence is calculated using the multi-scale entropy formula, expressed as follows:

[0065] ;

[0066] ;

[0067] in, The sample entropy value represents the coarse-grained sequence; The dimension of the pattern is a positive integer; Represents the similarity tolerance, a positive real number; Indicated in the scale factor Below, the length of the coarse-grained sequence; Indicates the scale factor; Indicated in the scale factor Below, the length is The probability of a match between vectors; Indicated in the scale factor Below, the length is The probability of a match between vectors; Indicated in the scale factor Below, the length is The probability of matching between vectors; Represents the vector length variable, when hour, That is ,when hour, That is ; and This represents the starting index of the vector in the coarse-grained sequence, with values ​​ranging from 1 to... ; Indicates the first in the coarse-grained sequence Starting from one data point, continuously take... A vector composed of data points; Indicates the first in the coarse-grained sequence Starting from one data point, continuously take... A vector composed of data points; Representing vectors sum vector The distance between them; This indicates an indicator function; the value of the indicator function is 1 when the condition within the parentheses is true, and 0 otherwise.

[0068] The theoretical framework based on multi-scale entropy analysis defines the pattern dimension as 2. If the value is 1, only a single data point is compared, which cannot capture the structural information in the coarse-grained sequence. If the value is 3 or greater, the length of the coarse-grained sequence needs to be increased to obtain a sufficient number of vector matches to ensure statistical reliability, which leads to an increase in computational cost.

[0069] A similarity tolerance is defined based on signal-noise characteristics and statistical stability requirements, with a value ranging from 0.1 to 0.25 times the coarse-grained sequence standard deviation. If the noise level is below 0.1 times the standard deviation of the coarse-grained sequence, noise will be misjudged as valid information, leading to an overestimation of the sample entropy. If the value is higher than 0.25, effective information will be ignored, resulting in the sample entropy value being underestimated;

[0070] Arrange the sample entropy values ​​of all coarse-grained sequences in ascending order of scale factor to generate a multi-scale entropy feature vector.

[0071] S2.2 Extract historical test data from the preset test database, and construct a compatibility fault feature knowledge base based on the historical test data. Input the multi-scale entropy feature vector into the compatibility fault feature knowledge base to match historical fault features.

[0072] It should be noted that the data table structure is established and fields are defined (such as chip model, test timestamp, voltage parameter column, current parameter column, temperature parameter column, signal waveform parameter column, and historical fault characteristics). The historical data sequence and corresponding historical fault characteristics are imported into the data table structure in batches in the form of records. An index is created based on the chip model and historical fault characteristic fields to complete the construction of the test database.

[0073] Historical test data is extracted from the test database, including historical data sequences such as power ripple, dynamic power consumption current, junction temperature change and signal eye diagram waveform collected in historical chip tests, as well as corresponding historical fault features; multi-scale entropy calculation is performed on each historical data sequence to generate historical multi-scale entropy feature vectors, and the historical multi-scale entropy feature vectors are associated with the corresponding historical fault features and stored in the form of a compatibility fault feature knowledge base in the form of a data table.

[0074] Input the multi-scale entropy feature vector into the compatibility fault feature knowledge base, calculate the distance between the multi-scale entropy feature vector and the historical multi-scale entropy feature vector, and use this distance to measure the similarity between the two. The expression is as follows:

[0075] ;

[0076] in, This represents the distance between the multi-scale entropy eigenvector and the historical multi-scale entropy eigenvector; Represents the multi-scale entropy feature vector; Represents the historical multi-scale entropy feature vector; Represents the multi-scale entropy eigenvector In the Feature values ​​in each dimension; Represents the historical multi-scale entropy feature vector In the Feature values ​​in each dimension; The total dimension of the multi-scale entropy feature vector and the historical multi-scale entropy feature vector; Indicates the index of the dimension, with values ​​ranging from 1 to... ;

[0077] Find the historical multi-scale entropy feature vector with the smallest distance; the corresponding historical fault feature is the matched historical fault feature.

[0078] S2.3. Weighted fusion of historical fault features to generate a baseline fault mode feature vector; concatenation and fusion of the multi-scale entropy feature vector and the baseline fault mode feature vector to generate a chip health status feature vector.

[0079] It should be noted that the inverse distance between the multi-scale entropy feature vector and each historical multi-scale entropy feature vector is used as the basic weight. To avoid the denominator being invalid when the distance is zero, a smoothing constant (valued at 10) is added to each distance. This is based on the requirements of numerical computation stability and the weight allocation conventions in machine learning. -5 If the value is greater than 10 -5 This will distort the distance relationship and disrupt the weight distribution. If the value is less than 10... -5 If the smoothing effect is lost due to floating-point rounding failure, then the historical multi-scale entropy feature vector with smaller distance will receive a larger weight;

[0080] Multiple historical fault feature vectors that have been matched are weighted and summed according to their corresponding basic weights to generate a baseline fault mode feature vector. The multi-scale entropy feature vector and the baseline fault mode feature vector are then concatenated end to end to form a new vector, which is the chip health status feature vector.

[0081] It should also be noted that existing technologies typically assess chip status using only single-scale entropy analysis or fixed threshold matching. While this can achieve basic fault detection, it is difficult to capture the cross-scale characteristics of complex faults, resulting in poor adaptability to unknown faults and a high false alarm rate. This solution comprehensively extracts cross-scale information of faults by calculating multi-scale entropy feature vectors and generates a baseline fault vector adapted to the current chip status through a historical fault feature fusion mechanism. By concatenating and fusing real-time and historical features, it achieves quantitative assessment of compatibility faults, solving the problems of insensitivity to complex faults and poor flexibility.

[0082] S3. Construct a transfer meta-learning model, input the chip health status feature vector into the transfer meta-learning model, and generate risk probability scores and fault root cause classification results through forward inference calculation.

[0083] S3.1 Construct a feature encoding layer based on the ReLU activation function, a risk probability scoring layer based on the Sigmoid activation function, and a fault root cause classification layer based on the Softmax activation function;

[0084] It should be noted that the specific dimension of the input vector, i.e. the length of the chip health status feature vector, should be clearly defined. The output dimension should be configured according to functional requirements. For example, multiple fully connected layers need to be stacked for the feature encoding layer, and the number of output nodes for each fully connected layer should be set independently. A single output node should be set for the risk probability scoring layer, and the output dimension for the fault root cause classification layer should be set to be equal to the number of fault categories. The weight matrix and bias vector should be initialized. Each element of the weight matrix should be randomly sampled and assigned a value from a normal distribution, and all elements of the bias vector should be set to zero to complete the construction of the fully connected layer.

[0085] Using fully connected layers as the core building block, three functional layers are constructed by configuring different activation functions and output dimensions: The feature encoding layer is constructed by stacking multiple fully connected layers and applying a ReLU activation function after the linear computation output of each layer to achieve non-linear feature abstraction; the risk probability scoring layer is constructed by setting a fully connected layer with a single output node and applying a Sigmoid activation function after the linear computation output to generate risk probability values ​​between 0 and 1; and the fault root cause classification layer is constructed by setting a fully connected layer with an output dimension equal to the number of fault categories and applying a Softmax activation function after the linear computation output to generate the probability distribution of fault categories.

[0086] It should also be noted that the reason why fully connected layers are used as core building blocks is that they have high versatility and flexibility. They can effectively process input data of any dimension through simple matrix operations and activation function combinations. The weight matrix and bias vector in fully connected layers can learn complex nonlinear mapping relationships in the data. By configuring different activation functions, they can be adapted to diverse task requirements such as feature encoding, risk scoring, and fault classification.

[0087] S3.2 Construct a transfer meta-learning model based on the feature encoding layer, risk probability scoring layer, and fault root cause classification layer;

[0088] It should be noted that the output of the feature encoding layer is directly connected to the input of the risk probability scoring layer and the input of the fault root cause classification layer, forming an overall structure with the feature encoding layer in front, and the risk probability scoring layer and the fault root cause classification layer in the back and arranged in parallel, thus completing the construction of the transfer meta-learning model.

[0089] Randomly sample values ​​from the normal distribution to fill each element of the weight matrix in each fully connected layer, and set all elements of the bias vectors of all fully connected layers to zero to complete the initialization of the weight matrix and bias vectors;

[0090] Historical multi-scale entropy feature vectors and corresponding historical fault features are used as training data and input into the transfer learning model. Risk probability scores and fault root cause classification results are calculated through forward propagation. Specifically: the historical multi-scale entropy feature vectors are input into the feature encoding layer. Each fully connected layer in the feature encoding layer performs a linear calculation on the historical multi-scale entropy feature vectors, multiplying the weight matrix and summing it with the bias vector. A ReLU activation function is applied to the linear calculation result, and the output of the ReLU activation function of the last fully connected layer is the abstract feature. The abstract feature is simultaneously input into the risk probability scoring layer and the fault root cause classification layer. The fully connected layer of the risk probability scoring layer performs a linear calculation on the abstract feature and applies a Sigmoid activation function to the linear calculation result, obtaining a risk probability score compressed to between 0 and 1. The fault root cause classification layer performs a linear calculation and applies a Softmax activation function to the linear calculation result, converting each element in the linear calculation result into a probability value for the corresponding fault category. The probability distribution of all fault categories is the fault root cause classification result.

[0091] The mean squared error loss and cross-entropy loss of the risk probability score, the root cause classification result of the fault, and the historical fault characteristics are calculated. The mean squared error loss and cross-entropy loss are added together according to the weight coefficients to obtain the total loss. The gradient descent algorithm is used to backpropagate and update all weight matrices and bias vectors according to the total loss. The forward calculation, calculation of total loss and backpropagation update operations are iterated until the rate of change of total loss is less than the convergence threshold, and the training of the transfer meta-learning model is completed.

[0092] The weighting coefficients are defined based on the balance between the magnitude of the loss function and the trade-off between task importance. The mean squared error loss weighting coefficient is set to 0.4, which balances the magnitude difference between the mean squared error loss and the cross-entropy loss (the mean squared error loss is usually of a higher magnitude than the cross-entropy loss). The weighting prioritizes the accuracy of the fault classification task. A value below 0.4 will lead to insufficient learning of the risk probability scoring task, resulting in excessive prediction bias, while a value above 0.4 will suppress the fault classification task, leading to a decrease in accuracy. The cross-entropy loss weighting coefficient is set to 0.6. A value above 0.6 will excessively suppress the risk probability scoring task, leading to prediction bias, while a value below 0.6 will not be able to offset the magnitude difference, resulting in a decrease in classification accuracy. The weighted sum of the mean squared error loss weighting coefficient and the cross-entropy loss weighting coefficient is 1.

[0093] A convergence threshold is defined based on a balance between training stability and computational efficiency; the value of the convergence threshold ranges from 1×10⁻⁶. -4 Up to 1×10 -6 Convergence threshold greater than 1×10-4 This can lead to premature training termination, preventing the transfer meta-learning model from fully learning features, resulting in a value less than 1×10. -6 The inability to trigger convergence due to the limitations of floating-point calculation precision can lead to indefinite training or overfitting.

[0094] S3.3. The feature encoding layer performs a nonlinear transformation on the chip health status feature vector to generate abstract features; the risk probability scoring layer and the fault root cause classification layer perform forward calculation on the abstract features to generate risk probability scores and fault root cause classification results.

[0095] It should be noted that the linear calculation output is obtained by multiplying the chip health state feature vector with the weight matrix of the first fully connected layer in the feature encoding layer and adding the bias vector. The ReLU activation function is then applied to the linear calculation output to obtain the first nonlinear transformation result. The product of the first nonlinear transformation result and the weight matrix of the second fully connected layer is then calculated and the bias vector is added. The ReLU activation function is then applied again to obtain the second nonlinear transformation result. The alternating calculation process of "linear transformation + ReLU activation" is repeated until all fully connected layers are passed, and the abstract feature is output.

[0096] Abstract features are simultaneously input into the risk probability scoring layer and the fault root cause classification layer. A risk probability score between 0 and 1 is calculated using the Sigmoid activation function, and the fault root cause classification result is calculated using the Softmax activation function, completing the forward computation process. The expression for calculating the risk probability score is:

[0097] ;

[0098] in, This represents a risk probability score, with the value compressed between 0 and 1. It indicates the probability of a chip experiencing a compatibility failure; the closer the value is to 1, the higher the risk. This represents the Sigmoid activation function; Representing abstract features; This represents the weight matrix of the risk probability scoring layer; This represents the bias vector of the risk probability scoring layer; The term "score" indicates that the current parameter belongs to the risk probability scoring layer.

[0099] The expression for calculating the root cause classification result is as follows:

[0100] ;

[0101] in, This represents the root cause classification result. Each element in the root cause classification result represents the probability value of the corresponding root cause category, and the sum of the probability values ​​of all root cause categories is 1. This represents the Softmax activation function, which transforms abstract features into a probability distribution. This represents the weight matrix of the root cause classification layer. This represents the bias vector of the fault root cause classification layer; The "category" indicates that the current parameter belongs to the fault root cause classification layer.

[0102] It should also be noted that existing technologies typically use independent models to perform risk scoring and fault classification separately. Although these can achieve basic functions, the lack of feature sharing between independent models leads to computational redundancy and an inability to capture the correlation between tasks, resulting in poor generalization ability. This solution constructs a shared feature encoding layer and combines it with a parallel risk probability scoring layer and a fault root cause classification layer to form an end-to-end multi-task transfer meta-learning model. It uses historical data for joint training to achieve automatic feature extraction and task collaborative optimization. It simultaneously outputs risk probability scoring and fault root cause classification results in a single forward propagation, solving the problems of low efficiency, low feature utilization, and reliance on manual intervention.

[0103] S4. Perform multi-dimensional structured integration and in-depth analysis of the risk probability score and fault root cause classification results to generate a compatibility in-depth diagnostic summary.

[0104] S4.1. Using predefined risk level mapping rules, convert risk probability scores into risk level identifiers; extract the fault root cause category with the highest probability value from the fault root cause classification results as the primary fault root cause.

[0105] It should be noted that the risk level mapping rule refers to dividing the continuous risk probability score into three threshold intervals (low-risk threshold interval, medium-risk threshold interval, and high-risk threshold interval), and assigning a risk level label (low-risk, medium-risk, and high-risk) to each threshold interval.

[0106] Based on the statistical distribution characteristics of risk probability scores in historical test data and industry consensus standards, low-risk, medium-risk, and high-risk threshold ranges are defined. The low-risk threshold range is 0 to 0.4; the medium-risk threshold range is 0.4 to 0.7; and the high-risk threshold range is 0.7 to 1.0. If the threshold range is set too narrowly (e.g., 0 to 0.3, 0.3 to 0.6, and 0.6 to 1.0), the risk level will be overly sensitive, and slight fluctuations in the score will trigger a level jump, reducing the stability of the assessment. If the threshold range is set too widely (e.g., 0 to 0.6, 0.6 to 0.8, and 0.8 to 1.0), the risk level differentiation will be insufficient, high-scoring risks will be diluted, and effective early warning will not be possible. The current division ensures that the low-risk threshold range covers most fault-free or slightly abnormal scenarios, the medium-risk threshold range captures potential unstable states, and the high-risk threshold range corresponds to high-probability fault events.

[0107] The risk probability score is compared with the threshold range in the risk level mapping rule. Based on the threshold range in which the risk probability score falls, the corresponding risk level identifier is extracted from the risk level mapping rule.

[0108] The root cause classification result is a probability distribution vector containing the probability values ​​of each root cause category. Iterate through all the probability values ​​of each root cause category in the root cause classification result, compare and find the root cause category with the highest probability value, and designate it as the primary root cause.

[0109] S4.2 Integrate the risk probability score, risk level identifier, primary root cause of failure and corresponding root cause category probability value to generate a compatibility deep diagnostic summary.

[0110] It should be noted that the risk probability score, risk level identifier, primary root cause of failure, and corresponding root cause category probability value are combined according to the summary format specification (based on the requirements of automated processing and the definition of data exchange format). The summary format specification specifies the field names, data types, arrangement order, and output format of the risk probability score, risk level identifier, primary root cause of failure, and corresponding root cause category probability value in the compatibility deep diagnostic summary to generate the compatibility deep diagnostic summary.

[0111] This embodiment also provides a computer device applicable to the memory chip compatibility testing method, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the memory chip compatibility testing method proposed in the above embodiment.

[0112] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0113] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the memory chip compatibility testing method proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0114] In summary, this invention achieves the collaborative acquisition and integration of various physical parameters during the operation of memory chips by: collecting multi-source heterogeneous data and generating multi-dimensional time-series datasets using cross-modal fusion algorithms, thus solving the problem of isolated data analysis and improving data utilization efficiency and the comprehensiveness of fault detection; combining and generating chip health status feature vectors to achieve multi-scale, cross-dimensional feature extraction of chip status, enabling the capture of latent fault modes and complex time-series features, and enhancing the accuracy and reliability of fault diagnosis; and integrating and generating compatibility deep diagnostic summaries to achieve automated and intelligent compatibility assessment, reducing manual intervention, improving testing efficiency and interpretability, and enhancing the accuracy, generalization ability, and engineering applicability of memory chip compatibility testing.

[0115] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for testing the compatibility of memory chips, characterized in that: include, Collect multi-source heterogeneous data generated when the memory chip under test runs a preset induced test load, and fuse them to generate a multi-dimensional time series dataset; The specific steps for calculating multi-scale entropy feature vectors based on multi-dimensional time series datasets are as follows. The multidimensional time series dataset was normalized using the Max-Min method; Calculate the sample entropy values ​​of the normalized multidimensional time series dataset, and combine all the sample entropy values ​​to generate a multi-scale entropy feature vector; The baseline fault mode feature vector is obtained from a pre-built compatibility fault feature knowledge base. The multi-scale entropy feature vector is then combined with the baseline fault mode feature vector to generate a chip health status feature vector. The specific steps are as follows: Historical test data is extracted from a pre-set test database, and a compatibility fault feature knowledge base is built based on the historical test data; Input the multi-scale entropy feature vector into the compatibility fault feature knowledge base to match historical fault features; Historical fault features are weighted and fused to generate a baseline fault mode feature vector. The multi-scale entropy feature vector is concatenated and fused with the baseline fault mode feature vector to generate the chip health status feature vector. The specific steps for constructing a transfer meta-learning model are as follows. A feature encoding layer is constructed based on the ReLU activation function, a risk probability scoring layer is constructed based on the Sigmoid activation function, and a fault root cause classification layer is constructed based on the Softmax activation function. A transfer meta-learning model is constructed based on the feature encoding layer, risk probability scoring layer, and fault root cause classification layer. The chip health status feature vector is input into the transfer meta-learning model, and risk probability scores and fault root cause classification results are generated through forward inference. The specific steps are as follows. The chip health status feature vector is input into the transfer meta-learning model, and the feature encoding layer performs a nonlinear transformation on the chip health status feature vector to generate abstract features. The abstract features are forward-computed through the risk probability scoring layer and the fault root cause classification layer to generate risk probability scores and fault root cause classification results. The risk probability score and root cause classification results are integrated and analyzed in a multi-dimensional structure to generate a deep compatibility diagnostic summary.

2. The memory chip compatibility testing method as described in claim 1, characterized in that: The process involves collecting multi-source heterogeneous data generated when the memory chip under test operates under a preset induced test load, fusing the collected data, and generating a multi-dimensional time series dataset. The specific steps are as follows: The preset induced test load is converted into an electrical signal sequence through protocol programming and applied to the memory chip under test, so that the memory chip under test is in the operating state. Collect multi-source heterogeneous data generated by the memory chip under test during operation, perform data cleaning and time synchronization on the multi-source heterogeneous data, and generate preprocessed multi-source data; Preprocessed multi-source data are aligned and stitched together along the time dimension to generate a multidimensional time series dataset.

3. The memory chip compatibility testing method as described in claim 1, characterized in that: The process of multi-dimensionally structured integration and in-depth analysis of risk probability scores and root cause classification results to generate a compatibility in-depth diagnostic summary involves the following steps: Risk probability scores are converted into risk level identifiers using predefined risk level mapping rules; From the root cause classification results, the root cause category with the highest probability value is extracted as the primary root cause. The risk probability score, risk level identifier, primary root cause of failure and corresponding root cause category probability value are integrated through a predefined summary format specification to generate a compatibility-deep diagnostic summary.

4. The memory chip compatibility testing method as described in claim 3, characterized in that: The predefined summary format specification defines the field names, data types, order of arrangement, and output format of risk probability score, risk level identifier, primary root cause of failure, and corresponding root cause category probability value in the compatibility deep diagnostic summary.

5. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the memory chip compatibility testing method according to any one of claims 1 to 4.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the memory chip compatibility testing method according to any one of claims 1 to 4.

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